This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND.

It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested.

Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger).

The patch is based on the work by Maxim Artamonov.

Signed-off-by: Maxim Artamonov scn1874@yandex.ru Signed-off-by: Magnus Lilja lilja.magnus@gmail.com --- cpu/arm1136/start.S | 9 +- include/asm-arm/arch-mx31/mx31-regs.h | 5 + include/fsl_nfc.h | 109 ++++++++++++++ nand_spl/nand_boot_fsl_nfc.c | 263 +++++++++++++++++++++++++++++++++ 4 files changed, 384 insertions(+), 2 deletions(-) create mode 100644 include/fsl_nfc.h create mode 100644 nand_spl/nand_boot_fsl_nfc.c

diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 28cb5fd..957f438 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -200,12 +200,15 @@ clbss_l:str r2, [r0] /* clear loop... */

ldr pc, _start_armboot

+#ifdef CONFIG_NAND_SPL +_start_armboot: .word nand_boot +#else #ifdef CONFIG_ONENAND_IPL _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot -#endif - +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */

/* ************************************************************************* @@ -217,6 +220,7 @@ _start_armboot: .word start_armboot * ************************************************************************* */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -243,6 +247,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

#ifndef CONFIG_PRELOADER /* diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index a8a05c8..c2e7dcf 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -194,4 +194,9 @@ #define CS5_BASE 0xB6000000 #define PCMCIA_MEM_BASE 0xC0000000

+/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 + #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h new file mode 100644 index 0000000..da5be37 --- /dev/null +++ b/include/fsl_nfc.h @@ -0,0 +1,109 @@ +/* + * + * (c) 2009 Magnus Lilja lilja.magnus@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_NFC_H +#define __FSL_NFC_H + +/* + * Register map and bit definitions for the Freescale NAND Flash + * Controller present in i.MX31 and other devices. + */ + +struct fsl_nfc_regs { + u32 main_area0[128]; /* @0x000 */ + u32 main_area1[128]; + u32 main_area2[128]; + u32 main_area3[128]; + u32 spare_area0[4]; + u32 spare_area1[4]; + u32 spare_area2[4]; + u32 spare_area3[4]; + u32 reserved1[64 - 16 + 64 * 5]; + u16 bufsiz; /* @ 0xe00 */ + u16 reserved2; + u16 buffer_address; + u16 flash_add; + u16 flash_cmd; + u16 configuration; + u16 ecc_status_result; + u16 ecc_rslt_main_area; + u16 ecc_rslt_spare_area; + u16 nf_wr_prot; + u16 unlock_start_blk_add; + u16 unlock_end_blk_add; + u16 nand_flash_wr_pr_st; + u16 nand_flash_config1; + u16 nand_flash_config2; +}; + +/* + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/* + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/* + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/* + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data + * Output operation + */ +#define NFC_OUTPUT 0x8 + +/* + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/* + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read + * Status operation + */ +#define NFC_STATUS 0x20 + +/* + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +#endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c new file mode 100644 index 0000000..df67b9b --- /dev/null +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -0,0 +1,263 @@ +/* + * (C) Copyright 2009 + * Magnus Lilja lilja.magnus@gmail.com + * + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr at denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm-arm/arch/mx31-regs.h> +#include <asm/io.h> +#include <fsl_nfc.h> + +static struct fsl_nfc_regs *nfc; + +static void nfc_wait_ready(void) +{ + uint32_t tmp; + + while (!(readw(&nfc->nand_flash_config2) & NFC_INT)) + ; + + /* Reset interrupt flag */ + tmp = readw(&nfc->nand_flash_config2); + tmp &= ~NFC_INT; + writew(tmp, &nfc->nand_flash_config2); +} + +static void nfc_nand_init(void) +{ + /* unlocking RAM Buff */ + writew(0x2, &nfc->configuration); + + /* hardware ECC checking and correct */ + writew(NFC_ECC_EN, &nfc->nand_flash_config1); +} + +static void nfc_nand_command(unsigned short command) +{ + writew(command, &nfc->flash_cmd); + writew(NFC_CMD, &nfc->nand_flash_config2); + nfc_wait_ready(); +} + +static void nfc_nand_page_address(unsigned int page_address) +{ + unsigned int page_count; + + writew(0x00, &nfc->flash_cmd); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + + /* code only for 2kb flash */ + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) { + writew(0x00, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + } + + page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; + + if (page_address <= page_count) { + page_count--; /* transform 0x01000000 to 0x00ffffff */ + do { + writew(page_address & 0xff, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + page_address = page_address >> 8; + page_count = page_count >> 8; + } while (page_count); + } +} + +static void nfc_nand_data_output(void) +{ + int i; + + /* + * The NAND controller requires four output commands for + * large page devices. + */ + for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { + writew(NFC_ECC_EN, &nfc->nand_flash_config1); + writew(i, &nfc->buffer_address); /* read in i:th buffer */ + writew(NFC_OUTPUT, &nfc->nand_flash_config2); + nfc_wait_ready(); + } +} + +static int nfc_nand_check_ecc(void) +{ + return readw(&nfc->ecc_status_result); +} + +static int nfc_read_page(unsigned int page_address, unsigned char *buf) +{ + int i; + u32 *src; + u32 *dst; + + writew(0, &nfc->buffer_address); /* read in first 0 buffer */ + nfc_nand_command(NAND_CMD_READ0); + nfc_nand_page_address(page_address); + + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + nfc_nand_command(NAND_CMD_READSTART); + + nfc_nand_data_output(); /* fill the main buffer 0 */ + + if (nfc_nand_check_ecc()) + return -1; + + src = &nfc->main_area0[0]; + dst = (u32 *)buf; + + /* main copy loop from NAND-buffer to SDRAM memory */ + for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) { + writel(readl(src), dst); + src++; + dst++; + } + + return 0; +} + +static int is_badblock(int pagenumber) +{ + int page = pagenumber; + int maxpagecheck = CONFIG_SYS_NAND_PAGE_SIZE == 0x800 ? 2 : 1; + u32 badblock; + u32 *src; + + // todo shall we check both or only one of them? + for (page = pagenumber; page < pagenumber + maxpagecheck; page++) { + writew(0, &nfc->buffer_address); /* read in first 0 buffer */ + nfc_nand_command(NAND_CMD_READ0); + nfc_nand_page_address(page); + + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + nfc_nand_command(NAND_CMD_READSTART); + + nfc_nand_data_output(); /* fill the main buffer 0 */ + + src = &nfc->spare_area0[0]; + + /* + * IMPORTANT NOTE: The nand flash controller uses a non- + * standard layout for large page devices. This can + * affect the position of the bad block marker. + */ + /* Get the bad block marker */ + badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]); + badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4); + badblock &= 0xff; + + /* bad block marker verify */ + if (badblock != 0xff) + return 1; /* potential bad block */ + } + + return 0; +} + +static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) +{ + int i; + unsigned int page; + unsigned int maxpages = CONFIG_SYS_NAND_SIZE / + CONFIG_SYS_NAND_PAGE_SIZE; + + nfc = (void *)NFC_BASE_ADDR; + + nfc_nand_init(); + + /* Convert to page number */ + page = from / CONFIG_SYS_NAND_PAGE_SIZE; + i = 0; + + while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) { + if (nfc_read_page(page, buf) < 0) + return -1; + + page++; + i++; + buf = buf + CONFIG_SYS_NAND_PAGE_SIZE; + + /* + * Check if we have crossed a block boundary, and if so + * check for bad block. + */ + if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { + /* + * Yes, new block. See if this block is good. If not, + * loop until we find i good block. + */ + while (is_badblock(page)) { + page = page + CONFIG_SYS_NAND_PAGE_COUNT; + /* Check i we've reached the end of flash. */ + if (page >= maxpages) + return -1; + } + } + } + + return 0; +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + nfc = (void *)NFC_BASE_ADDR; + + /* + * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must + * be aligned to full pages + */ + if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { + /* Copy from NAND successful, start U-boot */ + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot(); + } else { + /* Unrecoverable error when copying from NAND */ + while (1) { + /* Loop forever */ + } + } +} + +/* + * Called from start.S in case of an exception. + */ +void hang(void) +{ + while (1) { + /* Loop forever */ + } +}

Signed-off-by: Magnus Lilja lilja.magnus@gmail.com --- cpu/arm1136/mx31/Makefile | 1 + cpu/arm1136/mx31/devices.c | 56 ++++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31.h | 3 ++ 3 files changed, 60 insertions(+), 0 deletions(-) create mode 100644 cpu/arm1136/mx31/devices.c

diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index 1e49e8d..c8e18f7 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(SOC).a

COBJS += generic.o COBJS += timer.o +COBJS += devices.o

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/devices.c b/cpu/arm1136/mx31/devices.c new file mode 100644 index 0000000..1f4ca7e --- /dev/null +++ b/cpu/arm1136/mx31/devices.c @@ -0,0 +1,56 @@ +/* + * + * (C) Copyright 2009 Magnus Lilja lilja.magnus@gmail.com + * + * (c) 2007 Pengutronix, Sascha Hauer s.hauer@pengutronix.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx31-regs.h> +#include <asm/arch/mx31.h> + +#ifdef CONFIG_SYS_MX31_UART1 +void mx31_uart1_hw_init(void) +{ + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); +} +#endif + +#ifdef CONFIG_MXC_SPI +void mx31_spi2_hw_init(void) +{ + /* SPI2 */ + mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); +} +#endif diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h index 1d475dd..53b9f27 100644 --- a/include/asm-arm/arch-mx31/mx31.h +++ b/include/asm-arm/arch-mx31/mx31.h @@ -47,4 +47,7 @@ static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) } #endif

+void mx31_uart1_hw_init(void); +void mx31_spi2_hw_init(void); + #endif /* __ASM_ARCH_MX31_H */

Signed-off-by: Magnus Lilja lilja.magnus@gmail.com --- MAKEALL | 1 + Makefile | 14 +++- board/freescale/mx31pdk/config.mk | 4 + board/freescale/mx31pdk/lowlevel_init.S | 114 +++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 54 +++++++++++++ include/configs/mx31pdk.h | 21 ++++- nand_spl/board/freescale/mx31pdk/Makefile | 54 +++++++++++++ nand_spl/board/freescale/mx31pdk/config.mk | 5 + nand_spl/board/freescale/mx31pdk/u-boot.lds | 36 +++++++++ 9 files changed, 297 insertions(+), 6 deletions(-) create mode 100644 board/freescale/mx31pdk/lowlevel_init.S create mode 100644 nand_spl/board/freescale/mx31pdk/Makefile create mode 100644 nand_spl/board/freescale/mx31pdk/config.mk create mode 100644 nand_spl/board/freescale/mx31pdk/u-boot.lds

diff --git a/MAKEALL b/MAKEALL index 3976745..2f36506 100755 --- a/MAKEALL +++ b/MAKEALL @@ -552,6 +552,7 @@ LIST_ARM11=" \ imx31_phycore_eet \ mx31ads \ mx31pdk \ + mx31pdk_nand \ qong \ smdk6400 \ " diff --git a/Makefile b/Makefile index 41cccfc..0e9177e 100644 --- a/Makefile +++ b/Makefile @@ -376,7 +376,7 @@ $(LDSCRIPT): depend $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all

-$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin +$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin

$(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk @@ -3112,8 +3112,16 @@ imx31_phycore_config : unconfig mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31

-mx31pdk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 mx31pdk freescale mx31 +mx31pdk_config \ +mx31pdk_nand_config : unconfig + @mkdir -p $(obj)include + @if [ -n "$(findstring _nand_,$@)" ]; then \ + echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \ + else \ + echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \ + echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \ + fi + @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31

omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk index d34dc02..dcaa09f 100644 --- a/board/freescale/mx31pdk/config.mk +++ b/board/freescale/mx31pdk/config.mk @@ -1 +1,5 @@ +ifdef CONFIG_NAND_SPL +TEXT_BASE = 0x87ec0000 +else TEXT_BASE = 0x87f00000 +endif diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S new file mode 100644 index 0000000..f913f90 --- /dev/null +++ b/board/freescale/mx31pdk/lowlevel_init.S @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2009 Magnus Lilja lilja.magnus@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl lowlevel_init + +#include <asm/arch/mx31-regs.h> +#include <asm/macro.h> + +#define CCM_CCMR_SETUP 0x074B0BF5 +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ + PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ + PLL_MFN(12)) + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +#define ESDCFG0_MDDR_SETUP 0x006ac73a + +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + write32 IPU_CONF, IPU_CONF_DI_EN + write32 CCM_CCMR, CCM_CCMR_SETUP + + wait_timer 0x40000 + + write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE + write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS + + /* Set up clock to 532MHz */ + write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ + write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ + + write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* Set up MX31 DDR pins */ + write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 + write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 + write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 + write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 + write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 + write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 + write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 + write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 + write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 + write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 + write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 + write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 + write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 + write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 + write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 + write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 + write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 + write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 + write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 + write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 + write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 + write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 + write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 + write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 + write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 + write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 + write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 + + /* Set up MX31 DDR Memory Controller */ + write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP + write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP + + /* Perform DDR init sequence */ + write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE + write32 CSD0_BASE | 0x0f00, 0x12344321 + write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH + write32 CSD0_BASE, 0x12344321 + write32 CSD0_BASE, 0x12344321 + write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG + write8 CSD0_BASE | 0x00000033, 0xda + write8 CSD0_BASE | 0x01000000, 0xff + write32 WEIM_ESDCTL0, ESDCTL_RW + write32 CSD0_BASE, 0xDEADBEEF + write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL + + mov pc, lr diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 76f4d53..51b02a2 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -61,6 +61,29 @@ #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0)

+#define WEIM_ESDCTL0 0xB8001000 +#define WEIM_ESDCFG0 0xB8001004 +#define WEIM_ESDCTL1 0xB8001008 +#define WEIM_ESDCFG1 0xB800100C +#define WEIM_ESDMISC 0xB8001010 + +#define ESDCTL_SDE (1 << 31) +#define ESDCTL_CMD_RW (0 << 28) +#define ESDCTL_CMD_PRECHARGE (1 << 28) +#define ESDCTL_CMD_AUTOREFRESH (2 << 28) +#define ESDCTL_CMD_LOADMODEREG (3 << 28) +#define ESDCTL_CMD_MANUALREFRESH (4 << 28) +#define ESDCTL_ROW_13 (2 << 24) +#define ESDCTL_ROW(x) ((x) << 24) +#define ESDCTL_COL_9 (1 << 20) +#define ESDCTL_COL(x) ((x) << 20) +#define ESDCTL_DSIZ(x) ((x) << 16) +#define ESDCTL_SREFR(x) ((x) << 13) +#define ESDCTL_PWDT(x) ((x) << 10) +#define ESDCTL_FP(x) ((x) << 8) +#define ESDCTL_BL(x) ((x) << 7) +#define ESDCTL_PRCT(x) ((x) << 0) + #define WEIM_BASE 0xb8002000 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10) #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) @@ -181,6 +204,37 @@ #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)

+/* PAD control registers for SDR/DDR */ +#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) +#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) +#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) +#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) +#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) +#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) +#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) +#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) +#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) +#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) +#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) +#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) +#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) +#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) +#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) +#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) +#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) +#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) +#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) +#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) +#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) +#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) +#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) +#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) +#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) +#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) +#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) +#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) +#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) + /* * Memory regions and CS */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 72b9f3b..773170f 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -43,10 +43,10 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1

-/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other - * program to initialize the SDRAM. - */ +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif

/* * Size of malloc() pool @@ -158,4 +158,19 @@

#define CONFIG_ENV_SIZE (128 * 1024)

+/* NAND configuration for the NAND_SPL */ + +/* Start copying real U-boot from the second page */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +/* Load U-Boot to this address */ +#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #endif /* __CONFIG_H */ diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile new file mode 100644 index 0000000..a9572ba --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -0,0 +1,54 @@ +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL + +SOBJS = start.o lowlevel_init.o +COBJS = nand_boot_fsl_nfc.o + +SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c +SRCS += $(SRCTREE)/cpu/arm1136/start.S +SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $@ + +######################################################################### + +$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/nand_spl/%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mx31pdk/config.mk b/nand_spl/board/freescale/mx31pdk/config.mk new file mode 100644 index 0000000..198cafc --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/config.mk @@ -0,0 +1,5 @@ +PAD_TO := 2048 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds new file mode 100644 index 0000000..edd8430 --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/u-boot.lds @@ -0,0 +1,36 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + lowlevel_init.o (.text) + nand_boot_fsl_nfc.o (.text) + *(.text) + . = 2K; + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +}

Magnus

Please ensure when writing ARM macros that any architecture specific instructions are

restricted to the correct architecture.

This patch should be OK, this is just a heads up for any budding macro writers on the list

Regards

Peter

-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Magnus Lilja Sent: 09 June 2009 19:38 To: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 3/6] ARM: Add macros.h to be used in assemblerfile.

From: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

plagnioj@jcrosoft.com

include/asm-arm/macro.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 57 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/macro.h

diff --git a/include/asm-arm/macro.h b/include/asm-arm/macro.h new file mode 100644 index 0000000..a598776 --- /dev/null +++ b/include/asm-arm/macro.h @@ -0,0 +1,57 @@ +/*

• • include/asm-arm/macro.h
• • Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD

+plagnioj@jcrosoft.com

• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __ASM_ARM_MACRO_H__ +#define __ASM_ARM_MACRO_H__ +#ifdef __ASSEMBLY__

+.macro write32, addr, data

• ldr r4, =\addr
• ldr r5, =\data
• str r5, [r4]

+.endm

+.macro write16, addr, data

• ldr r4, =\addr
• ldrh r5, =\data
• strh r5, [r4]

+.endm

+.macro write8, addr, data

• ldr r4, =\addr
• ldrb r5, =\data
• strb r5, [r4]

+.endm

+.macro wait_timer, time

• ldr r4, =\time

+1:

• nop
• subs r4, r4, #1
• bcs 1b

+.endm

+#endif /* __ASSEMBLY__ */

+#endif /* __ASM_ARM_MACRO_H__ */

1.5.6

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Dear Magnus,

In message bef59ad70a27ef8496f88b85510f8d2c236e8cd9.1244572159.git.lilja.magnus@gmail.com you wrote:

Currently CONFIG_ONENAND_IPL is used in a number of #ifdef's in start.S. In preparation for adding support for NAND SPL the macro CONFIG_PRELOADER is introducted and replaces the CONFIG_ONENAND_IPL in start.S.

Signed-off-by: Magnus Lilja lilja.magnus@gmail.com

README | 5 +++++ cpu/arm1136/start.S | 24 ++++++++++++------------ onenand_ipl/board/apollon/Makefile | 4 ++-- 3 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/README b/README index 561c100..86cf628 100644 --- a/README +++ b/README @@ -2702,6 +2702,11 @@ Low Level (hardware related) configuration options: some other boot loader or by a debugger which performs these initializations itself.

+- CONFIG_PRELOADER

• [ARM only] Modifies the behaviour of start.S when
  

• compiling a loader that is executed before the actual
  

• U-Boot. E.g. when compiling a NAND SPL.
  

Is there a special reason for making this ARM only?

Best regards,

Wolfgang Denk