Re: [U-Boot] [PATCH 1/3] arm: tegra20: implement early pmic rail configuration
On 20 Aug 2015 22:00, Stephen Warren swarren@wwwdotorg.org wrote:
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is never set so low that AVP operation at reset is impossible...
Exactly.
udelay(1000);all the delays in this patch seem very large. What drove the choice of the delay values?
Three things: I2C transfers at that speed will take at least around some 3 to 4 hundred us to complete so we stay at the save side. Plus the T30 equivalent file uses the exact same delays so it can't be that wrong. My testing also showed that setting it anywhere much lower will cause reliability issues.
On 08/20/2015 05:06 PM, Marcel Ziswiler wrote:
On 20 Aug 2015 22:00, Stephen Warren swarren@wwwdotorg.org wrote:
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is never set so low that AVP operation at reset is impossible...
Exactly.
udelay(1000);all the delays in this patch seem very large. What drove the choice of the delay values?
Three things: I2C transfers at that speed will take at least around some 3 to 4 hundred us to complete so we stay at the save side.
The I2C transfers should have already synchronously completed, so there should be no need to wait for those. If that's not true, there's a serious bug that needs to be fixed.
Plus the T30 equivalent file uses the exact same delays so it can't be that wrong. My testing also showed that setting it anywhere much lower will cause reliability issues.
OK, consistency with other code seems reasonable. I still think there's little point in such long delays though, but that could be fixed later.
participants (2)
-
Marcel Ziswiler -
Stephen Warren