[PATCH v2] board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for rockchip and also a reference board for board vendors.
Hardware: SoC: RK3588 DRAM: LPDDR4X 8GB Debug: UART2 via USB PCIe: 3x4 *1 SATA *2 HDMI out *2 HDMI IN *1 USB2.0 Host *2 USB3.0 Host *1 Type C *1 MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - Use the same dts name as kernel
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi | 21 ++++ arch/arm/dts/rk3588-evb1-v10.dts | 129 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 7 ++ board/rockchip/evb_rk3588/Kconfig | 15 +++ board/rockchip/evb_rk3588/MAINTAINERS | 7 ++ board/rockchip/evb_rk3588/Makefile | 6 ++ board/rockchip/evb_rk3588/evb-rk3588.c | 39 +++++++ configs/evb-rk3588_defconfig | 69 ++++++++++++ doc/board/rockchip/rockchip.rst | 10 ++ include/configs/evb_rk3588.h | 15 +++ 11 files changed, 319 insertions(+) create mode 100644 arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-evb1-v10.dts create mode 100644 board/rockchip/evb_rk3588/Kconfig create mode 100644 board/rockchip/evb_rk3588/MAINTAINERS create mode 100644 board/rockchip/evb_rk3588/Makefile create mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c create mode 100644 configs/evb-rk3588_defconfig create mode 100644 include/configs/evb_rk3588.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c160e884bf6..f854c092893 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ + rk3588-evb1-v10.dtb \ rk3588-rock-5b.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi new file mode 100644 index 00000000000..bd2e2594863 --- /dev/null +++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen { + u-boot,spl-boot-order = &sdhci; + }; +}; + +&sdhci { + bootph-all; +}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts new file mode 100644 index 00000000000..b91af0204db --- /dev/null +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 V10 Board"; + compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index aee71ca1dab..3596b82f1f1 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -1,5 +1,11 @@ if ROCKCHIP_RK3588
+config TARGET_EVB_RK3588 + bool "Rockchip EVB1 v10" + select BOARD_LATE_INIT + help + RK3588 EVB is a evaluation board for Rockchp RK3588. + config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT @@ -51,6 +57,7 @@ config SYS_MALLOC_F_LEN default 0x80000
source board/edgeble/neural-compute-module-6/Kconfig +source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5b-rk3588/Kconfig
endif diff --git a/board/rockchip/evb_rk3588/Kconfig b/board/rockchip/evb_rk3588/Kconfig new file mode 100644 index 00000000000..d38efe61d83 --- /dev/null +++ b/board/rockchip/evb_rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3588 + +config SYS_BOARD + default "evb_rk3588" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS new file mode 100644 index 00000000000..7b7df3c5a8a --- /dev/null +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +EVB-RK3588 +M: Kever Yang kever.yang@rock-chips.com +S: Maintained +F: board/rockchip/evb_rk3588 +F: include/configs/evb_rk3588.h +F: configs/evb-rk3588_defconfig +F: arch/arm/dts/rk3588-evb-u-boot.dtsi diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile new file mode 100644 index 00000000000..240d2ec597e --- /dev/null +++ b/board/rockchip/evb_rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. +# + +obj-y += evb-rk3588.o diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c new file mode 100644 index 00000000000..caf94d8d29c --- /dev/null +++ b/board/rockchip/evb_rk3588/evb-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return rk3588_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig new file mode 100644 index 00000000000..ddeadb8a760 --- /dev/null +++ b/configs/evb-rk3588_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b5563b8f7f9..af6e466de1e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -91,6 +91,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3568 (evb-rk3568)
* rk3588 + - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588) - Radxa ROCK 5B (rock5b-rk3588)
@@ -185,6 +186,15 @@ To build rk3568 boards: make evb-rk3568_defconfig make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3588 boards: + +.. code-block:: bash + + export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.33.elf + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin + make evb-rk3588_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + Flashing --------
diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h new file mode 100644 index 00000000000..4568e2cace6 --- /dev/null +++ b/include/configs/evb_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __EVB_RK3588_H +#define __EVB_RK3588_H + +#include <configs/rk3588_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif
On Thu, 2 Mar 2023 at 12:43, Kever Yang kever.yang@rock-chips.com wrote:
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for rockchip and also a reference board for board vendors.
Hardware: SoC: RK3588 DRAM: LPDDR4X 8GB Debug: UART2 via USB PCIe: 3x4 *1 SATA *2 HDMI out *2 HDMI IN *1 USB2.0 Host *2 USB3.0 Host *1 Type C *1 MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- Use the same dts name as kernel
Thanks.
Reviewed-by: Jagan Teki jagan@edgeble.ai
Hello! I'm not rockchip maintainer, so please do not send me rockchip patches unless it is something for which I really should take an attention.
On Thursday 02 March 2023 15:12:57 Kever Yang wrote:
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for rockchip and also a reference board for board vendors.
Hardware: SoC: RK3588 DRAM: LPDDR4X 8GB Debug: UART2 via USB PCIe: 3x4 *1 SATA *2 HDMI out *2 HDMI IN *1 USB2.0 Host *2 USB3.0 Host *1 Type C *1 MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- Use the same dts name as kernel
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi | 21 ++++ arch/arm/dts/rk3588-evb1-v10.dts | 129 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 7 ++ board/rockchip/evb_rk3588/Kconfig | 15 +++ board/rockchip/evb_rk3588/MAINTAINERS | 7 ++ board/rockchip/evb_rk3588/Makefile | 6 ++ board/rockchip/evb_rk3588/evb-rk3588.c | 39 +++++++ configs/evb-rk3588_defconfig | 69 ++++++++++++ doc/board/rockchip/rockchip.rst | 10 ++ include/configs/evb_rk3588.h | 15 +++ 11 files changed, 319 insertions(+) create mode 100644 arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-evb1-v10.dts create mode 100644 board/rockchip/evb_rk3588/Kconfig create mode 100644 board/rockchip/evb_rk3588/MAINTAINERS create mode 100644 board/rockchip/evb_rk3588/Makefile create mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c create mode 100644 configs/evb-rk3588_defconfig create mode 100644 include/configs/evb_rk3588.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c160e884bf6..f854c092893 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \
- rk3588-evb1-v10.dtb \ rk3588-rock-5b.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi new file mode 100644 index 00000000000..bd2e2594863 --- /dev/null +++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2023 Rockchip Electronics Co., Ltd.
- */
+#include "rk3588-u-boot.dtsi"
+/ {
- aliases {
mmc0 = &sdmmc;mmc1 = &sdhci;- };
- chosen {
u-boot,spl-boot-order = &sdhci;- };
+};
+&sdhci {
- bootph-all;
+}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts new file mode 100644 index 00000000000..b91af0204db --- /dev/null +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi"
+/ {
- model = "Rockchip RK3588 EVB1 V10 Board";
- compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
- aliases {
mmc0 = &sdhci;serial2 = &uart2;- };
- chosen {
stdout-path = "serial2:1500000n8";- };
- backlight: backlight {
compatible = "pwm-backlight";power-supply = <&vcc12v_dcin>;pwms = <&pwm2 0 25000 0>;- };
- vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
+};
+&gmac0 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii-rxid";
- pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2&gmac0_rx_bus2&gmac0_rgmii_clk&gmac0_rgmii_bus>;- pinctrl-names = "default";
- rx_delay = <0x00>;
- tx_delay = <0x43>;
- status = "okay";
+};
+&i2c2 {
- status = "okay";
- hym8563: rtc@51 {
compatible = "haoyu,hym8563";reg = <0x51>;#clock-cells = <0>;clock-output-names = "hym8563";pinctrl-names = "default";pinctrl-0 = <&hym8563_int>;interrupt-parent = <&gpio0>;interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;wakeup-source;- };
+};
+&mdio0 {
- rgmii_phy: ethernet-phy@1 {
/* RTL8211F */compatible = "ethernet-phy-id001c.c916";reg = <0x1>;pinctrl-names = "default";pinctrl-0 = <&rtl8211f_rst>;reset-assert-us = <20000>;reset-deassert-us = <100000>;reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;- };
+};
+&pinctrl {
- rtl8211f {
rtl8211f_rst: rtl8211f-rst {rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- hym8563 {
hym8563_int: hym8563-int {rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;};- };
+};
+&pwm2 {
- status = "okay";
+};
+&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
+};
+&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
+}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index aee71ca1dab..3596b82f1f1 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -1,5 +1,11 @@ if ROCKCHIP_RK3588
+config TARGET_EVB_RK3588
- bool "Rockchip EVB1 v10"
- select BOARD_LATE_INIT
- help
RK3588 EVB is a evaluation board for Rockchp RK3588.config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT @@ -51,6 +57,7 @@ config SYS_MALLOC_F_LEN default 0x80000
source board/edgeble/neural-compute-module-6/Kconfig +source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5b-rk3588/Kconfig
endif diff --git a/board/rockchip/evb_rk3588/Kconfig b/board/rockchip/evb_rk3588/Kconfig new file mode 100644 index 00000000000..d38efe61d83 --- /dev/null +++ b/board/rockchip/evb_rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3588
+config SYS_BOARD
- default "evb_rk3588"
+config SYS_VENDOR
- default "rockchip"
+config SYS_CONFIG_NAME
- default "evb_rk3588"
+config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+endif diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS new file mode 100644 index 00000000000..7b7df3c5a8a --- /dev/null +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +EVB-RK3588 +M: Kever Yang kever.yang@rock-chips.com +S: Maintained +F: board/rockchip/evb_rk3588 +F: include/configs/evb_rk3588.h +F: configs/evb-rk3588_defconfig +F: arch/arm/dts/rk3588-evb-u-boot.dtsi diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile new file mode 100644 index 00000000000..240d2ec597e --- /dev/null +++ b/board/rockchip/evb_rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. +#
+obj-y += evb-rk3588.o diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c new file mode 100644 index 00000000000..caf94d8d29c --- /dev/null +++ b/board/rockchip/evb_rk3588/evb-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
+#include <fdtdec.h> +#include <fdt_support.h>
+#ifdef CONFIG_OF_BOARD_SETUP +static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) +{
- struct fdt_memory gap1 = {
.start = 0x3fc000000,.end = 0x3fc4fffff,- };
- struct fdt_memory gap2 = {
.start = 0x3fff00000,.end = 0x3ffffffff,- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
- /*
* Inject the reserved-memory nodes into the DTS*/- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
NULL, flags);- if (ret)
return ret;- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
NULL, flags);+}
+int ft_board_setup(void *blob, struct bd_info *bd) +{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
+} +#endif diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig new file mode 100644 index 00000000000..ddeadb8a760 --- /dev/null +++ b/configs/evb-rk3588_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b5563b8f7f9..af6e466de1e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -91,6 +91,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3568 (evb-rk3568)
- rk3588
- Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588) - Radxa ROCK 5B (rock5b-rk3588)@@ -185,6 +186,15 @@ To build rk3568 boards: make evb-rk3568_defconfig make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3588 boards:
+.. code-block:: bash
export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.33.elfexport ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.binmake evb-rk3588_defconfigmake CROSS_COMPILE=aarch64-linux-gnu-Flashing
diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h new file mode 100644 index 00000000000..4568e2cace6 --- /dev/null +++ b/include/configs/evb_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (c) 2023 Rockchip Electronics Co., Ltd.
- */
+#ifndef __EVB_RK3588_H +#define __EVB_RK3588_H
+#include <configs/rk3588_common.h>
+#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \"stderr=serial,vidconsole\0"+#endif
2.25.1
participants (3)
-
Jagan Teki -
Kever Yang -
Pali Rohár