[U-Boot] [PATCH V3 1/6] imx: add dummpy cpu type MXC_CPU_MX6QP/DP
Add dummy cpu type MXC_CPU_MX6QP/DP. Since i.MX6QP use a revision 2, but with cpu type i.MX6Q, we need the MXC_CPU_MX6QP and to decrease major with 1 to let print_cpuinfo print the correct info.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v3: New patch This patch is to make print_cpuinfo display correct cpu info, also fix is_mx6dqp
Changes v2: none
arch/arm/cpu/armv7/mx6/soc.c | 11 +++++++++-- arch/arm/imx-common/cpu.c | 4 ++++ arch/arm/include/asm/arch-imx/cpu.h | 2 ++ arch/arm/include/asm/arch-mx6/sys_proto.h | 4 +--- 4 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..d3a3b2e 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,12 +62,12 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); - u32 major; + u32 major, cfg = 0;
if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; + cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { if (!cfg) @@ -81,6 +81,13 @@ u32 get_cpu_rev(void)
} major = ((reg >> 8) & 0xff); + if ((major >= 1) && + ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { + major--; + type = MXC_CPU_MX6QP; + if (cfg == 1) + type = MXC_CPU_MX6DP; + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + (0x10 * (major + 1))); } diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 5e56cfe..03086c0 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -122,6 +122,10 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX6QP: + return "6QP"; /* Quad-Plus version of the mx6 */ + case MXC_CPU_MX6DP: + return "6DP"; /* Quad-Plus version of the mx6 */ case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ case MXC_CPU_MX6D: diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4715f4e..99e0e32 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -12,6 +12,8 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6D 0x64 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ +#define MXC_CPU_MX6DP 0x68 +#define MXC_CPU_MX6QP 0x69
#define CS0_128 0 #define CS0_64M_CS1_64M 1 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 28c77a4..eee8ca8 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const);
-#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_2_0)) +#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
/* * Initializes on-chip ethernet controllers.
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v3: Move bit definition to crm_regs.h.
Changes v2: 1. Remove #ifdef, but use runtime check 2. A few bit definitions are introduced in c files, because to other platforms the macro will make compilation fail, also there are no other places refer the bit macro definitions.
arch/arm/cpu/armv7/mx6/clock.c | 30 +++++++++++++------- arch/arm/cpu/armv7/mx6/soc.c | 5 +++- arch/arm/include/asm/arch-mx6/crm_regs.h | 48 +++++++++++++++++--------------- 3 files changed, 49 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ae99945..446fe84 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -323,10 +323,12 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) - if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) - return MXC_HCLK; /* OSC 24Mhz */ -#endif + if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || + is_mx6dqp()) { + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ + } + perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1); @@ -337,10 +339,13 @@ static u32 get_uart_clk(void) u32 reg, uart_podf; u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) - if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) - freq = MXC_HCLK; -#endif + + if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || + is_mx6dqp()) { + if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) + freq = MXC_HCLK; + } + reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
@@ -352,8 +357,13 @@ static u32 get_cspi_clk(void) u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2); - reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; - cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + + if (is_mx6dqp()) { + if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) + return MXC_HCLK / (cspi_podf + 1); + }
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d3a3b2e..e80c09c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -342,9 +342,12 @@ static void set_ahb_rate(u32 val) static void clear_mmdc_ch_mask(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */ - writel(0, &mxc_ccm->ccdr); + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + writel(reg, &mxc_ccm->ccdr); }
static void init_bandgap(void) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 887d048..5bbf6e0 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -123,6 +123,8 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +/* Exists on i.MX6QP */ +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
/* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -195,10 +197,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 -#ifndef CONFIG_MX6SX -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) -#endif +/* Exists on i.MX6QP */ +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
/* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) @@ -229,10 +229,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 #endif -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) +/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 -#endif + #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
/* Define the bits in register CSCMR2 */ @@ -244,15 +244,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#ifdef CONFIG_MX6SX +/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 + #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 -#else -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 -#endif
/* Define the bits in register CSCDR1 */ #ifndef CONFIG_MX6SX @@ -273,16 +270,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #endif -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#ifdef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#endif -#endif #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
/* Define the bits in register CS1CDR */ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) @@ -316,9 +307,14 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ + (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16)) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ + (is_mx6dqp() ? 15 : 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ + (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16)) + #endif #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 @@ -384,6 +380,9 @@ struct mxc_ccm_reg { /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 +/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) + /* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 @@ -728,6 +727,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) #endif
+/* PRG_CLK0 exists on i.MX6QP */ +#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) + #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
From: "Ye.Li" B37916@freescale.com
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v3: none Changes v2: none
arch/arm/cpu/armv7/mx6/hab.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c index 8dee595..bf7dbf0 100644 --- a/arch/arm/cpu/armv7/mx6/hab.c +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -252,7 +252,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) * do cache flushes. don't think any * exist, so we ignore them. */ - writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); + if (!is_mx6dqp()) + writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); } else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) { writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Brown Oliver B37094@freescale.com Signed-off-by: Ye.Li B37916@freescale.com ---
Changes v3: Remove ipu qos settings
Changes v2: 1. runtime check 2. introduce ipu qos settings for better performance
arch/arm/cpu/armv7/mx6/clock.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 446fe84..eb2712d 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -866,6 +866,16 @@ void enable_ipu_clock(void) reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { + reg = readl(&mxc_ccm->CCGR6); + reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK; + writel(reg, &mxc_ccm->CCGR6); + + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + } } #endif /***************************************************/
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
if (is_mx6dqp()) {reg = readl(&mxc_ccm->CCGR6);reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;writel(reg, &mxc_ccm->CCGR6);
What about using setbits_le32 instead?
reg = readl(&mxc_ccm->CCGR3);reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK;writel(reg, &mxc_ccm->CCGR3);}
Same here.
Regards,
Fabio Estevam
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Brown Oliver B37094@freescale.com Signed-off-by: Ye.Li B37916@freescale.com
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable.
Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v3: New patch Changes v2: none
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 9 +++++++++ board/freescale/mx6sabresd/mx6sabresd.c | 10 ++++++++++ include/configs/mx6qsabreauto.h | 5 ----- include/configs/mx6sabre_common.h | 21 +++++++++++++++++++-- include/configs/mx6sabresd.h | 5 ----- 5 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index b76e4eb..943a4bd 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -522,6 +522,15 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "SABREAUTO"); + + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + setenv("board_rev", "MX6Q"); + else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + setenv("board_rev", "MX6DL"); +#endif + return 0; }
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 23f8f6b..4f0694a 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -679,6 +679,16 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "SABRESD"); + + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + setenv("board_rev", "MX6Q"); + else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + setenv("board_rev", "MX6DL"); +#endif + return 0; }
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 2260344..11cf538 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -12,11 +12,6 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" -#if defined CONFIG_MX6Q -#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" -#elif defined CONFIG_MX6DL -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb" -#endif #define CONFIG_MMCROOT "/dev/mmcblk0p2" #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c8c9f81..397ad7b 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -76,10 +76,12 @@ #define EMMC_ENV "" #endif
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -149,9 +151,24 @@ "fi; " \ "else " \ "bootz; " \ - "fi;\0" + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; " \ + "fi;\0" \ +
#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ "if run loadbootscript; then " \ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 41162ca..5f635ca 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -19,11 +19,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" #define CONFIG_MMCROOT "/dev/mmcblk1p2" -#if defined(CONFIG_MX6Q) -#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabresd.dtb" -#elif defined(CONFIG_MX6DL) -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabresd.dtb" -#endif #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable.
Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan Peng.Fan@freescale.com
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment
No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed.
Signed-off-by: Robin Gong b38343@freescale.com Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v3: 1. runtime setting DTB 2. In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. All the patches in this patch set have been reworked with CONFIG_MX6QP removed to align with runtime check, but this IMX_CONFIG is needed at build time. Future, when SPL is converted, this config can be removed.
Changes v2: 1. Remove unused macro in current upstream uboot. 2. setup_fec, remove non 6qp code. Add comments for gpr setting. 3. mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged.
board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++++++++++++++++++++++++++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 33 ++++-- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6sabre_common.h | 2 + 4 files changed, 176 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 0000000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include <config.h> + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x12420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x00bb0008 0x00000004 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 943a4bd..98602f8 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-int board_eth_init(bd_t *bis) +static void setup_fec(void) { + if (is_mx6dqp()) { + /* + * select ENET MAC0 TX clock from PLL + */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + enable_fec_anatop_clock(ENET_125MHZ); + } + setup_iomux_enet(); +} + +int board_eth_init(bd_t *bis) +{ + setup_fec();
return cpu_eth_init(bis); } @@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) int power_init_board(void) { struct pmic *p; - unsigned int ret; + unsigned int value;
p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM); - if (ret < 0) - return ret; + if (is_mx6dqp()) { + /* set SW2 staby volatage 0.975V*/ + pmic_reg_read(p, PFUZE100_SW2STBY, &value); + value &= ~0x3f; + value |= 0x17; + pmic_reg_write(p, PFUZE100_SW2STBY, value); + }
- return 0; + return pfuze_mode_init(p, APS_PFM); }
#ifdef CONFIG_CMD_BMODE @@ -525,7 +542,9 @@ int board_late_init(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG setenv("board_name", "SABREAUTO");
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + if (is_mx6dqp()) + setenv("board_rev", "MX6QP"); + else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) setenv("board_rev", "MX6Q"); else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) setenv("board_rev", "MX6DL"); diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 0000000..606391e --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q" +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 397ad7b..5873c48 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -154,6 +154,8 @@ "fi;\0" \ "findfdt="\ "if test $fdt_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
- Add DDR script for mx6qpsabreauto board.
- On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
- On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment
No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed.
Signed-off-by: Robin Gong b38343@freescale.com Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
On Mon, Jun 29, 2015 at 11:58 AM, Peng Fan Peng.Fan@freescale.com wrote:
switch (imxtype) {
case MXC_CPU_MX6QP:return "6QP"; /* Quad-Plus version of the mx6 */case MXC_CPU_MX6DP:return "6DP"; /* Quad-Plus version of the mx6 */
Here you meant "Dual-Plus" instead.
participants (2)
-
Fabio Estevam -
Peng Fan