[U-Boot] [PATCH 0/6] ARM: uniphier: update PLL settings and clean-up NAND settings
1-3: update PLL init code 4-6: clean up NAND adhoc code (the last two are only applicable after the Denali DT driver is applied.) http://patchwork.ozlabs.org/patch/805959/
Masahiro Yamada (6): ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings ARM: uniphier: move PLLCTRL register macros to each SoC .c file ARM: uniphier: add PLL settings for PXs3 ARM: uniphier: remove unneeded NAND config options ARM: uniphier: enable CONFIG_NAND_DENALI_DT ARM: uniphier: remove ad-hoc pin settings for NAND
arch/arm/mach-uniphier/board_init.c | 27 +++-------------- arch/arm/mach-uniphier/clk/pll-ld11.c | 13 ++++++++- arch/arm/mach-uniphier/clk/pll-ld20.c | 21 ++++++++++++- arch/arm/mach-uniphier/clk/pll-pxs3.c | 55 +++++++++++++++++++++++++++++++++++ arch/arm/mach-uniphier/sc64-regs.h | 21 ------------- configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_pro4_defconfig | 1 + configs/uniphier_pxs2_ld6b_defconfig | 1 + include/configs/uniphier.h | 3 -- 9 files changed, 94 insertions(+), 49 deletions(-)
The #include <common.h> was added for mdelay(). Later, the declaration of mdelay was moved to <linux/delay.h> by commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h").
There is no need to include <common.h> now.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/clk/pll-ld11.c | 2 +- arch/arm/mach-uniphier/clk/pll-ld20.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 02befa298b46..b4a97d21610f 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <linux/delay.h> #include <linux/io.h>
#include "../init.h" diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 121a3690e834..50b91598d64d 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <linux/delay.h>
#include "../init.h" #include "../sc64-regs.h"
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/clk/pll-ld11.c | 11 +++++++++++ arch/arm/mach-uniphier/clk/pll-ld20.c | 19 +++++++++++++++++++ arch/arm/mach-uniphier/sc64-regs.h | 21 --------------------- 3 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index b4a97d21610f..1a7ec2952524 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -11,6 +11,17 @@ #include "../sc64-regs.h" #include "pll.h"
+/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + void uniphier_ld11_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 50b91598d64d..5e072c6dff77 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -11,6 +11,25 @@ #include "../sc64-regs.h" #include "pll.h"
+/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + void uniphier_ld20_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d3aa18530d97..d0a51f239c38 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -12,27 +12,6 @@
#define SC_BASE_ADDR 0x61840000
-/* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ - -/* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) - -/* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) - #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/clk/pll-pxs3.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 201d3517a86a..e84d52b80f3b 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -1,9 +1,64 @@ /* + * Copyright (C) 2017 Socionext Inc. + * * SPDX-License-Identifier: GPL-2.0+ */
+#include <linux/delay.h> + #include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ +#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) +#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) +#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) +#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
void uniphier_pxs3_pll_init(void) { + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); }
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the NAND initialization process is driven by the driver itself. CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
include/configs/uniphier.h | 3 --- 1 file changed, 3 deletions(-)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 9a64063c3ee6..884e59c35e41 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -83,7 +83,6 @@ #endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 #define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE 1024 @@ -91,8 +90,6 @@ #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) - #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
Migrate to the DT-based NAND init entry.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_pro4_defconfig | 1 + configs/uniphier_pxs2_ld6b_defconfig | 1 + 3 files changed, 3 insertions(+)
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index be0ae70f1a89..39f80188105e 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -37,6 +37,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 5ba8879af6ae..f4181b164163 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -36,6 +36,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index 22c21548b6d7..a7b517ea8da2 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -37,6 +37,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y
This is now set up by the pinctrl driver when the NAND driver is probed. Remove the legacy code.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/board_init.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index ed58d07f7e50..9c0bed0b8b26 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -78,7 +78,6 @@ static void uniphier_ld20_misc_init(void)
struct uniphier_initdata { unsigned int soc_id; - bool nand_2cs; void (*sbc_init)(void); void (*pll_init)(void); void (*clk_init)(void); @@ -89,7 +88,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, - .nand_2cs = true, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, .clk_init = uniphier_ld4_clk_init, @@ -98,7 +96,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO4) { .soc_id = UNIPHIER_PRO4_ID, - .nand_2cs = false, .sbc_init = uniphier_sbc_init_savepin, .pll_init = uniphier_pro4_pll_init, .clk_init = uniphier_pro4_clk_init, @@ -107,7 +104,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_SLD8) { .soc_id = UNIPHIER_SLD8_ID, - .nand_2cs = true, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, .clk_init = uniphier_ld4_clk_init, @@ -116,7 +112,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO5) { .soc_id = UNIPHIER_PRO5_ID, - .nand_2cs = true, .sbc_init = uniphier_sbc_init_savepin, .clk_init = uniphier_pro5_clk_init, }, @@ -124,7 +119,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS2) { .soc_id = UNIPHIER_PXS2_ID, - .nand_2cs = true, .sbc_init = uniphier_pxs2_sbc_init, .clk_init = uniphier_pxs2_clk_init, }, @@ -132,7 +126,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { .soc_id = UNIPHIER_LD6B_ID, - .nand_2cs = true, .sbc_init = uniphier_pxs2_sbc_init, .clk_init = uniphier_pxs2_clk_init, }, @@ -140,7 +133,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) { .soc_id = UNIPHIER_LD11_ID, - .nand_2cs = false, .sbc_init = uniphier_ld11_sbc_init, .pll_init = uniphier_ld11_pll_init, .clk_init = uniphier_ld11_clk_init, @@ -150,7 +142,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD20) { .soc_id = UNIPHIER_LD20_ID, - .nand_2cs = false, .sbc_init = uniphier_ld11_sbc_init, .pll_init = uniphier_ld20_pll_init, .clk_init = uniphier_ld20_clk_init, @@ -160,7 +151,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) { .soc_id = UNIPHIER_PXS3_ID, - .nand_2cs = false, .sbc_init = uniphier_pxs2_sbc_init, .pll_init = uniphier_pxs3_pll_init, .clk_init = uniphier_pxs3_clk_init, @@ -188,33 +178,24 @@ int board_init(void)
led_puts("U0");
- if (IS_ENABLED(CONFIG_NAND_DENALI)) { - ret = uniphier_pin_init(initdata->nand_2cs ? - "nand2cs_grp" : "nand_grp"); - if (ret) - pr_err("failed to init NAND pins\n"); - } - - led_puts("U1"); - if (initdata->pll_init) initdata->pll_init();
- led_puts("U2"); + led_puts("U1");
if (initdata->clk_init) initdata->clk_init();
- led_puts("U3"); + led_puts("U2");
if (initdata->misc_init) initdata->misc_init();
- led_puts("U4"); + led_puts("U3");
uniphier_setup_xirq();
- led_puts("U5"); + led_puts("U4");
support_card_late_init();
2017-08-26 17:57 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:
1-3: update PLL init code 4-6: clean up NAND adhoc code (the last two are only applicable after the Denali DT driver is applied.) http://patchwork.ozlabs.org/patch/805959/
Series, applied.
participants (1)
-
Masahiro Yamada