Hi all,

Please find attached a little patch wich adds the initialization of the SPR 311 in start.S. As mentionned in the Motorola "G2 PowerPC Core Reference Manual" 2.1.2.13, this SPR is used as a copy of the MBAR.

Best regards

CHANGELOG: Patch by Pierre AUBERT, 03 Feb 2004 - cpu/mpc5xxx/start.S: copy MBAR into SPR311

Best regards

diff -ur u-boot/cpu/mpc5xxx/start.S u-boot-paub/cpu/mpc5xxx/start.S --- u-boot/cpu/mpc5xxx/start.S 2004-01-02 15:00:02.000000000 +0100 +++ u-boot-paub/cpu/mpc5xxx/start.S 2004-02-03 14:05:45.000000000 +0100 @@ -142,6 +142,8 @@ lis r3, CFG_MBAR@h ori r3, r3, CFG_MBAR@l #if defined(CONFIG_MPC5200) + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 #endif #if defined(CONFIG_MGT5100) diff -ur u-boot/include/asm-ppc/processor.h u-boot-paub/include/asm-ppc/processor.h --- u-boot/include/asm-ppc/processor.h 2003-12-07 00:55:11.000000000 +0100 +++ u-boot-paub/include/asm-ppc/processor.h 2004-02-03 14:05:09.000000000 +0100 @@ -261,6 +261,7 @@ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ @@ -491,6 +492,7 @@ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_E500) #define PIR SPRN_PIR #endif