[PATCH v2 0/2] arm: socfpga: enable CONFIG_BOOTCOMMAND for cyclone5
From: Joyce Ooi joyce.ooi@intel.com
This patch series enables CONFIG_BOOTCOMMAND in cyclone5 defconfig to execute Intel FPGA u-boot script if it's available and enable FPGA bridge when FPGA is in user mode.
v2: add u-boot script and add checking if FPGA is in user mode
Joyce Ooi (2): arm: socfpga: checks if FPGA is in user mode before enabling FPGA bridge configs: socfpga: add CONFIG_BOOTCOMMAND for cyclone5
arch/arm/mach-socfpga/misc_gen5.c | 43 +++++++++++++++++++++----------------- configs/socfpga_cyclone5_defconfig | 3 ++- include/configs/socfpga_common.h | 3 +++ 3 files changed, 29 insertions(+), 20 deletions(-)
From: Joyce Ooi joyce.ooi@intel.com
This patch adds a checking to ensure that FPGA is in user mode before enabling FPGA bridge to prevent unexpected behavior or error.
Signed-off-by: Joyce Ooi joyce.ooi@intel.com --- v2: this patch is added in patch version 2 --- arch/arm/mach-socfpga/misc_gen5.c | 43 ++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 7209e8d6db7..7885ab2b6bc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -221,26 +221,31 @@ void do_bridge_reset(int enable, unsigned int mask) int i;
if (enable) { - socfpga_bridges_set_handoff_regs(!(mask & BIT(0)), - !(mask & BIT(1)), - !(mask & BIT(2))); - for (i = 0; i < 2; i++) { /* Reload SW setting cache */ - iswgrp_handoff[i] = - readl(socfpga_get_sysmgr_addr() + - SYSMGR_ISWGRP_HANDOFF_OFFSET(i)); + if (fpgamgr_test_fpga_ready()) { + socfpga_bridges_set_handoff_regs(!(mask & BIT(0)), + !(mask & BIT(1)), + !(mask & BIT(2))); + for (i = 0; i < 2; i++) { /* Reload SW setting cache */ + iswgrp_handoff[i] = + readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(i)); + } + + writel(iswgrp_handoff[2], + socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_FPGAINFGRP_MODULE); + writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); + writel(iswgrp_handoff[0], + socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); + writel(iswgrp_handoff[1], &nic301_regs->remap); + + writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); + writel(iswgrp_handoff[0], + socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); + } else { + puts("Bridges: Failed to enable because FPGA is not "); + puts("in user mode\n"); } - - writel(iswgrp_handoff[2], - socfpga_get_sysmgr_addr() + - SYSMGR_GEN5_FPGAINFGRP_MODULE); - writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); - writel(iswgrp_handoff[0], - socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); - writel(iswgrp_handoff[1], &nic301_regs->remap); - - writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); - writel(iswgrp_handoff[0], - socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); } else { writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE);
From: Joyce Ooi joyce.ooi@intel.com
Add CONFIG_BOOTCOMMAND in cyclone5 defconfig to run fatscript and enable FPGA bridge when FPGA is in user mode. The fatscript executes the Intel FPGA u-boot script if it's available so that customers can add any customization (such as configuring registers) without modifying the codes.
Signed-off-by: Joyce Ooi joyce.ooi@intel.com --- v2: add u-boot script --- configs/socfpga_cyclone5_defconfig | 3 ++- include/configs/socfpga_common.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 1633ca1deb5..132b7b7fa81 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -8,7 +8,8 @@ CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fatscript; bridge enable; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 07c9745eba9..87746541321 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -245,6 +245,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ "fdt_addr_r=0x02000000\0" \ "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" \ "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ "socfpga_legacy_reset_compat=1\0" \
participants (1)
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Ooi, Joyce