[U-Boot-Users] [PATCH] Add support for the MPC8349E-mITX-GP
From: Timur Tabi timur@freescale.com
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX.
Signed-off-by: Timur Tabi timur@freescale.com --- MAINTAINERS | 1 + Makefile | 16 ++- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 105 ++-------- include/configs/MPC8349ITX.h | 463 ++++++++++++++++------------------------- include/mpc83xx.h | 41 ++++ 6 files changed, 264 insertions(+), 368 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS index ce20def..e65699f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -347,6 +347,7 @@ John Zhan zhanz@sinovee.com Timur Tabi timur@freescale.com
MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349
Kim Phillips kim.phillips@freescale.com
diff --git a/Makefile b/Makefile index 1dbdf4d..10d961f 100644 --- a/Makefile +++ b/Makefile @@ -1624,8 +1624,20 @@ MPC8360EMDS_SLAVE_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
-MPC8349ITX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +MPC8349ITX_config \ +MPC8349ITX_LOWBOOT_config \ +MPC8349ITXGP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/mpc8349itx + @CTYPE=$(subst MPC,,$(@:_config=)); \ + echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h + @if [ "$(findstring GP,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @if [ "$(findstring LOWBOOT,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
######################################################################### ## MPC85xx Systems diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk index 2e11311..1901fdc 100644 --- a/board/mpc8349itx/config.mk +++ b/board/mpc8349itx/config.mk @@ -21,10 +21,14 @@ #
# -# MPC8349ITX +# MPC8349E-mITX and MPC8349E-mITX-GP #
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE TEXT_BASE = 0xFEF00000 +endif
ifneq ($(OBJTREE),$(SRCTREE)) # We are building u-boot in a separate directory, use generated diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 4838e70..aefdaf7 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -134,88 +134,6 @@ volatile static struct pci_controller ho }; #endif /* CONFIG_PCI */
-/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) \ - && !defined(CONFIG_COMPACT_FLASH) - - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ - asm("sync"); - *sdram_addr = 0xff; /*1 time*/ - udelay(100); - *sdram_addr = 0xff; /*2 times*/ - udelay(100); - *sdram_addr = 0xff; /*3 times*/ - udelay(100); - *sdram_addr = 0xff; /*4 times*/ - udelay(100); - *sdram_addr = 0xff; /*5 times*/ - udelay(100); - *sdram_addr = 0xff; /*6 times*/ - udelay(100); - *sdram_addr = 0xff; /*7 times*/ - udelay(100); - *sdram_addr = 0xff; /*8 times*/ - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - -#else - puts("SDRAM on Local Bus is NOT available!\n"); - -#ifdef CFG_BR2_PRELIM - lbc->bank[2].br = CFG_BR2_PRELIM; - lbc->bank[2].or = CFG_OR2_PRELIM; -#endif - -#ifdef CFG_BR3_PRELIM - lbc->bank[3].br = CFG_BR3_PRELIM; - lbc->bank[3].or = CFG_OR3_PRELIM; -#endif -#endif -} - long int initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; @@ -246,7 +164,6 @@ long int initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize * 1024 * 1024; @@ -254,7 +171,11 @@ long int initdram(int board_type)
int checkboard(void) { +#ifdef CONFIG_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif
return 0; } @@ -267,6 +188,7 @@ int checkboard(void) */ int misc_init_f(void) { +#ifdef CFG_VSC7385_BASE volatile u32 *vsc7385_cpuctrl;
/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -286,6 +208,7 @@ int misc_init_f(void)
vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); *vsc7385_cpuctrl |= 0x0c; +#endif
#ifdef CONFIG_COMPACT_FLASH /* UPM Table Configuration Code */ @@ -355,9 +278,19 @@ int misc_init_r(void) #ifdef CFG_I2C_EEPROM_ADDR static u8 eeprom_data[] = /* HRCW data */ { - 0xaa, 0x55, 0xaa, - 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, - 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CFG_HRCW_LOW >> 24) & 0xFF, + (CFG_HRCW_LOW >> 16) & 0xFF, + (CFG_HRCW_LOW >> 8) & 0xFF, + CFG_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CFG_HRCW_HIGH >> 24) & 0xFF, + (CFG_HRCW_HIGH >> 16) & 0xFF, + (CFG_HRCW_HIGH >> 8) & 0xFF, + CFG_HRCW_HIGH & 0xFF };
u8 data[sizeof(eeprom_data)]; diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb29..2774a65 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -21,7 +21,7 @@ */
/* - MPC8349E-mITX board configuration file + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Memory map:
@@ -31,11 +31,11 @@ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFF00_0000-0xFF7F_FFFF First 8MB bank of Flash memory + 0xFF80_0000-0xFFFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
I2C address list: Align. Board @@ -56,7 +56,9 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#undef DEBUG +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif
/* * High Level Configuration Options @@ -64,14 +66,26 @@ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */
+#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + + +/* On-board devices */ + #define CONFIG_PCI
+#ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ +#endif #define CONFIG_RTC_DS1337
-/* I2C */ #define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
+/* + * Device configurations + */ + +/* I2C */ #ifdef CONFIG_HARD_I2C
#define CONFIG_MISC_INIT_F @@ -111,59 +125,40 @@
#endif
-#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE +/* Compact Flash */ +#ifdef CONFIG_COMPACT_FLASH
-#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1
-#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2
-#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
-#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ +#define CONFIG_DOS_PARTITION
-/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif
/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. + * DDR Setup */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000
-#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* Mb */ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
@@ -171,46 +166,76 @@ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ #endif
-/* FLASH on the Local Bus */ +/* + *Flash on the Local Bus + */ + #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#ifdef CONFIG_MPC8349ITX + +/* The MPC8349E-mITX has 16MB of flash in two banks */ + +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} + +#else + +/* The MPC8349E-mITX-GP has only 8MB of flash in one bank */ + +#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 3 /* log2 of the above value */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ + +#endif + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ + #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
-/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ +/* Vitesse 7385 */
-#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#ifdef CONFIG_MPC8349ITX
-#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ +#define CFG_VSC7385_BASE 0xF8000000
-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#endif
-#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ +/* LED */ + +#define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
@@ -219,32 +244,16 @@ #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_CF_BASE -#define CFG_ATA_DATA_OFFSET 0x0000 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 -#define CFG_ATA_STRIDE 2 - -#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
-#define CONFIG_DOS_PARTITION - -#define CFG_MID_FLASH_JUMP 0x7F000000 +/* + * U-Boot memory configuration + */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
- #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -253,10 +262,10 @@
#define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
-#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -272,98 +281,10 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000
-#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* * Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -374,20 +295,16 @@ #define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
-/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP
/* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 @@ -397,6 +314,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+/* + * PCI + */ #ifdef CONFIG_PCI
#define CONFIG_MPC83XX_PCI2 @@ -447,14 +367,18 @@
#endif
+#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + /* TSEC */
#ifdef CONFIG_TSEC_ENET
-#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI -#endif - #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
@@ -468,6 +392,7 @@ #endif
#ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ @@ -479,14 +404,15 @@
#endif
- /* * Environment */ +#define CONFIG_ENV_OVERWRITE + #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -533,16 +459,23 @@ /* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif
/* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -562,15 +495,15 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */ +/* + * Cache Configuration + */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -578,12 +511,12 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1)
-#ifdef PCI_64BIT +#ifdef CFG_LOWBOOT #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ + HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -596,7 +529,7 @@ HRCWH_PCI_HOST |\ HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -606,30 +539,33 @@ HRCWH_TSEC2M_IN_GMII ) #endif
-/* System performance */ +/* + * System performance + */ #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */
-/* System IO Config */ +/* + * System IO Config + */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_INIT 0x000000000
-#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ +/* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-/* PCI @ 0x80000000 */ +/* PCI */ #ifdef CONFIG_PCI #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -706,49 +642,27 @@ #endif
#ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif
-#if 1 -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin -#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0
+#ifdef CONFIG_MPC8349ITX #define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_UBOOTPATH u-boot.bin +#else +#define CONFIG_HOSTNAME mpc8349emitxgp #endif
-#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 +/* Default path and filenames */ +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 -#else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ -#endif +#define CONFIG_BOOTDELAY 0
#define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) @@ -756,47 +670,38 @@ #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtfile=mpc8349emitx.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr"
#undef MK_STR #undef XMK_STR diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0ca..41180e8 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -221,6 +221,47 @@ #define OR_SDRAM_EAD 0x00000001 #define OR_SDRAM_EAD_SHIFT 0
+#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + /* * Hard Reset Configration Word - High */
On Wed, 17 Jan 2007 09:09:45 -0600 timur@freescale.com wrote:
From: Timur Tabi timur@freescale.com
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX.
Signed-off-by: Timur Tabi timur@freescale.com
MAINTAINERS | 1 + Makefile | 16 ++- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 105 ++-------- include/configs/MPC8349ITX.h | 463 ++++++++++++++++------------------------- include/mpc83xx.h | 41 ++++
Timur, this looks good except new boards should at least have their own config file; I have a problem with multiple ifdef CONFIG_MPC8349ITX checks in MPC8349ITX.h.
Also, there are unrelated modifications in this patch - please respin.
Thanks,
Kim
Kim Phillips wrote:
On Wed, 17 Jan 2007 09:09:45 -0600 timur@freescale.com wrote:
From: Timur Tabi timur@freescale.com
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX.
Signed-off-by: Timur Tabi timur@freescale.com
MAINTAINERS | 1 + Makefile | 16 ++- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 105 ++-------- include/configs/MPC8349ITX.h | 463 ++++++++++++++++------------------------- include/mpc83xx.h | 41 ++++
Timur, this looks good except new boards should at least have their own config file; I have a problem with multiple ifdef CONFIG_MPC8349ITX checks in MPC8349ITX.h.
The ITX and the ITX-GP are basically the same board, except the ITX has a few extra peripherals. It doesn't make sense to have separate config files.
As for the ifdefs, there are only three - one that defines the CF card that only the ITX has, one for the flash sizes, and another for the command prompt. I could technically move these into the Makefile, eliminating any ifdefs from the header file. Do you want me to do that?
Also, there are unrelated modifications in this patch - please respin.
Could you be more specific? The cleanups to the header files and the source files are for the purpose of improving the ability of the same code to support two boards.
On Jan 25, 2007, at 10:41 PM, Timur Tabi wrote:
Kim Phillips wrote:
On Wed, 17 Jan 2007 09:09:45 -0600 timur@freescale.com wrote:
From: Timur Tabi timur@freescale.com
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX.
Signed-off-by: Timur Tabi timur@freescale.com
MAINTAINERS | 1 + Makefile | 16 ++- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 105 ++-------- include/configs/MPC8349ITX.h | 463 +++++++++++++++ +------------------------- include/mpc83xx.h | 41 ++++
Timur, this looks good except new boards should at least have their own config file; I have a problem with multiple ifdef CONFIG_MPC8349ITX checks in MPC8349ITX.h.
The ITX and the ITX-GP are basically the same board, except the ITX has a few extra peripherals. It doesn't make sense to have separate config files.
As for the ifdefs, there are only three - one that defines the CF card that only the ITX has, one for the flash sizes, and another for the command prompt. I could technically move these into the Makefile, eliminating any ifdefs from the header file. Do you want me to do that?
Since they are different physical boards they should have different <config>.h, that rule's been pretty standard in u-boot.
- k
In message BB798853-8000-4747-A6BD-26E5E71AD80B@kernel.crashing.org you wrote:
Since they are different physical boards they should have different <config>.h, that rule's been pretty standard in u-boot.
No, not at all. We have many similar boards share one configuration file - especially in the case of modules that can be used on different carrier boards.
Best regards,
Wolfgang Denk
On Fri, 26 Jan 2007 10:46:54 +0100 Wolfgang Denk wd@denx.de wrote:
In message BB798853-8000-4747-A6BD-26E5E71AD80B@kernel.crashing.org you wrote:
Since they are different physical boards they should have different <config>.h, that rule's been pretty standard in u-boot.
No, not at all. We have many similar boards share one configuration file - especially in the case of modules that can be used on different carrier boards.
I didn't see any that had the same config behaviour as this patch does (ifdeffing itself). In any case, the ITX and ITX-GP do not have any modular properties. Plus, there are more similarly 'fixed' boards coming that are similar, but in different ways, to the ITX and the ITX-GP.
My reluctance is stemmed from the prediction of the growing number of ifdefs in the config file. Perhaps the best thing to do here is have the main config file have a single set of ifdefs for each individual board, and include that board's delta config from a sub-board config file. All common elements remain in the main config file, and if a board define is not matched, #error out.
Kim
Kim Phillips wrote:
On Fri, 26 Jan 2007 10:46:54 +0100 Wolfgang Denk wd@denx.de wrote:
In message BB798853-8000-4747-A6BD-26E5E71AD80B@kernel.crashing.org you wrote:
Since they are different physical boards they should have different <config>.h, that rule's been pretty standard in u-boot.
No, not at all. We have many similar boards share one configuration file - especially in the case of modules that can be used on different carrier boards.
I didn't see any that had the same config behaviour as this patch does (ifdeffing itself).
Some boards solve this problem by specifying the options in the Makefile. However, Wolfgang says he doesn't like this.
My reluctance is stemmed from the prediction of the growing number of ifdefs in the config file. Perhaps the best thing to do here is have the main config file have a single set of ifdefs for each individual board, and include that board's delta config from a sub-board config file. All common elements remain in the main config file, and if a board define is not matched, #error out.
I presume you mean board-specific ifdefs in a config file, and not just any ifdefs. Frankly, I don't think 3 board-specific ifdefs is that many.
Technically speaking, the config file for the ITX will work on the ITX-GP, but you'll have to deal with:
1) A warning stating that flash bank #2 is missing 2) Loading support for compact flash and IDE, and a message saying that IDE times out. 3) A command prompt that says "MPC8349E-mITX" instead of "MPC8349E-mITX-GP"
I could modify the header file to make it somewhat more generic, but I can't completely eliminate "#ifdef CONFIG_MPC8349ITX" unless I move some config stuff to the Makefile, by adding something like this to the make rule:
[if ITX and not ITX-GP] echo "#define CONFIG_COMPACT_FLASH" >> $(obj)include/config.h echo "#define CFG_MAX_FLASH_BANKS 2" >> $(obj)include/config.h echo '#define CFG_PROMPT "MPC8349E-mITX> "' >> $(obj)include/config.h
And then use this code in the config file to handle the flash configuration:
#define CFG_FLASH_SIZE (CFG_MAX_FLASH_BANKS * 8) #define CFG_MAX_FLASH_BANKS (2 + CFG_MAX_FLASH_BANKS) #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
This produces this warning when compiling cfi_flash.c, however:
cfi_flash.c:167: warning: excess elements in array initializer cfi_flash.c:167: warning: (near initialization for 'bank_base')
To fix that, we could modify cfi_flash.c like this:
-static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; +static ulong bank_base[] = CFG_FLASH_BANKS_LIST;
Again, Wolfgang says he doesn't like options in Makefiles, although personally I don't have a problem with that. I just mention the above for purposes of discussion.
In message 45BA3CB3.7020908@freescale.com you wrote:
Some boards solve this problem by specifying the options in the Makefile. However, Wolfgang says he doesn't like this.
It depends. There once was a time, when I thought something like the TQM82xx code was a good thing. Actually it was an improvement over what we had before that. But I've learned a lesson or two, and today I would not accept such a mess again.
Onthe other hand, if you just have to switch between lowboot and highboot configurations, or between configurations with LCD or without, then a bit of configuration selection in the Makefile is IMHO ok. Just don't write pages of code, please.
I presume you mean board-specific ifdefs in a config file, and not just any ifdefs. Frankly, I don't think 3 board-specific ifdefs is that many.
Neither do I. And it's definitely better than having 2 config files which are 98% copy & paste and otherwise just a PITA to keep in sync.
to the Makefile, by adding something like this to the make rule:
[if ITX and not ITX-GP] echo "#define CONFIG_COMPACT_FLASH" >> $(obj)include/config.h echo "#define CFG_MAX_FLASH_BANKS 2" >> $(obj)include/config.h echo '#define CFG_PROMPT "MPC8349E-mITX> "' >> $(obj)include/config.h
No. Please don't write code in the Makefile, just select the right configuration name, and that's it.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
[if ITX and not ITX-GP] echo "#define CONFIG_COMPACT_FLASH" >> $(obj)include/config.h echo "#define CFG_MAX_FLASH_BANKS 2" >> $(obj)include/config.h echo '#define CFG_PROMPT "MPC8349E-mITX> "' >> $(obj)include/config.h
No. Please don't write code in the Makefile, just select the right configuration name, and that's it.
The patch currently does this:
MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @CTYPE=$(subst MPC,,$(@:_config=)); \ echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
Is this bad? Should I have done this instead:
MPC8349ITX_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @echo "#define CONFIG_MPC8349ITX" >> $(obj)include/config.h @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
MPC8349ITX_LOWBOOT_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @echo "#define CONFIG_MPC8349ITX" >> $(obj)include/config.h @echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @echo "#define CONFIG_MPC8349ITXGP" >> $(obj)include/config.h @echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
In message 45BA718E.1070005@freescale.com you wrote:
The patch currently does this:
MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @CTYPE=$(subst MPC,,$(@:_config=)); \ echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
I would not reject such a patch. It looks resonable to me. [You could get rid of the CTYPE thingy which would save one line.]
Is this bad? Should I have done this instead:
No, that would be definitely worse.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
In message 45BA718E.1070005@freescale.com you wrote:
The patch currently does this:
MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @CTYPE=$(subst MPC,,$(@:_config=)); \ echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
I would not reject such a patch. It looks resonable to me. [You could get rid of the CTYPE thingy which would save one line.]
How else would I do this, then?
echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h ^^^^^^^^^
In message 45BA777B.303@freescale.com you wrote:
Wolfgang Denk wrote:
In message 45BA718E.1070005@freescale.com you wrote:
The patch currently does this:
MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/mpc8349itx @CTYPE=$(subst MPC,,$(@:_config=)); \ echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx
I would not reject such a patch. It looks resonable to me. [You could get rid of the CTYPE thingy which would save one line.]
How else would I do this, then?
echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h ^^^^^^^^^
echo "#define CONFIG_$(@:_config=)" >> $(obj)include/config.h
?
I mean, you define a variable which is just used once, so insert the value directly. And then, why strip the "MPC" part just to add it again?
Best regards,
Wolfgang Denk
Hi Timur,
On Friday 26 January 2007 18:38, Timur Tabi wrote:
I presume you mean board-specific ifdefs in a config file, and not just any ifdefs. Frankly, I don't think 3 board-specific ifdefs is that many.
Technically speaking, the config file for the ITX will work on the ITX-GP, but you'll have to deal with:
- A warning stating that flash bank #2 is missing
Please check the CFG_FLASH_QUIET_TEST config option. The README states:
- CFG_FLASH_QUIET_TEST If this option is defined, the common CFI flash doesn't print it's warning upon not recognized FLASH banks. This is useful, if some of the configured banks are only optionally available.
Best regards, Stefan
In message 20070126111917.50cf05ed.kim.phillips@freescale.com you wrote:
My reluctance is stemmed from the prediction of the growing number of ifdefs in the config file. Perhaps the best thing to do here is have the main config file have a single set of ifdefs for each individual board, and include that board's delta config from a sub-board config file. All common elements remain in the main config file, and if a board define is not matched, #error out.
Distributing the necessary configuration information for one board over several files does not improve anything. On contrary, it just makes it more difficult to get an overview of which configuration is doing what.
Best regards,
Wolfgang Denk
In message 45B9868B.5000709@freescale.com you wrote:
The ITX and the ITX-GP are basically the same board, except the ITX has a few extra peripherals. It doesn't make sense to have separate config files.
Agreed.
As for the ifdefs, there are only three - one that defines the CF card that only the ITX has, one for the flash sizes, and another for the
Why do you need to define the flash sizes? They should get auto-detected.
command prompt. I could technically move these into the Makefile, eliminating any ifdefs from the header file. Do you want me to do that?
No, please keep the Makefile simple.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
As for the ifdefs, there are only three - one that defines the CF card that only the ITX has, one for the flash sizes, and another for the
Why do you need to define the flash sizes? They should get auto-detected.
The ITX has two 8MB flash chips, whereas the ITX-GP has one. My understanding is that U-Boot can't find the 2nd flash chip unless it's told about it via CFG_FLASH_BANKS_LIST.
In message 45BA1408.7060602@freescale.com you wrote:
Why do you need to define the flash sizes? They should get auto-detected.
The ITX has two 8MB flash chips, whereas the ITX-GP has one. My understanding is that U-Boot can't find the 2nd flash chip unless it's told about it via CFG_FLASH_BANKS_LIST.
Configure to have always 2 banks then; one board will then report one bank missing.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
Configure to have always 2 banks then; one board will then report one bank missing.
I'll try it, but does it really matter? I already need to differentiate between the boards because the ITX-GP is lowboot and the ITX is highboot, and so the HRCWs are different.
Besides, isn't it bad trying to do I/O from memory that doesn't exist? Won't it cause an exception?
In message 45BA1845.7080908@freescale.com you wrote:
I'll try it, but does it really matter? I already need to differentiate between the boards because the ITX-GP is lowboot and the ITX is highboot, and so the HRCWs are different.
No, it does not really matter then. Also, my concern was more about your statement to have different flash _sizes_ - these should get autoadjusted. Number of banks is a bit different.
Besides, isn't it bad trying to do I/O from memory that doesn't exist? Won't it cause an exception?
If the memory is mapped, no.
Best regards,
Wolfgang Denk
participants (6)
-
Kim Phillips -
Kumar Gala -
Stefan Roese -
Timur Tabi -
timur＠freescale.com
-
Wolfgang Denk