Drop in favour of dts/upstream. This is just the clock headers.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 -------- include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 ---- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 169 ----------- include/dt-bindings/clock/qcom,gcc-msm8916.h | 179 ----------- include/dt-bindings/clock/qcom,gcc-msm8996.h | 362 ----------------------- include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 ----------- include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 --------------- include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 -- include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 - include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 ------------------ include/dt-bindings/clock/qcom,rpmcc.h | 174 ----------- include/dt-bindings/clock/qcom,rpmh.h | 37 --- include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 - include/dt-bindings/clock/qcom,videocc-sdm845.h | 35 --- 14 files changed, 1903 deletions(-)

diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h deleted file mode 100644 index 4f7a2d2320bf..000000000000 --- a/include/dt-bindings/clock/qcom,camcc-sdm845.h +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H - -/* CAM_CC clock registers */ -#define CAM_CC_BPS_AHB_CLK 0 -#define CAM_CC_BPS_AREG_CLK 1 -#define CAM_CC_BPS_AXI_CLK 2 -#define CAM_CC_BPS_CLK 3 -#define CAM_CC_BPS_CLK_SRC 4 -#define CAM_CC_CAMNOC_ATB_CLK 5 -#define CAM_CC_CAMNOC_AXI_CLK 6 -#define CAM_CC_CCI_CLK 7 -#define CAM_CC_CCI_CLK_SRC 8 -#define CAM_CC_CPAS_AHB_CLK 9 -#define CAM_CC_CPHY_RX_CLK_SRC 10 -#define CAM_CC_CSI0PHYTIMER_CLK 11 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 -#define CAM_CC_CSI1PHYTIMER_CLK 13 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 -#define CAM_CC_CSI2PHYTIMER_CLK 15 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 -#define CAM_CC_CSI3PHYTIMER_CLK 17 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 -#define CAM_CC_CSIPHY0_CLK 19 -#define CAM_CC_CSIPHY1_CLK 20 -#define CAM_CC_CSIPHY2_CLK 21 -#define CAM_CC_CSIPHY3_CLK 22 -#define CAM_CC_FAST_AHB_CLK_SRC 23 -#define CAM_CC_FD_CORE_CLK 24 -#define CAM_CC_FD_CORE_CLK_SRC 25 -#define CAM_CC_FD_CORE_UAR_CLK 26 -#define CAM_CC_ICP_APB_CLK 27 -#define CAM_CC_ICP_ATB_CLK 28 -#define CAM_CC_ICP_CLK 29 -#define CAM_CC_ICP_CLK_SRC 30 -#define CAM_CC_ICP_CTI_CLK 31 -#define CAM_CC_ICP_TS_CLK 32 -#define CAM_CC_IFE_0_AXI_CLK 33 -#define CAM_CC_IFE_0_CLK 34 -#define CAM_CC_IFE_0_CLK_SRC 35 -#define CAM_CC_IFE_0_CPHY_RX_CLK 36 -#define CAM_CC_IFE_0_CSID_CLK 37 -#define CAM_CC_IFE_0_CSID_CLK_SRC 38 -#define CAM_CC_IFE_0_DSP_CLK 39 -#define CAM_CC_IFE_1_AXI_CLK 40 -#define CAM_CC_IFE_1_CLK 41 -#define CAM_CC_IFE_1_CLK_SRC 42 -#define CAM_CC_IFE_1_CPHY_RX_CLK 43 -#define CAM_CC_IFE_1_CSID_CLK 44 -#define CAM_CC_IFE_1_CSID_CLK_SRC 45 -#define CAM_CC_IFE_1_DSP_CLK 46 -#define CAM_CC_IFE_LITE_CLK 47 -#define CAM_CC_IFE_LITE_CLK_SRC 48 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 -#define CAM_CC_IFE_LITE_CSID_CLK 50 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 -#define CAM_CC_IPE_0_AHB_CLK 52 -#define CAM_CC_IPE_0_AREG_CLK 53 -#define CAM_CC_IPE_0_AXI_CLK 54 -#define CAM_CC_IPE_0_CLK 55 -#define CAM_CC_IPE_0_CLK_SRC 56 -#define CAM_CC_IPE_1_AHB_CLK 57 -#define CAM_CC_IPE_1_AREG_CLK 58 -#define CAM_CC_IPE_1_AXI_CLK 59 -#define CAM_CC_IPE_1_CLK 60 -#define CAM_CC_IPE_1_CLK_SRC 61 -#define CAM_CC_JPEG_CLK 62 -#define CAM_CC_JPEG_CLK_SRC 63 -#define CAM_CC_LRME_CLK 64 -#define CAM_CC_LRME_CLK_SRC 65 -#define CAM_CC_MCLK0_CLK 66 -#define CAM_CC_MCLK0_CLK_SRC 67 -#define CAM_CC_MCLK1_CLK 68 -#define CAM_CC_MCLK1_CLK_SRC 69 -#define CAM_CC_MCLK2_CLK 70 -#define CAM_CC_MCLK2_CLK_SRC 71 -#define CAM_CC_MCLK3_CLK 72 -#define CAM_CC_MCLK3_CLK_SRC 73 -#define CAM_CC_PLL0 74 -#define CAM_CC_PLL0_OUT_EVEN 75 -#define CAM_CC_PLL1 76 -#define CAM_CC_PLL1_OUT_EVEN 77 -#define CAM_CC_PLL2 78 -#define CAM_CC_PLL2_OUT_EVEN 79 -#define CAM_CC_PLL3 80 -#define CAM_CC_PLL3_OUT_EVEN 81 -#define CAM_CC_SLOW_AHB_CLK_SRC 82 -#define CAM_CC_SOC_AHB_CLK 83 -#define CAM_CC_SYS_TMR_CLK 84 - -/* CAM_CC Resets */ -#define TITAN_CAM_CC_CCI_BCR 0 -#define TITAN_CAM_CC_CPAS_BCR 1 -#define TITAN_CAM_CC_CSI0PHY_BCR 2 -#define TITAN_CAM_CC_CSI1PHY_BCR 3 -#define TITAN_CAM_CC_CSI2PHY_BCR 4 -#define TITAN_CAM_CC_MCLK0_BCR 5 -#define TITAN_CAM_CC_MCLK1_BCR 6 -#define TITAN_CAM_CC_MCLK2_BCR 7 -#define TITAN_CAM_CC_MCLK3_BCR 8 -#define TITAN_CAM_CC_TITAN_TOP_BCR 9 - -/* CAM_CC GDSCRs */ -#define BPS_GDSC 0 -#define IPE_0_GDSC 1 -#define IPE_1_GDSC 2 -#define IFE_0_GDSC 3 -#define IFE_1_GDSC 4 -#define TITAN_TOP_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h deleted file mode 100644 index 4016fd1d5b46..000000000000 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H - -/* DISP_CC clock registers */ -#define DISP_CC_MDSS_AHB_CLK 0 -#define DISP_CC_MDSS_AXI_CLK 1 -#define DISP_CC_MDSS_BYTE0_CLK 2 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 -#define DISP_CC_MDSS_BYTE1_CLK 5 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 -#define DISP_CC_MDSS_ESC0_CLK 8 -#define DISP_CC_MDSS_ESC0_CLK_SRC 9 -#define DISP_CC_MDSS_ESC1_CLK 10 -#define DISP_CC_MDSS_ESC1_CLK_SRC 11 -#define DISP_CC_MDSS_MDP_CLK 12 -#define DISP_CC_MDSS_MDP_CLK_SRC 13 -#define DISP_CC_MDSS_MDP_LUT_CLK 14 -#define DISP_CC_MDSS_PCLK0_CLK 15 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 -#define DISP_CC_MDSS_PCLK1_CLK 17 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 -#define DISP_CC_MDSS_ROT_CLK 19 -#define DISP_CC_MDSS_ROT_CLK_SRC 20 -#define DISP_CC_MDSS_RSCC_AHB_CLK 21 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 -#define DISP_CC_MDSS_VSYNC_CLK 23 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 -#define DISP_CC_PLL0 25 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 -#define DISP_CC_MDSS_DP_AUX_CLK 28 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 -#define DISP_CC_MDSS_DP_LINK_CLK 32 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 -#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 -#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 -#define DISP_CC_MDSS_DP_PIXEL_CLK 37 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 - -/* DISP_CC Reset */ -#define DISP_CC_MDSS_RSCC_BCR 0 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h deleted file mode 100644 index 7e8a7be6dcda..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_CLK_IPQ4019_H__ -#define __QCOM_CLK_IPQ4019_H__ - -#define GCC_DUMMY_CLK 0 -#define AUDIO_CLK_SRC 1 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 -#define BLSP1_UART1_APPS_CLK_SRC 6 -#define BLSP1_UART2_APPS_CLK_SRC 7 -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 -#define GCC_APPS_CLK_SRC 9 -#define GCC_APPS_AHB_CLK_SRC 10 -#define GP1_CLK_SRC 11 -#define GP2_CLK_SRC 12 -#define GP3_CLK_SRC 13 -#define SDCC1_APPS_CLK_SRC 14 -#define FEPHY_125M_DLY_CLK_SRC 15 -#define WCSS2G_CLK_SRC 16 -#define WCSS5G_CLK_SRC 17 -#define GCC_APSS_AHB_CLK 18 -#define GCC_AUDIO_AHB_CLK 19 -#define GCC_AUDIO_PWM_CLK 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 -#define GCC_BLSP1_UART1_APPS_CLK 26 -#define GCC_BLSP1_UART2_APPS_CLK 27 -#define GCC_DCD_XO_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP2_CLK 30 -#define GCC_GP3_CLK 31 -#define GCC_BOOT_ROM_AHB_CLK 32 -#define GCC_CRYPTO_AHB_CLK 33 -#define GCC_CRYPTO_AXI_CLK 34 -#define GCC_CRYPTO_CLK 35 -#define GCC_ESS_CLK 36 -#define GCC_IMEM_AXI_CLK 37 -#define GCC_IMEM_CFG_AHB_CLK 38 -#define GCC_PCIE_AHB_CLK 39 -#define GCC_PCIE_AXI_M_CLK 40 -#define GCC_PCIE_AXI_S_CLK 41 -#define GCC_PCNOC_AHB_CLK 42 -#define GCC_PRNG_AHB_CLK 43 -#define GCC_QPIC_AHB_CLK 44 -#define GCC_QPIC_CLK 45 -#define GCC_SDCC1_AHB_CLK 46 -#define GCC_SDCC1_APPS_CLK 47 -#define GCC_SNOC_PCNOC_AHB_CLK 48 -#define GCC_SYS_NOC_125M_CLK 49 -#define GCC_SYS_NOC_AXI_CLK 50 -#define GCC_TCSR_AHB_CLK 51 -#define GCC_TLMM_AHB_CLK 52 -#define GCC_USB2_MASTER_CLK 53 -#define GCC_USB2_SLEEP_CLK 54 -#define GCC_USB2_MOCK_UTMI_CLK 55 -#define GCC_USB3_MASTER_CLK 56 -#define GCC_USB3_SLEEP_CLK 57 -#define GCC_USB3_MOCK_UTMI_CLK 58 -#define GCC_WCSS2G_CLK 59 -#define GCC_WCSS2G_REF_CLK 60 -#define GCC_WCSS2G_RTC_CLK 61 -#define GCC_WCSS5G_CLK 62 -#define GCC_WCSS5G_REF_CLK 63 -#define GCC_WCSS5G_RTC_CLK 64 -#define GCC_APSS_DDRPLL_VCO 65 -#define GCC_SDCC_PLLDIV_CLK 66 -#define GCC_FEPLL_VCO 67 -#define GCC_FEPLL125_CLK 68 -#define GCC_FEPLL125DLY_CLK 69 -#define GCC_FEPLL200_CLK 70 -#define GCC_FEPLL500_CLK 71 -#define GCC_FEPLL_WCSS2G_CLK 72 -#define GCC_FEPLL_WCSS5G_CLK 73 -#define GCC_APSS_CPU_PLLDIV_CLK 74 -#define GCC_PCNOC_AHB_CLK_SRC 75 - -#define WIFI0_CPU_INIT_RESET 0 -#define WIFI0_RADIO_SRIF_RESET 1 -#define WIFI0_RADIO_WARM_RESET 2 -#define WIFI0_RADIO_COLD_RESET 3 -#define WIFI0_CORE_WARM_RESET 4 -#define WIFI0_CORE_COLD_RESET 5 -#define WIFI1_CPU_INIT_RESET 6 -#define WIFI1_RADIO_SRIF_RESET 7 -#define WIFI1_RADIO_WARM_RESET 8 -#define WIFI1_RADIO_COLD_RESET 9 -#define WIFI1_CORE_WARM_RESET 10 -#define WIFI1_CORE_COLD_RESET 11 -#define USB3_UNIPHY_PHY_ARES 12 -#define USB3_HSPHY_POR_ARES 13 -#define USB3_HSPHY_S_ARES 14 -#define USB2_HSPHY_POR_ARES 15 -#define USB2_HSPHY_S_ARES 16 -#define PCIE_PHY_AHB_ARES 17 -#define PCIE_AHB_ARES 18 -#define PCIE_PWR_ARES 19 -#define PCIE_PIPE_STICKY_ARES 20 -#define PCIE_AXI_M_STICKY_ARES 21 -#define PCIE_PHY_ARES 22 -#define PCIE_PARF_XPU_ARES 23 -#define PCIE_AXI_S_XPU_ARES 24 -#define PCIE_AXI_M_VMIDMT_ARES 25 -#define PCIE_PIPE_ARES 26 -#define PCIE_AXI_S_ARES 27 -#define PCIE_AXI_M_ARES 28 -#define ESS_RESET 29 -#define GCC_BLSP1_BCR 30 -#define GCC_BLSP1_QUP1_BCR 31 -#define GCC_BLSP1_UART1_BCR 32 -#define GCC_BLSP1_QUP2_BCR 33 -#define GCC_BLSP1_UART2_BCR 34 -#define GCC_BIMC_BCR 35 -#define GCC_TLMM_BCR 36 -#define GCC_IMEM_BCR 37 -#define GCC_ESS_BCR 38 -#define GCC_PRNG_BCR 39 -#define GCC_BOOT_ROM_BCR 40 -#define GCC_CRYPTO_BCR 41 -#define GCC_SDCC1_BCR 42 -#define GCC_SEC_CTRL_BCR 43 -#define GCC_AUDIO_BCR 44 -#define GCC_QPIC_BCR 45 -#define GCC_PCIE_BCR 46 -#define GCC_USB2_BCR 47 -#define GCC_USB2_PHY_BCR 48 -#define GCC_USB3_BCR 49 -#define GCC_USB3_PHY_BCR 50 -#define GCC_SYSTEM_NOC_BCR 51 -#define GCC_PCNOC_BCR 52 -#define GCC_DCD_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_TCSR_BCR 68 -#define GCC_QDSS_BCR 69 -#define GCC_MPM_BCR 70 -#define GCC_SPDM_BCR 71 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h deleted file mode 100644 index 563034406184..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H -#define _DT_BINDINGS_CLK_MSM_GCC_8916_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define BIMC_PLL 2 -#define BIMC_PLL_VOTE 3 -#define GPLL1 4 -#define GPLL1_VOTE 5 -#define GPLL2 6 -#define GPLL2_VOTE 7 -#define PCNOC_BFDCD_CLK_SRC 8 -#define SYSTEM_NOC_BFDCD_CLK_SRC 9 -#define CAMSS_AHB_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI1_CLK_SRC 13 -#define GFX3D_CLK_SRC 14 -#define VFE0_CLK_SRC 15 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 -#define BLSP1_UART1_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define CCI_CLK_SRC 30 -#define CAMSS_GP0_CLK_SRC 31 -#define CAMSS_GP1_CLK_SRC 32 -#define JPEG0_CLK_SRC 33 -#define MCLK0_CLK_SRC 34 -#define MCLK1_CLK_SRC 35 -#define CSI0PHYTIMER_CLK_SRC 36 -#define CSI1PHYTIMER_CLK_SRC 37 -#define CPP_CLK_SRC 38 -#define CRYPTO_CLK_SRC 39 -#define GP1_CLK_SRC 40 -#define GP2_CLK_SRC 41 -#define GP3_CLK_SRC 42 -#define BYTE0_CLK_SRC 43 -#define ESC0_CLK_SRC 44 -#define MDP_CLK_SRC 45 -#define PCLK0_CLK_SRC 46 -#define VSYNC_CLK_SRC 47 -#define PDM2_CLK_SRC 48 -#define SDCC1_APPS_CLK_SRC 49 -#define SDCC2_APPS_CLK_SRC 50 -#define APSS_TCU_CLK_SRC 51 -#define USB_HS_SYSTEM_CLK_SRC 52 -#define VCODEC0_CLK_SRC 53 -#define GCC_BLSP1_AHB_CLK 54 -#define GCC_BLSP1_SLEEP_CLK 55 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 -#define GCC_BLSP1_UART1_APPS_CLK 68 -#define GCC_BLSP1_UART2_APPS_CLK 69 -#define GCC_BOOT_ROM_AHB_CLK 70 -#define GCC_CAMSS_CCI_AHB_CLK 71 -#define GCC_CAMSS_CCI_CLK 72 -#define GCC_CAMSS_CSI0_AHB_CLK 73 -#define GCC_CAMSS_CSI0_CLK 74 -#define GCC_CAMSS_CSI0PHY_CLK 75 -#define GCC_CAMSS_CSI0PIX_CLK 76 -#define GCC_CAMSS_CSI0RDI_CLK 77 -#define GCC_CAMSS_CSI1_AHB_CLK 78 -#define GCC_CAMSS_CSI1_CLK 79 -#define GCC_CAMSS_CSI1PHY_CLK 80 -#define GCC_CAMSS_CSI1PIX_CLK 81 -#define GCC_CAMSS_CSI1RDI_CLK 82 -#define GCC_CAMSS_CSI_VFE0_CLK 83 -#define GCC_CAMSS_GP0_CLK 84 -#define GCC_CAMSS_GP1_CLK 85 -#define GCC_CAMSS_ISPIF_AHB_CLK 86 -#define GCC_CAMSS_JPEG0_CLK 87 -#define GCC_CAMSS_JPEG_AHB_CLK 88 -#define GCC_CAMSS_JPEG_AXI_CLK 89 -#define GCC_CAMSS_MCLK0_CLK 90 -#define GCC_CAMSS_MCLK1_CLK 91 -#define GCC_CAMSS_MICRO_AHB_CLK 92 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 -#define GCC_CAMSS_AHB_CLK 95 -#define GCC_CAMSS_TOP_AHB_CLK 96 -#define GCC_CAMSS_CPP_AHB_CLK 97 -#define GCC_CAMSS_CPP_CLK 98 -#define GCC_CAMSS_VFE0_CLK 99 -#define GCC_CAMSS_VFE_AHB_CLK 100 -#define GCC_CAMSS_VFE_AXI_CLK 101 -#define GCC_CRYPTO_AHB_CLK 102 -#define GCC_CRYPTO_AXI_CLK 103 -#define GCC_CRYPTO_CLK 104 -#define GCC_OXILI_GMEM_CLK 105 -#define GCC_GP1_CLK 106 -#define GCC_GP2_CLK 107 -#define GCC_GP3_CLK 108 -#define GCC_MDSS_AHB_CLK 109 -#define GCC_MDSS_AXI_CLK 110 -#define GCC_MDSS_BYTE0_CLK 111 -#define GCC_MDSS_ESC0_CLK 112 -#define GCC_MDSS_MDP_CLK 113 -#define GCC_MDSS_PCLK0_CLK 114 -#define GCC_MDSS_VSYNC_CLK 115 -#define GCC_MSS_CFG_AHB_CLK 116 -#define GCC_OXILI_AHB_CLK 117 -#define GCC_OXILI_GFX3D_CLK 118 -#define GCC_PDM2_CLK 119 -#define GCC_PDM_AHB_CLK 120 -#define GCC_PRNG_AHB_CLK 121 -#define GCC_SDCC1_AHB_CLK 122 -#define GCC_SDCC1_APPS_CLK 123 -#define GCC_SDCC2_AHB_CLK 124 -#define GCC_SDCC2_APPS_CLK 125 -#define GCC_GTCU_AHB_CLK 126 -#define GCC_JPEG_TBU_CLK 127 -#define GCC_MDP_TBU_CLK 128 -#define GCC_SMMU_CFG_CLK 129 -#define GCC_VENUS_TBU_CLK 130 -#define GCC_VFE_TBU_CLK 131 -#define GCC_USB2A_PHY_SLEEP_CLK 132 -#define GCC_USB_HS_AHB_CLK 133 -#define GCC_USB_HS_SYSTEM_CLK 134 -#define GCC_VENUS0_AHB_CLK 135 -#define GCC_VENUS0_AXI_CLK 136 -#define GCC_VENUS0_VCODEC0_CLK 137 -#define BIMC_DDR_CLK_SRC 138 -#define GCC_APSS_TCU_CLK 139 -#define GCC_GFX_TCU_CLK 140 -#define BIMC_GPU_CLK_SRC 141 -#define GCC_BIMC_GFX_CLK 142 -#define GCC_BIMC_GPU_CLK 143 -#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 -#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 -#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 -#define ULTAUDIO_XO_CLK_SRC 147 -#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 -#define CODEC_DIGCODEC_CLK_SRC 149 -#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 -#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 -#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 -#define GCC_ULTAUDIO_STC_XO_CLK 153 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 -#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 -#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 -#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 -#define GCC_CODEC_DIGCODEC_CLK 159 -#define GCC_MSS_Q6_BIMC_AXI_CLK 160 - -/* Indexes for GDSCs */ -#define BIMC_GDSC 0 -#define VENUS_GDSC 1 -#define MDSS_GDSC 2 -#define JPEG_GDSC 3 -#define VFE_GDSC 4 -#define OXILI_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h deleted file mode 100644 index ddfd6fd73081..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define _DT_BINDINGS_CLK_MSM_GCC_8996_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -/* U-Boot: KConfig check in CI erroneously picks this up, it's unused - * anyway so comment it out for now - */ -//#define CONFIG _NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 -#define GCC_EDP_CLKREF_CLK 221 -#define GCC_MSS_CFG_AHB_CLK 222 -#define GCC_MSS_Q6_BIMC_AXI_CLK 223 -#define GCC_MSS_SNOC_AXI_CLK 224 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 -#define GCC_DCC_AHB_CLK 226 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 -#define GCC_MMSS_GPLL0_DIV_CLK 228 -#define GCC_MSS_GPLL0_DIV_CLK 229 - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PIMEM_BCR 5 -#define GCC_QDSS_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_20_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_QUSB2PHY_SEC_BCR 10 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_BIMC_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 -#define GCC_APB2JTAG_BCR 76 -#define GCC_RBCPR_CX_BCR 77 -#define GCC_RBCPR_MX_BCR 78 -#define GCC_PCIE_0_BCR 79 -#define GCC_PCIE_0_PHY_BCR 80 -#define GCC_PCIE_1_BCR 81 -#define GCC_PCIE_1_PHY_BCR 82 -#define GCC_PCIE_2_BCR 83 -#define GCC_PCIE_2_PHY_BCR 84 -#define GCC_PCIE_PHY_BCR 85 -#define GCC_DCD_BCR 86 -#define GCC_OBT_ODT_BCR 87 -#define GCC_UFS_BCR 88 -#define GCC_SSC_BCR 89 -#define GCC_VS_BCR 90 -#define GCC_AGGRE0_NOC_BCR 91 -#define GCC_AGGRE1_NOC_BCR 92 -#define GCC_AGGRE2_NOC_BCR 93 -#define GCC_DCC_BCR 94 -#define GCC_IPA_BCR 95 -#define GCC_QSPI_BCR 96 -#define GCC_SKL_BCR 97 -#define GCC_MSMPU_BCR 98 -#define GCC_MSS_Q6_BCR 99 -#define GCC_QREFS_VBG_CAL_BCR 100 -#define GCC_PCIE_PHY_COM_BCR 101 -#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 -#define GCC_USB3_PHY_BCR 103 -#define GCC_USB3PHY_PHY_BCR 104 -#define GCC_MSS_RESTART 105 - - -/* Indexes for GDSCs */ -#define AGGRE0_NOC_GDSC 0 -#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 -#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 -#define HLOS1_VOTE_LPASS_CORE_GDSC 3 -#define USB30_GDSC 4 -#define PCIE0_GDSC 5 -#define PCIE1_GDSC 6 -#define PCIE2_GDSC 7 -#define UFS_GDSC 8 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h deleted file mode 100644 index bc3051543347..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H - -#define GCC_APSS_AHB_CLK_SRC 0 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 -#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 -#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 -#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 -#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 -#define GCC_BYTE0_CLK_SRC 18 -#define GCC_EMAC_CLK_SRC 19 -#define GCC_EMAC_PTP_CLK_SRC 20 -#define GCC_ESC0_CLK_SRC 21 -#define GCC_APSS_AHB_CLK 22 -#define GCC_APSS_AXI_CLK 23 -#define GCC_BIMC_APSS_AXI_CLK 24 -#define GCC_BIMC_GFX_CLK 25 -#define GCC_BIMC_MDSS_CLK 26 -#define GCC_BLSP1_AHB_CLK 27 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 -#define GCC_BLSP1_UART0_APPS_CLK 38 -#define GCC_BLSP1_UART1_APPS_CLK 39 -#define GCC_BLSP1_UART2_APPS_CLK 40 -#define GCC_BLSP1_UART3_APPS_CLK 41 -#define GCC_BLSP2_AHB_CLK 42 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART0_APPS_CLK 45 -#define GCC_BOOT_ROM_AHB_CLK 46 -#define GCC_DCC_CLK 47 -#define GCC_GENI_IR_H_CLK 48 -#define GCC_ETH_AXI_CLK 49 -#define GCC_ETH_PTP_CLK 50 -#define GCC_ETH_RGMII_CLK 51 -#define GCC_ETH_SLAVE_AHB_CLK 52 -#define GCC_GENI_IR_S_CLK 53 -#define GCC_GP1_CLK 54 -#define GCC_GP2_CLK 55 -#define GCC_GP3_CLK 56 -#define GCC_MDSS_AHB_CLK 57 -#define GCC_MDSS_AXI_CLK 58 -#define GCC_MDSS_BYTE0_CLK 59 -#define GCC_MDSS_ESC0_CLK 60 -#define GCC_MDSS_HDMI_APP_CLK 61 -#define GCC_MDSS_HDMI_PCLK_CLK 62 -#define GCC_MDSS_MDP_CLK 63 -#define GCC_MDSS_PCLK0_CLK 64 -#define GCC_MDSS_VSYNC_CLK 65 -#define GCC_OXILI_AHB_CLK 66 -#define GCC_OXILI_GFX3D_CLK 67 -#define GCC_PCIE_0_AUX_CLK 68 -#define GCC_PCIE_0_CFG_AHB_CLK 69 -#define GCC_PCIE_0_MSTR_AXI_CLK 70 -#define GCC_PCIE_0_PIPE_CLK 71 -#define GCC_PCIE_0_SLV_AXI_CLK 72 -#define GCC_PCNOC_USB2_CLK 73 -#define GCC_PCNOC_USB3_CLK 74 -#define GCC_PDM2_CLK 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_VSYNC_CLK_SRC 77 -#define GCC_PRNG_AHB_CLK 78 -#define GCC_PWM0_XO512_CLK 79 -#define GCC_PWM1_XO512_CLK 80 -#define GCC_PWM2_XO512_CLK 81 -#define GCC_SDCC1_AHB_CLK 82 -#define GCC_SDCC1_APPS_CLK 83 -#define GCC_SDCC1_ICE_CORE_CLK 84 -#define GCC_SDCC2_AHB_CLK 85 -#define GCC_SDCC2_APPS_CLK 86 -#define GCC_SYS_NOC_USB3_CLK 87 -#define GCC_USB20_MOCK_UTMI_CLK 88 -#define GCC_USB2A_PHY_SLEEP_CLK 89 -#define GCC_USB30_MASTER_CLK 90 -#define GCC_USB30_MOCK_UTMI_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB3_PHY_AUX_CLK 93 -#define GCC_USB3_PHY_PIPE_CLK 94 -#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 -#define GCC_USB_HS_SYSTEM_CLK 96 -#define GCC_GFX3D_CLK_SRC 97 -#define GCC_GP1_CLK_SRC 98 -#define GCC_GP2_CLK_SRC 99 -#define GCC_GP3_CLK_SRC 100 -#define GCC_GPLL0_OUT_MAIN 101 -#define GCC_GPLL1_OUT_MAIN 102 -#define GCC_GPLL3_OUT_MAIN 103 -#define GCC_GPLL4_OUT_MAIN 104 -#define GCC_HDMI_APP_CLK_SRC 105 -#define GCC_HDMI_PCLK_CLK_SRC 106 -#define GCC_MDP_CLK_SRC 107 -#define GCC_PCIE_0_AUX_CLK_SRC 108 -#define GCC_PCIE_0_PIPE_CLK_SRC 109 -#define GCC_PCLK0_CLK_SRC 110 -#define GCC_PDM2_CLK_SRC 111 -#define GCC_SDCC1_APPS_CLK_SRC 112 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 -#define GCC_SDCC2_APPS_CLK_SRC 114 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 -#define GCC_USB30_MASTER_CLK_SRC 116 -#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 -#define GCC_USB3_PHY_AUX_CLK_SRC 118 -#define GCC_USB_HS_SYSTEM_CLK_SRC 119 -#define GCC_GPLL0_AO_CLK_SRC 120 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 -#define GCC_GPLL0_AO_OUT_MAIN 123 -#define GCC_GPLL0_SLEEP_CLK_SRC 124 -#define GCC_GPLL6 125 -#define GCC_GPLL6_OUT_AUX 126 -#define GCC_MDSS_MDP_VOTE_CLK 127 -#define GCC_MDSS_ROTATOR_VOTE_CLK 128 -#define GCC_BIMC_GPU_CLK 129 -#define GCC_GTCU_AHB_CLK 130 -#define GCC_GFX_TCU_CLK 131 -#define GCC_GFX_TBU_CLK 132 -#define GCC_SMMU_CFG_CLK 133 -#define GCC_APSS_TCU_CLK 134 -#define GCC_CRYPTO_AHB_CLK 135 -#define GCC_CRYPTO_AXI_CLK 136 -#define GCC_CRYPTO_CLK 137 -#define GCC_MDP_TBU_CLK 138 -#define GCC_QDSS_DAP_CLK 139 -#define GCC_DCC_XO_CLK 140 -#define GCC_WCSS_Q6_AHB_CLK 141 -#define GCC_WCSS_Q6_AXIM_CLK 142 -#define GCC_CDSP_CFG_AHB_CLK 143 -#define GCC_BIMC_CDSP_CLK 144 -#define GCC_CDSP_TBU_CLK 145 -#define GCC_CDSP_BIMC_CLK_SRC 146 - -#define GCC_GENI_IR_BCR 0 -#define GCC_USB_HS_BCR 1 -#define GCC_USB2_HS_PHY_ONLY_BCR 2 -#define GCC_QUSB2_PHY_BCR 3 -#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 -#define GCC_USB2A_PHY_BCR 5 -#define GCC_USB3_PHY_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB3PHY_PHY_BCR 8 -#define GCC_PCIE_0_BCR 9 -#define GCC_PCIE_0_PHY_BCR 10 -#define GCC_PCIE_0_LINK_DOWN_BCR 11 -#define GCC_PCIEPHY_0_PHY_BCR 12 -#define GCC_EMAC_BCR 13 -#define GCC_CDSP_RESTART 14 -#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 -#define GCC_PCIE_0_AHB_ARES 16 -#define GCC_PCIE_0_AXI_SLAVE_ARES 17 -#define GCC_PCIE_0_AXI_MASTER_ARES 18 -#define GCC_PCIE_0_CORE_STICKY_ARES 19 -#define GCC_PCIE_0_SLEEP_ARES 20 -#define GCC_PCIE_0_PIPE_ARES 21 -#define GCC_WDSP_RESTART 22 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h deleted file mode 100644 index 968fa65b9c42..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H - -/* GCC clock registers */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 -#define GCC_BOOT_ROM_AHB_CLK 5 -#define GCC_CAMERA_AHB_CLK 6 -#define GCC_CAMERA_AXI_CLK 7 -#define GCC_CAMERA_XO_CLK 8 -#define GCC_CE1_AHB_CLK 9 -#define GCC_CE1_AXI_CLK 10 -#define GCC_CE1_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_RBCPR_CLK 16 -#define GCC_CPUSS_RBCPR_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DISP_AHB_CLK 19 -#define GCC_DISP_AXI_CLK 20 -#define GCC_DISP_GPLL0_CLK_SRC 21 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_GP1_CLK 24 -#define GCC_GP1_CLK_SRC 25 -#define GCC_GP2_CLK 26 -#define GCC_GP2_CLK_SRC 27 -#define GCC_GP3_CLK 28 -#define GCC_GP3_CLK_SRC 29 -#define GCC_GPU_CFG_AHB_CLK 30 -#define GCC_GPU_GPLL0_CLK_SRC 31 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_MSS_AXIS2_CLK 35 -#define GCC_MSS_CFG_AHB_CLK 36 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 -#define GCC_MSS_MFAB_AXIS_CLK 38 -#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 -#define GCC_MSS_SNOC_AXI_CLK 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_1_AUX_CLK 49 -#define GCC_PCIE_1_AUX_CLK_SRC 50 -#define GCC_PCIE_1_CFG_AHB_CLK 51 -#define GCC_PCIE_1_CLKREF_CLK 52 -#define GCC_PCIE_1_MSTR_AXI_CLK 53 -#define GCC_PCIE_1_PIPE_CLK 54 -#define GCC_PCIE_1_SLV_AXI_CLK 55 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 -#define GCC_PCIE_PHY_AUX_CLK 57 -#define GCC_PCIE_PHY_REFGEN_CLK 58 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 -#define GCC_PDM2_CLK 60 -#define GCC_PDM2_CLK_SRC 61 -#define GCC_PDM_AHB_CLK 62 -#define GCC_PDM_XO4_CLK 63 -#define GCC_PRNG_AHB_CLK 64 -#define GCC_QMIP_CAMERA_AHB_CLK 65 -#define GCC_QMIP_DISP_AHB_CLK 66 -#define GCC_QMIP_VIDEO_AHB_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK 68 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S1_CLK 70 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 -#define GCC_QUPV3_WRAP0_S2_CLK 72 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 -#define GCC_QUPV3_WRAP0_S3_CLK 74 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 -#define GCC_QUPV3_WRAP0_S4_CLK 76 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 -#define GCC_QUPV3_WRAP0_S5_CLK 78 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 -#define GCC_QUPV3_WRAP0_S6_CLK 80 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 -#define GCC_QUPV3_WRAP0_S7_CLK 82 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S0_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S1_CLK 86 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S2_CLK 88 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 -#define GCC_QUPV3_WRAP1_S3_CLK 90 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 -#define GCC_QUPV3_WRAP1_S4_CLK 92 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 -#define GCC_QUPV3_WRAP1_S5_CLK 94 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 -#define GCC_QUPV3_WRAP1_S6_CLK 96 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 -#define GCC_QUPV3_WRAP1_S7_CLK 98 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC2_APPS_CLK_SRC 106 -#define GCC_SDCC4_AHB_CLK 107 -#define GCC_SDCC4_APPS_CLK 108 -#define GCC_SDCC4_APPS_CLK_SRC 109 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 -#define GCC_TSIF_AHB_CLK 111 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 -#define GCC_TSIF_REF_CLK 113 -#define GCC_TSIF_REF_CLK_SRC 114 -#define GCC_UFS_CARD_AHB_CLK 115 -#define GCC_UFS_CARD_AXI_CLK 116 -#define GCC_UFS_CARD_AXI_CLK_SRC 117 -#define GCC_UFS_CARD_CLKREF_CLK 118 -#define GCC_UFS_CARD_ICE_CORE_CLK 119 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 -#define GCC_UFS_CARD_PHY_AUX_CLK 121 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_MEM_CLKREF_CLK 128 -#define GCC_UFS_PHY_AHB_CLK 129 -#define GCC_UFS_PHY_AXI_CLK 130 -#define GCC_UFS_PHY_AXI_CLK_SRC 131 -#define GCC_UFS_PHY_ICE_CORE_CLK 132 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 -#define GCC_UFS_PHY_PHY_AUX_CLK 134 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 -#define GCC_USB30_PRIM_MASTER_CLK 141 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 -#define GCC_USB30_PRIM_SLEEP_CLK 145 -#define GCC_USB30_SEC_MASTER_CLK 146 -#define GCC_USB30_SEC_MASTER_CLK_SRC 147 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 -#define GCC_USB30_SEC_SLEEP_CLK 150 -#define GCC_USB3_PRIM_CLKREF_CLK 151 -#define GCC_USB3_PRIM_PHY_AUX_CLK 152 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 -#define GCC_USB3_SEC_CLKREF_CLK 156 -#define GCC_USB3_SEC_PHY_AUX_CLK 157 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 -#define GCC_USB3_SEC_PHY_PIPE_CLK 159 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 -#define GCC_VIDEO_AHB_CLK 162 -#define GCC_VIDEO_AXI_CLK 163 -#define GCC_VIDEO_XO_CLK 164 -#define GPLL0 165 -#define GPLL0_OUT_EVEN 166 -#define GPLL0_OUT_MAIN 167 -#define GCC_GPU_IREF_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_APPS_CLK_SRC 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_APC_VS_CLK 174 -#define GCC_GPU_VS_CLK 175 -#define GCC_MSS_VS_CLK 176 -#define GCC_VDDA_VS_CLK 177 -#define GCC_VDDCX_VS_CLK 178 -#define GCC_VDDMX_VS_CLK 179 -#define GCC_VS_CTRL_AHB_CLK 180 -#define GCC_VS_CTRL_CLK 181 -#define GCC_VS_CTRL_CLK_SRC 182 -#define GCC_VSENSOR_CLK_SRC 183 -#define GPLL4 184 -#define GCC_CPUSS_DVM_BUS_CLK 185 -#define GCC_CPUSS_GNOC_CLK 186 -#define GCC_QSPI_CORE_CLK_SRC 187 -#define GCC_QSPI_CORE_CLK 188 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 -#define GCC_LPASS_Q6_AXI_CLK 190 -#define GCC_LPASS_SWAY_CLK 191 - -/* GCC Resets */ -#define GCC_MMSS_BCR 0 -#define GCC_PCIE_0_BCR 1 -#define GCC_PCIE_1_BCR 2 -#define GCC_PCIE_PHY_BCR 3 -#define GCC_PDM_BCR 4 -#define GCC_PRNG_BCR 5 -#define GCC_QUPV3_WRAPPER_0_BCR 6 -#define GCC_QUPV3_WRAPPER_1_BCR 7 -#define GCC_QUSB2PHY_PRIM_BCR 8 -#define GCC_QUSB2PHY_SEC_BCR 9 -#define GCC_SDCC2_BCR 10 -#define GCC_SDCC4_BCR 11 -#define GCC_TSIF_BCR 12 -#define GCC_UFS_CARD_BCR 13 -#define GCC_UFS_PHY_BCR 14 -#define GCC_USB30_PRIM_BCR 15 -#define GCC_USB30_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3PHY_PHY_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_PHY_SEC_BCR 20 -#define GCC_USB3PHY_PHY_SEC_BCR 21 -#define GCC_USB3_DP_PHY_SEC_BCR 22 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 -#define GCC_PCIE_0_PHY_BCR 24 -#define GCC_PCIE_1_PHY_BCR 25 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define PCIE_1_GDSC 1 -#define UFS_CARD_GDSC 2 -#define UFS_PHY_GDSC 3 -#define USB30_PRIM_GDSC 4 -#define USB30_SEC_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 - -#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h deleted file mode 100644 index 9690d901b50a..000000000000 --- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H - -/* GPU_CC clock registers */ -#define GPU_CC_CX_GMU_CLK 0 -#define GPU_CC_CXO_CLK 1 -#define GPU_CC_GMU_CLK_SRC 2 -#define GPU_CC_PLL1 3 - -/* GPU_CC Resets */ -#define GPUCC_GPU_CC_CX_BCR 0 -#define GPUCC_GPU_CC_GMU_BCR 1 -#define GPUCC_GPU_CC_XO_BCR 2 - -/* GPU_CC GDSCRs */ -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h deleted file mode 100644 index 659050846f61..000000000000 --- a/include/dt-bindings/clock/qcom,lpass-sdm845.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H -#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H - -#define LPASS_Q6SS_AHBM_AON_CLK 0 -#define LPASS_Q6SS_AHBS_AON_CLK 1 -#define LPASS_QDSP6SS_XO_CLK 2 -#define LPASS_QDSP6SS_SLEEP_CLK 3 -#define LPASS_QDSP6SS_CORE_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h deleted file mode 100644 index d51f9ac70566..000000000000 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ /dev/null @@ -1,295 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H - -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 -#define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 - -#define MMAGICAHB_BCR 0 -#define MMAGIC_CFG_BCR 1 -#define MISC_BCR 2 -#define BTO_BCR 3 -#define MMAGICAXI_BCR 4 -#define MMAGICMAXI_BCR 5 -#define DSA_BCR 6 -#define MMAGIC_CAMSS_BCR 7 -#define THROTTLE_CAMSS_BCR 8 -#define SMMU_VFE_BCR 9 -#define SMMU_CPP_BCR 10 -#define SMMU_JPEG_BCR 11 -#define MMAGIC_MDSS_BCR 12 -#define THROTTLE_MDSS_BCR 13 -#define SMMU_ROT_BCR 14 -#define SMMU_MDP_BCR 15 -#define MMAGIC_VIDEO_BCR 16 -#define THROTTLE_VIDEO_BCR 17 -#define SMMU_VIDEO_BCR 18 -#define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 - -/* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h deleted file mode 100644 index 46309c9953b2..000000000000 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H -#define _DT_BINDINGS_CLK_MSM_RPMCC_H - -/* RPM clocks */ -#define RPM_PXO_CLK 0 -#define RPM_PXO_A_CLK 1 -#define RPM_CXO_CLK 2 -#define RPM_CXO_A_CLK 3 -#define RPM_APPS_FABRIC_CLK 4 -#define RPM_APPS_FABRIC_A_CLK 5 -#define RPM_CFPB_CLK 6 -#define RPM_CFPB_A_CLK 7 -#define RPM_QDSS_CLK 8 -#define RPM_QDSS_A_CLK 9 -#define RPM_DAYTONA_FABRIC_CLK 10 -#define RPM_DAYTONA_FABRIC_A_CLK 11 -#define RPM_EBI1_CLK 12 -#define RPM_EBI1_A_CLK 13 -#define RPM_MM_FABRIC_CLK 14 -#define RPM_MM_FABRIC_A_CLK 15 -#define RPM_MMFPB_CLK 16 -#define RPM_MMFPB_A_CLK 17 -#define RPM_SYS_FABRIC_CLK 18 -#define RPM_SYS_FABRIC_A_CLK 19 -#define RPM_SFPB_CLK 20 -#define RPM_SFPB_A_CLK 21 -#define RPM_SMI_CLK 22 -#define RPM_SMI_A_CLK 23 -#define RPM_PLL4_CLK 24 -#define RPM_XO_D0 25 -#define RPM_XO_D1 26 -#define RPM_XO_A0 27 -#define RPM_XO_A1 28 -#define RPM_XO_A2 29 -#define RPM_NSS_FABRIC_0_CLK 30 -#define RPM_NSS_FABRIC_0_A_CLK 31 -#define RPM_NSS_FABRIC_1_CLK 32 -#define RPM_NSS_FABRIC_1_A_CLK 33 - -/* SMD RPM clocks */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_AGGR1_NOC_CLK 62 -#define RPM_SMD_AGGR1_NOC_A_CLK 63 -#define RPM_SMD_AGGR2_NOC_CLK 64 -#define RPM_SMD_AGGR2_NOC_A_CLK 65 -#define RPM_SMD_MMAXI_CLK 66 -#define RPM_SMD_MMAXI_A_CLK 67 -#define RPM_SMD_IPA_CLK 68 -#define RPM_SMD_IPA_A_CLK 69 -#define RPM_SMD_CE1_CLK 70 -#define RPM_SMD_CE1_A_CLK 71 -#define RPM_SMD_DIV_CLK3 72 -#define RPM_SMD_DIV_A_CLK3 73 -#define RPM_SMD_LN_BB_CLK 74 -#define RPM_SMD_LN_BB_A_CLK 75 -#define RPM_SMD_BIMC_GPU_CLK 76 -#define RPM_SMD_BIMC_GPU_A_CLK 77 -#define RPM_SMD_QPIC_CLK 78 -#define RPM_SMD_QPIC_CLK_A 79 -#define RPM_SMD_LN_BB_CLK1 80 -#define RPM_SMD_LN_BB_CLK1_A 81 -#define RPM_SMD_LN_BB_CLK2 82 -#define RPM_SMD_LN_BB_CLK2_A 83 -#define RPM_SMD_LN_BB_CLK3_PIN 84 -#define RPM_SMD_LN_BB_CLK3_A_PIN 85 -#define RPM_SMD_RF_CLK3 86 -#define RPM_SMD_RF_CLK3_A 87 -#define RPM_SMD_RF_CLK3_PIN 88 -#define RPM_SMD_RF_CLK3_A_PIN 89 -#define RPM_SMD_MMSSNOC_AXI_CLK 90 -#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 -#define RPM_SMD_CNOC_PERIPH_CLK 92 -#define RPM_SMD_CNOC_PERIPH_A_CLK 93 -#define RPM_SMD_LN_BB_CLK3 94 -#define RPM_SMD_LN_BB_CLK3_A 95 -#define RPM_SMD_LN_BB_CLK1_PIN 96 -#define RPM_SMD_LN_BB_CLK1_A_PIN 97 -#define RPM_SMD_LN_BB_CLK2_PIN 98 -#define RPM_SMD_LN_BB_CLK2_A_PIN 99 -#define RPM_SMD_SYSMMNOC_CLK 100 -#define RPM_SMD_SYSMMNOC_A_CLK 101 -#define RPM_SMD_CE2_CLK 102 -#define RPM_SMD_CE2_A_CLK 103 -#define RPM_SMD_CE3_CLK 104 -#define RPM_SMD_CE3_A_CLK 105 -#define RPM_SMD_QUP_CLK 106 -#define RPM_SMD_QUP_A_CLK 107 -#define RPM_SMD_MMRT_CLK 108 -#define RPM_SMD_MMRT_A_CLK 109 -#define RPM_SMD_MMNRT_CLK 110 -#define RPM_SMD_MMNRT_A_CLK 111 -#define RPM_SMD_SNOC_PERIPH_CLK 112 -#define RPM_SMD_SNOC_PERIPH_A_CLK 113 -#define RPM_SMD_SNOC_LPASS_CLK 114 -#define RPM_SMD_SNOC_LPASS_A_CLK 115 -#define RPM_SMD_HWKM_CLK 116 -#define RPM_SMD_HWKM_A_CLK 117 -#define RPM_SMD_PKA_CLK 118 -#define RPM_SMD_PKA_A_CLK 119 -#define RPM_SMD_CPUSS_GNOC_CLK 120 -#define RPM_SMD_CPUSS_GNOC_A_CLK 121 -#define RPM_SMD_MSS_CFG_AHB_CLK 122 -#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 -#define RPM_SMD_BIMC_FREQ_LOG 124 -#define RPM_SMD_LN_BB_CLK_PIN 125 -#define RPM_SMD_LN_BB_A_CLK_PIN 126 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h deleted file mode 100644 index 0a7d1be0d124..000000000000 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ - - -#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H -#define _DT_BINDINGS_CLK_MSM_RPMH_H - -/* RPMh controlled clocks */ -#define RPMH_CXO_CLK 0 -#define RPMH_CXO_CLK_A 1 -#define RPMH_LN_BB_CLK2 2 -#define RPMH_LN_BB_CLK2_A 3 -#define RPMH_LN_BB_CLK3 4 -#define RPMH_LN_BB_CLK3_A 5 -#define RPMH_RF_CLK1 6 -#define RPMH_RF_CLK1_A 7 -#define RPMH_RF_CLK2 8 -#define RPMH_RF_CLK2_A 9 -#define RPMH_RF_CLK3 10 -#define RPMH_RF_CLK3_A 11 -#define RPMH_IPA_CLK 12 -#define RPMH_LN_BB_CLK1 13 -#define RPMH_LN_BB_CLK1_A 14 -#define RPMH_CE_CLK 15 -#define RPMH_QPIC_CLK 16 -#define RPMH_DIV_CLK1 17 -#define RPMH_DIV_CLK1_A 18 -#define RPMH_RF_CLK4 19 -#define RPMH_RF_CLK4_A 20 -#define RPMH_RF_CLK5 21 -#define RPMH_RF_CLK5_A 22 -#define RPMH_PKA_CLK 23 -#define RPMH_HWKM_CLK 24 -#define RPMH_QLINK_CLK 25 -#define RPMH_QLINK_CLK_A 26 - -#endif diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h deleted file mode 100644 index 838faef57c67..000000000000 --- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Linaro Ltd - */ - -#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H -#define _DT_BINDINGS_CLK_TURING_QCS404_H - -#define TURING_Q6SS_Q6_AXIM_CLK 0 -#define TURING_Q6SS_AHBM_AON_CLK 1 -#define TURING_WRAPPER_AON_CLK 2 -#define TURING_Q6SS_AHBS_AON_CLK 3 -#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h deleted file mode 100644 index 1b868165e8ce..000000000000 --- a/include/dt-bindings/clock/qcom,videocc-sdm845.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H - -/* VIDEO_CC clock registers */ -#define VIDEO_CC_APB_CLK 0 -#define VIDEO_CC_AT_CLK 1 -#define VIDEO_CC_QDSS_TRIG_CLK 2 -#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 -#define VIDEO_CC_VCODEC0_AXI_CLK 4 -#define VIDEO_CC_VCODEC0_CORE_CLK 5 -#define VIDEO_CC_VCODEC1_AXI_CLK 6 -#define VIDEO_CC_VCODEC1_CORE_CLK 7 -#define VIDEO_CC_VENUS_AHB_CLK 8 -#define VIDEO_CC_VENUS_CLK_SRC 9 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 -#define VIDEO_PLL0 12 - -/* VIDEO_CC Resets */ -#define VIDEO_CC_VENUS_BCR 0 -#define VIDEO_CC_VCODEC0_BCR 1 -#define VIDEO_CC_VCODEC1_BCR 2 -#define VIDEO_CC_INTERFACE_BCR 3 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 -#define VCODEC1_GDSC 2 - -#endif

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/sun20i-d1-ccu.h | 158 -------------------- include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 --- include/dt-bindings/clock/sun4i-a10-ccu.h | 202 -------------------------- include/dt-bindings/clock/sun4i-a10-pll2.h | 53 ------- include/dt-bindings/clock/sun50i-a64-ccu.h | 138 ------------------ include/dt-bindings/clock/sun50i-h6-ccu.h | 125 ---------------- include/dt-bindings/clock/sun50i-h6-r-ccu.h | 27 ---- include/dt-bindings/clock/sun50i-h616-ccu.h | 116 --------------- include/dt-bindings/clock/sun5i-ccu.h | 97 ------------- include/dt-bindings/clock/sun6i-a31-ccu.h | 193 ------------------------ include/dt-bindings/clock/sun6i-rtc.h | 10 -- include/dt-bindings/clock/sun7i-a20-ccu.h | 53 ------- include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 129 ---------------- include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 ------------------ include/dt-bindings/clock/sun8i-de2.h | 21 --- include/dt-bindings/clock/sun8i-h3-ccu.h | 152 ------------------- include/dt-bindings/clock/sun8i-r-ccu.h | 59 -------- include/dt-bindings/clock/sun8i-r40-ccu.h | 191 ------------------------ include/dt-bindings/clock/sun8i-tcon-top.h | 11 -- include/dt-bindings/clock/sun8i-v3s-ccu.h | 111 -------------- include/dt-bindings/clock/sun9i-a80-ccu.h | 162 --------------------- include/dt-bindings/clock/sun9i-a80-de.h | 80 ---------- include/dt-bindings/clock/sun9i-a80-usb.h | 59 -------- include/dt-bindings/clock/suniv-ccu-f1c100s.h | 72 --------- 24 files changed, 2378 deletions(-)

diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h deleted file mode 100644 index fdbfb404f92a..000000000000 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland samuel@sholland.org - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ - -#define CLK_PLL_CPUX 0 -#define CLK_PLL_DDR0 1 -#define CLK_PLL_PERIPH0_4X 2 -#define CLK_PLL_PERIPH0_2X 3 -#define CLK_PLL_PERIPH0_800M 4 -#define CLK_PLL_PERIPH0 5 -#define CLK_PLL_PERIPH0_DIV3 6 -#define CLK_PLL_VIDEO0_4X 7 -#define CLK_PLL_VIDEO0_2X 8 -#define CLK_PLL_VIDEO0 9 -#define CLK_PLL_VIDEO1_4X 10 -#define CLK_PLL_VIDEO1_2X 11 -#define CLK_PLL_VIDEO1 12 -#define CLK_PLL_VE 13 -#define CLK_PLL_AUDIO0_4X 14 -#define CLK_PLL_AUDIO0_2X 15 -#define CLK_PLL_AUDIO0 16 -#define CLK_PLL_AUDIO1 17 -#define CLK_PLL_AUDIO1_DIV2 18 -#define CLK_PLL_AUDIO1_DIV5 19 -#define CLK_CPUX 20 -#define CLK_CPUX_AXI 21 -#define CLK_CPUX_APB 22 -#define CLK_PSI_AHB 23 -#define CLK_APB0 24 -#define CLK_APB1 25 -#define CLK_MBUS 26 -#define CLK_DE 27 -#define CLK_BUS_DE 28 -#define CLK_DI 29 -#define CLK_BUS_DI 30 -#define CLK_G2D 31 -#define CLK_BUS_G2D 32 -#define CLK_CE 33 -#define CLK_BUS_CE 34 -#define CLK_VE 35 -#define CLK_BUS_VE 36 -#define CLK_BUS_DMA 37 -#define CLK_BUS_MSGBOX0 38 -#define CLK_BUS_MSGBOX1 39 -#define CLK_BUS_MSGBOX2 40 -#define CLK_BUS_SPINLOCK 41 -#define CLK_BUS_HSTIMER 42 -#define CLK_AVS 43 -#define CLK_BUS_DBG 44 -#define CLK_BUS_PWM 45 -#define CLK_BUS_IOMMU 46 -#define CLK_DRAM 47 -#define CLK_MBUS_DMA 48 -#define CLK_MBUS_VE 49 -#define CLK_MBUS_CE 50 -#define CLK_MBUS_TVIN 51 -#define CLK_MBUS_CSI 52 -#define CLK_MBUS_G2D 53 -#define CLK_MBUS_RISCV 54 -#define CLK_BUS_DRAM 55 -#define CLK_MMC0 56 -#define CLK_MMC1 57 -#define CLK_MMC2 58 -#define CLK_BUS_MMC0 59 -#define CLK_BUS_MMC1 60 -#define CLK_BUS_MMC2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_UART4 66 -#define CLK_BUS_UART5 67 -#define CLK_BUS_I2C0 68 -#define CLK_BUS_I2C1 69 -#define CLK_BUS_I2C2 70 -#define CLK_BUS_I2C3 71 -#define CLK_SPI0 72 -#define CLK_SPI1 73 -#define CLK_BUS_SPI0 74 -#define CLK_BUS_SPI1 75 -#define CLK_EMAC_25M 76 -#define CLK_BUS_EMAC 77 -#define CLK_IR_TX 78 -#define CLK_BUS_IR_TX 79 -#define CLK_BUS_GPADC 80 -#define CLK_BUS_THS 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_I2S2_ASRC 85 -#define CLK_BUS_I2S0 86 -#define CLK_BUS_I2S1 87 -#define CLK_BUS_I2S2 88 -#define CLK_SPDIF_TX 89 -#define CLK_SPDIF_RX 90 -#define CLK_BUS_SPDIF 91 -#define CLK_DMIC 92 -#define CLK_BUS_DMIC 93 -#define CLK_AUDIO_DAC 94 -#define CLK_AUDIO_ADC 95 -#define CLK_BUS_AUDIO 96 -#define CLK_USB_OHCI0 97 -#define CLK_USB_OHCI1 98 -#define CLK_BUS_OHCI0 99 -#define CLK_BUS_OHCI1 100 -#define CLK_BUS_EHCI0 101 -#define CLK_BUS_EHCI1 102 -#define CLK_BUS_OTG 103 -#define CLK_BUS_LRADC 104 -#define CLK_BUS_DPSS_TOP 105 -#define CLK_HDMI_24M 106 -#define CLK_HDMI_CEC_32K 107 -#define CLK_HDMI_CEC 108 -#define CLK_BUS_HDMI 109 -#define CLK_MIPI_DSI 110 -#define CLK_BUS_MIPI_DSI 111 -#define CLK_TCON_LCD0 112 -#define CLK_BUS_TCON_LCD0 113 -#define CLK_TCON_TV 114 -#define CLK_BUS_TCON_TV 115 -#define CLK_TVE 116 -#define CLK_BUS_TVE_TOP 117 -#define CLK_BUS_TVE 118 -#define CLK_TVD 119 -#define CLK_BUS_TVD_TOP 120 -#define CLK_BUS_TVD 121 -#define CLK_LEDC 122 -#define CLK_BUS_LEDC 123 -#define CLK_CSI_TOP 124 -#define CLK_CSI_MCLK 125 -#define CLK_BUS_CSI 126 -#define CLK_TPADC 127 -#define CLK_BUS_TPADC 128 -#define CLK_BUS_TZMA 129 -#define CLK_DSP 130 -#define CLK_BUS_DSP_CFG 131 -#define CLK_RISCV 132 -#define CLK_RISCV_AXI 133 -#define CLK_BUS_RISCV_CFG 134 -#define CLK_FANOUT_24M 135 -#define CLK_FANOUT_12M 136 -#define CLK_FANOUT_16M 137 -#define CLK_FANOUT_25M 138 -#define CLK_FANOUT_32K 139 -#define CLK_FANOUT_27M 140 -#define CLK_FANOUT_PCLK 141 -#define CLK_FANOUT0 142 -#define CLK_FANOUT1 143 -#define CLK_FANOUT2 144 -#define CLK_BUS_CAN0 145 -#define CLK_BUS_CAN1 146 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h deleted file mode 100644 index f95c170711e5..000000000000 --- a/include/dt-bindings/clock/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland samuel@sholland.org - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ - -#define CLK_R_AHB 0 - -#define CLK_BUS_R_TIMER 2 -#define CLK_BUS_R_TWD 3 -#define CLK_BUS_R_PPU 4 -#define CLK_R_IR_RX 5 -#define CLK_BUS_R_IR_RX 6 -#define CLK_BUS_R_RTC 7 -#define CLK_BUS_R_CPUCFG 8 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h deleted file mode 100644 index e4fa61be5c75..000000000000 --- a/include/dt-bindings/clock/sun4i-a10-ccu.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes plaes@plaes.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ -#define _DT_BINDINGS_CLK_SUN4I_A10_H_ - -#define CLK_HOSC 1 -#define CLK_PLL_VIDEO0_2X 9 -#define CLK_PLL_VIDEO1_2X 18 -#define CLK_CPU 20 - -/* AHB Gates */ -#define CLK_AHB_OTG 26 -#define CLK_AHB_EHCI0 27 -#define CLK_AHB_OHCI0 28 -#define CLK_AHB_EHCI1 29 -#define CLK_AHB_OHCI1 30 -#define CLK_AHB_SS 31 -#define CLK_AHB_DMA 32 -#define CLK_AHB_BIST 33 -#define CLK_AHB_MMC0 34 -#define CLK_AHB_MMC1 35 -#define CLK_AHB_MMC2 36 -#define CLK_AHB_MMC3 37 -#define CLK_AHB_MS 38 -#define CLK_AHB_NAND 39 -#define CLK_AHB_SDRAM 40 -#define CLK_AHB_ACE 41 -#define CLK_AHB_EMAC 42 -#define CLK_AHB_TS 43 -#define CLK_AHB_SPI0 44 -#define CLK_AHB_SPI1 45 -#define CLK_AHB_SPI2 46 -#define CLK_AHB_SPI3 47 -#define CLK_AHB_PATA 48 -#define CLK_AHB_SATA 49 -#define CLK_AHB_GPS 50 -#define CLK_AHB_HSTIMER 51 -#define CLK_AHB_VE 52 -#define CLK_AHB_TVD 53 -#define CLK_AHB_TVE0 54 -#define CLK_AHB_TVE1 55 -#define CLK_AHB_LCD0 56 -#define CLK_AHB_LCD1 57 -#define CLK_AHB_CSI0 58 -#define CLK_AHB_CSI1 59 -#define CLK_AHB_HDMI0 60 -#define CLK_AHB_HDMI1 61 -#define CLK_AHB_DE_BE0 62 -#define CLK_AHB_DE_BE1 63 -#define CLK_AHB_DE_FE0 64 -#define CLK_AHB_DE_FE1 65 -#define CLK_AHB_GMAC 66 -#define CLK_AHB_MP 67 -#define CLK_AHB_GPU 68 - -/* APB0 Gates */ -#define CLK_APB0_CODEC 69 -#define CLK_APB0_SPDIF 70 -#define CLK_APB0_I2S0 71 -#define CLK_APB0_AC97 72 -#define CLK_APB0_I2S1 73 -#define CLK_APB0_PIO 74 -#define CLK_APB0_IR0 75 -#define CLK_APB0_IR1 76 -#define CLK_APB0_I2S2 77 -#define CLK_APB0_KEYPAD 78 - -/* APB1 Gates */ -#define CLK_APB1_I2C0 79 -#define CLK_APB1_I2C1 80 -#define CLK_APB1_I2C2 81 -#define CLK_APB1_I2C3 82 -#define CLK_APB1_CAN 83 -#define CLK_APB1_SCR 84 -#define CLK_APB1_PS20 85 -#define CLK_APB1_PS21 86 -#define CLK_APB1_I2C4 87 -#define CLK_APB1_UART0 88 -#define CLK_APB1_UART1 89 -#define CLK_APB1_UART2 90 -#define CLK_APB1_UART3 91 -#define CLK_APB1_UART4 92 -#define CLK_APB1_UART5 93 -#define CLK_APB1_UART6 94 -#define CLK_APB1_UART7 95 - -/* IP clocks */ -#define CLK_NAND 96 -#define CLK_MS 97 -#define CLK_MMC0 98 -#define CLK_MMC0_OUTPUT 99 -#define CLK_MMC0_SAMPLE 100 -#define CLK_MMC1 101 -#define CLK_MMC1_OUTPUT 102 -#define CLK_MMC1_SAMPLE 103 -#define CLK_MMC2 104 -#define CLK_MMC2_OUTPUT 105 -#define CLK_MMC2_SAMPLE 106 -#define CLK_MMC3 107 -#define CLK_MMC3_OUTPUT 108 -#define CLK_MMC3_SAMPLE 109 -#define CLK_TS 110 -#define CLK_SS 111 -#define CLK_SPI0 112 -#define CLK_SPI1 113 -#define CLK_SPI2 114 -#define CLK_PATA 115 -#define CLK_IR0 116 -#define CLK_IR1 117 -#define CLK_I2S0 118 -#define CLK_AC97 119 -#define CLK_SPDIF 120 -#define CLK_KEYPAD 121 -#define CLK_SATA 122 -#define CLK_USB_OHCI0 123 -#define CLK_USB_OHCI1 124 -#define CLK_USB_PHY 125 -#define CLK_GPS 126 -#define CLK_SPI3 127 -#define CLK_I2S1 128 -#define CLK_I2S2 129 - -/* DRAM Gates */ -#define CLK_DRAM_VE 130 -#define CLK_DRAM_CSI0 131 -#define CLK_DRAM_CSI1 132 -#define CLK_DRAM_TS 133 -#define CLK_DRAM_TVD 134 -#define CLK_DRAM_TVE0 135 -#define CLK_DRAM_TVE1 136 -#define CLK_DRAM_OUT 137 -#define CLK_DRAM_DE_FE1 138 -#define CLK_DRAM_DE_FE0 139 -#define CLK_DRAM_DE_BE0 140 -#define CLK_DRAM_DE_BE1 141 -#define CLK_DRAM_MP 142 -#define CLK_DRAM_ACE 143 - -/* Display Engine Clocks */ -#define CLK_DE_BE0 144 -#define CLK_DE_BE1 145 -#define CLK_DE_FE0 146 -#define CLK_DE_FE1 147 -#define CLK_DE_MP 148 -#define CLK_TCON0_CH0 149 -#define CLK_TCON1_CH0 150 -#define CLK_CSI_SCLK 151 -#define CLK_TVD_SCLK2 152 -#define CLK_TVD 153 -#define CLK_TCON0_CH1_SCLK2 154 -#define CLK_TCON0_CH1 155 -#define CLK_TCON1_CH1_SCLK2 156 -#define CLK_TCON1_CH1 157 -#define CLK_CSI0 158 -#define CLK_CSI1 159 -#define CLK_CODEC 160 -#define CLK_VE 161 -#define CLK_AVS 162 -#define CLK_ACE 163 -#define CLK_HDMI 164 -#define CLK_GPU 165 - -#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h deleted file mode 100644 index 071c8112d531..000000000000 --- a/include/dt-bindings/clock/sun4i-a10-pll2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ -#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ - -#define SUN4I_A10_PLL2_1X 0 -#define SUN4I_A10_PLL2_2X 1 -#define SUN4I_A10_PLL2_4X 2 -#define SUN4I_A10_PLL2_8X 3 - -#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h deleted file mode 100644 index 175892189e9d..000000000000 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ -#define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -#define CLK_PLL_VIDEO0 7 -#define CLK_PLL_PERIPH0 11 - -#define CLK_CPUX 21 -#define CLK_BUS_MIPI_DSI 28 -#define CLK_BUS_CE 29 -#define CLK_BUS_DMA 30 -#define CLK_BUS_MMC0 31 -#define CLK_BUS_MMC1 32 -#define CLK_BUS_MMC2 33 -#define CLK_BUS_NAND 34 -#define CLK_BUS_DRAM 35 -#define CLK_BUS_EMAC 36 -#define CLK_BUS_TS 37 -#define CLK_BUS_HSTIMER 38 -#define CLK_BUS_SPI0 39 -#define CLK_BUS_SPI1 40 -#define CLK_BUS_OTG 41 -#define CLK_BUS_EHCI0 42 -#define CLK_BUS_EHCI1 43 -#define CLK_BUS_OHCI0 44 -#define CLK_BUS_OHCI1 45 -#define CLK_BUS_VE 46 -#define CLK_BUS_TCON0 47 -#define CLK_BUS_TCON1 48 -#define CLK_BUS_DEINTERLACE 49 -#define CLK_BUS_CSI 50 -#define CLK_BUS_HDMI 51 -#define CLK_BUS_DE 52 -#define CLK_BUS_GPU 53 -#define CLK_BUS_MSGBOX 54 -#define CLK_BUS_SPINLOCK 55 -#define CLK_BUS_CODEC 56 -#define CLK_BUS_SPDIF 57 -#define CLK_BUS_PIO 58 -#define CLK_BUS_THS 59 -#define CLK_BUS_I2S0 60 -#define CLK_BUS_I2S1 61 -#define CLK_BUS_I2S2 62 -#define CLK_BUS_I2C0 63 -#define CLK_BUS_I2C1 64 -#define CLK_BUS_I2C2 65 -#define CLK_BUS_SCR 66 -#define CLK_BUS_UART0 67 -#define CLK_BUS_UART1 68 -#define CLK_BUS_UART2 69 -#define CLK_BUS_UART3 70 -#define CLK_BUS_UART4 71 -#define CLK_BUS_DBG 72 -#define CLK_THS 73 -#define CLK_NAND 74 -#define CLK_MMC0 75 -#define CLK_MMC1 76 -#define CLK_MMC2 77 -#define CLK_TS 78 -#define CLK_CE 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_SPDIF 85 -#define CLK_USB_PHY0 86 -#define CLK_USB_PHY1 87 -#define CLK_USB_HSIC 88 -#define CLK_USB_HSIC_12M 89 - -#define CLK_USB_OHCI0 91 - -#define CLK_USB_OHCI1 93 -#define CLK_DRAM 94 -#define CLK_DRAM_VE 95 -#define CLK_DRAM_CSI 96 -#define CLK_DRAM_DEINTERLACE 97 -#define CLK_DRAM_TS 98 -#define CLK_DE 99 -#define CLK_TCON0 100 -#define CLK_TCON1 101 -#define CLK_DEINTERLACE 102 -#define CLK_CSI_MISC 103 -#define CLK_CSI_SCLK 104 -#define CLK_CSI_MCLK 105 -#define CLK_VE 106 -#define CLK_AC_DIG 107 -#define CLK_AC_DIG_4X 108 -#define CLK_AVS 109 -#define CLK_HDMI 110 -#define CLK_HDMI_DDC 111 -#define CLK_MBUS 112 -#define CLK_DSI_DPHY 113 -#define CLK_GPU 114 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h deleted file mode 100644 index ef9123d81937..000000000000 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_H_ - -#define CLK_PLL_PERIPH0 3 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_GPU 33 -#define CLK_BUS_GPU 34 -#define CLK_CE 35 -#define CLK_BUS_CE 36 -#define CLK_VE 37 -#define CLK_BUS_VE 38 -#define CLK_EMCE 39 -#define CLK_BUS_EMCE 40 -#define CLK_VP9 41 -#define CLK_BUS_VP9 42 -#define CLK_BUS_DMA 43 -#define CLK_BUS_MSGBOX 44 -#define CLK_BUS_SPINLOCK 45 -#define CLK_BUS_HSTIMER 46 -#define CLK_AVS 47 -#define CLK_BUS_DBG 48 -#define CLK_BUS_PSI 49 -#define CLK_BUS_PWM 50 -#define CLK_BUS_IOMMU 51 - -#define CLK_MBUS_DMA 53 -#define CLK_MBUS_VE 54 -#define CLK_MBUS_CE 55 -#define CLK_MBUS_TS 56 -#define CLK_MBUS_NAND 57 -#define CLK_MBUS_CSI 58 -#define CLK_MBUS_DEINTERLACE 59 - -#define CLK_NAND0 61 -#define CLK_NAND1 62 -#define CLK_BUS_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_BUS_MMC0 67 -#define CLK_BUS_MMC1 68 -#define CLK_BUS_MMC2 69 -#define CLK_BUS_UART0 70 -#define CLK_BUS_UART1 71 -#define CLK_BUS_UART2 72 -#define CLK_BUS_UART3 73 -#define CLK_BUS_I2C0 74 -#define CLK_BUS_I2C1 75 -#define CLK_BUS_I2C2 76 -#define CLK_BUS_I2C3 77 -#define CLK_BUS_SCR0 78 -#define CLK_BUS_SCR1 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_BUS_SPI0 82 -#define CLK_BUS_SPI1 83 -#define CLK_BUS_EMAC 84 -#define CLK_TS 85 -#define CLK_BUS_TS 86 -#define CLK_IR_TX 87 -#define CLK_BUS_IR_TX 88 -#define CLK_BUS_THS 89 -#define CLK_I2S3 90 -#define CLK_I2S0 91 -#define CLK_I2S1 92 -#define CLK_I2S2 93 -#define CLK_BUS_I2S0 94 -#define CLK_BUS_I2S1 95 -#define CLK_BUS_I2S2 96 -#define CLK_BUS_I2S3 97 -#define CLK_SPDIF 98 -#define CLK_BUS_SPDIF 99 -#define CLK_DMIC 100 -#define CLK_BUS_DMIC 101 -#define CLK_AUDIO_HUB 102 -#define CLK_BUS_AUDIO_HUB 103 -#define CLK_USB_OHCI0 104 -#define CLK_USB_PHY0 105 -#define CLK_USB_PHY1 106 -#define CLK_USB_OHCI3 107 -#define CLK_USB_PHY3 108 -#define CLK_USB_HSIC_12M 109 -#define CLK_USB_HSIC 110 -#define CLK_BUS_OHCI0 111 -#define CLK_BUS_OHCI3 112 -#define CLK_BUS_EHCI0 113 -#define CLK_BUS_XHCI 114 -#define CLK_BUS_EHCI3 115 -#define CLK_BUS_OTG 116 -#define CLK_PCIE_REF_100M 117 -#define CLK_PCIE_REF 118 -#define CLK_PCIE_REF_OUT 119 -#define CLK_PCIE_MAXI 120 -#define CLK_PCIE_AUX 121 -#define CLK_BUS_PCIE 122 -#define CLK_HDMI 123 -#define CLK_HDMI_SLOW 124 -#define CLK_HDMI_CEC 125 -#define CLK_BUS_HDMI 126 -#define CLK_BUS_TCON_TOP 127 -#define CLK_TCON_LCD0 128 -#define CLK_BUS_TCON_LCD0 129 -#define CLK_TCON_TV0 130 -#define CLK_BUS_TCON_TV0 131 -#define CLK_CSI_CCI 132 -#define CLK_CSI_TOP 133 -#define CLK_CSI_MCLK 134 -#define CLK_BUS_CSI 135 -#define CLK_HDCP 136 -#define CLK_BUS_HDCP 137 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h deleted file mode 100644 index a96087abc86f..000000000000 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Icenowy Zheng icenowy@aosc.xyz - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_R_APB1 2 - -#define CLK_R_APB1_TIMER 4 -#define CLK_R_APB1_TWD 5 -#define CLK_R_APB1_PWM 6 -#define CLK_R_APB2_UART 7 -#define CLK_R_APB2_I2C 8 -#define CLK_R_APB1_IR 9 -#define CLK_R_APB1_W1 10 - -#define CLK_IR 11 -#define CLK_W1 12 - -#define CLK_R_APB2_RSB 13 -#define CLK_R_APB1_RTC 14 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h deleted file mode 100644 index 6f8f01e67628..000000000000 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ -#define _DT_BINDINGS_CLK_SUN50I_H616_H_ - -#define CLK_PLL_PERIPH0 4 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_G2D 33 -#define CLK_BUS_G2D 34 -#define CLK_GPU0 35 -#define CLK_BUS_GPU 36 -#define CLK_GPU1 37 -#define CLK_CE 38 -#define CLK_BUS_CE 39 -#define CLK_VE 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_DMA 42 -#define CLK_BUS_HSTIMER 43 -#define CLK_AVS 44 -#define CLK_BUS_DBG 45 -#define CLK_BUS_PSI 46 -#define CLK_BUS_PWM 47 -#define CLK_BUS_IOMMU 48 - -#define CLK_MBUS_DMA 50 -#define CLK_MBUS_VE 51 -#define CLK_MBUS_CE 52 -#define CLK_MBUS_TS 53 -#define CLK_MBUS_NAND 54 -#define CLK_MBUS_G2D 55 - -#define CLK_NAND0 57 -#define CLK_NAND1 58 -#define CLK_BUS_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC1 61 -#define CLK_MMC2 62 -#define CLK_BUS_MMC0 63 -#define CLK_BUS_MMC1 64 -#define CLK_BUS_MMC2 65 -#define CLK_BUS_UART0 66 -#define CLK_BUS_UART1 67 -#define CLK_BUS_UART2 68 -#define CLK_BUS_UART3 69 -#define CLK_BUS_UART4 70 -#define CLK_BUS_UART5 71 -#define CLK_BUS_I2C0 72 -#define CLK_BUS_I2C1 73 -#define CLK_BUS_I2C2 74 -#define CLK_BUS_I2C3 75 -#define CLK_BUS_I2C4 76 -#define CLK_SPI0 77 -#define CLK_SPI1 78 -#define CLK_BUS_SPI0 79 -#define CLK_BUS_SPI1 80 -#define CLK_EMAC_25M 81 -#define CLK_BUS_EMAC0 82 -#define CLK_BUS_EMAC1 83 -#define CLK_TS 84 -#define CLK_BUS_TS 85 -#define CLK_BUS_THS 86 -#define CLK_SPDIF 87 -#define CLK_BUS_SPDIF 88 -#define CLK_DMIC 89 -#define CLK_BUS_DMIC 90 -#define CLK_AUDIO_CODEC_1X 91 -#define CLK_AUDIO_CODEC_4X 92 -#define CLK_BUS_AUDIO_CODEC 93 -#define CLK_AUDIO_HUB 94 -#define CLK_BUS_AUDIO_HUB 95 -#define CLK_USB_OHCI0 96 -#define CLK_USB_PHY0 97 -#define CLK_USB_OHCI1 98 -#define CLK_USB_PHY1 99 -#define CLK_USB_OHCI2 100 -#define CLK_USB_PHY2 101 -#define CLK_USB_OHCI3 102 -#define CLK_USB_PHY3 103 -#define CLK_BUS_OHCI0 104 -#define CLK_BUS_OHCI1 105 -#define CLK_BUS_OHCI2 106 -#define CLK_BUS_OHCI3 107 -#define CLK_BUS_EHCI0 108 -#define CLK_BUS_EHCI1 109 -#define CLK_BUS_EHCI2 110 -#define CLK_BUS_EHCI3 111 -#define CLK_BUS_OTG 112 -#define CLK_BUS_KEYADC 113 -#define CLK_HDMI 114 -#define CLK_HDMI_SLOW 115 -#define CLK_HDMI_CEC 116 -#define CLK_BUS_HDMI 117 -#define CLK_BUS_TCON_TOP 118 -#define CLK_TCON_TV0 119 -#define CLK_TCON_TV1 120 -#define CLK_BUS_TCON_TV0 121 -#define CLK_BUS_TCON_TV1 122 -#define CLK_TVE0 123 -#define CLK_BUS_TVE_TOP 124 -#define CLK_BUS_TVE0 125 -#define CLK_HDCP 126 -#define CLK_BUS_HDCP 127 -#define CLK_PLL_SYSTEM_32K 128 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h deleted file mode 100644 index 75fe5619c3d9..000000000000 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard maxime.ripard@free-electrons.com - */ - -#ifndef _DT_BINDINGS_CLK_SUN5I_H_ -#define _DT_BINDINGS_CLK_SUN5I_H_ - -#define CLK_HOSC 1 - -#define CLK_PLL_VIDEO0_2X 9 - -#define CLK_PLL_VIDEO1_2X 16 -#define CLK_CPU 17 - -#define CLK_AHB_OTG 23 -#define CLK_AHB_EHCI 24 -#define CLK_AHB_OHCI 25 -#define CLK_AHB_SS 26 -#define CLK_AHB_DMA 27 -#define CLK_AHB_BIST 28 -#define CLK_AHB_MMC0 29 -#define CLK_AHB_MMC1 30 -#define CLK_AHB_MMC2 31 -#define CLK_AHB_NAND 32 -#define CLK_AHB_SDRAM 33 -#define CLK_AHB_EMAC 34 -#define CLK_AHB_TS 35 -#define CLK_AHB_SPI0 36 -#define CLK_AHB_SPI1 37 -#define CLK_AHB_SPI2 38 -#define CLK_AHB_GPS 39 -#define CLK_AHB_HSTIMER 40 -#define CLK_AHB_VE 41 -#define CLK_AHB_TVE 42 -#define CLK_AHB_LCD 43 -#define CLK_AHB_CSI 44 -#define CLK_AHB_HDMI 45 -#define CLK_AHB_DE_BE 46 -#define CLK_AHB_DE_FE 47 -#define CLK_AHB_IEP 48 -#define CLK_AHB_GPU 49 -#define CLK_APB0_CODEC 50 -#define CLK_APB0_SPDIF 51 -#define CLK_APB0_I2S 52 -#define CLK_APB0_PIO 53 -#define CLK_APB0_IR 54 -#define CLK_APB0_KEYPAD 55 -#define CLK_APB1_I2C0 56 -#define CLK_APB1_I2C1 57 -#define CLK_APB1_I2C2 58 -#define CLK_APB1_UART0 59 -#define CLK_APB1_UART1 60 -#define CLK_APB1_UART2 61 -#define CLK_APB1_UART3 62 -#define CLK_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_TS 67 -#define CLK_SS 68 -#define CLK_SPI0 69 -#define CLK_SPI1 70 -#define CLK_SPI2 71 -#define CLK_IR 72 -#define CLK_I2S 73 -#define CLK_SPDIF 74 -#define CLK_KEYPAD 75 -#define CLK_USB_OHCI 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_GPS 79 -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_TS 82 -#define CLK_DRAM_TVE 83 -#define CLK_DRAM_DE_FE 84 -#define CLK_DRAM_DE_BE 85 -#define CLK_DRAM_ACE 86 -#define CLK_DRAM_IEP 87 -#define CLK_DE_BE 88 -#define CLK_DE_FE 89 -#define CLK_TCON_CH0 90 - -#define CLK_TCON_CH1 92 -#define CLK_CSI 93 -#define CLK_VE 94 -#define CLK_CODEC 95 -#define CLK_AVS 96 -#define CLK_HDMI 97 -#define CLK_GPU 98 -#define CLK_MBUS 99 -#define CLK_IEP 100 - -#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h deleted file mode 100644 index 39878d9dce9f..000000000000 --- a/include/dt-bindings/clock/sun6i-a31-ccu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ -#define _DT_BINDINGS_CLK_SUN6I_A31_H_ - -#define CLK_PLL_VIDEO0_2X 7 - -#define CLK_PLL_PERIPH 10 - -#define CLK_PLL_VIDEO1_2X 13 - -#define CLK_PLL_MIPI 15 - -#define CLK_CPU 18 - -#define CLK_AHB1_MIPIDSI 23 -#define CLK_AHB1_SS 24 -#define CLK_AHB1_DMA 25 -#define CLK_AHB1_MMC0 26 -#define CLK_AHB1_MMC1 27 -#define CLK_AHB1_MMC2 28 -#define CLK_AHB1_MMC3 29 -#define CLK_AHB1_NAND1 30 -#define CLK_AHB1_NAND0 31 -#define CLK_AHB1_SDRAM 32 -#define CLK_AHB1_EMAC 33 -#define CLK_AHB1_TS 34 -#define CLK_AHB1_HSTIMER 35 -#define CLK_AHB1_SPI0 36 -#define CLK_AHB1_SPI1 37 -#define CLK_AHB1_SPI2 38 -#define CLK_AHB1_SPI3 39 -#define CLK_AHB1_OTG 40 -#define CLK_AHB1_EHCI0 41 -#define CLK_AHB1_EHCI1 42 -#define CLK_AHB1_OHCI0 43 -#define CLK_AHB1_OHCI1 44 -#define CLK_AHB1_OHCI2 45 -#define CLK_AHB1_VE 46 -#define CLK_AHB1_LCD0 47 -#define CLK_AHB1_LCD1 48 -#define CLK_AHB1_CSI 49 -#define CLK_AHB1_HDMI 50 -#define CLK_AHB1_BE0 51 -#define CLK_AHB1_BE1 52 -#define CLK_AHB1_FE0 53 -#define CLK_AHB1_FE1 54 -#define CLK_AHB1_MP 55 -#define CLK_AHB1_GPU 56 -#define CLK_AHB1_DEU0 57 -#define CLK_AHB1_DEU1 58 -#define CLK_AHB1_DRC0 59 -#define CLK_AHB1_DRC1 60 - -#define CLK_APB1_CODEC 61 -#define CLK_APB1_SPDIF 62 -#define CLK_APB1_DIGITAL_MIC 63 -#define CLK_APB1_PIO 64 -#define CLK_APB1_DAUDIO0 65 -#define CLK_APB1_DAUDIO1 66 - -#define CLK_APB2_I2C0 67 -#define CLK_APB2_I2C1 68 -#define CLK_APB2_I2C2 69 -#define CLK_APB2_I2C3 70 -#define CLK_APB2_UART0 71 -#define CLK_APB2_UART1 72 -#define CLK_APB2_UART2 73 -#define CLK_APB2_UART3 74 -#define CLK_APB2_UART4 75 -#define CLK_APB2_UART5 76 - -#define CLK_NAND0 77 -#define CLK_NAND1 78 -#define CLK_MMC0 79 -#define CLK_MMC0_SAMPLE 80 -#define CLK_MMC0_OUTPUT 81 -#define CLK_MMC1 82 -#define CLK_MMC1_SAMPLE 83 -#define CLK_MMC1_OUTPUT 84 -#define CLK_MMC2 85 -#define CLK_MMC2_SAMPLE 86 -#define CLK_MMC2_OUTPUT 87 -#define CLK_MMC3 88 -#define CLK_MMC3_SAMPLE 89 -#define CLK_MMC3_OUTPUT 90 -#define CLK_TS 91 -#define CLK_SS 92 -#define CLK_SPI0 93 -#define CLK_SPI1 94 -#define CLK_SPI2 95 -#define CLK_SPI3 96 -#define CLK_DAUDIO0 97 -#define CLK_DAUDIO1 98 -#define CLK_SPDIF 99 -#define CLK_USB_PHY0 100 -#define CLK_USB_PHY1 101 -#define CLK_USB_PHY2 102 -#define CLK_USB_OHCI0 103 -#define CLK_USB_OHCI1 104 -#define CLK_USB_OHCI2 105 - -#define CLK_DRAM_VE 110 -#define CLK_DRAM_CSI_ISP 111 -#define CLK_DRAM_TS 112 -#define CLK_DRAM_DRC0 113 -#define CLK_DRAM_DRC1 114 -#define CLK_DRAM_DEU0 115 -#define CLK_DRAM_DEU1 116 -#define CLK_DRAM_FE0 117 -#define CLK_DRAM_FE1 118 -#define CLK_DRAM_BE0 119 -#define CLK_DRAM_BE1 120 -#define CLK_DRAM_MP 121 - -#define CLK_BE0 122 -#define CLK_BE1 123 -#define CLK_FE0 124 -#define CLK_FE1 125 -#define CLK_MP 126 -#define CLK_LCD0_CH0 127 -#define CLK_LCD1_CH0 128 -#define CLK_LCD0_CH1 129 -#define CLK_LCD1_CH1 130 -#define CLK_CSI0_SCLK 131 -#define CLK_CSI0_MCLK 132 -#define CLK_CSI1_MCLK 133 -#define CLK_VE 134 -#define CLK_CODEC 135 -#define CLK_AVS 136 -#define CLK_DIGITAL_MIC 137 -#define CLK_HDMI 138 -#define CLK_HDMI_DDC 139 -#define CLK_PS 140 - -#define CLK_MIPI_DSI 143 -#define CLK_MIPI_DSI_DPHY 144 -#define CLK_MIPI_CSI_DPHY 145 -#define CLK_IEP_DRC0 146 -#define CLK_IEP_DRC1 147 -#define CLK_IEP_DEU0 148 -#define CLK_IEP_DEU1 149 -#define CLK_GPU_CORE 150 -#define CLK_GPU_MEMORY 151 -#define CLK_GPU_HYD 152 -#define CLK_ATS 153 -#define CLK_TRACE 154 - -#define CLK_OUT_A 155 -#define CLK_OUT_B 156 -#define CLK_OUT_C 157 - -#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h deleted file mode 100644 index 3bd3aa3d57ce..000000000000 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ -#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ - -#define CLK_OSC32K 0 -#define CLK_OSC32K_FANOUT 1 -#define CLK_IOSC 2 - -#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h deleted file mode 100644 index 045a5178da0c..000000000000 --- a/include/dt-bindings/clock/sun7i-a20-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes plaes@plaes.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ -#define _DT_BINDINGS_CLK_SUN7I_A20_H_ - -#include <dt-bindings/clock/sun4i-a10-ccu.h> - -#define CLK_MBUS 166 -#define CLK_HDMI1_SLOW 167 -#define CLK_HDMI1 168 -#define CLK_OUT_A 169 -#define CLK_OUT_B 170 - -#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h deleted file mode 100644 index eb524d0bbd01..000000000000 --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ - -#define CLK_PLL_MIPI 13 - -#define CLK_CPUX 18 - -#define CLK_BUS_MIPI_DSI 23 -#define CLK_BUS_SS 24 -#define CLK_BUS_DMA 25 -#define CLK_BUS_MMC0 26 -#define CLK_BUS_MMC1 27 -#define CLK_BUS_MMC2 28 -#define CLK_BUS_NAND 29 -#define CLK_BUS_DRAM 30 -#define CLK_BUS_HSTIMER 31 -#define CLK_BUS_SPI0 32 -#define CLK_BUS_SPI1 33 -#define CLK_BUS_OTG 34 -#define CLK_BUS_EHCI 35 -#define CLK_BUS_OHCI 36 -#define CLK_BUS_VE 37 -#define CLK_BUS_LCD 38 -#define CLK_BUS_CSI 39 -#define CLK_BUS_DE_BE 40 -#define CLK_BUS_DE_FE 41 -#define CLK_BUS_GPU 42 -#define CLK_BUS_MSGBOX 43 -#define CLK_BUS_SPINLOCK 44 -#define CLK_BUS_DRC 45 -#define CLK_BUS_SAT 46 -#define CLK_BUS_CODEC 47 -#define CLK_BUS_PIO 48 -#define CLK_BUS_I2S0 49 -#define CLK_BUS_I2S1 50 -#define CLK_BUS_I2C0 51 -#define CLK_BUS_I2C1 52 -#define CLK_BUS_I2C2 53 -#define CLK_BUS_UART0 54 -#define CLK_BUS_UART1 55 -#define CLK_BUS_UART2 56 -#define CLK_BUS_UART3 57 -#define CLK_BUS_UART4 58 -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_USB_PHY0 74 -#define CLK_USB_PHY1 75 -#define CLK_USB_HSIC 76 -#define CLK_USB_HSIC_12M 77 -#define CLK_USB_OHCI 78 - -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_DRC 82 -#define CLK_DRAM_DE_FE 83 -#define CLK_DRAM_DE_BE 84 -#define CLK_DE_BE 85 -#define CLK_DE_FE 86 -#define CLK_LCD_CH0 87 -#define CLK_LCD_CH1 88 -#define CLK_CSI_SCLK 89 -#define CLK_CSI_MCLK 90 -#define CLK_VE 91 -#define CLK_AC_DIG 92 -#define CLK_AC_DIG_4X 93 -#define CLK_AVS 94 - -#define CLK_DSI_SCLK 96 -#define CLK_DSI_DPHY 97 -#define CLK_DRC 98 -#define CLK_GPU 99 -#define CLK_ATS 100 - -#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h deleted file mode 100644 index 78af5085f630..000000000000 --- a/include/dt-bindings/clock/sun8i-a83t-ccu.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ - -#define CLK_PLL_PERIPH 6 - -#define CLK_PLL_DE 9 - -#define CLK_C0CPUX 11 -#define CLK_C1CPUX 12 - -#define CLK_BUS_MIPI_DSI 19 -#define CLK_BUS_SS 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_HSTIMER 28 -#define CLK_BUS_SPI0 29 -#define CLK_BUS_SPI1 30 -#define CLK_BUS_OTG 31 -#define CLK_BUS_EHCI0 32 -#define CLK_BUS_EHCI1 33 -#define CLK_BUS_OHCI0 34 - -#define CLK_BUS_VE 35 -#define CLK_BUS_TCON0 36 -#define CLK_BUS_TCON1 37 -#define CLK_BUS_CSI 38 -#define CLK_BUS_HDMI 39 -#define CLK_BUS_DE 40 -#define CLK_BUS_GPU 41 -#define CLK_BUS_MSGBOX 42 -#define CLK_BUS_SPINLOCK 43 - -#define CLK_BUS_SPDIF 44 -#define CLK_BUS_PIO 45 -#define CLK_BUS_I2S0 46 -#define CLK_BUS_I2S1 47 -#define CLK_BUS_I2S2 48 -#define CLK_BUS_TDM 49 - -#define CLK_BUS_I2C0 50 -#define CLK_BUS_I2C1 51 -#define CLK_BUS_I2C2 52 -#define CLK_BUS_UART0 53 -#define CLK_BUS_UART1 54 -#define CLK_BUS_UART2 55 -#define CLK_BUS_UART3 56 -#define CLK_BUS_UART4 57 - -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_I2S2 74 -#define CLK_TDM 75 -#define CLK_SPDIF 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_USB_HSIC 79 -#define CLK_USB_HSIC_12M 80 -#define CLK_USB_OHCI0 81 - -#define CLK_DRAM_VE 83 -#define CLK_DRAM_CSI 84 - -#define CLK_TCON0 85 -#define CLK_TCON1 86 -#define CLK_CSI_MISC 87 -#define CLK_MIPI_CSI 88 -#define CLK_CSI_MCLK 89 -#define CLK_CSI_SCLK 90 -#define CLK_VE 91 -#define CLK_AVS 92 -#define CLK_HDMI 93 -#define CLK_HDMI_SLOW 94 - -#define CLK_MIPI_DSI0 96 -#define CLK_MIPI_DSI1 97 -#define CLK_GPU_CORE 98 -#define CLK_GPU_MEMORY 99 -#define CLK_GPU_HYD 100 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h deleted file mode 100644 index 7768f73b051e..000000000000 --- a/include/dt-bindings/clock/sun8i-de2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng icenowy@aosc.io - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ - -#define CLK_BUS_MIXER0 0 -#define CLK_BUS_MIXER1 1 -#define CLK_BUS_WB 2 - -#define CLK_MIXER0 6 -#define CLK_MIXER1 7 -#define CLK_WB 8 - -#define CLK_BUS_ROT 9 -#define CLK_ROT 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h deleted file mode 100644 index 5d4ada2c22e6..000000000000 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ -#define _DT_BINDINGS_CLK_SUN8I_H3_H_ - -#define CLK_PLL_VIDEO 6 - -#define CLK_PLL_PERIPH0 9 - -#define CLK_CPUX 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_TS 28 -#define CLK_BUS_HSTIMER 29 -#define CLK_BUS_SPI0 30 -#define CLK_BUS_SPI1 31 -#define CLK_BUS_OTG 32 -#define CLK_BUS_EHCI0 33 -#define CLK_BUS_EHCI1 34 -#define CLK_BUS_EHCI2 35 -#define CLK_BUS_EHCI3 36 -#define CLK_BUS_OHCI0 37 -#define CLK_BUS_OHCI1 38 -#define CLK_BUS_OHCI2 39 -#define CLK_BUS_OHCI3 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_TCON0 42 -#define CLK_BUS_TCON1 43 -#define CLK_BUS_DEINTERLACE 44 -#define CLK_BUS_CSI 45 -#define CLK_BUS_TVE 46 -#define CLK_BUS_HDMI 47 -#define CLK_BUS_DE 48 -#define CLK_BUS_GPU 49 -#define CLK_BUS_MSGBOX 50 -#define CLK_BUS_SPINLOCK 51 -#define CLK_BUS_CODEC 52 -#define CLK_BUS_SPDIF 53 -#define CLK_BUS_PIO 54 -#define CLK_BUS_THS 55 -#define CLK_BUS_I2S0 56 -#define CLK_BUS_I2S1 57 -#define CLK_BUS_I2S2 58 -#define CLK_BUS_I2C0 59 -#define CLK_BUS_I2C1 60 -#define CLK_BUS_I2C2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_SCR0 66 -#define CLK_BUS_EPHY 67 -#define CLK_BUS_DBG 68 - -#define CLK_THS 69 -#define CLK_NAND 70 -#define CLK_MMC0 71 -#define CLK_MMC0_SAMPLE 72 -#define CLK_MMC0_OUTPUT 73 -#define CLK_MMC1 74 -#define CLK_MMC1_SAMPLE 75 -#define CLK_MMC1_OUTPUT 76 -#define CLK_MMC2 77 -#define CLK_MMC2_SAMPLE 78 -#define CLK_MMC2_OUTPUT 79 -#define CLK_TS 80 -#define CLK_CE 81 -#define CLK_SPI0 82 -#define CLK_SPI1 83 -#define CLK_I2S0 84 -#define CLK_I2S1 85 -#define CLK_I2S2 86 -#define CLK_SPDIF 87 -#define CLK_USB_PHY0 88 -#define CLK_USB_PHY1 89 -#define CLK_USB_PHY2 90 -#define CLK_USB_PHY3 91 -#define CLK_USB_OHCI0 92 -#define CLK_USB_OHCI1 93 -#define CLK_USB_OHCI2 94 -#define CLK_USB_OHCI3 95 -#define CLK_DRAM 96 -#define CLK_DRAM_VE 97 -#define CLK_DRAM_CSI 98 -#define CLK_DRAM_DEINTERLACE 99 -#define CLK_DRAM_TS 100 -#define CLK_DE 101 -#define CLK_TCON0 102 -#define CLK_TVE 103 -#define CLK_DEINTERLACE 104 -#define CLK_CSI_MISC 105 -#define CLK_CSI_SCLK 106 -#define CLK_CSI_MCLK 107 -#define CLK_VE 108 -#define CLK_AC_DIG 109 -#define CLK_AVS 110 -#define CLK_HDMI 111 -#define CLK_HDMI_DDC 112 -#define CLK_MBUS 113 -#define CLK_GPU 114 - -/* New clocks imported in H5 */ -#define CLK_BUS_SCR1 115 - -#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h deleted file mode 100644 index 779d20aa0d05..000000000000 --- a/include/dt-bindings/clock/sun8i-r-ccu.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng icenowy@aosc.xyz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_APB0_PIO 3 -#define CLK_APB0_IR 4 -#define CLK_APB0_TIMER 5 -#define CLK_APB0_RSB 6 -#define CLK_APB0_UART 7 -/* 8 is reserved for CLK_APB0_W1 on A31 */ -#define CLK_APB0_I2C 9 -#define CLK_APB0_TWD 10 - -#define CLK_IR 11 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h deleted file mode 100644 index d7337b55a4ef..000000000000 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ -#define _DT_BINDINGS_CLK_SUN8I_R40_H_ - -#define CLK_PLL_VIDEO0 7 - -#define CLK_PLL_VIDEO1 16 - -#define CLK_CPU 24 - -#define CLK_BUS_MIPI_DSI 29 -#define CLK_BUS_CE 30 -#define CLK_BUS_DMA 31 -#define CLK_BUS_MMC0 32 -#define CLK_BUS_MMC1 33 -#define CLK_BUS_MMC2 34 -#define CLK_BUS_MMC3 35 -#define CLK_BUS_NAND 36 -#define CLK_BUS_DRAM 37 -#define CLK_BUS_EMAC 38 -#define CLK_BUS_TS 39 -#define CLK_BUS_HSTIMER 40 -#define CLK_BUS_SPI0 41 -#define CLK_BUS_SPI1 42 -#define CLK_BUS_SPI2 43 -#define CLK_BUS_SPI3 44 -#define CLK_BUS_SATA 45 -#define CLK_BUS_OTG 46 -#define CLK_BUS_EHCI0 47 -#define CLK_BUS_EHCI1 48 -#define CLK_BUS_EHCI2 49 -#define CLK_BUS_OHCI0 50 -#define CLK_BUS_OHCI1 51 -#define CLK_BUS_OHCI2 52 -#define CLK_BUS_VE 53 -#define CLK_BUS_MP 54 -#define CLK_BUS_DEINTERLACE 55 -#define CLK_BUS_CSI0 56 -#define CLK_BUS_CSI1 57 -#define CLK_BUS_HDMI1 58 -#define CLK_BUS_HDMI0 59 -#define CLK_BUS_DE 60 -#define CLK_BUS_TVE0 61 -#define CLK_BUS_TVE1 62 -#define CLK_BUS_TVE_TOP 63 -#define CLK_BUS_GMAC 64 -#define CLK_BUS_GPU 65 -#define CLK_BUS_TVD0 66 -#define CLK_BUS_TVD1 67 -#define CLK_BUS_TVD2 68 -#define CLK_BUS_TVD3 69 -#define CLK_BUS_TVD_TOP 70 -#define CLK_BUS_TCON_LCD0 71 -#define CLK_BUS_TCON_LCD1 72 -#define CLK_BUS_TCON_TV0 73 -#define CLK_BUS_TCON_TV1 74 -#define CLK_BUS_TCON_TOP 75 -#define CLK_BUS_CODEC 76 -#define CLK_BUS_SPDIF 77 -#define CLK_BUS_AC97 78 -#define CLK_BUS_PIO 79 -#define CLK_BUS_IR0 80 -#define CLK_BUS_IR1 81 -#define CLK_BUS_THS 82 -#define CLK_BUS_KEYPAD 83 -#define CLK_BUS_I2S0 84 -#define CLK_BUS_I2S1 85 -#define CLK_BUS_I2S2 86 -#define CLK_BUS_I2C0 87 -#define CLK_BUS_I2C1 88 -#define CLK_BUS_I2C2 89 -#define CLK_BUS_I2C3 90 -#define CLK_BUS_CAN 91 -#define CLK_BUS_SCR 92 -#define CLK_BUS_PS20 93 -#define CLK_BUS_PS21 94 -#define CLK_BUS_I2C4 95 -#define CLK_BUS_UART0 96 -#define CLK_BUS_UART1 97 -#define CLK_BUS_UART2 98 -#define CLK_BUS_UART3 99 -#define CLK_BUS_UART4 100 -#define CLK_BUS_UART5 101 -#define CLK_BUS_UART6 102 -#define CLK_BUS_UART7 103 -#define CLK_BUS_DBG 104 - -#define CLK_THS 105 -#define CLK_NAND 106 -#define CLK_MMC0 107 -#define CLK_MMC1 108 -#define CLK_MMC2 109 -#define CLK_MMC3 110 -#define CLK_TS 111 -#define CLK_CE 112 -#define CLK_SPI0 113 -#define CLK_SPI1 114 -#define CLK_SPI2 115 -#define CLK_SPI3 116 -#define CLK_I2S0 117 -#define CLK_I2S1 118 -#define CLK_I2S2 119 -#define CLK_AC97 120 -#define CLK_SPDIF 121 -#define CLK_KEYPAD 122 -#define CLK_SATA 123 -#define CLK_USB_PHY0 124 -#define CLK_USB_PHY1 125 -#define CLK_USB_PHY2 126 -#define CLK_USB_OHCI0 127 -#define CLK_USB_OHCI1 128 -#define CLK_USB_OHCI2 129 -#define CLK_IR0 130 -#define CLK_IR1 131 - -#define CLK_DRAM_VE 133 -#define CLK_DRAM_CSI0 134 -#define CLK_DRAM_CSI1 135 -#define CLK_DRAM_TS 136 -#define CLK_DRAM_TVD 137 -#define CLK_DRAM_MP 138 -#define CLK_DRAM_DEINTERLACE 139 -#define CLK_DE 140 -#define CLK_MP 141 -#define CLK_TCON_LCD0 142 -#define CLK_TCON_LCD1 143 -#define CLK_TCON_TV0 144 -#define CLK_TCON_TV1 145 -#define CLK_DEINTERLACE 146 -#define CLK_CSI1_MCLK 147 -#define CLK_CSI_SCLK 148 -#define CLK_CSI0_MCLK 149 -#define CLK_VE 150 -#define CLK_CODEC 151 -#define CLK_AVS 152 -#define CLK_HDMI 153 -#define CLK_HDMI_SLOW 154 -#define CLK_MBUS 155 -#define CLK_DSI_DPHY 156 -#define CLK_TVE0 157 -#define CLK_TVE1 158 -#define CLK_TVD0 159 -#define CLK_TVD1 160 -#define CLK_TVD2 161 -#define CLK_TVD3 162 -#define CLK_GPU 163 -#define CLK_OUTA 164 -#define CLK_OUTB 165 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h deleted file mode 100644 index 25164d767835..000000000000 --- a/include/dt-bindings/clock/sun8i-tcon-top.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (C) 2018 Jernej Skrabec jernej.skrabec@siol.net */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ - -#define CLK_TCON_TOP_TV0 0 -#define CLK_TCON_TOP_TV1 1 -#define CLK_TCON_TOP_DSI 2 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h deleted file mode 100644 index 014ac6123d17..000000000000 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng icenowy@aosc.xyz - * - * Based on sun8i-h3-ccu.h, which is: - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ -#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ - -#define CLK_CPU 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_DRAM 25 -#define CLK_BUS_EMAC 26 -#define CLK_BUS_HSTIMER 27 -#define CLK_BUS_SPI0 28 -#define CLK_BUS_OTG 29 -#define CLK_BUS_EHCI0 30 -#define CLK_BUS_OHCI0 31 -#define CLK_BUS_VE 32 -#define CLK_BUS_TCON0 33 -#define CLK_BUS_CSI 34 -#define CLK_BUS_DE 35 -#define CLK_BUS_CODEC 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_I2C0 38 -#define CLK_BUS_I2C1 39 -#define CLK_BUS_UART0 40 -#define CLK_BUS_UART1 41 -#define CLK_BUS_UART2 42 -#define CLK_BUS_EPHY 43 -#define CLK_BUS_DBG 44 - -#define CLK_MMC0 45 -#define CLK_MMC0_SAMPLE 46 -#define CLK_MMC0_OUTPUT 47 -#define CLK_MMC1 48 -#define CLK_MMC1_SAMPLE 49 -#define CLK_MMC1_OUTPUT 50 -#define CLK_MMC2 51 -#define CLK_MMC2_SAMPLE 52 -#define CLK_MMC2_OUTPUT 53 -#define CLK_CE 54 -#define CLK_SPI0 55 -#define CLK_USB_PHY0 56 -#define CLK_USB_OHCI0 57 - -#define CLK_DRAM_VE 59 -#define CLK_DRAM_CSI 60 -#define CLK_DRAM_EHCI 61 -#define CLK_DRAM_OHCI 62 -#define CLK_DE 63 -#define CLK_TCON0 64 -#define CLK_CSI_MISC 65 -#define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_VE 69 -#define CLK_AC_DIG 70 -#define CLK_AVS 71 - -#define CLK_MIPI_CSI 73 - -/* Clocks not available on V3s */ -#define CLK_BUS_I2S0 75 -#define CLK_I2S0 76 - -#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h deleted file mode 100644 index 6ea1492a73a6..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-ccu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ - -#define CLK_PLL_AUDIO 2 -#define CLK_PLL_PERIPH0 3 - -#define CLK_C0CPUX 12 -#define CLK_C1CPUX 13 - -#define CLK_OUT_A 27 -#define CLK_OUT_B 28 - -#define CLK_NAND0_0 29 -#define CLK_NAND0_1 30 -#define CLK_NAND1_0 31 -#define CLK_NAND1_1 32 -#define CLK_MMC0 33 -#define CLK_MMC0_SAMPLE 34 -#define CLK_MMC0_OUTPUT 35 -#define CLK_MMC1 36 -#define CLK_MMC1_SAMPLE 37 -#define CLK_MMC1_OUTPUT 38 -#define CLK_MMC2 39 -#define CLK_MMC2_SAMPLE 40 -#define CLK_MMC2_OUTPUT 41 -#define CLK_MMC3 42 -#define CLK_MMC3_SAMPLE 43 -#define CLK_MMC3_OUTPUT 44 -#define CLK_TS 45 -#define CLK_SS 46 -#define CLK_SPI0 47 -#define CLK_SPI1 48 -#define CLK_SPI2 49 -#define CLK_SPI3 50 -#define CLK_I2S0 51 -#define CLK_I2S1 52 -#define CLK_SPDIF 53 -#define CLK_SDRAM 54 -#define CLK_DE 55 -#define CLK_EDP 56 -#define CLK_MP 57 -#define CLK_LCD0 58 -#define CLK_LCD1 59 -#define CLK_MIPI_DSI0 60 -#define CLK_MIPI_DSI1 61 -#define CLK_HDMI 62 -#define CLK_HDMI_SLOW 63 -#define CLK_MIPI_CSI 64 -#define CLK_CSI_ISP 65 -#define CLK_CSI_MISC 66 -#define CLK_CSI0_MCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_FD 69 -#define CLK_VE 70 -#define CLK_AVS 71 -#define CLK_GPU_CORE 72 -#define CLK_GPU_MEMORY 73 -#define CLK_GPU_AXI 74 -#define CLK_SATA 75 -#define CLK_AC97 76 -#define CLK_MIPI_HSI 77 -#define CLK_GPADC 78 -#define CLK_CIR_TX 79 - -#define CLK_BUS_FD 80 -#define CLK_BUS_VE 81 -#define CLK_BUS_GPU_CTRL 82 -#define CLK_BUS_SS 83 -#define CLK_BUS_MMC 84 -#define CLK_BUS_NAND0 85 -#define CLK_BUS_NAND1 86 -#define CLK_BUS_SDRAM 87 -#define CLK_BUS_MIPI_HSI 88 -#define CLK_BUS_SATA 89 -#define CLK_BUS_TS 90 -#define CLK_BUS_SPI0 91 -#define CLK_BUS_SPI1 92 -#define CLK_BUS_SPI2 93 -#define CLK_BUS_SPI3 94 - -#define CLK_BUS_OTG 95 -#define CLK_BUS_USB 96 -#define CLK_BUS_GMAC 97 -#define CLK_BUS_MSGBOX 98 -#define CLK_BUS_SPINLOCK 99 -#define CLK_BUS_HSTIMER 100 -#define CLK_BUS_DMA 101 - -#define CLK_BUS_LCD0 102 -#define CLK_BUS_LCD1 103 -#define CLK_BUS_EDP 104 -#define CLK_BUS_CSI 105 -#define CLK_BUS_HDMI 106 -#define CLK_BUS_DE 107 -#define CLK_BUS_MP 108 -#define CLK_BUS_MIPI_DSI 109 - -#define CLK_BUS_SPDIF 110 -#define CLK_BUS_PIO 111 -#define CLK_BUS_AC97 112 -#define CLK_BUS_I2S0 113 -#define CLK_BUS_I2S1 114 -#define CLK_BUS_LRADC 115 -#define CLK_BUS_GPADC 116 -#define CLK_BUS_TWD 117 -#define CLK_BUS_CIR_TX 118 - -#define CLK_BUS_I2C0 119 -#define CLK_BUS_I2C1 120 -#define CLK_BUS_I2C2 121 -#define CLK_BUS_I2C3 122 -#define CLK_BUS_I2C4 123 -#define CLK_BUS_UART0 124 -#define CLK_BUS_UART1 125 -#define CLK_BUS_UART2 126 -#define CLK_BUS_UART3 127 -#define CLK_BUS_UART4 128 -#define CLK_BUS_UART5 129 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h deleted file mode 100644 index 3dad6c3cd131..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-de.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ - -#define CLK_FE0 0 -#define CLK_FE1 1 -#define CLK_FE2 2 -#define CLK_IEP_DEU0 3 -#define CLK_IEP_DEU1 4 -#define CLK_BE0 5 -#define CLK_BE1 6 -#define CLK_BE2 7 -#define CLK_IEP_DRC0 8 -#define CLK_IEP_DRC1 9 -#define CLK_MERGE 10 - -#define CLK_DRAM_FE0 11 -#define CLK_DRAM_FE1 12 -#define CLK_DRAM_FE2 13 -#define CLK_DRAM_DEU0 14 -#define CLK_DRAM_DEU1 15 -#define CLK_DRAM_BE0 16 -#define CLK_DRAM_BE1 17 -#define CLK_DRAM_BE2 18 -#define CLK_DRAM_DRC0 19 -#define CLK_DRAM_DRC1 20 - -#define CLK_BUS_FE0 21 -#define CLK_BUS_FE1 22 -#define CLK_BUS_FE2 23 -#define CLK_BUS_DEU0 24 -#define CLK_BUS_DEU1 25 -#define CLK_BUS_BE0 26 -#define CLK_BUS_BE1 27 -#define CLK_BUS_BE2 28 -#define CLK_BUS_DRC0 29 -#define CLK_BUS_DRC1 30 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h deleted file mode 100644 index 783a60d2ccea..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ - -#define CLK_BUS_HCI0 0 -#define CLK_USB_OHCI0 1 -#define CLK_BUS_HCI1 2 -#define CLK_BUS_HCI2 3 -#define CLK_USB_OHCI2 4 - -#define CLK_USB0_PHY 5 -#define CLK_USB1_HSIC 6 -#define CLK_USB1_PHY 7 -#define CLK_USB2_HSIC 8 -#define CLK_USB2_PHY 9 -#define CLK_USB_HSIC 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h deleted file mode 100644 index d7570765f424..000000000000 --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 Icenowy Zheng icenowy@aosc.xyz - * - */ - -#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ - -#define CLK_CPU 11 - -#define CLK_BUS_DMA 14 -#define CLK_BUS_MMC0 15 -#define CLK_BUS_MMC1 16 -#define CLK_BUS_DRAM 17 -#define CLK_BUS_SPI0 18 -#define CLK_BUS_SPI1 19 -#define CLK_BUS_OTG 20 -#define CLK_BUS_VE 21 -#define CLK_BUS_LCD 22 -#define CLK_BUS_DEINTERLACE 23 -#define CLK_BUS_CSI 24 -#define CLK_BUS_TVD 25 -#define CLK_BUS_TVE 26 -#define CLK_BUS_DE_BE 27 -#define CLK_BUS_DE_FE 28 -#define CLK_BUS_CODEC 29 -#define CLK_BUS_SPDIF 30 -#define CLK_BUS_IR 31 -#define CLK_BUS_RSB 32 -#define CLK_BUS_I2S0 33 -#define CLK_BUS_I2C0 34 -#define CLK_BUS_I2C1 35 -#define CLK_BUS_I2C2 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_UART0 38 -#define CLK_BUS_UART1 39 -#define CLK_BUS_UART2 40 - -#define CLK_MMC0 41 -#define CLK_MMC0_SAMPLE 42 -#define CLK_MMC0_OUTPUT 43 -#define CLK_MMC1 44 -#define CLK_MMC1_SAMPLE 45 -#define CLK_MMC1_OUTPUT 46 -#define CLK_I2S 47 -#define CLK_SPDIF 48 - -#define CLK_USB_PHY0 49 - -#define CLK_DRAM_VE 50 -#define CLK_DRAM_CSI 51 -#define CLK_DRAM_DEINTERLACE 52 -#define CLK_DRAM_TVD 53 -#define CLK_DRAM_DE_FE 54 -#define CLK_DRAM_DE_BE 55 - -#define CLK_DE_BE 56 -#define CLK_DE_FE 57 -#define CLK_TCON 58 -#define CLK_DEINTERLACE 59 -#define CLK_TVE2_CLK 60 -#define CLK_TVE1_CLK 61 -#define CLK_TVD 62 -#define CLK_CSI 63 -#define CLK_VE 64 -#define CLK_CODEC 65 -#define CLK_AVS 66 - -#define CLK_IR 67 - -#endif

Drop in favour of dts/upstream.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/imx5-clock.h | 219 ------------- include/dt-bindings/clock/imx6qdl-clock.h | 278 ----------------- include/dt-bindings/clock/imx6sl-clock.h | 178 ----------- include/dt-bindings/clock/imx6sll-clock.h | 210 ------------- include/dt-bindings/clock/imx6sx-clock.h | 281 ----------------- include/dt-bindings/clock/imx6ul-clock.h | 262 ---------------- include/dt-bindings/clock/imx7d-clock.h | 456 ---------------------------- include/dt-bindings/clock/imx7ulp-clock.h | 119 -------- include/dt-bindings/clock/imx8mm-clock.h | 286 ----------------- include/dt-bindings/clock/imx8mn-clock.h | 262 ---------------- include/dt-bindings/clock/imx8mp-clock.h | 401 ------------------------ include/dt-bindings/clock/imx8mq-clock.h | 431 -------------------------- include/dt-bindings/clock/imx8ulp-clock.h | 258 ---------------- include/dt-bindings/clock/imx93-clock.h | 208 ------------- include/dt-bindings/clock/imxrt1050-clock.h | 72 ----- 15 files changed, 3921 deletions(-)

diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h deleted file mode 100644 index d382fc71aa83..000000000000 --- a/include/dt-bindings/clock/imx5-clock.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2013 Lucas Stach, Pengutronix l.stach@pengutronix.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX5_H -#define __DT_BINDINGS_CLOCK_IMX5_H - -#define IMX5_CLK_DUMMY 0 -#define IMX5_CLK_CKIL 1 -#define IMX5_CLK_OSC 2 -#define IMX5_CLK_CKIH1 3 -#define IMX5_CLK_CKIH2 4 -#define IMX5_CLK_AHB 5 -#define IMX5_CLK_IPG 6 -#define IMX5_CLK_AXI_A 7 -#define IMX5_CLK_AXI_B 8 -#define IMX5_CLK_UART_PRED 9 -#define IMX5_CLK_UART_ROOT 10 -#define IMX5_CLK_ESDHC_A_PRED 11 -#define IMX5_CLK_ESDHC_B_PRED 12 -#define IMX5_CLK_ESDHC_C_SEL 13 -#define IMX5_CLK_ESDHC_D_SEL 14 -#define IMX5_CLK_EMI_SEL 15 -#define IMX5_CLK_EMI_SLOW_PODF 16 -#define IMX5_CLK_NFC_PODF 17 -#define IMX5_CLK_ECSPI_PRED 18 -#define IMX5_CLK_ECSPI_PODF 19 -#define IMX5_CLK_USBOH3_PRED 20 -#define IMX5_CLK_USBOH3_PODF 21 -#define IMX5_CLK_USB_PHY_PRED 22 -#define IMX5_CLK_USB_PHY_PODF 23 -#define IMX5_CLK_CPU_PODF 24 -#define IMX5_CLK_DI_PRED 25 -#define IMX5_CLK_TVE_SEL 27 -#define IMX5_CLK_UART1_IPG_GATE 28 -#define IMX5_CLK_UART1_PER_GATE 29 -#define IMX5_CLK_UART2_IPG_GATE 30 -#define IMX5_CLK_UART2_PER_GATE 31 -#define IMX5_CLK_UART3_IPG_GATE 32 -#define IMX5_CLK_UART3_PER_GATE 33 -#define IMX5_CLK_I2C1_GATE 34 -#define IMX5_CLK_I2C2_GATE 35 -#define IMX5_CLK_GPT_IPG_GATE 36 -#define IMX5_CLK_PWM1_IPG_GATE 37 -#define IMX5_CLK_PWM1_HF_GATE 38 -#define IMX5_CLK_PWM2_IPG_GATE 39 -#define IMX5_CLK_PWM2_HF_GATE 40 -#define IMX5_CLK_GPT_HF_GATE 41 -#define IMX5_CLK_FEC_GATE 42 -#define IMX5_CLK_USBOH3_PER_GATE 43 -#define IMX5_CLK_ESDHC1_IPG_GATE 44 -#define IMX5_CLK_ESDHC2_IPG_GATE 45 -#define IMX5_CLK_ESDHC3_IPG_GATE 46 -#define IMX5_CLK_ESDHC4_IPG_GATE 47 -#define IMX5_CLK_SSI1_IPG_GATE 48 -#define IMX5_CLK_SSI2_IPG_GATE 49 -#define IMX5_CLK_SSI3_IPG_GATE 50 -#define IMX5_CLK_ECSPI1_IPG_GATE 51 -#define IMX5_CLK_ECSPI1_PER_GATE 52 -#define IMX5_CLK_ECSPI2_IPG_GATE 53 -#define IMX5_CLK_ECSPI2_PER_GATE 54 -#define IMX5_CLK_CSPI_IPG_GATE 55 -#define IMX5_CLK_SDMA_GATE 56 -#define IMX5_CLK_EMI_SLOW_GATE 57 -#define IMX5_CLK_IPU_SEL 58 -#define IMX5_CLK_IPU_GATE 59 -#define IMX5_CLK_NFC_GATE 60 -#define IMX5_CLK_IPU_DI1_GATE 61 -#define IMX5_CLK_VPU_SEL 62 -#define IMX5_CLK_VPU_GATE 63 -#define IMX5_CLK_VPU_REFERENCE_GATE 64 -#define IMX5_CLK_UART4_IPG_GATE 65 -#define IMX5_CLK_UART4_PER_GATE 66 -#define IMX5_CLK_UART5_IPG_GATE 67 -#define IMX5_CLK_UART5_PER_GATE 68 -#define IMX5_CLK_TVE_GATE 69 -#define IMX5_CLK_TVE_PRED 70 -#define IMX5_CLK_ESDHC1_PER_GATE 71 -#define IMX5_CLK_ESDHC2_PER_GATE 72 -#define IMX5_CLK_ESDHC3_PER_GATE 73 -#define IMX5_CLK_ESDHC4_PER_GATE 74 -#define IMX5_CLK_USB_PHY_GATE 75 -#define IMX5_CLK_HSI2C_GATE 76 -#define IMX5_CLK_MIPI_HSC1_GATE 77 -#define IMX5_CLK_MIPI_HSC2_GATE 78 -#define IMX5_CLK_MIPI_ESC_GATE 79 -#define IMX5_CLK_MIPI_HSP_GATE 80 -#define IMX5_CLK_LDB_DI1_DIV_3_5 81 -#define IMX5_CLK_LDB_DI1_DIV 82 -#define IMX5_CLK_LDB_DI0_DIV_3_5 83 -#define IMX5_CLK_LDB_DI0_DIV 84 -#define IMX5_CLK_LDB_DI1_GATE 85 -#define IMX5_CLK_CAN2_SERIAL_GATE 86 -#define IMX5_CLK_CAN2_IPG_GATE 87 -#define IMX5_CLK_I2C3_GATE 88 -#define IMX5_CLK_LP_APM 89 -#define IMX5_CLK_PERIPH_APM 90 -#define IMX5_CLK_MAIN_BUS 91 -#define IMX5_CLK_AHB_MAX 92 -#define IMX5_CLK_AIPS_TZ1 93 -#define IMX5_CLK_AIPS_TZ2 94 -#define IMX5_CLK_TMAX1 95 -#define IMX5_CLK_TMAX2 96 -#define IMX5_CLK_TMAX3 97 -#define IMX5_CLK_SPBA 98 -#define IMX5_CLK_UART_SEL 99 -#define IMX5_CLK_ESDHC_A_SEL 100 -#define IMX5_CLK_ESDHC_B_SEL 101 -#define IMX5_CLK_ESDHC_A_PODF 102 -#define IMX5_CLK_ESDHC_B_PODF 103 -#define IMX5_CLK_ECSPI_SEL 104 -#define IMX5_CLK_USBOH3_SEL 105 -#define IMX5_CLK_USB_PHY_SEL 106 -#define IMX5_CLK_IIM_GATE 107 -#define IMX5_CLK_USBOH3_GATE 108 -#define IMX5_CLK_EMI_FAST_GATE 109 -#define IMX5_CLK_IPU_DI0_GATE 110 -#define IMX5_CLK_GPC_DVFS 111 -#define IMX5_CLK_PLL1_SW 112 -#define IMX5_CLK_PLL2_SW 113 -#define IMX5_CLK_PLL3_SW 114 -#define IMX5_CLK_IPU_DI0_SEL 115 -#define IMX5_CLK_IPU_DI1_SEL 116 -#define IMX5_CLK_TVE_EXT_SEL 117 -#define IMX5_CLK_MX51_MIPI 118 -#define IMX5_CLK_PLL4_SW 119 -#define IMX5_CLK_LDB_DI1_SEL 120 -#define IMX5_CLK_DI_PLL4_PODF 121 -#define IMX5_CLK_LDB_DI0_SEL 122 -#define IMX5_CLK_LDB_DI0_GATE 123 -#define IMX5_CLK_USB_PHY1_GATE 124 -#define IMX5_CLK_USB_PHY2_GATE 125 -#define IMX5_CLK_PER_LP_APM 126 -#define IMX5_CLK_PER_PRED1 127 -#define IMX5_CLK_PER_PRED2 128 -#define IMX5_CLK_PER_PODF 129 -#define IMX5_CLK_PER_ROOT 130 -#define IMX5_CLK_SSI_APM 131 -#define IMX5_CLK_SSI1_ROOT_SEL 132 -#define IMX5_CLK_SSI2_ROOT_SEL 133 -#define IMX5_CLK_SSI3_ROOT_SEL 134 -#define IMX5_CLK_SSI_EXT1_SEL 135 -#define IMX5_CLK_SSI_EXT2_SEL 136 -#define IMX5_CLK_SSI_EXT1_COM_SEL 137 -#define IMX5_CLK_SSI_EXT2_COM_SEL 138 -#define IMX5_CLK_SSI1_ROOT_PRED 139 -#define IMX5_CLK_SSI1_ROOT_PODF 140 -#define IMX5_CLK_SSI2_ROOT_PRED 141 -#define IMX5_CLK_SSI2_ROOT_PODF 142 -#define IMX5_CLK_SSI_EXT1_PRED 143 -#define IMX5_CLK_SSI_EXT1_PODF 144 -#define IMX5_CLK_SSI_EXT2_PRED 145 -#define IMX5_CLK_SSI_EXT2_PODF 146 -#define IMX5_CLK_SSI1_ROOT_GATE 147 -#define IMX5_CLK_SSI2_ROOT_GATE 148 -#define IMX5_CLK_SSI3_ROOT_GATE 149 -#define IMX5_CLK_SSI_EXT1_GATE 150 -#define IMX5_CLK_SSI_EXT2_GATE 151 -#define IMX5_CLK_EPIT1_IPG_GATE 152 -#define IMX5_CLK_EPIT1_HF_GATE 153 -#define IMX5_CLK_EPIT2_IPG_GATE 154 -#define IMX5_CLK_EPIT2_HF_GATE 155 -#define IMX5_CLK_CAN_SEL 156 -#define IMX5_CLK_CAN1_SERIAL_GATE 157 -#define IMX5_CLK_CAN1_IPG_GATE 158 -#define IMX5_CLK_OWIRE_GATE 159 -#define IMX5_CLK_GPU3D_SEL 160 -#define IMX5_CLK_GPU2D_SEL 161 -#define IMX5_CLK_GPU3D_GATE 162 -#define IMX5_CLK_GPU2D_GATE 163 -#define IMX5_CLK_GARB_GATE 164 -#define IMX5_CLK_CKO1_SEL 165 -#define IMX5_CLK_CKO1_PODF 166 -#define IMX5_CLK_CKO1 167 -#define IMX5_CLK_CKO2_SEL 168 -#define IMX5_CLK_CKO2_PODF 169 -#define IMX5_CLK_CKO2 170 -#define IMX5_CLK_SRTC_GATE 171 -#define IMX5_CLK_PATA_GATE 172 -#define IMX5_CLK_SATA_GATE 173 -#define IMX5_CLK_SPDIF_XTAL_SEL 174 -#define IMX5_CLK_SPDIF0_SEL 175 -#define IMX5_CLK_SPDIF1_SEL 176 -#define IMX5_CLK_SPDIF0_PRED 177 -#define IMX5_CLK_SPDIF0_PODF 178 -#define IMX5_CLK_SPDIF1_PRED 179 -#define IMX5_CLK_SPDIF1_PODF 180 -#define IMX5_CLK_SPDIF0_COM_SEL 181 -#define IMX5_CLK_SPDIF1_COM_SEL 182 -#define IMX5_CLK_SPDIF0_GATE 183 -#define IMX5_CLK_SPDIF1_GATE 184 -#define IMX5_CLK_SPDIF_IPG_GATE 185 -#define IMX5_CLK_OCRAM 186 -#define IMX5_CLK_SAHARA_IPG_GATE 187 -#define IMX5_CLK_SATA_REF 188 -#define IMX5_CLK_STEP_SEL 189 -#define IMX5_CLK_CPU_PODF_SEL 190 -#define IMX5_CLK_ARM 191 -#define IMX5_CLK_FIRI_PRED 192 -#define IMX5_CLK_FIRI_SEL 193 -#define IMX5_CLK_FIRI_PODF 194 -#define IMX5_CLK_FIRI_SERIAL_GATE 195 -#define IMX5_CLK_FIRI_IPG_GATE 196 -#define IMX5_CLK_CSI0_MCLK1_PRED 197 -#define IMX5_CLK_CSI0_MCLK1_SEL 198 -#define IMX5_CLK_CSI0_MCLK1_PODF 199 -#define IMX5_CLK_CSI0_MCLK1_GATE 200 -#define IMX5_CLK_IEEE1588_PRED 201 -#define IMX5_CLK_IEEE1588_SEL 202 -#define IMX5_CLK_IEEE1588_PODF 203 -#define IMX5_CLK_IEEE1588_GATE 204 -#define IMX5_CLK_END 205 - -#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h deleted file mode 100644 index e20c43cc36f6..000000000000 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H -#define __DT_BINDINGS_CLOCK_IMX6QDL_H - -#define IMX6QDL_CLK_DUMMY 0 -#define IMX6QDL_CLK_CKIL 1 -#define IMX6QDL_CLK_CKIH 2 -#define IMX6QDL_CLK_OSC 3 -#define IMX6QDL_CLK_PLL2_PFD0_352M 4 -#define IMX6QDL_CLK_PLL2_PFD1_594M 5 -#define IMX6QDL_CLK_PLL2_PFD2_396M 6 -#define IMX6QDL_CLK_PLL3_PFD0_720M 7 -#define IMX6QDL_CLK_PLL3_PFD1_540M 8 -#define IMX6QDL_CLK_PLL3_PFD2_508M 9 -#define IMX6QDL_CLK_PLL3_PFD3_454M 10 -#define IMX6QDL_CLK_PLL2_198M 11 -#define IMX6QDL_CLK_PLL3_120M 12 -#define IMX6QDL_CLK_PLL3_80M 13 -#define IMX6QDL_CLK_PLL3_60M 14 -#define IMX6QDL_CLK_TWD 15 -#define IMX6QDL_CLK_STEP 16 -#define IMX6QDL_CLK_PLL1_SW 17 -#define IMX6QDL_CLK_PERIPH_PRE 18 -#define IMX6QDL_CLK_PERIPH2_PRE 19 -#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 -#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 -#define IMX6QDL_CLK_AXI_SEL 22 -#define IMX6QDL_CLK_ESAI_SEL 23 -#define IMX6QDL_CLK_ASRC_SEL 24 -#define IMX6QDL_CLK_SPDIF_SEL 25 -#define IMX6QDL_CLK_GPU2D_AXI 26 -#define IMX6QDL_CLK_GPU3D_AXI 27 -#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 -#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 -#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 -#define IMX6QDL_CLK_IPU1_SEL 31 -#define IMX6QDL_CLK_IPU2_SEL 32 -#define IMX6QDL_CLK_LDB_DI0_SEL 33 -#define IMX6QDL_CLK_LDB_DI1_SEL 34 -#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 -#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 -#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 -#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 -#define IMX6QDL_CLK_IPU1_DI0_SEL 39 -#define IMX6QDL_CLK_IPU1_DI1_SEL 40 -#define IMX6QDL_CLK_IPU2_DI0_SEL 41 -#define IMX6QDL_CLK_IPU2_DI1_SEL 42 -#define IMX6QDL_CLK_HSI_TX_SEL 43 -#define IMX6QDL_CLK_PCIE_AXI_SEL 44 -#define IMX6QDL_CLK_SSI1_SEL 45 -#define IMX6QDL_CLK_SSI2_SEL 46 -#define IMX6QDL_CLK_SSI3_SEL 47 -#define IMX6QDL_CLK_USDHC1_SEL 48 -#define IMX6QDL_CLK_USDHC2_SEL 49 -#define IMX6QDL_CLK_USDHC3_SEL 50 -#define IMX6QDL_CLK_USDHC4_SEL 51 -#define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 -#define IMX6QDL_CLK_VDO_AXI_SEL 55 -#define IMX6QDL_CLK_VPU_AXI_SEL 56 -#define IMX6QDL_CLK_CKO1_SEL 57 -#define IMX6QDL_CLK_PERIPH 58 -#define IMX6QDL_CLK_PERIPH2 59 -#define IMX6QDL_CLK_PERIPH_CLK2 60 -#define IMX6QDL_CLK_PERIPH2_CLK2 61 -#define IMX6QDL_CLK_IPG 62 -#define IMX6QDL_CLK_IPG_PER 63 -#define IMX6QDL_CLK_ESAI_PRED 64 -#define IMX6QDL_CLK_ESAI_PODF 65 -#define IMX6QDL_CLK_ASRC_PRED 66 -#define IMX6QDL_CLK_ASRC_PODF 67 -#define IMX6QDL_CLK_SPDIF_PRED 68 -#define IMX6QDL_CLK_SPDIF_PODF 69 -#define IMX6QDL_CLK_CAN_ROOT 70 -#define IMX6QDL_CLK_ECSPI_ROOT 71 -#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 -#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 -#define IMX6QDL_CLK_GPU3D_SHADER 74 -#define IMX6QDL_CLK_IPU1_PODF 75 -#define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 -#define IMX6QDL_CLK_IPU1_DI0_PRE 79 -#define IMX6QDL_CLK_IPU1_DI1_PRE 80 -#define IMX6QDL_CLK_IPU2_DI0_PRE 81 -#define IMX6QDL_CLK_IPU2_DI1_PRE 82 -#define IMX6QDL_CLK_HSI_TX_PODF 83 -#define IMX6QDL_CLK_SSI1_PRED 84 -#define IMX6QDL_CLK_SSI1_PODF 85 -#define IMX6QDL_CLK_SSI2_PRED 86 -#define IMX6QDL_CLK_SSI2_PODF 87 -#define IMX6QDL_CLK_SSI3_PRED 88 -#define IMX6QDL_CLK_SSI3_PODF 89 -#define IMX6QDL_CLK_UART_SERIAL_PODF 90 -#define IMX6QDL_CLK_USDHC1_PODF 91 -#define IMX6QDL_CLK_USDHC2_PODF 92 -#define IMX6QDL_CLK_USDHC3_PODF 93 -#define IMX6QDL_CLK_USDHC4_PODF 94 -#define IMX6QDL_CLK_ENFC_PRED 95 -#define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 -#define IMX6QDL_CLK_VPU_AXI_PODF 99 -#define IMX6QDL_CLK_CKO1_PODF 100 -#define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 -#define IMX6QDL_CLK_ARM 104 -#define IMX6QDL_CLK_AHB 105 -#define IMX6QDL_CLK_APBH_DMA 106 -#define IMX6QDL_CLK_ASRC 107 -#define IMX6QDL_CLK_CAN1_IPG 108 -#define IMX6QDL_CLK_CAN1_SERIAL 109 -#define IMX6QDL_CLK_CAN2_IPG 110 -#define IMX6QDL_CLK_CAN2_SERIAL 111 -#define IMX6QDL_CLK_ECSPI1 112 -#define IMX6QDL_CLK_ECSPI2 113 -#define IMX6QDL_CLK_ECSPI3 114 -#define IMX6QDL_CLK_ECSPI4 115 -#define IMX6Q_CLK_ECSPI5 116 -#define IMX6DL_CLK_I2C4 116 -#define IMX6QDL_CLK_ENET 117 -#define IMX6QDL_CLK_ESAI_EXTAL 118 -#define IMX6QDL_CLK_GPT_IPG 119 -#define IMX6QDL_CLK_GPT_IPG_PER 120 -#define IMX6QDL_CLK_GPU2D_CORE 121 -#define IMX6QDL_CLK_GPU3D_CORE 122 -#define IMX6QDL_CLK_HDMI_IAHB 123 -#define IMX6QDL_CLK_HDMI_ISFR 124 -#define IMX6QDL_CLK_I2C1 125 -#define IMX6QDL_CLK_I2C2 126 -#define IMX6QDL_CLK_I2C3 127 -#define IMX6QDL_CLK_IIM 128 -#define IMX6QDL_CLK_ENFC 129 -#define IMX6QDL_CLK_IPU1 130 -#define IMX6QDL_CLK_IPU1_DI0 131 -#define IMX6QDL_CLK_IPU1_DI1 132 -#define IMX6QDL_CLK_IPU2 133 -#define IMX6QDL_CLK_IPU2_DI0 134 -#define IMX6QDL_CLK_LDB_DI0 135 -#define IMX6QDL_CLK_LDB_DI1 136 -#define IMX6QDL_CLK_IPU2_DI1 137 -#define IMX6QDL_CLK_HSI_TX 138 -#define IMX6QDL_CLK_MLB 139 -#define IMX6QDL_CLK_MMDC_CH0_AXI 140 -#define IMX6QDL_CLK_MMDC_CH1_AXI 141 -#define IMX6QDL_CLK_OCRAM 142 -#define IMX6QDL_CLK_OPENVG_AXI 143 -#define IMX6QDL_CLK_PCIE_AXI 144 -#define IMX6QDL_CLK_PWM1 145 -#define IMX6QDL_CLK_PWM2 146 -#define IMX6QDL_CLK_PWM3 147 -#define IMX6QDL_CLK_PWM4 148 -#define IMX6QDL_CLK_PER1_BCH 149 -#define IMX6QDL_CLK_GPMI_BCH_APB 150 -#define IMX6QDL_CLK_GPMI_BCH 151 -#define IMX6QDL_CLK_GPMI_IO 152 -#define IMX6QDL_CLK_GPMI_APB 153 -#define IMX6QDL_CLK_SATA 154 -#define IMX6QDL_CLK_SDMA 155 -#define IMX6QDL_CLK_SPBA 156 -#define IMX6QDL_CLK_SSI1 157 -#define IMX6QDL_CLK_SSI2 158 -#define IMX6QDL_CLK_SSI3 159 -#define IMX6QDL_CLK_UART_IPG 160 -#define IMX6QDL_CLK_UART_SERIAL 161 -#define IMX6QDL_CLK_USBOH3 162 -#define IMX6QDL_CLK_USDHC1 163 -#define IMX6QDL_CLK_USDHC2 164 -#define IMX6QDL_CLK_USDHC3 165 -#define IMX6QDL_CLK_USDHC4 166 -#define IMX6QDL_CLK_VDO_AXI 167 -#define IMX6QDL_CLK_VPU_AXI 168 -#define IMX6QDL_CLK_CKO1 169 -#define IMX6QDL_CLK_PLL1_SYS 170 -#define IMX6QDL_CLK_PLL2_BUS 171 -#define IMX6QDL_CLK_PLL3_USB_OTG 172 -#define IMX6QDL_CLK_PLL4_AUDIO 173 -#define IMX6QDL_CLK_PLL5_VIDEO 174 -#define IMX6QDL_CLK_PLL8_MLB 175 -#define IMX6QDL_CLK_PLL7_USB_HOST 176 -#define IMX6QDL_CLK_PLL6_ENET 177 -#define IMX6QDL_CLK_SSI1_IPG 178 -#define IMX6QDL_CLK_SSI2_IPG 179 -#define IMX6QDL_CLK_SSI3_IPG 180 -#define IMX6QDL_CLK_ROM 181 -#define IMX6QDL_CLK_USBPHY1 182 -#define IMX6QDL_CLK_USBPHY2 183 -#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 -#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 -#define IMX6QDL_CLK_SATA_REF 186 -#define IMX6QDL_CLK_SATA_REF_100M 187 -#define IMX6QDL_CLK_PCIE_REF 188 -#define IMX6QDL_CLK_PCIE_REF_125M 189 -#define IMX6QDL_CLK_ENET_REF 190 -#define IMX6QDL_CLK_USBPHY1_GATE 191 -#define IMX6QDL_CLK_USBPHY2_GATE 192 -#define IMX6QDL_CLK_PLL4_POST_DIV 193 -#define IMX6QDL_CLK_PLL5_POST_DIV 194 -#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 -#define IMX6QDL_CLK_EIM_SLOW 196 -#define IMX6QDL_CLK_SPDIF 197 -#define IMX6QDL_CLK_CKO2_SEL 198 -#define IMX6QDL_CLK_CKO2_PODF 199 -#define IMX6QDL_CLK_CKO2 200 -#define IMX6QDL_CLK_CKO 201 -#define IMX6QDL_CLK_VDOA 202 -#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 -#define IMX6QDL_CLK_LVDS1_SEL 204 -#define IMX6QDL_CLK_LVDS2_SEL 205 -#define IMX6QDL_CLK_LVDS1_GATE 206 -#define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_MLB_SEL 259 -#define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_EPIT1 261 -#define IMX6QDL_CLK_EPIT2 262 -#define IMX6QDL_CLK_MMDC_P0_IPG 263 -#define IMX6QDL_CLK_DCIC1 264 -#define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 - -#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h deleted file mode 100644 index 31364d2caae6..000000000000 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H -#define __DT_BINDINGS_CLOCK_IMX6SL_H - -#define IMX6SL_CLK_DUMMY 0 -#define IMX6SL_CLK_CKIL 1 -#define IMX6SL_CLK_OSC 2 -#define IMX6SL_CLK_PLL1_SYS 3 -#define IMX6SL_CLK_PLL2_BUS 4 -#define IMX6SL_CLK_PLL3_USB_OTG 5 -#define IMX6SL_CLK_PLL4_AUDIO 6 -#define IMX6SL_CLK_PLL5_VIDEO 7 -#define IMX6SL_CLK_PLL6_ENET 8 -#define IMX6SL_CLK_PLL7_USB_HOST 9 -#define IMX6SL_CLK_USBPHY1 10 -#define IMX6SL_CLK_USBPHY2 11 -#define IMX6SL_CLK_USBPHY1_GATE 12 -#define IMX6SL_CLK_USBPHY2_GATE 13 -#define IMX6SL_CLK_PLL4_POST_DIV 14 -#define IMX6SL_CLK_PLL5_POST_DIV 15 -#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 -#define IMX6SL_CLK_ENET_REF 17 -#define IMX6SL_CLK_PLL2_PFD0 18 -#define IMX6SL_CLK_PLL2_PFD1 19 -#define IMX6SL_CLK_PLL2_PFD2 20 -#define IMX6SL_CLK_PLL3_PFD0 21 -#define IMX6SL_CLK_PLL3_PFD1 22 -#define IMX6SL_CLK_PLL3_PFD2 23 -#define IMX6SL_CLK_PLL3_PFD3 24 -#define IMX6SL_CLK_PLL2_198M 25 -#define IMX6SL_CLK_PLL3_120M 26 -#define IMX6SL_CLK_PLL3_80M 27 -#define IMX6SL_CLK_PLL3_60M 28 -#define IMX6SL_CLK_STEP 29 -#define IMX6SL_CLK_PLL1_SW 30 -#define IMX6SL_CLK_OCRAM_ALT_SEL 31 -#define IMX6SL_CLK_OCRAM_SEL 32 -#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 -#define IMX6SL_CLK_PRE_PERIPH_SEL 34 -#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 -#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 -#define IMX6SL_CLK_CSI_SEL 37 -#define IMX6SL_CLK_LCDIF_AXI_SEL 38 -#define IMX6SL_CLK_USDHC1_SEL 39 -#define IMX6SL_CLK_USDHC2_SEL 40 -#define IMX6SL_CLK_USDHC3_SEL 41 -#define IMX6SL_CLK_USDHC4_SEL 42 -#define IMX6SL_CLK_SSI1_SEL 43 -#define IMX6SL_CLK_SSI2_SEL 44 -#define IMX6SL_CLK_SSI3_SEL 45 -#define IMX6SL_CLK_PERCLK_SEL 46 -#define IMX6SL_CLK_PXP_AXI_SEL 47 -#define IMX6SL_CLK_EPDC_AXI_SEL 48 -#define IMX6SL_CLK_GPU2D_OVG_SEL 49 -#define IMX6SL_CLK_GPU2D_SEL 50 -#define IMX6SL_CLK_LCDIF_PIX_SEL 51 -#define IMX6SL_CLK_EPDC_PIX_SEL 52 -#define IMX6SL_CLK_SPDIF0_SEL 53 -#define IMX6SL_CLK_SPDIF1_SEL 54 -#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 -#define IMX6SL_CLK_ECSPI_SEL 56 -#define IMX6SL_CLK_UART_SEL 57 -#define IMX6SL_CLK_PERIPH 58 -#define IMX6SL_CLK_PERIPH2 59 -#define IMX6SL_CLK_OCRAM_PODF 60 -#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 -#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 -#define IMX6SL_CLK_IPG 63 -#define IMX6SL_CLK_CSI_PODF 64 -#define IMX6SL_CLK_LCDIF_AXI_PODF 65 -#define IMX6SL_CLK_USDHC1_PODF 66 -#define IMX6SL_CLK_USDHC2_PODF 67 -#define IMX6SL_CLK_USDHC3_PODF 68 -#define IMX6SL_CLK_USDHC4_PODF 69 -#define IMX6SL_CLK_SSI1_PRED 70 -#define IMX6SL_CLK_SSI1_PODF 71 -#define IMX6SL_CLK_SSI2_PRED 72 -#define IMX6SL_CLK_SSI2_PODF 73 -#define IMX6SL_CLK_SSI3_PRED 74 -#define IMX6SL_CLK_SSI3_PODF 75 -#define IMX6SL_CLK_PERCLK 76 -#define IMX6SL_CLK_PXP_AXI_PODF 77 -#define IMX6SL_CLK_EPDC_AXI_PODF 78 -#define IMX6SL_CLK_GPU2D_OVG_PODF 79 -#define IMX6SL_CLK_GPU2D_PODF 80 -#define IMX6SL_CLK_LCDIF_PIX_PRED 81 -#define IMX6SL_CLK_EPDC_PIX_PRED 82 -#define IMX6SL_CLK_LCDIF_PIX_PODF 83 -#define IMX6SL_CLK_EPDC_PIX_PODF 84 -#define IMX6SL_CLK_SPDIF0_PRED 85 -#define IMX6SL_CLK_SPDIF0_PODF 86 -#define IMX6SL_CLK_SPDIF1_PRED 87 -#define IMX6SL_CLK_SPDIF1_PODF 88 -#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 -#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 -#define IMX6SL_CLK_ECSPI_ROOT 91 -#define IMX6SL_CLK_UART_ROOT 92 -#define IMX6SL_CLK_AHB 93 -#define IMX6SL_CLK_MMDC_ROOT 94 -#define IMX6SL_CLK_ARM 95 -#define IMX6SL_CLK_ECSPI1 96 -#define IMX6SL_CLK_ECSPI2 97 -#define IMX6SL_CLK_ECSPI3 98 -#define IMX6SL_CLK_ECSPI4 99 -#define IMX6SL_CLK_EPIT1 100 -#define IMX6SL_CLK_EPIT2 101 -#define IMX6SL_CLK_EXTERN_AUDIO 102 -#define IMX6SL_CLK_GPT 103 -#define IMX6SL_CLK_GPT_SERIAL 104 -#define IMX6SL_CLK_GPU2D_OVG 105 -#define IMX6SL_CLK_I2C1 106 -#define IMX6SL_CLK_I2C2 107 -#define IMX6SL_CLK_I2C3 108 -#define IMX6SL_CLK_OCOTP 109 -#define IMX6SL_CLK_CSI 110 -#define IMX6SL_CLK_PXP_AXI 111 -#define IMX6SL_CLK_EPDC_AXI 112 -#define IMX6SL_CLK_LCDIF_AXI 113 -#define IMX6SL_CLK_LCDIF_PIX 114 -#define IMX6SL_CLK_EPDC_PIX 115 -#define IMX6SL_CLK_OCRAM 116 -#define IMX6SL_CLK_PWM1 117 -#define IMX6SL_CLK_PWM2 118 -#define IMX6SL_CLK_PWM3 119 -#define IMX6SL_CLK_PWM4 120 -#define IMX6SL_CLK_SDMA 121 -#define IMX6SL_CLK_SPDIF 122 -#define IMX6SL_CLK_SSI1 123 -#define IMX6SL_CLK_SSI2 124 -#define IMX6SL_CLK_SSI3 125 -#define IMX6SL_CLK_UART 126 -#define IMX6SL_CLK_UART_SERIAL 127 -#define IMX6SL_CLK_USBOH3 128 -#define IMX6SL_CLK_USDHC1 129 -#define IMX6SL_CLK_USDHC2 130 -#define IMX6SL_CLK_USDHC3 131 -#define IMX6SL_CLK_USDHC4 132 -#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 -#define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_ENET 135 -#define IMX6SL_CLK_LVDS1_SEL 136 -#define IMX6SL_CLK_LVDS1_OUT 137 -#define IMX6SL_CLK_LVDS1_IN 138 -#define IMX6SL_CLK_ANACLK1 139 -#define IMX6SL_PLL1_BYPASS_SRC 140 -#define IMX6SL_PLL2_BYPASS_SRC 141 -#define IMX6SL_PLL3_BYPASS_SRC 142 -#define IMX6SL_PLL4_BYPASS_SRC 143 -#define IMX6SL_PLL5_BYPASS_SRC 144 -#define IMX6SL_PLL6_BYPASS_SRC 145 -#define IMX6SL_PLL7_BYPASS_SRC 146 -#define IMX6SL_CLK_PLL1 147 -#define IMX6SL_CLK_PLL2 148 -#define IMX6SL_CLK_PLL3 149 -#define IMX6SL_CLK_PLL4 150 -#define IMX6SL_CLK_PLL5 151 -#define IMX6SL_CLK_PLL6 152 -#define IMX6SL_CLK_PLL7 153 -#define IMX6SL_PLL1_BYPASS 154 -#define IMX6SL_PLL2_BYPASS 155 -#define IMX6SL_PLL3_BYPASS 156 -#define IMX6SL_PLL4_BYPASS 157 -#define IMX6SL_PLL5_BYPASS 158 -#define IMX6SL_PLL6_BYPASS 159 -#define IMX6SL_PLL7_BYPASS 160 -#define IMX6SL_CLK_SSI1_IPG 161 -#define IMX6SL_CLK_SSI2_IPG 162 -#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_MMDC_P0_IPG 165 -#define IMX6SL_CLK_MMDC_P1_IPG 166 -#define IMX6SL_CLK_END 167 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h deleted file mode 100644 index 494fd0c37fb5..000000000000 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H -#define __DT_BINDINGS_CLOCK_IMX6SLL_H - -#define IMX6SLL_CLK_DUMMY 0 -#define IMX6SLL_CLK_CKIL 1 -#define IMX6SLL_CLK_OSC 2 -#define IMX6SLL_PLL1_BYPASS_SRC 3 -#define IMX6SLL_PLL2_BYPASS_SRC 4 -#define IMX6SLL_PLL3_BYPASS_SRC 5 -#define IMX6SLL_PLL4_BYPASS_SRC 6 -#define IMX6SLL_PLL5_BYPASS_SRC 7 -#define IMX6SLL_PLL6_BYPASS_SRC 8 -#define IMX6SLL_PLL7_BYPASS_SRC 9 -#define IMX6SLL_CLK_PLL1 10 -#define IMX6SLL_CLK_PLL2 11 -#define IMX6SLL_CLK_PLL3 12 -#define IMX6SLL_CLK_PLL4 13 -#define IMX6SLL_CLK_PLL5 14 -#define IMX6SLL_CLK_PLL6 15 -#define IMX6SLL_CLK_PLL7 16 -#define IMX6SLL_PLL1_BYPASS 17 -#define IMX6SLL_PLL2_BYPASS 18 -#define IMX6SLL_PLL3_BYPASS 19 -#define IMX6SLL_PLL4_BYPASS 20 -#define IMX6SLL_PLL5_BYPASS 21 -#define IMX6SLL_PLL6_BYPASS 22 -#define IMX6SLL_PLL7_BYPASS 23 -#define IMX6SLL_CLK_PLL1_SYS 24 -#define IMX6SLL_CLK_PLL2_BUS 25 -#define IMX6SLL_CLK_PLL3_USB_OTG 26 -#define IMX6SLL_CLK_PLL4_AUDIO 27 -#define IMX6SLL_CLK_PLL5_VIDEO 28 -#define IMX6SLL_CLK_PLL6_ENET 29 -#define IMX6SLL_CLK_PLL7_USB_HOST 30 -#define IMX6SLL_CLK_USBPHY1 31 -#define IMX6SLL_CLK_USBPHY2 32 -#define IMX6SLL_CLK_USBPHY1_GATE 33 -#define IMX6SLL_CLK_USBPHY2_GATE 34 -#define IMX6SLL_CLK_PLL2_PFD0 35 -#define IMX6SLL_CLK_PLL2_PFD1 36 -#define IMX6SLL_CLK_PLL2_PFD2 37 -#define IMX6SLL_CLK_PLL2_PFD3 38 -#define IMX6SLL_CLK_PLL3_PFD0 39 -#define IMX6SLL_CLK_PLL3_PFD1 40 -#define IMX6SLL_CLK_PLL3_PFD2 41 -#define IMX6SLL_CLK_PLL3_PFD3 42 -#define IMX6SLL_CLK_PLL4_POST_DIV 43 -#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 -#define IMX6SLL_CLK_PLL5_POST_DIV 45 -#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 -#define IMX6SLL_CLK_PLL2_198M 47 -#define IMX6SLL_CLK_PLL3_120M 48 -#define IMX6SLL_CLK_PLL3_80M 49 -#define IMX6SLL_CLK_PLL3_60M 50 -#define IMX6SLL_CLK_STEP 51 -#define IMX6SLL_CLK_PLL1_SW 52 -#define IMX6SLL_CLK_AXI_ALT_SEL 53 -#define IMX6SLL_CLK_AXI_SEL 54 -#define IMX6SLL_CLK_PERIPH_PRE 55 -#define IMX6SLL_CLK_PERIPH2_PRE 56 -#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 -#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 -#define IMX6SLL_CLK_PERCLK_SEL 59 -#define IMX6SLL_CLK_USDHC1_SEL 60 -#define IMX6SLL_CLK_USDHC2_SEL 61 -#define IMX6SLL_CLK_USDHC3_SEL 62 -#define IMX6SLL_CLK_SSI1_SEL 63 -#define IMX6SLL_CLK_SSI2_SEL 64 -#define IMX6SLL_CLK_SSI3_SEL 65 -#define IMX6SLL_CLK_PXP_SEL 66 -#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 -#define IMX6SLL_CLK_LCDIF_SEL 68 -#define IMX6SLL_CLK_EPDC_PRE_SEL 69 -#define IMX6SLL_CLK_SPDIF_SEL 70 -#define IMX6SLL_CLK_ECSPI_SEL 71 -#define IMX6SLL_CLK_UART_SEL 72 -#define IMX6SLL_CLK_ARM 73 -#define IMX6SLL_CLK_PERIPH 74 -#define IMX6SLL_CLK_PERIPH2 75 -#define IMX6SLL_CLK_PERIPH2_CLK2 76 -#define IMX6SLL_CLK_PERIPH_CLK2 77 -#define IMX6SLL_CLK_MMDC_PODF 78 -#define IMX6SLL_CLK_AXI_PODF 79 -#define IMX6SLL_CLK_AHB 80 -#define IMX6SLL_CLK_IPG 81 -#define IMX6SLL_CLK_PERCLK 82 -#define IMX6SLL_CLK_USDHC1_PODF 83 -#define IMX6SLL_CLK_USDHC2_PODF 84 -#define IMX6SLL_CLK_USDHC3_PODF 85 -#define IMX6SLL_CLK_SSI1_PRED 86 -#define IMX6SLL_CLK_SSI2_PRED 87 -#define IMX6SLL_CLK_SSI3_PRED 88 -#define IMX6SLL_CLK_SSI1_PODF 89 -#define IMX6SLL_CLK_SSI2_PODF 90 -#define IMX6SLL_CLK_SSI3_PODF 91 -#define IMX6SLL_CLK_PXP_PODF 92 -#define IMX6SLL_CLK_LCDIF_PRED 93 -#define IMX6SLL_CLK_LCDIF_PODF 94 -#define IMX6SLL_CLK_EPDC_SEL 95 -#define IMX6SLL_CLK_EPDC_PODF 96 -#define IMX6SLL_CLK_SPDIF_PRED 97 -#define IMX6SLL_CLK_SPDIF_PODF 98 -#define IMX6SLL_CLK_ECSPI_PODF 99 -#define IMX6SLL_CLK_UART_PODF 100 - -/* CCGR 0 */ -#define IMX6SLL_CLK_AIPSTZ1 101 -#define IMX6SLL_CLK_AIPSTZ2 102 -#define IMX6SLL_CLK_DCP 103 -#define IMX6SLL_CLK_UART2_IPG 104 -#define IMX6SLL_CLK_UART2_SERIAL 105 - -/* CCGR 1 */ -#define IMX6SLL_CLK_ECSPI1 106 -#define IMX6SLL_CLK_ECSPI2 107 -#define IMX6SLL_CLK_ECSPI3 108 -#define IMX6SLL_CLK_ECSPI4 109 -#define IMX6SLL_CLK_UART3_IPG 110 -#define IMX6SLL_CLK_UART3_SERIAL 111 -#define IMX6SLL_CLK_UART4_IPG 112 -#define IMX6SLL_CLK_UART4_SERIAL 113 -#define IMX6SLL_CLK_EPIT1 114 -#define IMX6SLL_CLK_EPIT2 115 -#define IMX6SLL_CLK_GPT_BUS 116 -#define IMX6SLL_CLK_GPT_SERIAL 117 - -/* CCGR2 */ -#define IMX6SLL_CLK_CSI 118 -#define IMX6SLL_CLK_I2C1 119 -#define IMX6SLL_CLK_I2C2 120 -#define IMX6SLL_CLK_I2C3 121 -#define IMX6SLL_CLK_OCOTP 122 -#define IMX6SLL_CLK_LCDIF_APB 123 -#define IMX6SLL_CLK_PXP 124 - -/* CCGR3 */ -#define IMX6SLL_CLK_UART5_IPG 125 -#define IMX6SLL_CLK_UART5_SERIAL 126 -#define IMX6SLL_CLK_EPDC_AXI 127 -#define IMX6SLL_CLK_EPDC_PIX 128 -#define IMX6SLL_CLK_LCDIF_PIX 129 -#define IMX6SLL_CLK_WDOG1 130 -#define IMX6SLL_CLK_MMDC_P0_FAST 131 -#define IMX6SLL_CLK_MMDC_P0_IPG 132 -#define IMX6SLL_CLK_OCRAM 133 - -/* CCGR4 */ -#define IMX6SLL_CLK_PWM1 134 -#define IMX6SLL_CLK_PWM2 135 -#define IMX6SLL_CLK_PWM3 136 -#define IMX6SLL_CLK_PWM4 137 - -/* CCGR 5 */ -#define IMX6SLL_CLK_ROM 138 -#define IMX6SLL_CLK_SDMA 139 -#define IMX6SLL_CLK_KPP 140 -#define IMX6SLL_CLK_WDOG2 141 -#define IMX6SLL_CLK_SPBA 142 -#define IMX6SLL_CLK_SPDIF 143 -#define IMX6SLL_CLK_SPDIF_GCLK 144 -#define IMX6SLL_CLK_SSI1 145 -#define IMX6SLL_CLK_SSI1_IPG 146 -#define IMX6SLL_CLK_SSI2 147 -#define IMX6SLL_CLK_SSI2_IPG 148 -#define IMX6SLL_CLK_SSI3 149 -#define IMX6SLL_CLK_SSI3_IPG 150 -#define IMX6SLL_CLK_UART1_IPG 151 -#define IMX6SLL_CLK_UART1_SERIAL 152 - -/* CCGR 6 */ -#define IMX6SLL_CLK_USBOH3 153 -#define IMX6SLL_CLK_USDHC1 154 -#define IMX6SLL_CLK_USDHC2 155 -#define IMX6SLL_CLK_USDHC3 156 - -#define IMX6SLL_CLK_IPP_DI0 157 -#define IMX6SLL_CLK_IPP_DI1 158 -#define IMX6SLL_CLK_LDB_DI0_SEL 159 -#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 -#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 -#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 -#define IMX6SLL_CLK_LDB_DI0 163 -#define IMX6SLL_CLK_LDB_DI1_SEL 164 -#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 -#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 -#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 -#define IMX6SLL_CLK_LDB_DI1 168 -#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 -#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 -#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 -#define IMX6SLL_CLK_EXTERN_AUDIO 172 - -#define IMX6SLL_CLK_GPIO1 173 -#define IMX6SLL_CLK_GPIO2 174 -#define IMX6SLL_CLK_GPIO3 175 -#define IMX6SLL_CLK_GPIO4 176 -#define IMX6SLL_CLK_GPIO5 177 -#define IMX6SLL_CLK_GPIO6 178 -#define IMX6SLL_CLK_MMDC_P1_IPG 179 - -#define IMX6SLL_CLK_END 180 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h deleted file mode 100644 index 1c64997d6196..000000000000 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ /dev/null @@ -1,281 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H -#define __DT_BINDINGS_CLOCK_IMX6SX_H - -#define IMX6SX_CLK_DUMMY 0 -#define IMX6SX_CLK_CKIL 1 -#define IMX6SX_CLK_CKIH 2 -#define IMX6SX_CLK_OSC 3 -#define IMX6SX_CLK_PLL1_SYS 4 -#define IMX6SX_CLK_PLL2_BUS 5 -#define IMX6SX_CLK_PLL3_USB_OTG 6 -#define IMX6SX_CLK_PLL4_AUDIO 7 -#define IMX6SX_CLK_PLL5_VIDEO 8 -#define IMX6SX_CLK_PLL6_ENET 9 -#define IMX6SX_CLK_PLL7_USB_HOST 10 -#define IMX6SX_CLK_USBPHY1 11 -#define IMX6SX_CLK_USBPHY2 12 -#define IMX6SX_CLK_USBPHY1_GATE 13 -#define IMX6SX_CLK_USBPHY2_GATE 14 -#define IMX6SX_CLK_PCIE_REF 15 -#define IMX6SX_CLK_PCIE_REF_125M 16 -#define IMX6SX_CLK_ENET_REF 17 -#define IMX6SX_CLK_PLL2_PFD0 18 -#define IMX6SX_CLK_PLL2_PFD1 19 -#define IMX6SX_CLK_PLL2_PFD2 20 -#define IMX6SX_CLK_PLL2_PFD3 21 -#define IMX6SX_CLK_PLL3_PFD0 22 -#define IMX6SX_CLK_PLL3_PFD1 23 -#define IMX6SX_CLK_PLL3_PFD2 24 -#define IMX6SX_CLK_PLL3_PFD3 25 -#define IMX6SX_CLK_PLL2_198M 26 -#define IMX6SX_CLK_PLL3_120M 27 -#define IMX6SX_CLK_PLL3_80M 28 -#define IMX6SX_CLK_PLL3_60M 29 -#define IMX6SX_CLK_TWD 30 -#define IMX6SX_CLK_PLL4_POST_DIV 31 -#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 -#define IMX6SX_CLK_PLL5_POST_DIV 33 -#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 -#define IMX6SX_CLK_STEP 35 -#define IMX6SX_CLK_PLL1_SW 36 -#define IMX6SX_CLK_OCRAM_SEL 37 -#define IMX6SX_CLK_PERIPH_PRE 38 -#define IMX6SX_CLK_PERIPH2_PRE 39 -#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 -#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 -#define IMX6SX_CLK_PCIE_AXI_SEL 42 -#define IMX6SX_CLK_GPU_AXI_SEL 43 -#define IMX6SX_CLK_GPU_CORE_SEL 44 -#define IMX6SX_CLK_EIM_SLOW_SEL 45 -#define IMX6SX_CLK_USDHC1_SEL 46 -#define IMX6SX_CLK_USDHC2_SEL 47 -#define IMX6SX_CLK_USDHC3_SEL 48 -#define IMX6SX_CLK_USDHC4_SEL 49 -#define IMX6SX_CLK_SSI1_SEL 50 -#define IMX6SX_CLK_SSI2_SEL 51 -#define IMX6SX_CLK_SSI3_SEL 52 -#define IMX6SX_CLK_QSPI1_SEL 53 -#define IMX6SX_CLK_PERCLK_SEL 54 -#define IMX6SX_CLK_VID_SEL 55 -#define IMX6SX_CLK_ESAI_SEL 56 -#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 -#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 -#define IMX6SX_CLK_CAN_SEL 59 -#define IMX6SX_CLK_UART_SEL 60 -#define IMX6SX_CLK_QSPI2_SEL 61 -#define IMX6SX_CLK_LDB_DI1_SEL 62 -#define IMX6SX_CLK_LDB_DI0_SEL 63 -#define IMX6SX_CLK_SPDIF_SEL 64 -#define IMX6SX_CLK_AUDIO_SEL 65 -#define IMX6SX_CLK_ENET_PRE_SEL 66 -#define IMX6SX_CLK_ENET_SEL 67 -#define IMX6SX_CLK_M4_PRE_SEL 68 -#define IMX6SX_CLK_M4_SEL 69 -#define IMX6SX_CLK_ECSPI_SEL 70 -#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 -#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 -#define IMX6SX_CLK_LCDIF1_SEL 73 -#define IMX6SX_CLK_LCDIF2_SEL 74 -#define IMX6SX_CLK_DISPLAY_SEL 75 -#define IMX6SX_CLK_CSI_SEL 76 -#define IMX6SX_CLK_CKO1_SEL 77 -#define IMX6SX_CLK_CKO2_SEL 78 -#define IMX6SX_CLK_CKO 79 -#define IMX6SX_CLK_PERIPH_CLK2 80 -#define IMX6SX_CLK_PERIPH2_CLK2 81 -#define IMX6SX_CLK_IPG 82 -#define IMX6SX_CLK_GPU_CORE_PODF 83 -#define IMX6SX_CLK_GPU_AXI_PODF 84 -#define IMX6SX_CLK_LCDIF1_PODF 85 -#define IMX6SX_CLK_QSPI1_PODF 86 -#define IMX6SX_CLK_EIM_SLOW_PODF 87 -#define IMX6SX_CLK_LCDIF2_PODF 88 -#define IMX6SX_CLK_PERCLK 89 -#define IMX6SX_CLK_VID_PODF 90 -#define IMX6SX_CLK_CAN_PODF 91 -#define IMX6SX_CLK_USDHC1_PODF 92 -#define IMX6SX_CLK_USDHC2_PODF 93 -#define IMX6SX_CLK_USDHC3_PODF 94 -#define IMX6SX_CLK_USDHC4_PODF 95 -#define IMX6SX_CLK_UART_PODF 96 -#define IMX6SX_CLK_ESAI_PRED 97 -#define IMX6SX_CLK_ESAI_PODF 98 -#define IMX6SX_CLK_SSI3_PRED 99 -#define IMX6SX_CLK_SSI3_PODF 100 -#define IMX6SX_CLK_SSI1_PRED 101 -#define IMX6SX_CLK_SSI1_PODF 102 -#define IMX6SX_CLK_QSPI2_PRED 103 -#define IMX6SX_CLK_QSPI2_PODF 104 -#define IMX6SX_CLK_SSI2_PRED 105 -#define IMX6SX_CLK_SSI2_PODF 106 -#define IMX6SX_CLK_SPDIF_PRED 107 -#define IMX6SX_CLK_SPDIF_PODF 108 -#define IMX6SX_CLK_AUDIO_PRED 109 -#define IMX6SX_CLK_AUDIO_PODF 110 -#define IMX6SX_CLK_ENET_PODF 111 -#define IMX6SX_CLK_M4_PODF 112 -#define IMX6SX_CLK_ECSPI_PODF 113 -#define IMX6SX_CLK_LCDIF1_PRED 114 -#define IMX6SX_CLK_LCDIF2_PRED 115 -#define IMX6SX_CLK_DISPLAY_PODF 116 -#define IMX6SX_CLK_CSI_PODF 117 -#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 -#define IMX6SX_CLK_LDB_DI0_DIV_7 119 -#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 -#define IMX6SX_CLK_LDB_DI1_DIV_7 121 -#define IMX6SX_CLK_CKO1_PODF 122 -#define IMX6SX_CLK_CKO2_PODF 123 -#define IMX6SX_CLK_PERIPH 124 -#define IMX6SX_CLK_PERIPH2 125 -#define IMX6SX_CLK_OCRAM 126 -#define IMX6SX_CLK_AHB 127 -#define IMX6SX_CLK_MMDC_PODF 128 -#define IMX6SX_CLK_ARM 129 -#define IMX6SX_CLK_AIPS_TZ1 130 -#define IMX6SX_CLK_AIPS_TZ2 131 -#define IMX6SX_CLK_APBH_DMA 132 -#define IMX6SX_CLK_ASRC_GATE 133 -#define IMX6SX_CLK_CAAM_MEM 134 -#define IMX6SX_CLK_CAAM_ACLK 135 -#define IMX6SX_CLK_CAAM_IPG 136 -#define IMX6SX_CLK_CAN1_IPG 137 -#define IMX6SX_CLK_CAN1_SERIAL 138 -#define IMX6SX_CLK_CAN2_IPG 139 -#define IMX6SX_CLK_CAN2_SERIAL 140 -#define IMX6SX_CLK_CPU_DEBUG 141 -#define IMX6SX_CLK_DCIC1 142 -#define IMX6SX_CLK_DCIC2 143 -#define IMX6SX_CLK_AIPS_TZ3 144 -#define IMX6SX_CLK_ECSPI1 145 -#define IMX6SX_CLK_ECSPI2 146 -#define IMX6SX_CLK_ECSPI3 147 -#define IMX6SX_CLK_ECSPI4 148 -#define IMX6SX_CLK_ECSPI5 149 -#define IMX6SX_CLK_EPIT1 150 -#define IMX6SX_CLK_EPIT2 151 -#define IMX6SX_CLK_ESAI_EXTAL 152 -#define IMX6SX_CLK_WAKEUP 153 -#define IMX6SX_CLK_GPT_BUS 154 -#define IMX6SX_CLK_GPT_SERIAL 155 -#define IMX6SX_CLK_GPU 156 -#define IMX6SX_CLK_OCRAM_S 157 -#define IMX6SX_CLK_CANFD 158 -#define IMX6SX_CLK_CSI 159 -#define IMX6SX_CLK_I2C1 160 -#define IMX6SX_CLK_I2C2 161 -#define IMX6SX_CLK_I2C3 162 -#define IMX6SX_CLK_OCOTP 163 -#define IMX6SX_CLK_IOMUXC 164 -#define IMX6SX_CLK_IPMUX1 165 -#define IMX6SX_CLK_IPMUX2 166 -#define IMX6SX_CLK_IPMUX3 167 -#define IMX6SX_CLK_TZASC1 168 -#define IMX6SX_CLK_LCDIF_APB 169 -#define IMX6SX_CLK_PXP_AXI 170 -#define IMX6SX_CLK_M4 171 -#define IMX6SX_CLK_ENET 172 -#define IMX6SX_CLK_DISPLAY_AXI 173 -#define IMX6SX_CLK_LCDIF2_PIX 174 -#define IMX6SX_CLK_LCDIF1_PIX 175 -#define IMX6SX_CLK_LDB_DI0 176 -#define IMX6SX_CLK_QSPI1 177 -#define IMX6SX_CLK_MLB 178 -#define IMX6SX_CLK_MMDC_P0_FAST 179 -#define IMX6SX_CLK_MMDC_P0_IPG 180 -#define IMX6SX_CLK_AXI 181 -#define IMX6SX_CLK_PCIE_AXI 182 -#define IMX6SX_CLK_QSPI2 183 -#define IMX6SX_CLK_PER1_BCH 184 -#define IMX6SX_CLK_PER2_MAIN 185 -#define IMX6SX_CLK_PWM1 186 -#define IMX6SX_CLK_PWM2 187 -#define IMX6SX_CLK_PWM3 188 -#define IMX6SX_CLK_PWM4 189 -#define IMX6SX_CLK_GPMI_BCH_APB 190 -#define IMX6SX_CLK_GPMI_BCH 191 -#define IMX6SX_CLK_GPMI_IO 192 -#define IMX6SX_CLK_GPMI_APB 193 -#define IMX6SX_CLK_ROM 194 -#define IMX6SX_CLK_SDMA 195 -#define IMX6SX_CLK_SPBA 196 -#define IMX6SX_CLK_SPDIF 197 -#define IMX6SX_CLK_SSI1_IPG 198 -#define IMX6SX_CLK_SSI2_IPG 199 -#define IMX6SX_CLK_SSI3_IPG 200 -#define IMX6SX_CLK_SSI1 201 -#define IMX6SX_CLK_SSI2 202 -#define IMX6SX_CLK_SSI3 203 -#define IMX6SX_CLK_UART_IPG 204 -#define IMX6SX_CLK_UART_SERIAL 205 -#define IMX6SX_CLK_SAI1 206 -#define IMX6SX_CLK_SAI2 207 -#define IMX6SX_CLK_USBOH3 208 -#define IMX6SX_CLK_USDHC1 209 -#define IMX6SX_CLK_USDHC2 210 -#define IMX6SX_CLK_USDHC3 211 -#define IMX6SX_CLK_USDHC4 212 -#define IMX6SX_CLK_EIM_SLOW 213 -#define IMX6SX_CLK_PWM8 214 -#define IMX6SX_CLK_VADC 215 -#define IMX6SX_CLK_GIS 216 -#define IMX6SX_CLK_I2C4 217 -#define IMX6SX_CLK_PWM5 218 -#define IMX6SX_CLK_PWM6 219 -#define IMX6SX_CLK_PWM7 220 -#define IMX6SX_CLK_CKO1 221 -#define IMX6SX_CLK_CKO2 222 -#define IMX6SX_CLK_IPP_DI0 223 -#define IMX6SX_CLK_IPP_DI1 224 -#define IMX6SX_CLK_ENET_AHB 225 -#define IMX6SX_CLK_OCRAM_PODF 226 -#define IMX6SX_CLK_GPT_3M 227 -#define IMX6SX_CLK_ENET_PTP 228 -#define IMX6SX_CLK_ENET_PTP_REF 229 -#define IMX6SX_CLK_ENET2_REF 230 -#define IMX6SX_CLK_ENET2_REF_125M 231 -#define IMX6SX_CLK_AUDIO 232 -#define IMX6SX_CLK_LVDS1_SEL 233 -#define IMX6SX_CLK_LVDS1_OUT 234 -#define IMX6SX_CLK_ASRC_IPG 235 -#define IMX6SX_CLK_ASRC_MEM 236 -#define IMX6SX_CLK_SAI1_IPG 237 -#define IMX6SX_CLK_SAI2_IPG 238 -#define IMX6SX_CLK_ESAI_IPG 239 -#define IMX6SX_CLK_ESAI_MEM 240 -#define IMX6SX_CLK_LVDS1_IN 241 -#define IMX6SX_CLK_ANACLK1 242 -#define IMX6SX_PLL1_BYPASS_SRC 243 -#define IMX6SX_PLL2_BYPASS_SRC 244 -#define IMX6SX_PLL3_BYPASS_SRC 245 -#define IMX6SX_PLL4_BYPASS_SRC 246 -#define IMX6SX_PLL5_BYPASS_SRC 247 -#define IMX6SX_PLL6_BYPASS_SRC 248 -#define IMX6SX_PLL7_BYPASS_SRC 249 -#define IMX6SX_CLK_PLL1 250 -#define IMX6SX_CLK_PLL2 251 -#define IMX6SX_CLK_PLL3 252 -#define IMX6SX_CLK_PLL4 253 -#define IMX6SX_CLK_PLL5 254 -#define IMX6SX_CLK_PLL6 255 -#define IMX6SX_CLK_PLL7 256 -#define IMX6SX_PLL1_BYPASS 257 -#define IMX6SX_PLL2_BYPASS 258 -#define IMX6SX_PLL3_BYPASS 259 -#define IMX6SX_PLL4_BYPASS 260 -#define IMX6SX_PLL5_BYPASS 261 -#define IMX6SX_PLL6_BYPASS 262 -#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_LVDS2_SEL 265 -#define IMX6SX_CLK_LVDS2_OUT 266 -#define IMX6SX_CLK_LVDS2_IN 267 -#define IMX6SX_CLK_ANACLK2 268 -#define IMX6SX_CLK_MMDC_P1_IPG 269 -#define IMX6SX_CLK_CLK_END 270 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h deleted file mode 100644 index 79094338e6f1..000000000000 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H -#define __DT_BINDINGS_CLOCK_IMX6UL_H - -#define IMX6UL_CLK_DUMMY 0 -#define IMX6UL_CLK_CKIL 1 -#define IMX6UL_CLK_CKIH 2 -#define IMX6UL_CLK_OSC 3 -#define IMX6UL_PLL1_BYPASS_SRC 4 -#define IMX6UL_PLL2_BYPASS_SRC 5 -#define IMX6UL_PLL3_BYPASS_SRC 6 -#define IMX6UL_PLL4_BYPASS_SRC 7 -#define IMX6UL_PLL5_BYPASS_SRC 8 -#define IMX6UL_PLL6_BYPASS_SRC 9 -#define IMX6UL_PLL7_BYPASS_SRC 10 -#define IMX6UL_CLK_PLL1 11 -#define IMX6UL_CLK_PLL2 12 -#define IMX6UL_CLK_PLL3 13 -#define IMX6UL_CLK_PLL4 14 -#define IMX6UL_CLK_PLL5 15 -#define IMX6UL_CLK_PLL6 16 -#define IMX6UL_CLK_PLL7 17 -#define IMX6UL_PLL1_BYPASS 18 -#define IMX6UL_PLL2_BYPASS 19 -#define IMX6UL_PLL3_BYPASS 20 -#define IMX6UL_PLL4_BYPASS 21 -#define IMX6UL_PLL5_BYPASS 22 -#define IMX6UL_PLL6_BYPASS 23 -#define IMX6UL_PLL7_BYPASS 24 -#define IMX6UL_CLK_PLL1_SYS 25 -#define IMX6UL_CLK_PLL2_BUS 26 -#define IMX6UL_CLK_PLL3_USB_OTG 27 -#define IMX6UL_CLK_PLL4_AUDIO 28 -#define IMX6UL_CLK_PLL5_VIDEO 29 -#define IMX6UL_CLK_PLL6_ENET 30 -#define IMX6UL_CLK_PLL7_USB_HOST 31 -#define IMX6UL_CLK_USBPHY1 32 -#define IMX6UL_CLK_USBPHY2 33 -#define IMX6UL_CLK_USBPHY1_GATE 34 -#define IMX6UL_CLK_USBPHY2_GATE 35 -#define IMX6UL_CLK_PLL2_PFD0 36 -#define IMX6UL_CLK_PLL2_PFD1 37 -#define IMX6UL_CLK_PLL2_PFD2 38 -#define IMX6UL_CLK_PLL2_PFD3 39 -#define IMX6UL_CLK_PLL3_PFD0 40 -#define IMX6UL_CLK_PLL3_PFD1 41 -#define IMX6UL_CLK_PLL3_PFD2 42 -#define IMX6UL_CLK_PLL3_PFD3 43 -#define IMX6UL_CLK_ENET_REF 44 -#define IMX6UL_CLK_ENET2_REF 45 -#define IMX6UL_CLK_ENET2_REF_125M 46 -#define IMX6UL_CLK_ENET_PTP_REF 47 -#define IMX6UL_CLK_ENET_PTP 48 -#define IMX6UL_CLK_PLL4_POST_DIV 49 -#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 -#define IMX6UL_CLK_PLL5_POST_DIV 51 -#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 -#define IMX6UL_CLK_PLL2_198M 53 -#define IMX6UL_CLK_PLL3_80M 54 -#define IMX6UL_CLK_PLL3_60M 55 -#define IMX6UL_CLK_STEP 56 -#define IMX6UL_CLK_PLL1_SW 57 -#define IMX6UL_CLK_AXI_ALT_SEL 58 -#define IMX6UL_CLK_AXI_SEL 59 -#define IMX6UL_CLK_PERIPH_PRE 60 -#define IMX6UL_CLK_PERIPH2_PRE 61 -#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 -#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 -#define IMX6UL_CLK_USDHC1_SEL 64 -#define IMX6UL_CLK_USDHC2_SEL 65 -#define IMX6UL_CLK_BCH_SEL 66 -#define IMX6UL_CLK_GPMI_SEL 67 -#define IMX6UL_CLK_EIM_SLOW_SEL 68 -#define IMX6UL_CLK_SPDIF_SEL 69 -#define IMX6UL_CLK_SAI1_SEL 70 -#define IMX6UL_CLK_SAI2_SEL 71 -#define IMX6UL_CLK_SAI3_SEL 72 -#define IMX6UL_CLK_LCDIF_PRE_SEL 73 -#define IMX6UL_CLK_SIM_PRE_SEL 74 -#define IMX6UL_CLK_LDB_DI0_SEL 75 -#define IMX6UL_CLK_LDB_DI1_SEL 76 -#define IMX6UL_CLK_ENFC_SEL 77 -#define IMX6UL_CLK_CAN_SEL 78 -#define IMX6UL_CLK_ECSPI_SEL 79 -#define IMX6UL_CLK_UART_SEL 80 -#define IMX6UL_CLK_QSPI1_SEL 81 -#define IMX6UL_CLK_PERCLK_SEL 82 -#define IMX6UL_CLK_LCDIF_SEL 83 -#define IMX6UL_CLK_SIM_SEL 84 -#define IMX6UL_CLK_PERIPH 85 -#define IMX6UL_CLK_PERIPH2 86 -#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 -#define IMX6UL_CLK_LDB_DI0_DIV_7 88 -#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 -#define IMX6UL_CLK_LDB_DI1_DIV_7 90 -#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 -#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 -#define IMX6UL_CLK_ARM 93 -#define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 -#define IMX6UL_CLK_AHB 96 -#define IMX6UL_CLK_MMDC_PODF 97 -#define IMX6UL_CLK_AXI_PODF 98 -#define IMX6UL_CLK_PERCLK 99 -#define IMX6UL_CLK_IPG 100 -#define IMX6UL_CLK_USDHC1_PODF 101 -#define IMX6UL_CLK_USDHC2_PODF 102 -#define IMX6UL_CLK_BCH_PODF 103 -#define IMX6UL_CLK_GPMI_PODF 104 -#define IMX6UL_CLK_EIM_SLOW_PODF 105 -#define IMX6UL_CLK_SPDIF_PRED 106 -#define IMX6UL_CLK_SPDIF_PODF 107 -#define IMX6UL_CLK_SAI1_PRED 108 -#define IMX6UL_CLK_SAI1_PODF 109 -#define IMX6UL_CLK_SAI2_PRED 110 -#define IMX6UL_CLK_SAI2_PODF 111 -#define IMX6UL_CLK_SAI3_PRED 112 -#define IMX6UL_CLK_SAI3_PODF 113 -#define IMX6UL_CLK_LCDIF_PRED 114 -#define IMX6UL_CLK_LCDIF_PODF 115 -#define IMX6UL_CLK_SIM_PODF 116 -#define IMX6UL_CLK_QSPI1_PDOF 117 -#define IMX6UL_CLK_ENFC_PRED 118 -#define IMX6UL_CLK_ENFC_PODF 119 -#define IMX6UL_CLK_CAN_PODF 120 -#define IMX6UL_CLK_ECSPI_PODF 121 -#define IMX6UL_CLK_UART_PODF 122 -#define IMX6UL_CLK_ADC1 123 -#define IMX6UL_CLK_ADC2 124 -#define IMX6UL_CLK_AIPSTZ1 125 -#define IMX6UL_CLK_AIPSTZ2 126 -#define IMX6UL_CLK_AIPSTZ3 127 -#define IMX6UL_CLK_APBHDMA 128 -#define IMX6UL_CLK_ASRC_IPG 129 -#define IMX6UL_CLK_ASRC_MEM 130 -#define IMX6UL_CLK_GPMI_BCH_APB 131 -#define IMX6UL_CLK_GPMI_BCH 132 -#define IMX6UL_CLK_GPMI_IO 133 -#define IMX6UL_CLK_GPMI_APB 134 -#define IMX6UL_CLK_CAAM_MEM 135 -#define IMX6UL_CLK_CAAM_ACLK 136 -#define IMX6UL_CLK_CAAM_IPG 137 -#define IMX6UL_CLK_CSI 138 -#define IMX6UL_CLK_ECSPI1 139 -#define IMX6UL_CLK_ECSPI2 140 -#define IMX6UL_CLK_ECSPI3 141 -#define IMX6UL_CLK_ECSPI4 142 -#define IMX6UL_CLK_EIM 143 -#define IMX6UL_CLK_ENET 144 -#define IMX6UL_CLK_ENET_AHB 145 -#define IMX6UL_CLK_EPIT1 146 -#define IMX6UL_CLK_EPIT2 147 -#define IMX6UL_CLK_CAN1_IPG 148 -#define IMX6UL_CLK_CAN1_SERIAL 149 -#define IMX6UL_CLK_CAN2_IPG 150 -#define IMX6UL_CLK_CAN2_SERIAL 151 -#define IMX6UL_CLK_GPT1_BUS 152 -#define IMX6UL_CLK_GPT1_SERIAL 153 -#define IMX6UL_CLK_GPT2_BUS 154 -#define IMX6UL_CLK_GPT2_SERIAL 155 -#define IMX6UL_CLK_I2C1 156 -#define IMX6UL_CLK_I2C2 157 -#define IMX6UL_CLK_I2C3 158 -#define IMX6UL_CLK_I2C4 159 -#define IMX6UL_CLK_IOMUXC 160 -#define IMX6UL_CLK_LCDIF_APB 161 -#define IMX6UL_CLK_LCDIF_PIX 162 -#define IMX6UL_CLK_MMDC_P0_FAST 163 -#define IMX6UL_CLK_MMDC_P0_IPG 164 -#define IMX6UL_CLK_OCOTP 165 -#define IMX6UL_CLK_OCRAM 166 -#define IMX6UL_CLK_PWM1 167 -#define IMX6UL_CLK_PWM2 168 -#define IMX6UL_CLK_PWM3 169 -#define IMX6UL_CLK_PWM4 170 -#define IMX6UL_CLK_PWM5 171 -#define IMX6UL_CLK_PWM6 172 -#define IMX6UL_CLK_PWM7 173 -#define IMX6UL_CLK_PWM8 174 -#define IMX6UL_CLK_PXP 175 -#define IMX6UL_CLK_QSPI 176 -#define IMX6UL_CLK_ROM 177 -#define IMX6UL_CLK_SAI1 178 -#define IMX6UL_CLK_SAI1_IPG 179 -#define IMX6UL_CLK_SAI2 180 -#define IMX6UL_CLK_SAI2_IPG 181 -#define IMX6UL_CLK_SAI3 182 -#define IMX6UL_CLK_SAI3_IPG 183 -#define IMX6UL_CLK_SDMA 184 -#define IMX6UL_CLK_SIM 185 -#define IMX6UL_CLK_SIM_S 186 -#define IMX6UL_CLK_SPBA 187 -#define IMX6UL_CLK_SPDIF 188 -#define IMX6UL_CLK_UART1_IPG 189 -#define IMX6UL_CLK_UART1_SERIAL 190 -#define IMX6UL_CLK_UART2_IPG 191 -#define IMX6UL_CLK_UART2_SERIAL 192 -#define IMX6UL_CLK_UART3_IPG 193 -#define IMX6UL_CLK_UART3_SERIAL 194 -#define IMX6UL_CLK_UART4_IPG 195 -#define IMX6UL_CLK_UART4_SERIAL 196 -#define IMX6UL_CLK_UART5_IPG 197 -#define IMX6UL_CLK_UART5_SERIAL 198 -#define IMX6UL_CLK_UART6_IPG 199 -#define IMX6UL_CLK_UART6_SERIAL 200 -#define IMX6UL_CLK_UART7_IPG 201 -#define IMX6UL_CLK_UART7_SERIAL 202 -#define IMX6UL_CLK_UART8_IPG 203 -#define IMX6UL_CLK_UART8_SERIAL 204 -#define IMX6UL_CLK_USBOH3 205 -#define IMX6UL_CLK_USDHC1 206 -#define IMX6UL_CLK_USDHC2 207 -#define IMX6UL_CLK_WDOG1 208 -#define IMX6UL_CLK_WDOG2 209 -#define IMX6UL_CLK_WDOG3 210 -#define IMX6UL_CLK_LDB_DI0 211 -#define IMX6UL_CLK_AXI 212 -#define IMX6UL_CLK_SPDIF_GCLK 213 -#define IMX6UL_CLK_GPT_3M 214 -#define IMX6UL_CLK_SIM2 215 -#define IMX6UL_CLK_SIM1 216 -#define IMX6UL_CLK_IPP_DI0 217 -#define IMX6UL_CLK_IPP_DI1 218 -#define IMX6UL_CA7_SECONDARY_SEL 219 -#define IMX6UL_CLK_PER_BCH 220 -#define IMX6UL_CLK_CSI_SEL 221 -#define IMX6UL_CLK_CSI_PODF 222 -#define IMX6UL_CLK_PLL3_120M 223 -#define IMX6UL_CLK_KPP 224 -#define IMX6ULL_CLK_ESAI_PRED 225 -#define IMX6ULL_CLK_ESAI_PODF 226 -#define IMX6ULL_CLK_ESAI_EXTAL 227 -#define IMX6ULL_CLK_ESAI_MEM 228 -#define IMX6ULL_CLK_ESAI_IPG 229 -#define IMX6ULL_CLK_DCP_CLK 230 -#define IMX6ULL_CLK_EPDC_PRE_SEL 231 -#define IMX6ULL_CLK_EPDC_SEL 232 -#define IMX6ULL_CLK_EPDC_PODF 233 -#define IMX6ULL_CLK_EPDC_ACLK 234 -#define IMX6ULL_CLK_EPDC_PIX 235 -#define IMX6ULL_CLK_ESAI_SEL 236 -#define IMX6UL_CLK_CKO1_SEL 237 -#define IMX6UL_CLK_CKO1_PODF 238 -#define IMX6UL_CLK_CKO1 239 -#define IMX6UL_CLK_CKO2_SEL 240 -#define IMX6UL_CLK_CKO2_PODF 241 -#define IMX6UL_CLK_CKO2 242 -#define IMX6UL_CLK_CKO 243 -#define IMX6UL_CLK_GPIO1 244 -#define IMX6UL_CLK_GPIO2 245 -#define IMX6UL_CLK_GPIO3 246 -#define IMX6UL_CLK_GPIO4 247 -#define IMX6UL_CLK_GPIO5 248 -#define IMX6UL_CLK_MMDC_P1_IPG 249 - -#define IMX6UL_CLK_END 250 - -#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h deleted file mode 100644 index 1d4c0dfe0202..000000000000 --- a/include/dt-bindings/clock/imx7d-clock.h +++ /dev/null @@ -1,456 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7D_H -#define __DT_BINDINGS_CLOCK_IMX7D_H - -#define IMX7D_OSC_24M_CLK 0 -#define IMX7D_PLL_ARM_MAIN 1 -#define IMX7D_PLL_ARM_MAIN_CLK 2 -#define IMX7D_PLL_ARM_MAIN_SRC 3 -#define IMX7D_PLL_ARM_MAIN_BYPASS 4 -#define IMX7D_PLL_SYS_MAIN 5 -#define IMX7D_PLL_SYS_MAIN_CLK 6 -#define IMX7D_PLL_SYS_MAIN_SRC 7 -#define IMX7D_PLL_SYS_MAIN_BYPASS 8 -#define IMX7D_PLL_SYS_MAIN_480M 9 -#define IMX7D_PLL_SYS_MAIN_240M 10 -#define IMX7D_PLL_SYS_MAIN_120M 11 -#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 -#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 -#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 -#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 -#define IMX7D_PLL_SYS_PFD0_196M 16 -#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 -#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 -#define IMX7D_PLL_SYS_PFD1_166M 19 -#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 -#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 -#define IMX7D_PLL_SYS_PFD2_135M 22 -#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 -#define IMX7D_PLL_SYS_PFD3_CLK 24 -#define IMX7D_PLL_SYS_PFD4_CLK 25 -#define IMX7D_PLL_SYS_PFD5_CLK 26 -#define IMX7D_PLL_SYS_PFD6_CLK 27 -#define IMX7D_PLL_SYS_PFD7_CLK 28 -#define IMX7D_PLL_ENET_MAIN 29 -#define IMX7D_PLL_ENET_MAIN_CLK 30 -#define IMX7D_PLL_ENET_MAIN_SRC 31 -#define IMX7D_PLL_ENET_MAIN_BYPASS 32 -#define IMX7D_PLL_ENET_MAIN_500M 33 -#define IMX7D_PLL_ENET_MAIN_250M 34 -#define IMX7D_PLL_ENET_MAIN_125M 35 -#define IMX7D_PLL_ENET_MAIN_100M 36 -#define IMX7D_PLL_ENET_MAIN_50M 37 -#define IMX7D_PLL_ENET_MAIN_40M 38 -#define IMX7D_PLL_ENET_MAIN_25M 39 -#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 -#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 -#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 -#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 -#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 -#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 -#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 -#define IMX7D_PLL_DRAM_MAIN 47 -#define IMX7D_PLL_DRAM_MAIN_CLK 48 -#define IMX7D_PLL_DRAM_MAIN_SRC 49 -#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 -#define IMX7D_PLL_DRAM_MAIN_533M 51 -#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 -#define IMX7D_PLL_AUDIO_MAIN 53 -#define IMX7D_PLL_AUDIO_MAIN_CLK 54 -#define IMX7D_PLL_AUDIO_MAIN_SRC 55 -#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 -#define IMX7D_PLL_VIDEO_MAIN_CLK 57 -#define IMX7D_PLL_VIDEO_MAIN 58 -#define IMX7D_PLL_VIDEO_MAIN_SRC 59 -#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 -#define IMX7D_USB_MAIN_480M_CLK 61 -#define IMX7D_ARM_A7_ROOT_CLK 62 -#define IMX7D_ARM_A7_ROOT_SRC 63 -#define IMX7D_ARM_A7_ROOT_CG 64 -#define IMX7D_ARM_A7_ROOT_DIV 65 -#define IMX7D_ARM_M4_ROOT_CLK 66 -#define IMX7D_ARM_M4_ROOT_SRC 67 -#define IMX7D_ARM_M4_ROOT_CG 68 -#define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ -#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ -#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ -#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ -#define IMX7D_MAIN_AXI_ROOT_CLK 74 -#define IMX7D_MAIN_AXI_ROOT_SRC 75 -#define IMX7D_MAIN_AXI_ROOT_CG 76 -#define IMX7D_MAIN_AXI_ROOT_DIV 77 -#define IMX7D_DISP_AXI_ROOT_CLK 78 -#define IMX7D_DISP_AXI_ROOT_SRC 79 -#define IMX7D_DISP_AXI_ROOT_CG 80 -#define IMX7D_DISP_AXI_ROOT_DIV 81 -#define IMX7D_ENET_AXI_ROOT_CLK 82 -#define IMX7D_ENET_AXI_ROOT_SRC 83 -#define IMX7D_ENET_AXI_ROOT_CG 84 -#define IMX7D_ENET_AXI_ROOT_DIV 85 -#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 -#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 -#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 -#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 -#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 -#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 -#define IMX7D_AHB_CHANNEL_ROOT_CG 92 -#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 -#define IMX7D_DRAM_PHYM_ROOT_CLK 94 -#define IMX7D_DRAM_PHYM_ROOT_SRC 95 -#define IMX7D_DRAM_PHYM_ROOT_CG 96 -#define IMX7D_DRAM_PHYM_ROOT_DIV 97 -#define IMX7D_DRAM_ROOT_CLK 98 -#define IMX7D_DRAM_ROOT_SRC 99 -#define IMX7D_DRAM_ROOT_CG 100 -#define IMX7D_DRAM_ROOT_DIV 101 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 -#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 -#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 -#define IMX7D_DRAM_ALT_ROOT_CLK 106 -#define IMX7D_DRAM_ALT_ROOT_SRC 107 -#define IMX7D_DRAM_ALT_ROOT_CG 108 -#define IMX7D_DRAM_ALT_ROOT_DIV 109 -#define IMX7D_USB_HSIC_ROOT_CLK 110 -#define IMX7D_USB_HSIC_ROOT_SRC 111 -#define IMX7D_USB_HSIC_ROOT_CG 112 -#define IMX7D_USB_HSIC_ROOT_DIV 113 -#define IMX7D_PCIE_CTRL_ROOT_CLK 114 -#define IMX7D_PCIE_CTRL_ROOT_SRC 115 -#define IMX7D_PCIE_CTRL_ROOT_CG 116 -#define IMX7D_PCIE_CTRL_ROOT_DIV 117 -#define IMX7D_PCIE_PHY_ROOT_CLK 118 -#define IMX7D_PCIE_PHY_ROOT_SRC 119 -#define IMX7D_PCIE_PHY_ROOT_CG 120 -#define IMX7D_PCIE_PHY_ROOT_DIV 121 -#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 -#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 -#define IMX7D_EPDC_PIXEL_ROOT_CG 124 -#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 -#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 -#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 -#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 -#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 -#define IMX7D_MIPI_DSI_ROOT_CLK 130 -#define IMX7D_MIPI_DSI_ROOT_SRC 131 -#define IMX7D_MIPI_DSI_ROOT_CG 132 -#define IMX7D_MIPI_DSI_ROOT_DIV 133 -#define IMX7D_MIPI_CSI_ROOT_CLK 134 -#define IMX7D_MIPI_CSI_ROOT_SRC 135 -#define IMX7D_MIPI_CSI_ROOT_CG 136 -#define IMX7D_MIPI_CSI_ROOT_DIV 137 -#define IMX7D_MIPI_DPHY_ROOT_CLK 138 -#define IMX7D_MIPI_DPHY_ROOT_SRC 139 -#define IMX7D_MIPI_DPHY_ROOT_CG 140 -#define IMX7D_MIPI_DPHY_ROOT_DIV 141 -#define IMX7D_SAI1_ROOT_CLK 142 -#define IMX7D_SAI1_ROOT_SRC 143 -#define IMX7D_SAI1_ROOT_CG 144 -#define IMX7D_SAI1_ROOT_DIV 145 -#define IMX7D_SAI2_ROOT_CLK 146 -#define IMX7D_SAI2_ROOT_SRC 147 -#define IMX7D_SAI2_ROOT_CG 148 -#define IMX7D_SAI2_ROOT_DIV 149 -#define IMX7D_SAI3_ROOT_CLK 150 -#define IMX7D_SAI3_ROOT_SRC 151 -#define IMX7D_SAI3_ROOT_CG 152 -#define IMX7D_SAI3_ROOT_DIV 153 -#define IMX7D_SPDIF_ROOT_CLK 154 -#define IMX7D_SPDIF_ROOT_SRC 155 -#define IMX7D_SPDIF_ROOT_CG 156 -#define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_IPG_ROOT_CLK 158 -#define IMX7D_ENET1_REF_ROOT_SRC 159 -#define IMX7D_ENET1_REF_ROOT_CG 160 -#define IMX7D_ENET1_REF_ROOT_DIV 161 -#define IMX7D_ENET1_TIME_ROOT_CLK 162 -#define IMX7D_ENET1_TIME_ROOT_SRC 163 -#define IMX7D_ENET1_TIME_ROOT_CG 164 -#define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_IPG_ROOT_CLK 166 -#define IMX7D_ENET2_REF_ROOT_SRC 167 -#define IMX7D_ENET2_REF_ROOT_CG 168 -#define IMX7D_ENET2_REF_ROOT_DIV 169 -#define IMX7D_ENET2_TIME_ROOT_CLK 170 -#define IMX7D_ENET2_TIME_ROOT_SRC 171 -#define IMX7D_ENET2_TIME_ROOT_CG 172 -#define IMX7D_ENET2_TIME_ROOT_DIV 173 -#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 -#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 -#define IMX7D_ENET_PHY_REF_ROOT_CG 176 -#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 -#define IMX7D_EIM_ROOT_CLK 178 -#define IMX7D_EIM_ROOT_SRC 179 -#define IMX7D_EIM_ROOT_CG 180 -#define IMX7D_EIM_ROOT_DIV 181 -#define IMX7D_NAND_ROOT_CLK 182 -#define IMX7D_NAND_ROOT_SRC 183 -#define IMX7D_NAND_ROOT_CG 184 -#define IMX7D_NAND_ROOT_DIV 185 -#define IMX7D_QSPI_ROOT_CLK 186 -#define IMX7D_QSPI_ROOT_SRC 187 -#define IMX7D_QSPI_ROOT_CG 188 -#define IMX7D_QSPI_ROOT_DIV 189 -#define IMX7D_USDHC1_ROOT_CLK 190 -#define IMX7D_USDHC1_ROOT_SRC 191 -#define IMX7D_USDHC1_ROOT_CG 192 -#define IMX7D_USDHC1_ROOT_DIV 193 -#define IMX7D_USDHC2_ROOT_CLK 194 -#define IMX7D_USDHC2_ROOT_SRC 195 -#define IMX7D_USDHC2_ROOT_CG 196 -#define IMX7D_USDHC2_ROOT_DIV 197 -#define IMX7D_USDHC3_ROOT_CLK 198 -#define IMX7D_USDHC3_ROOT_SRC 199 -#define IMX7D_USDHC3_ROOT_CG 200 -#define IMX7D_USDHC3_ROOT_DIV 201 -#define IMX7D_CAN1_ROOT_CLK 202 -#define IMX7D_CAN1_ROOT_SRC 203 -#define IMX7D_CAN1_ROOT_CG 204 -#define IMX7D_CAN1_ROOT_DIV 205 -#define IMX7D_CAN2_ROOT_CLK 206 -#define IMX7D_CAN2_ROOT_SRC 207 -#define IMX7D_CAN2_ROOT_CG 208 -#define IMX7D_CAN2_ROOT_DIV 209 -#define IMX7D_I2C1_ROOT_CLK 210 -#define IMX7D_I2C1_ROOT_SRC 211 -#define IMX7D_I2C1_ROOT_CG 212 -#define IMX7D_I2C1_ROOT_DIV 213 -#define IMX7D_I2C2_ROOT_CLK 214 -#define IMX7D_I2C2_ROOT_SRC 215 -#define IMX7D_I2C2_ROOT_CG 216 -#define IMX7D_I2C2_ROOT_DIV 217 -#define IMX7D_I2C3_ROOT_CLK 218 -#define IMX7D_I2C3_ROOT_SRC 219 -#define IMX7D_I2C3_ROOT_CG 220 -#define IMX7D_I2C3_ROOT_DIV 221 -#define IMX7D_I2C4_ROOT_CLK 222 -#define IMX7D_I2C4_ROOT_SRC 223 -#define IMX7D_I2C4_ROOT_CG 224 -#define IMX7D_I2C4_ROOT_DIV 225 -#define IMX7D_UART1_ROOT_CLK 226 -#define IMX7D_UART1_ROOT_SRC 227 -#define IMX7D_UART1_ROOT_CG 228 -#define IMX7D_UART1_ROOT_DIV 229 -#define IMX7D_UART2_ROOT_CLK 230 -#define IMX7D_UART2_ROOT_SRC 231 -#define IMX7D_UART2_ROOT_CG 232 -#define IMX7D_UART2_ROOT_DIV 233 -#define IMX7D_UART3_ROOT_CLK 234 -#define IMX7D_UART3_ROOT_SRC 235 -#define IMX7D_UART3_ROOT_CG 236 -#define IMX7D_UART3_ROOT_DIV 237 -#define IMX7D_UART4_ROOT_CLK 238 -#define IMX7D_UART4_ROOT_SRC 239 -#define IMX7D_UART4_ROOT_CG 240 -#define IMX7D_UART4_ROOT_DIV 241 -#define IMX7D_UART5_ROOT_CLK 242 -#define IMX7D_UART5_ROOT_SRC 243 -#define IMX7D_UART5_ROOT_CG 244 -#define IMX7D_UART5_ROOT_DIV 245 -#define IMX7D_UART6_ROOT_CLK 246 -#define IMX7D_UART6_ROOT_SRC 247 -#define IMX7D_UART6_ROOT_CG 248 -#define IMX7D_UART6_ROOT_DIV 249 -#define IMX7D_UART7_ROOT_CLK 250 -#define IMX7D_UART7_ROOT_SRC 251 -#define IMX7D_UART7_ROOT_CG 252 -#define IMX7D_UART7_ROOT_DIV 253 -#define IMX7D_ECSPI1_ROOT_CLK 254 -#define IMX7D_ECSPI1_ROOT_SRC 255 -#define IMX7D_ECSPI1_ROOT_CG 256 -#define IMX7D_ECSPI1_ROOT_DIV 257 -#define IMX7D_ECSPI2_ROOT_CLK 258 -#define IMX7D_ECSPI2_ROOT_SRC 259 -#define IMX7D_ECSPI2_ROOT_CG 260 -#define IMX7D_ECSPI2_ROOT_DIV 261 -#define IMX7D_ECSPI3_ROOT_CLK 262 -#define IMX7D_ECSPI3_ROOT_SRC 263 -#define IMX7D_ECSPI3_ROOT_CG 264 -#define IMX7D_ECSPI3_ROOT_DIV 265 -#define IMX7D_ECSPI4_ROOT_CLK 266 -#define IMX7D_ECSPI4_ROOT_SRC 267 -#define IMX7D_ECSPI4_ROOT_CG 268 -#define IMX7D_ECSPI4_ROOT_DIV 269 -#define IMX7D_PWM1_ROOT_CLK 270 -#define IMX7D_PWM1_ROOT_SRC 271 -#define IMX7D_PWM1_ROOT_CG 272 -#define IMX7D_PWM1_ROOT_DIV 273 -#define IMX7D_PWM2_ROOT_CLK 274 -#define IMX7D_PWM2_ROOT_SRC 275 -#define IMX7D_PWM2_ROOT_CG 276 -#define IMX7D_PWM2_ROOT_DIV 277 -#define IMX7D_PWM3_ROOT_CLK 278 -#define IMX7D_PWM3_ROOT_SRC 279 -#define IMX7D_PWM3_ROOT_CG 280 -#define IMX7D_PWM3_ROOT_DIV 281 -#define IMX7D_PWM4_ROOT_CLK 282 -#define IMX7D_PWM4_ROOT_SRC 283 -#define IMX7D_PWM4_ROOT_CG 284 -#define IMX7D_PWM4_ROOT_DIV 285 -#define IMX7D_FLEXTIMER1_ROOT_CLK 286 -#define IMX7D_FLEXTIMER1_ROOT_SRC 287 -#define IMX7D_FLEXTIMER1_ROOT_CG 288 -#define IMX7D_FLEXTIMER1_ROOT_DIV 289 -#define IMX7D_FLEXTIMER2_ROOT_CLK 290 -#define IMX7D_FLEXTIMER2_ROOT_SRC 291 -#define IMX7D_FLEXTIMER2_ROOT_CG 292 -#define IMX7D_FLEXTIMER2_ROOT_DIV 293 -#define IMX7D_SIM1_ROOT_CLK 294 -#define IMX7D_SIM1_ROOT_SRC 295 -#define IMX7D_SIM1_ROOT_CG 296 -#define IMX7D_SIM1_ROOT_DIV 297 -#define IMX7D_SIM2_ROOT_CLK 298 -#define IMX7D_SIM2_ROOT_SRC 299 -#define IMX7D_SIM2_ROOT_CG 300 -#define IMX7D_SIM2_ROOT_DIV 301 -#define IMX7D_GPT1_ROOT_CLK 302 -#define IMX7D_GPT1_ROOT_SRC 303 -#define IMX7D_GPT1_ROOT_CG 304 -#define IMX7D_GPT1_ROOT_DIV 305 -#define IMX7D_GPT2_ROOT_CLK 306 -#define IMX7D_GPT2_ROOT_SRC 307 -#define IMX7D_GPT2_ROOT_CG 308 -#define IMX7D_GPT2_ROOT_DIV 309 -#define IMX7D_GPT3_ROOT_CLK 310 -#define IMX7D_GPT3_ROOT_SRC 311 -#define IMX7D_GPT3_ROOT_CG 312 -#define IMX7D_GPT3_ROOT_DIV 313 -#define IMX7D_GPT4_ROOT_CLK 314 -#define IMX7D_GPT4_ROOT_SRC 315 -#define IMX7D_GPT4_ROOT_CG 316 -#define IMX7D_GPT4_ROOT_DIV 317 -#define IMX7D_TRACE_ROOT_CLK 318 -#define IMX7D_TRACE_ROOT_SRC 319 -#define IMX7D_TRACE_ROOT_CG 320 -#define IMX7D_TRACE_ROOT_DIV 321 -#define IMX7D_WDOG1_ROOT_CLK 322 -#define IMX7D_WDOG_ROOT_SRC 323 -#define IMX7D_WDOG_ROOT_CG 324 -#define IMX7D_WDOG_ROOT_DIV 325 -#define IMX7D_CSI_MCLK_ROOT_CLK 326 -#define IMX7D_CSI_MCLK_ROOT_SRC 327 -#define IMX7D_CSI_MCLK_ROOT_CG 328 -#define IMX7D_CSI_MCLK_ROOT_DIV 329 -#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 -#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 -#define IMX7D_AUDIO_MCLK_ROOT_CG 332 -#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 -#define IMX7D_WRCLK_ROOT_CLK 334 -#define IMX7D_WRCLK_ROOT_SRC 335 -#define IMX7D_WRCLK_ROOT_CG 336 -#define IMX7D_WRCLK_ROOT_DIV 337 -#define IMX7D_CLKO1_ROOT_SRC 338 -#define IMX7D_CLKO1_ROOT_CG 339 -#define IMX7D_CLKO1_ROOT_DIV 340 -#define IMX7D_CLKO2_ROOT_SRC 341 -#define IMX7D_CLKO2_ROOT_CG 342 -#define IMX7D_CLKO2_ROOT_DIV 343 -#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 -#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 -#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 -#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 -#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 -#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 -#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 -#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 -#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 -#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 -#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 -#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 -#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 -#define IMX7D_SAI1_ROOT_PRE_DIV 357 -#define IMX7D_SAI2_ROOT_PRE_DIV 358 -#define IMX7D_SAI3_ROOT_PRE_DIV 359 -#define IMX7D_SPDIF_ROOT_PRE_DIV 360 -#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 -#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 -#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 -#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 -#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 -#define IMX7D_EIM_ROOT_PRE_DIV 366 -#define IMX7D_NAND_ROOT_PRE_DIV 367 -#define IMX7D_QSPI_ROOT_PRE_DIV 368 -#define IMX7D_USDHC1_ROOT_PRE_DIV 369 -#define IMX7D_USDHC2_ROOT_PRE_DIV 370 -#define IMX7D_USDHC3_ROOT_PRE_DIV 371 -#define IMX7D_CAN1_ROOT_PRE_DIV 372 -#define IMX7D_CAN2_ROOT_PRE_DIV 373 -#define IMX7D_I2C1_ROOT_PRE_DIV 374 -#define IMX7D_I2C2_ROOT_PRE_DIV 375 -#define IMX7D_I2C3_ROOT_PRE_DIV 376 -#define IMX7D_I2C4_ROOT_PRE_DIV 377 -#define IMX7D_UART1_ROOT_PRE_DIV 378 -#define IMX7D_UART2_ROOT_PRE_DIV 379 -#define IMX7D_UART3_ROOT_PRE_DIV 380 -#define IMX7D_UART4_ROOT_PRE_DIV 381 -#define IMX7D_UART5_ROOT_PRE_DIV 382 -#define IMX7D_UART6_ROOT_PRE_DIV 383 -#define IMX7D_UART7_ROOT_PRE_DIV 384 -#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 -#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 -#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 -#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 -#define IMX7D_PWM1_ROOT_PRE_DIV 389 -#define IMX7D_PWM2_ROOT_PRE_DIV 390 -#define IMX7D_PWM3_ROOT_PRE_DIV 391 -#define IMX7D_PWM4_ROOT_PRE_DIV 392 -#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 -#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 -#define IMX7D_SIM1_ROOT_PRE_DIV 395 -#define IMX7D_SIM2_ROOT_PRE_DIV 396 -#define IMX7D_GPT1_ROOT_PRE_DIV 397 -#define IMX7D_GPT2_ROOT_PRE_DIV 398 -#define IMX7D_GPT3_ROOT_PRE_DIV 399 -#define IMX7D_GPT4_ROOT_PRE_DIV 400 -#define IMX7D_TRACE_ROOT_PRE_DIV 401 -#define IMX7D_WDOG_ROOT_PRE_DIV 402 -#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 -#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 -#define IMX7D_WRCLK_ROOT_PRE_DIV 405 -#define IMX7D_CLKO1_ROOT_PRE_DIV 406 -#define IMX7D_CLKO2_ROOT_PRE_DIV 407 -#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 -#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 -#define IMX7D_LVDS1_IN_CLK 410 -#define IMX7D_LVDS1_OUT_SEL 411 -#define IMX7D_LVDS1_OUT_CLK 412 -#define IMX7D_CLK_DUMMY 413 -#define IMX7D_GPT_3M_CLK 414 -#define IMX7D_OCRAM_CLK 415 -#define IMX7D_OCRAM_S_CLK 416 -#define IMX7D_WDOG2_ROOT_CLK 417 -#define IMX7D_WDOG3_ROOT_CLK 418 -#define IMX7D_WDOG4_ROOT_CLK 419 -#define IMX7D_SDMA_CORE_CLK 420 -#define IMX7D_USB1_MAIN_480M_CLK 421 -#define IMX7D_USB_CTRL_CLK 422 -#define IMX7D_USB_PHY1_CLK 423 -#define IMX7D_USB_PHY2_CLK 424 -#define IMX7D_IPG_ROOT_CLK 425 -#define IMX7D_SAI1_IPG_CLK 426 -#define IMX7D_SAI2_IPG_CLK 427 -#define IMX7D_SAI3_IPG_CLK 428 -#define IMX7D_PLL_AUDIO_TEST_DIV 429 -#define IMX7D_PLL_AUDIO_POST_DIV 430 -#define IMX7D_PLL_VIDEO_TEST_DIV 431 -#define IMX7D_PLL_VIDEO_POST_DIV 432 -#define IMX7D_MU_ROOT_CLK 433 -#define IMX7D_SEMA4_HS_ROOT_CLK 434 -#define IMX7D_PLL_DRAM_TEST_DIV 435 -#define IMX7D_ADC_ROOT_CLK 436 -#define IMX7D_CLK_ARM 437 -#define IMX7D_CKIL 438 -#define IMX7D_OCOTP_CLK 439 -#define IMX7D_NAND_RAWNAND_CLK 440 -#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_SNVS_CLK 442 -#define IMX7D_CAAM_CLK 443 -#define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_PXP_CLK 445 -#define IMX7D_CLK_END 446 -#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h deleted file mode 100644 index b58370d146e2..000000000000 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H -#define __DT_BINDINGS_CLOCK_IMX7ULP_H - -/* SCG1 */ - -#define IMX7ULP_CLK_DUMMY 0 -#define IMX7ULP_CLK_ROSC 1 -#define IMX7ULP_CLK_SOSC 2 -#define IMX7ULP_CLK_FIRC 3 -#define IMX7ULP_CLK_SPLL_PRE_SEL 4 -#define IMX7ULP_CLK_SPLL_PRE_DIV 5 -#define IMX7ULP_CLK_SPLL 6 -#define IMX7ULP_CLK_SPLL_POST_DIV1 7 -#define IMX7ULP_CLK_SPLL_POST_DIV2 8 -#define IMX7ULP_CLK_SPLL_PFD0 9 -#define IMX7ULP_CLK_SPLL_PFD1 10 -#define IMX7ULP_CLK_SPLL_PFD2 11 -#define IMX7ULP_CLK_SPLL_PFD3 12 -#define IMX7ULP_CLK_SPLL_PFD_SEL 13 -#define IMX7ULP_CLK_SPLL_SEL 14 -#define IMX7ULP_CLK_APLL_PRE_SEL 15 -#define IMX7ULP_CLK_APLL_PRE_DIV 16 -#define IMX7ULP_CLK_APLL 17 -#define IMX7ULP_CLK_APLL_POST_DIV1 18 -#define IMX7ULP_CLK_APLL_POST_DIV2 19 -#define IMX7ULP_CLK_APLL_PFD0 20 -#define IMX7ULP_CLK_APLL_PFD1 21 -#define IMX7ULP_CLK_APLL_PFD2 22 -#define IMX7ULP_CLK_APLL_PFD3 23 -#define IMX7ULP_CLK_APLL_PFD_SEL 24 -#define IMX7ULP_CLK_APLL_SEL 25 -#define IMX7ULP_CLK_UPLL 26 -#define IMX7ULP_CLK_SYS_SEL 27 -#define IMX7ULP_CLK_CORE_DIV 28 -#define IMX7ULP_CLK_BUS_DIV 29 -#define IMX7ULP_CLK_PLAT_DIV 30 -#define IMX7ULP_CLK_DDR_SEL 31 -#define IMX7ULP_CLK_DDR_DIV 32 -#define IMX7ULP_CLK_NIC_SEL 33 -#define IMX7ULP_CLK_NIC0_DIV 34 -#define IMX7ULP_CLK_GPU_DIV 35 -#define IMX7ULP_CLK_NIC1_DIV 36 -#define IMX7ULP_CLK_NIC1_BUS_DIV 37 -#define IMX7ULP_CLK_NIC1_EXT_DIV 38 -/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 - -#define IMX7ULP_CLK_CORE 46 -#define IMX7ULP_CLK_HSRUN_CORE 47 - -#define IMX7ULP_CLK_SCG1_END 48 - -/* PCC2 */ -#define IMX7ULP_CLK_DMA1 0 -#define IMX7ULP_CLK_RGPIO2P1 1 -#define IMX7ULP_CLK_FLEXBUS 2 -#define IMX7ULP_CLK_SEMA42_1 3 -#define IMX7ULP_CLK_DMA_MUX1 4 -#define IMX7ULP_CLK_CAAM 6 -#define IMX7ULP_CLK_LPTPM4 7 -#define IMX7ULP_CLK_LPTPM5 8 -#define IMX7ULP_CLK_LPIT1 9 -#define IMX7ULP_CLK_LPSPI2 10 -#define IMX7ULP_CLK_LPSPI3 11 -#define IMX7ULP_CLK_LPI2C4 12 -#define IMX7ULP_CLK_LPI2C5 13 -#define IMX7ULP_CLK_LPUART4 14 -#define IMX7ULP_CLK_LPUART5 15 -#define IMX7ULP_CLK_FLEXIO1 16 -#define IMX7ULP_CLK_USB0 17 -#define IMX7ULP_CLK_USB1 18 -#define IMX7ULP_CLK_USB_PHY 19 -#define IMX7ULP_CLK_USB_PL301 20 -#define IMX7ULP_CLK_USDHC0 21 -#define IMX7ULP_CLK_USDHC1 22 -#define IMX7ULP_CLK_WDG1 23 -#define IMX7ULP_CLK_WDG2 24 - -#define IMX7ULP_CLK_PCC2_END 25 - -/* PCC3 */ -#define IMX7ULP_CLK_LPTPM6 0 -#define IMX7ULP_CLK_LPTPM7 1 -#define IMX7ULP_CLK_LPI2C6 2 -#define IMX7ULP_CLK_LPI2C7 3 -#define IMX7ULP_CLK_LPUART6 4 -#define IMX7ULP_CLK_LPUART7 5 -#define IMX7ULP_CLK_VIU 6 -#define IMX7ULP_CLK_DSI 7 -#define IMX7ULP_CLK_LCDIF 8 -#define IMX7ULP_CLK_MMDC 9 -#define IMX7ULP_CLK_PCTLC 10 -#define IMX7ULP_CLK_PCTLD 11 -#define IMX7ULP_CLK_PCTLE 12 -#define IMX7ULP_CLK_PCTLF 13 -#define IMX7ULP_CLK_GPU3D 14 -#define IMX7ULP_CLK_GPU2D 15 - -#define IMX7ULP_CLK_PCC3_END 16 - -/* SMC1 */ -#define IMX7ULP_CLK_ARM 0 - -#define IMX7ULP_CLK_SMC1_END 1 - -#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h deleted file mode 100644 index 1f768b2eeb1a..000000000000 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H -#define __DT_BINDINGS_CLOCK_IMX8MM_H - -#define IMX8MM_CLK_DUMMY 0 -#define IMX8MM_CLK_32K 1 -#define IMX8MM_CLK_24M 2 -#define IMX8MM_OSC_HDMI_CLK 3 -#define IMX8MM_CLK_EXT1 4 -#define IMX8MM_CLK_EXT2 5 -#define IMX8MM_CLK_EXT3 6 -#define IMX8MM_CLK_EXT4 7 -#define IMX8MM_AUDIO_PLL1_REF_SEL 8 -#define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 -#define IMX8MM_DRAM_PLL_REF_SEL 11 -#define IMX8MM_GPU_PLL_REF_SEL 12 -#define IMX8MM_VPU_PLL_REF_SEL 13 -#define IMX8MM_ARM_PLL_REF_SEL 14 -#define IMX8MM_SYS_PLL1_REF_SEL 15 -#define IMX8MM_SYS_PLL2_REF_SEL 16 -#define IMX8MM_SYS_PLL3_REF_SEL 17 -#define IMX8MM_AUDIO_PLL1 18 -#define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 -#define IMX8MM_DRAM_PLL 21 -#define IMX8MM_GPU_PLL 22 -#define IMX8MM_VPU_PLL 23 -#define IMX8MM_ARM_PLL 24 -#define IMX8MM_SYS_PLL1 25 -#define IMX8MM_SYS_PLL2 26 -#define IMX8MM_SYS_PLL3 27 -#define IMX8MM_AUDIO_PLL1_BYPASS 28 -#define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 -#define IMX8MM_DRAM_PLL_BYPASS 31 -#define IMX8MM_GPU_PLL_BYPASS 32 -#define IMX8MM_VPU_PLL_BYPASS 33 -#define IMX8MM_ARM_PLL_BYPASS 34 -#define IMX8MM_SYS_PLL1_BYPASS 35 -#define IMX8MM_SYS_PLL2_BYPASS 36 -#define IMX8MM_SYS_PLL3_BYPASS 37 -#define IMX8MM_AUDIO_PLL1_OUT 38 -#define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 -#define IMX8MM_DRAM_PLL_OUT 41 -#define IMX8MM_GPU_PLL_OUT 42 -#define IMX8MM_VPU_PLL_OUT 43 -#define IMX8MM_ARM_PLL_OUT 44 -#define IMX8MM_SYS_PLL1_OUT 45 -#define IMX8MM_SYS_PLL2_OUT 46 -#define IMX8MM_SYS_PLL3_OUT 47 -#define IMX8MM_SYS_PLL1_40M 48 -#define IMX8MM_SYS_PLL1_80M 49 -#define IMX8MM_SYS_PLL1_100M 50 -#define IMX8MM_SYS_PLL1_133M 51 -#define IMX8MM_SYS_PLL1_160M 52 -#define IMX8MM_SYS_PLL1_200M 53 -#define IMX8MM_SYS_PLL1_266M 54 -#define IMX8MM_SYS_PLL1_400M 55 -#define IMX8MM_SYS_PLL1_800M 56 -#define IMX8MM_SYS_PLL2_50M 57 -#define IMX8MM_SYS_PLL2_100M 58 -#define IMX8MM_SYS_PLL2_125M 59 -#define IMX8MM_SYS_PLL2_166M 60 -#define IMX8MM_SYS_PLL2_200M 61 -#define IMX8MM_SYS_PLL2_250M 62 -#define IMX8MM_SYS_PLL2_333M 63 -#define IMX8MM_SYS_PLL2_500M 64 -#define IMX8MM_SYS_PLL2_1000M 65 - -/* core */ -#define IMX8MM_CLK_A53_SRC 66 -#define IMX8MM_CLK_M4_SRC 67 -#define IMX8MM_CLK_VPU_SRC 68 -#define IMX8MM_CLK_GPU3D_SRC 69 -#define IMX8MM_CLK_GPU2D_SRC 70 -#define IMX8MM_CLK_A53_CG 71 -#define IMX8MM_CLK_M4_CG 72 -#define IMX8MM_CLK_VPU_CG 73 -#define IMX8MM_CLK_GPU3D_CG 74 -#define IMX8MM_CLK_GPU2D_CG 75 -#define IMX8MM_CLK_A53_DIV 76 -#define IMX8MM_CLK_M4_DIV 77 -#define IMX8MM_CLK_VPU_DIV 78 -#define IMX8MM_CLK_GPU3D_DIV 79 -#define IMX8MM_CLK_GPU2D_DIV 80 - -/* bus */ -#define IMX8MM_CLK_MAIN_AXI 81 -#define IMX8MM_CLK_ENET_AXI 82 -#define IMX8MM_CLK_NAND_USDHC_BUS 83 -#define IMX8MM_CLK_VPU_BUS 84 -#define IMX8MM_CLK_DISP_AXI 85 -#define IMX8MM_CLK_DISP_APB 86 -#define IMX8MM_CLK_DISP_RTRM 87 -#define IMX8MM_CLK_USB_BUS 88 -#define IMX8MM_CLK_GPU_AXI 89 -#define IMX8MM_CLK_GPU_AHB 90 -#define IMX8MM_CLK_NOC 91 -#define IMX8MM_CLK_NOC_APB 92 - -#define IMX8MM_CLK_AHB 93 -#define IMX8MM_CLK_AUDIO_AHB 94 -#define IMX8MM_CLK_IPG_ROOT 95 -#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 - -#define IMX8MM_CLK_DRAM_ALT 97 -#define IMX8MM_CLK_DRAM_APB 98 -#define IMX8MM_CLK_VPU_G1 99 -#define IMX8MM_CLK_VPU_G2 100 -#define IMX8MM_CLK_DISP_DTRC 101 -#define IMX8MM_CLK_DISP_DC8000 102 -#define IMX8MM_CLK_PCIE1_CTRL 103 -#define IMX8MM_CLK_PCIE1_PHY 104 -#define IMX8MM_CLK_PCIE1_AUX 105 -#define IMX8MM_CLK_DC_PIXEL 106 -#define IMX8MM_CLK_LCDIF_PIXEL 107 -#define IMX8MM_CLK_SAI1 108 -#define IMX8MM_CLK_SAI2 109 -#define IMX8MM_CLK_SAI3 110 -#define IMX8MM_CLK_SAI4 111 -#define IMX8MM_CLK_SAI5 112 -#define IMX8MM_CLK_SAI6 113 -#define IMX8MM_CLK_SPDIF1 114 -#define IMX8MM_CLK_SPDIF2 115 -#define IMX8MM_CLK_ENET_REF 116 -#define IMX8MM_CLK_ENET_TIMER 117 -#define IMX8MM_CLK_ENET_PHY_REF 118 -#define IMX8MM_CLK_NAND 119 -#define IMX8MM_CLK_QSPI 120 -#define IMX8MM_CLK_USDHC1 121 -#define IMX8MM_CLK_USDHC2 122 -#define IMX8MM_CLK_I2C1 123 -#define IMX8MM_CLK_I2C2 124 -#define IMX8MM_CLK_I2C3 125 -#define IMX8MM_CLK_I2C4 126 -#define IMX8MM_CLK_UART1 127 -#define IMX8MM_CLK_UART2 128 -#define IMX8MM_CLK_UART3 129 -#define IMX8MM_CLK_UART4 130 -#define IMX8MM_CLK_USB_CORE_REF 131 -#define IMX8MM_CLK_USB_PHY_REF 132 -#define IMX8MM_CLK_ECSPI1 133 -#define IMX8MM_CLK_ECSPI2 134 -#define IMX8MM_CLK_PWM1 135 -#define IMX8MM_CLK_PWM2 136 -#define IMX8MM_CLK_PWM3 137 -#define IMX8MM_CLK_PWM4 138 -#define IMX8MM_CLK_GPT1 139 -#define IMX8MM_CLK_WDOG 140 -#define IMX8MM_CLK_WRCLK 141 -#define IMX8MM_CLK_DSI_CORE 142 -#define IMX8MM_CLK_DSI_PHY_REF 143 -#define IMX8MM_CLK_DSI_DBI 144 -#define IMX8MM_CLK_USDHC3 145 -#define IMX8MM_CLK_CSI1_CORE 146 -#define IMX8MM_CLK_CSI1_PHY_REF 147 -#define IMX8MM_CLK_CSI1_ESC 148 -#define IMX8MM_CLK_CSI2_CORE 149 -#define IMX8MM_CLK_CSI2_PHY_REF 150 -#define IMX8MM_CLK_CSI2_ESC 151 -#define IMX8MM_CLK_PCIE2_CTRL 152 -#define IMX8MM_CLK_PCIE2_PHY 153 -#define IMX8MM_CLK_PCIE2_AUX 154 -#define IMX8MM_CLK_ECSPI3 155 -#define IMX8MM_CLK_PDM 156 -#define IMX8MM_CLK_VPU_H1 157 -#define IMX8MM_CLK_CLKO1 158 - -#define IMX8MM_CLK_ECSPI1_ROOT 159 -#define IMX8MM_CLK_ECSPI2_ROOT 160 -#define IMX8MM_CLK_ECSPI3_ROOT 161 -#define IMX8MM_CLK_ENET1_ROOT 162 -#define IMX8MM_CLK_GPT1_ROOT 163 -#define IMX8MM_CLK_I2C1_ROOT 164 -#define IMX8MM_CLK_I2C2_ROOT 165 -#define IMX8MM_CLK_I2C3_ROOT 166 -#define IMX8MM_CLK_I2C4_ROOT 167 -#define IMX8MM_CLK_OCOTP_ROOT 168 -#define IMX8MM_CLK_PCIE1_ROOT 169 -#define IMX8MM_CLK_PWM1_ROOT 170 -#define IMX8MM_CLK_PWM2_ROOT 171 -#define IMX8MM_CLK_PWM3_ROOT 172 -#define IMX8MM_CLK_PWM4_ROOT 173 -#define IMX8MM_CLK_QSPI_ROOT 174 -#define IMX8MM_CLK_NAND_ROOT 175 -#define IMX8MM_CLK_SAI1_ROOT 176 -#define IMX8MM_CLK_SAI1_IPG 177 -#define IMX8MM_CLK_SAI2_ROOT 178 -#define IMX8MM_CLK_SAI2_IPG 179 -#define IMX8MM_CLK_SAI3_ROOT 180 -#define IMX8MM_CLK_SAI3_IPG 181 -#define IMX8MM_CLK_SAI4_ROOT 182 -#define IMX8MM_CLK_SAI4_IPG 183 -#define IMX8MM_CLK_SAI5_ROOT 184 -#define IMX8MM_CLK_SAI5_IPG 185 -#define IMX8MM_CLK_SAI6_ROOT 186 -#define IMX8MM_CLK_SAI6_IPG 187 -#define IMX8MM_CLK_UART1_ROOT 188 -#define IMX8MM_CLK_UART2_ROOT 189 -#define IMX8MM_CLK_UART3_ROOT 190 -#define IMX8MM_CLK_UART4_ROOT 191 -#define IMX8MM_CLK_USB1_CTRL_ROOT 192 -#define IMX8MM_CLK_GPU3D_ROOT 193 -#define IMX8MM_CLK_USDHC1_ROOT 194 -#define IMX8MM_CLK_USDHC2_ROOT 195 -#define IMX8MM_CLK_WDOG1_ROOT 196 -#define IMX8MM_CLK_WDOG2_ROOT 197 -#define IMX8MM_CLK_WDOG3_ROOT 198 -#define IMX8MM_CLK_VPU_G1_ROOT 199 -#define IMX8MM_CLK_GPU_BUS_ROOT 200 -#define IMX8MM_CLK_VPU_H1_ROOT 201 -#define IMX8MM_CLK_VPU_G2_ROOT 202 -#define IMX8MM_CLK_PDM_ROOT 203 -#define IMX8MM_CLK_DISP_ROOT 204 -#define IMX8MM_CLK_DISP_AXI_ROOT 205 -#define IMX8MM_CLK_DISP_APB_ROOT 206 -#define IMX8MM_CLK_DISP_RTRM_ROOT 207 -#define IMX8MM_CLK_USDHC3_ROOT 208 -#define IMX8MM_CLK_TMU_ROOT 209 -#define IMX8MM_CLK_VPU_DEC_ROOT 210 -#define IMX8MM_CLK_SDMA1_ROOT 211 -#define IMX8MM_CLK_SDMA2_ROOT 212 -#define IMX8MM_CLK_SDMA3_ROOT 213 -#define IMX8MM_CLK_GPT_3M 214 -#define IMX8MM_CLK_ARM 215 -#define IMX8MM_CLK_PDM_IPG 216 -#define IMX8MM_CLK_GPU2D_ROOT 217 -#define IMX8MM_CLK_MU_ROOT 218 -#define IMX8MM_CLK_CSI1_ROOT 219 - -#define IMX8MM_CLK_DRAM_CORE 220 -#define IMX8MM_CLK_DRAM_ALT_ROOT 221 - -#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 - -#define IMX8MM_CLK_GPIO1_ROOT 223 -#define IMX8MM_CLK_GPIO2_ROOT 224 -#define IMX8MM_CLK_GPIO3_ROOT 225 -#define IMX8MM_CLK_GPIO4_ROOT 226 -#define IMX8MM_CLK_GPIO5_ROOT 227 - -#define IMX8MM_CLK_SNVS_ROOT 228 -#define IMX8MM_CLK_GIC 229 - -#define IMX8MM_SYS_PLL1_40M_CG 230 -#define IMX8MM_SYS_PLL1_80M_CG 231 -#define IMX8MM_SYS_PLL1_100M_CG 232 -#define IMX8MM_SYS_PLL1_133M_CG 233 -#define IMX8MM_SYS_PLL1_160M_CG 234 -#define IMX8MM_SYS_PLL1_200M_CG 235 -#define IMX8MM_SYS_PLL1_266M_CG 236 -#define IMX8MM_SYS_PLL1_400M_CG 237 -#define IMX8MM_SYS_PLL2_50M_CG 238 -#define IMX8MM_SYS_PLL2_100M_CG 239 -#define IMX8MM_SYS_PLL2_125M_CG 240 -#define IMX8MM_SYS_PLL2_166M_CG 241 -#define IMX8MM_SYS_PLL2_200M_CG 242 -#define IMX8MM_SYS_PLL2_250M_CG 243 -#define IMX8MM_SYS_PLL2_333M_CG 244 -#define IMX8MM_SYS_PLL2_500M_CG 245 - -#define IMX8MM_CLK_M4_CORE 246 -#define IMX8MM_CLK_VPU_CORE 247 -#define IMX8MM_CLK_GPU3D_CORE 248 -#define IMX8MM_CLK_GPU2D_CORE 249 - -#define IMX8MM_CLK_CLKO2 250 - -#define IMX8MM_CLK_A53_CORE 251 - -#define IMX8MM_CLK_CLKOUT1_SEL 252 -#define IMX8MM_CLK_CLKOUT1_DIV 253 -#define IMX8MM_CLK_CLKOUT1 254 -#define IMX8MM_CLK_CLKOUT2_SEL 255 -#define IMX8MM_CLK_CLKOUT2_DIV 256 -#define IMX8MM_CLK_CLKOUT2 257 - -#define IMX8MM_CLK_END 258 - -#endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h deleted file mode 100644 index 07b8a282c268..000000000000 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H -#define __DT_BINDINGS_CLOCK_IMX8MN_H - -#define IMX8MN_CLK_DUMMY 0 -#define IMX8MN_CLK_32K 1 -#define IMX8MN_CLK_24M 2 -#define IMX8MN_OSC_HDMI_CLK 3 -#define IMX8MN_CLK_EXT1 4 -#define IMX8MN_CLK_EXT2 5 -#define IMX8MN_CLK_EXT3 6 -#define IMX8MN_CLK_EXT4 7 -#define IMX8MN_AUDIO_PLL1_REF_SEL 8 -#define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 -#define IMX8MN_DRAM_PLL_REF_SEL 11 -#define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 -#define IMX8MN_ARM_PLL_REF_SEL 14 -#define IMX8MN_SYS_PLL1_REF_SEL 15 -#define IMX8MN_SYS_PLL2_REF_SEL 16 -#define IMX8MN_SYS_PLL3_REF_SEL 17 -#define IMX8MN_AUDIO_PLL1 18 -#define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 -#define IMX8MN_DRAM_PLL 21 -#define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 -#define IMX8MN_ARM_PLL 24 -#define IMX8MN_SYS_PLL1 25 -#define IMX8MN_SYS_PLL2 26 -#define IMX8MN_SYS_PLL3 27 -#define IMX8MN_AUDIO_PLL1_BYPASS 28 -#define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 -#define IMX8MN_DRAM_PLL_BYPASS 31 -#define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 -#define IMX8MN_ARM_PLL_BYPASS 34 -#define IMX8MN_SYS_PLL1_BYPASS 35 -#define IMX8MN_SYS_PLL2_BYPASS 36 -#define IMX8MN_SYS_PLL3_BYPASS 37 -#define IMX8MN_AUDIO_PLL1_OUT 38 -#define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 -#define IMX8MN_DRAM_PLL_OUT 41 -#define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 -#define IMX8MN_ARM_PLL_OUT 44 -#define IMX8MN_SYS_PLL1_OUT 45 -#define IMX8MN_SYS_PLL2_OUT 46 -#define IMX8MN_SYS_PLL3_OUT 47 -#define IMX8MN_SYS_PLL1_40M 48 -#define IMX8MN_SYS_PLL1_80M 49 -#define IMX8MN_SYS_PLL1_100M 50 -#define IMX8MN_SYS_PLL1_133M 51 -#define IMX8MN_SYS_PLL1_160M 52 -#define IMX8MN_SYS_PLL1_200M 53 -#define IMX8MN_SYS_PLL1_266M 54 -#define IMX8MN_SYS_PLL1_400M 55 -#define IMX8MN_SYS_PLL1_800M 56 -#define IMX8MN_SYS_PLL2_50M 57 -#define IMX8MN_SYS_PLL2_100M 58 -#define IMX8MN_SYS_PLL2_125M 59 -#define IMX8MN_SYS_PLL2_166M 60 -#define IMX8MN_SYS_PLL2_200M 61 -#define IMX8MN_SYS_PLL2_250M 62 -#define IMX8MN_SYS_PLL2_333M 63 -#define IMX8MN_SYS_PLL2_500M 64 -#define IMX8MN_SYS_PLL2_1000M 65 - -/* CORE CLOCK ROOT */ -#define IMX8MN_CLK_A53_SRC 66 -#define IMX8MN_CLK_GPU_CORE_SRC 67 -#define IMX8MN_CLK_GPU_SHADER_SRC 68 -#define IMX8MN_CLK_A53_CG 69 -#define IMX8MN_CLK_GPU_CORE_CG 70 -#define IMX8MN_CLK_GPU_SHADER_CG 71 -#define IMX8MN_CLK_A53_DIV 72 -#define IMX8MN_CLK_GPU_CORE_DIV 73 -#define IMX8MN_CLK_GPU_SHADER_DIV 74 - -/* BUS CLOCK ROOT */ -#define IMX8MN_CLK_MAIN_AXI 75 -#define IMX8MN_CLK_ENET_AXI 76 -#define IMX8MN_CLK_NAND_USDHC_BUS 77 -#define IMX8MN_CLK_DISP_AXI 78 -#define IMX8MN_CLK_DISP_APB 79 -#define IMX8MN_CLK_USB_BUS 80 -#define IMX8MN_CLK_GPU_AXI 81 -#define IMX8MN_CLK_GPU_AHB 82 -#define IMX8MN_CLK_NOC 83 -#define IMX8MN_CLK_AHB 84 -#define IMX8MN_CLK_AUDIO_AHB 85 - -/* IPG CLOCK ROOT */ -#define IMX8MN_CLK_IPG_ROOT 86 -#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 - -/* IP */ -#define IMX8MN_CLK_DRAM_CORE 88 -#define IMX8MN_CLK_DRAM_ALT 89 -#define IMX8MN_CLK_DRAM_APB 90 -#define IMX8MN_CLK_DRAM_ALT_ROOT 91 -#define IMX8MN_CLK_DISP_PIXEL 92 -#define IMX8MN_CLK_SAI2 93 -#define IMX8MN_CLK_SAI3 94 -#define IMX8MN_CLK_SAI5 95 -#define IMX8MN_CLK_SAI6 96 -#define IMX8MN_CLK_SPDIF1 97 -#define IMX8MN_CLK_ENET_REF 98 -#define IMX8MN_CLK_ENET_TIMER 99 -#define IMX8MN_CLK_ENET_PHY_REF 100 -#define IMX8MN_CLK_NAND 101 -#define IMX8MN_CLK_QSPI 102 -#define IMX8MN_CLK_USDHC1 103 -#define IMX8MN_CLK_USDHC2 104 -#define IMX8MN_CLK_I2C1 105 -#define IMX8MN_CLK_I2C2 106 -#define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 108 -#define IMX8MN_CLK_UART1 109 -#define IMX8MN_CLK_UART2 110 -#define IMX8MN_CLK_UART3 111 -#define IMX8MN_CLK_UART4 112 -#define IMX8MN_CLK_USB_CORE_REF 113 -#define IMX8MN_CLK_USB_PHY_REF 114 -#define IMX8MN_CLK_ECSPI1 115 -#define IMX8MN_CLK_ECSPI2 116 -#define IMX8MN_CLK_PWM1 117 -#define IMX8MN_CLK_PWM2 118 -#define IMX8MN_CLK_PWM3 119 -#define IMX8MN_CLK_PWM4 120 -#define IMX8MN_CLK_WDOG 121 -#define IMX8MN_CLK_WRCLK 122 -#define IMX8MN_CLK_CLKO1 123 -#define IMX8MN_CLK_CLKO2 124 -#define IMX8MN_CLK_DSI_CORE 125 -#define IMX8MN_CLK_DSI_PHY_REF 126 -#define IMX8MN_CLK_DSI_DBI 127 -#define IMX8MN_CLK_USDHC3 128 -#define IMX8MN_CLK_CAMERA_PIXEL 129 -#define IMX8MN_CLK_CSI1_PHY_REF 130 -#define IMX8MN_CLK_CSI2_PHY_REF 131 -#define IMX8MN_CLK_CSI2_ESC 132 -#define IMX8MN_CLK_ECSPI3 133 -#define IMX8MN_CLK_PDM 134 -#define IMX8MN_CLK_SAI7 135 - -#define IMX8MN_CLK_ECSPI1_ROOT 136 -#define IMX8MN_CLK_ECSPI2_ROOT 137 -#define IMX8MN_CLK_ECSPI3_ROOT 138 -#define IMX8MN_CLK_ENET1_ROOT 139 -#define IMX8MN_CLK_GPIO1_ROOT 140 -#define IMX8MN_CLK_GPIO2_ROOT 141 -#define IMX8MN_CLK_GPIO3_ROOT 142 -#define IMX8MN_CLK_GPIO4_ROOT 143 -#define IMX8MN_CLK_GPIO5_ROOT 144 -#define IMX8MN_CLK_I2C1_ROOT 145 -#define IMX8MN_CLK_I2C2_ROOT 146 -#define IMX8MN_CLK_I2C3_ROOT 147 -#define IMX8MN_CLK_I2C4_ROOT 148 -#define IMX8MN_CLK_MU_ROOT 149 -#define IMX8MN_CLK_OCOTP_ROOT 150 -#define IMX8MN_CLK_PWM1_ROOT 151 -#define IMX8MN_CLK_PWM2_ROOT 152 -#define IMX8MN_CLK_PWM3_ROOT 153 -#define IMX8MN_CLK_PWM4_ROOT 154 -#define IMX8MN_CLK_QSPI_ROOT 155 -#define IMX8MN_CLK_NAND_ROOT 156 -#define IMX8MN_CLK_SAI2_ROOT 157 -#define IMX8MN_CLK_SAI2_IPG 158 -#define IMX8MN_CLK_SAI3_ROOT 159 -#define IMX8MN_CLK_SAI3_IPG 160 -#define IMX8MN_CLK_SAI5_ROOT 161 -#define IMX8MN_CLK_SAI5_IPG 162 -#define IMX8MN_CLK_SAI6_ROOT 163 -#define IMX8MN_CLK_SAI6_IPG 164 -#define IMX8MN_CLK_SAI7_ROOT 165 -#define IMX8MN_CLK_SAI7_IPG 166 -#define IMX8MN_CLK_SDMA1_ROOT 167 -#define IMX8MN_CLK_SDMA2_ROOT 168 -#define IMX8MN_CLK_UART1_ROOT 169 -#define IMX8MN_CLK_UART2_ROOT 170 -#define IMX8MN_CLK_UART3_ROOT 171 -#define IMX8MN_CLK_UART4_ROOT 172 -#define IMX8MN_CLK_USB1_CTRL_ROOT 173 -#define IMX8MN_CLK_USDHC1_ROOT 174 -#define IMX8MN_CLK_USDHC2_ROOT 175 -#define IMX8MN_CLK_WDOG1_ROOT 176 -#define IMX8MN_CLK_WDOG2_ROOT 177 -#define IMX8MN_CLK_WDOG3_ROOT 178 -#define IMX8MN_CLK_GPU_BUS_ROOT 179 -#define IMX8MN_CLK_ASRC_ROOT 180 -#define IMX8MN_CLK_GPU3D_ROOT 181 -#define IMX8MN_CLK_PDM_ROOT 182 -#define IMX8MN_CLK_PDM_IPG 183 -#define IMX8MN_CLK_DISP_AXI_ROOT 184 -#define IMX8MN_CLK_DISP_APB_ROOT 185 -#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 -#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 -#define IMX8MN_CLK_USDHC3_ROOT 188 -#define IMX8MN_CLK_SDMA3_ROOT 189 -#define IMX8MN_CLK_TMU_ROOT 190 -#define IMX8MN_CLK_ARM 191 -#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 -#define IMX8MN_CLK_GPU_CORE_ROOT 193 -#define IMX8MN_CLK_GIC 194 - -#define IMX8MN_SYS_PLL1_40M_CG 195 -#define IMX8MN_SYS_PLL1_80M_CG 196 -#define IMX8MN_SYS_PLL1_100M_CG 197 -#define IMX8MN_SYS_PLL1_133M_CG 198 -#define IMX8MN_SYS_PLL1_160M_CG 199 -#define IMX8MN_SYS_PLL1_200M_CG 200 -#define IMX8MN_SYS_PLL1_266M_CG 201 -#define IMX8MN_SYS_PLL1_400M_CG 202 -#define IMX8MN_SYS_PLL2_50M_CG 203 -#define IMX8MN_SYS_PLL2_100M_CG 204 -#define IMX8MN_SYS_PLL2_125M_CG 205 -#define IMX8MN_SYS_PLL2_166M_CG 206 -#define IMX8MN_SYS_PLL2_200M_CG 207 -#define IMX8MN_SYS_PLL2_250M_CG 208 -#define IMX8MN_SYS_PLL2_333M_CG 209 -#define IMX8MN_SYS_PLL2_500M_CG 210 - -#define IMX8MN_CLK_SNVS_ROOT 211 -#define IMX8MN_CLK_GPU_CORE 212 -#define IMX8MN_CLK_GPU_SHADER 213 - -#define IMX8MN_CLK_A53_CORE 214 - -#define IMX8MN_CLK_CLKOUT1_SEL 215 -#define IMX8MN_CLK_CLKOUT1_DIV 216 -#define IMX8MN_CLK_CLKOUT1 217 -#define IMX8MN_CLK_CLKOUT2_SEL 218 -#define IMX8MN_CLK_CLKOUT2_DIV 219 -#define IMX8MN_CLK_CLKOUT2 220 - -#define IMX8MN_CLK_M7_CORE 221 - -#define IMX8MN_CLK_GPT_3M 222 -#define IMX8MN_CLK_GPT1 223 -#define IMX8MN_CLK_GPT1_ROOT 224 -#define IMX8MN_CLK_GPT2 225 -#define IMX8MN_CLK_GPT2_ROOT 226 -#define IMX8MN_CLK_GPT3 227 -#define IMX8MN_CLK_GPT3_ROOT 228 -#define IMX8MN_CLK_GPT4 229 -#define IMX8MN_CLK_GPT4_ROOT 230 -#define IMX8MN_CLK_GPT5 231 -#define IMX8MN_CLK_GPT5_ROOT 232 -#define IMX8MN_CLK_GPT6 233 -#define IMX8MN_CLK_GPT6_ROOT 234 - -#define IMX8MN_CLK_END 235 - -#endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h deleted file mode 100644 index 7da4243984b2..000000000000 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ /dev/null @@ -1,401 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H -#define __DT_BINDINGS_CLOCK_IMX8MP_H - -#define IMX8MP_CLK_DUMMY 0 -#define IMX8MP_CLK_32K 1 -#define IMX8MP_CLK_24M 2 -#define IMX8MP_OSC_HDMI_CLK 3 -#define IMX8MP_CLK_EXT1 4 -#define IMX8MP_CLK_EXT2 5 -#define IMX8MP_CLK_EXT3 6 -#define IMX8MP_CLK_EXT4 7 -#define IMX8MP_AUDIO_PLL1_REF_SEL 8 -#define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 -#define IMX8MP_DRAM_PLL_REF_SEL 11 -#define IMX8MP_GPU_PLL_REF_SEL 12 -#define IMX8MP_VPU_PLL_REF_SEL 13 -#define IMX8MP_ARM_PLL_REF_SEL 14 -#define IMX8MP_SYS_PLL1_REF_SEL 15 -#define IMX8MP_SYS_PLL2_REF_SEL 16 -#define IMX8MP_SYS_PLL3_REF_SEL 17 -#define IMX8MP_AUDIO_PLL1 18 -#define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 -#define IMX8MP_DRAM_PLL 21 -#define IMX8MP_GPU_PLL 22 -#define IMX8MP_VPU_PLL 23 -#define IMX8MP_ARM_PLL 24 -#define IMX8MP_SYS_PLL1 25 -#define IMX8MP_SYS_PLL2 26 -#define IMX8MP_SYS_PLL3 27 -#define IMX8MP_AUDIO_PLL1_BYPASS 28 -#define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 -#define IMX8MP_DRAM_PLL_BYPASS 31 -#define IMX8MP_GPU_PLL_BYPASS 32 -#define IMX8MP_VPU_PLL_BYPASS 33 -#define IMX8MP_ARM_PLL_BYPASS 34 -#define IMX8MP_SYS_PLL1_BYPASS 35 -#define IMX8MP_SYS_PLL2_BYPASS 36 -#define IMX8MP_SYS_PLL3_BYPASS 37 -#define IMX8MP_AUDIO_PLL1_OUT 38 -#define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 -#define IMX8MP_DRAM_PLL_OUT 41 -#define IMX8MP_GPU_PLL_OUT 42 -#define IMX8MP_VPU_PLL_OUT 43 -#define IMX8MP_ARM_PLL_OUT 44 -#define IMX8MP_SYS_PLL1_OUT 45 -#define IMX8MP_SYS_PLL2_OUT 46 -#define IMX8MP_SYS_PLL3_OUT 47 -#define IMX8MP_SYS_PLL1_40M 48 -#define IMX8MP_SYS_PLL1_80M 49 -#define IMX8MP_SYS_PLL1_100M 50 -#define IMX8MP_SYS_PLL1_133M 51 -#define IMX8MP_SYS_PLL1_160M 52 -#define IMX8MP_SYS_PLL1_200M 53 -#define IMX8MP_SYS_PLL1_266M 54 -#define IMX8MP_SYS_PLL1_400M 55 -#define IMX8MP_SYS_PLL1_800M 56 -#define IMX8MP_SYS_PLL2_50M 57 -#define IMX8MP_SYS_PLL2_100M 58 -#define IMX8MP_SYS_PLL2_125M 59 -#define IMX8MP_SYS_PLL2_166M 60 -#define IMX8MP_SYS_PLL2_200M 61 -#define IMX8MP_SYS_PLL2_250M 62 -#define IMX8MP_SYS_PLL2_333M 63 -#define IMX8MP_SYS_PLL2_500M 64 -#define IMX8MP_SYS_PLL2_1000M 65 -#define IMX8MP_CLK_A53_SRC 66 -#define IMX8MP_CLK_M7_SRC 67 -#define IMX8MP_CLK_ML_SRC 68 -#define IMX8MP_CLK_GPU3D_CORE_SRC 69 -#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 -#define IMX8MP_CLK_GPU2D_SRC 71 -#define IMX8MP_CLK_AUDIO_AXI_SRC 72 -#define IMX8MP_CLK_HSIO_AXI_SRC 73 -#define IMX8MP_CLK_MEDIA_ISP_SRC 74 -#define IMX8MP_CLK_A53_CG 75 -#define IMX8MP_CLK_M4_CG 76 -#define IMX8MP_CLK_ML_CG 77 -#define IMX8MP_CLK_GPU3D_CORE_CG 78 -#define IMX8MP_CLK_GPU3D_SHADER_CG 79 -#define IMX8MP_CLK_GPU2D_CG 80 -#define IMX8MP_CLK_AUDIO_AXI_CG 81 -#define IMX8MP_CLK_HSIO_AXI_CG 82 -#define IMX8MP_CLK_MEDIA_ISP_CG 83 -#define IMX8MP_CLK_A53_DIV 84 -#define IMX8MP_CLK_M7_DIV 85 -#define IMX8MP_CLK_ML_DIV 86 -#define IMX8MP_CLK_GPU3D_CORE_DIV 87 -#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 -#define IMX8MP_CLK_GPU2D_DIV 89 -#define IMX8MP_CLK_AUDIO_AXI_DIV 90 -#define IMX8MP_CLK_HSIO_AXI_DIV 91 -#define IMX8MP_CLK_MEDIA_ISP_DIV 92 -#define IMX8MP_CLK_MAIN_AXI 93 -#define IMX8MP_CLK_ENET_AXI 94 -#define IMX8MP_CLK_NAND_USDHC_BUS 95 -#define IMX8MP_CLK_VPU_BUS 96 -#define IMX8MP_CLK_MEDIA_AXI 97 -#define IMX8MP_CLK_MEDIA_APB 98 -#define IMX8MP_CLK_HDMI_APB 99 -#define IMX8MP_CLK_HDMI_AXI 100 -#define IMX8MP_CLK_GPU_AXI 101 -#define IMX8MP_CLK_GPU_AHB 102 -#define IMX8MP_CLK_NOC 103 -#define IMX8MP_CLK_NOC_IO 104 -#define IMX8MP_CLK_ML_AXI 105 -#define IMX8MP_CLK_ML_AHB 106 -#define IMX8MP_CLK_AHB 107 -#define IMX8MP_CLK_AUDIO_AHB 108 -#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 -#define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_DRAM_ALT 112 -#define IMX8MP_CLK_DRAM_APB 113 -#define IMX8MP_CLK_VPU_G1 114 -#define IMX8MP_CLK_VPU_G2 115 -#define IMX8MP_CLK_CAN1 116 -#define IMX8MP_CLK_CAN2 117 -#define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_AUX 120 -#define IMX8MP_CLK_I2C5 121 -#define IMX8MP_CLK_I2C6 122 -#define IMX8MP_CLK_SAI1 123 -#define IMX8MP_CLK_SAI2 124 -#define IMX8MP_CLK_SAI3 125 -/* #define IMX8MP_CLK_SAI4 126 */ -#define IMX8MP_CLK_SAI5 127 -#define IMX8MP_CLK_SAI6 128 -#define IMX8MP_CLK_ENET_QOS 129 -#define IMX8MP_CLK_ENET_QOS_TIMER 130 -#define IMX8MP_CLK_ENET_REF 131 -#define IMX8MP_CLK_ENET_TIMER 132 -#define IMX8MP_CLK_ENET_PHY_REF 133 -#define IMX8MP_CLK_NAND 134 -#define IMX8MP_CLK_QSPI 135 -#define IMX8MP_CLK_USDHC1 136 -#define IMX8MP_CLK_USDHC2 137 -#define IMX8MP_CLK_I2C1 138 -#define IMX8MP_CLK_I2C2 139 -#define IMX8MP_CLK_I2C3 140 -#define IMX8MP_CLK_I2C4 141 -#define IMX8MP_CLK_UART1 142 -#define IMX8MP_CLK_UART2 143 -#define IMX8MP_CLK_UART3 144 -#define IMX8MP_CLK_UART4 145 -#define IMX8MP_CLK_USB_CORE_REF 146 -#define IMX8MP_CLK_USB_PHY_REF 147 -#define IMX8MP_CLK_GIC 148 -#define IMX8MP_CLK_ECSPI1 149 -#define IMX8MP_CLK_ECSPI2 150 -#define IMX8MP_CLK_PWM1 151 -#define IMX8MP_CLK_PWM2 152 -#define IMX8MP_CLK_PWM3 153 -#define IMX8MP_CLK_PWM4 154 -#define IMX8MP_CLK_GPT1 155 -#define IMX8MP_CLK_GPT2 156 -#define IMX8MP_CLK_GPT3 157 -#define IMX8MP_CLK_GPT4 158 -#define IMX8MP_CLK_GPT5 159 -#define IMX8MP_CLK_GPT6 160 -#define IMX8MP_CLK_TRACE 161 -#define IMX8MP_CLK_WDOG 162 -#define IMX8MP_CLK_WRCLK 163 -#define IMX8MP_CLK_IPP_DO_CLKO1 164 -#define IMX8MP_CLK_IPP_DO_CLKO2 165 -#define IMX8MP_CLK_HDMI_FDCC_TST 166 -#define IMX8MP_CLK_HDMI_24M 167 -#define IMX8MP_CLK_HDMI_REF_266M 168 -#define IMX8MP_CLK_USDHC3 169 -#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 -#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 -#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 -#define IMX8MP_CLK_MEDIA_LDB 174 -#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 -#define IMX8MP_CLK_ECSPI3 179 -#define IMX8MP_CLK_PDM 180 -#define IMX8MP_CLK_VPU_VC8000E 181 -#define IMX8MP_CLK_SAI7 182 -#define IMX8MP_CLK_GPC_ROOT 183 -#define IMX8MP_CLK_ANAMIX_ROOT 184 -#define IMX8MP_CLK_CPU_ROOT 185 -#define IMX8MP_CLK_CSU_ROOT 186 -#define IMX8MP_CLK_DEBUG_ROOT 187 -#define IMX8MP_CLK_DRAM1_ROOT 188 -#define IMX8MP_CLK_ECSPI1_ROOT 189 -#define IMX8MP_CLK_ECSPI2_ROOT 190 -#define IMX8MP_CLK_ECSPI3_ROOT 191 -#define IMX8MP_CLK_ENET1_ROOT 192 -#define IMX8MP_CLK_GPIO1_ROOT 193 -#define IMX8MP_CLK_GPIO2_ROOT 194 -#define IMX8MP_CLK_GPIO3_ROOT 195 -#define IMX8MP_CLK_GPIO4_ROOT 196 -#define IMX8MP_CLK_GPIO5_ROOT 197 -#define IMX8MP_CLK_GPT1_ROOT 198 -#define IMX8MP_CLK_GPT2_ROOT 199 -#define IMX8MP_CLK_GPT3_ROOT 200 -#define IMX8MP_CLK_GPT4_ROOT 201 -#define IMX8MP_CLK_GPT5_ROOT 202 -#define IMX8MP_CLK_GPT6_ROOT 203 -#define IMX8MP_CLK_HS_ROOT 204 -#define IMX8MP_CLK_I2C1_ROOT 205 -#define IMX8MP_CLK_I2C2_ROOT 206 -#define IMX8MP_CLK_I2C3_ROOT 207 -#define IMX8MP_CLK_I2C4_ROOT 208 -#define IMX8MP_CLK_IOMUX_ROOT 209 -#define IMX8MP_CLK_IPMUX1_ROOT 210 -#define IMX8MP_CLK_IPMUX2_ROOT 211 -#define IMX8MP_CLK_IPMUX3_ROOT 212 -#define IMX8MP_CLK_MU_ROOT 213 -#define IMX8MP_CLK_OCOTP_ROOT 214 -#define IMX8MP_CLK_OCRAM_ROOT 215 -#define IMX8MP_CLK_OCRAM_S_ROOT 216 -#define IMX8MP_CLK_PCIE_ROOT 217 -#define IMX8MP_CLK_PERFMON1_ROOT 218 -#define IMX8MP_CLK_PERFMON2_ROOT 219 -#define IMX8MP_CLK_PWM1_ROOT 220 -#define IMX8MP_CLK_PWM2_ROOT 221 -#define IMX8MP_CLK_PWM3_ROOT 222 -#define IMX8MP_CLK_PWM4_ROOT 223 -#define IMX8MP_CLK_QOS_ROOT 224 -#define IMX8MP_CLK_QOS_ENET_ROOT 225 -#define IMX8MP_CLK_QSPI_ROOT 226 -#define IMX8MP_CLK_NAND_ROOT 227 -#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 -#define IMX8MP_CLK_RDC_ROOT 229 -#define IMX8MP_CLK_ROM_ROOT 230 -#define IMX8MP_CLK_I2C5_ROOT 231 -#define IMX8MP_CLK_I2C6_ROOT 232 -#define IMX8MP_CLK_CAN1_ROOT 233 -#define IMX8MP_CLK_CAN2_ROOT 234 -#define IMX8MP_CLK_SCTR_ROOT 235 -#define IMX8MP_CLK_SDMA1_ROOT 236 -#define IMX8MP_CLK_ENET_QOS_ROOT 237 -#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 -#define IMX8MP_CLK_SEMA1_ROOT 239 -#define IMX8MP_CLK_SEMA2_ROOT 240 -#define IMX8MP_CLK_IRQ_STEER_ROOT 241 -#define IMX8MP_CLK_SIM_ENET_ROOT 242 -#define IMX8MP_CLK_SIM_M_ROOT 243 -#define IMX8MP_CLK_SIM_MAIN_ROOT 244 -#define IMX8MP_CLK_SIM_S_ROOT 245 -#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 -#define IMX8MP_CLK_GPU2D_ROOT 247 -#define IMX8MP_CLK_GPU3D_ROOT 248 -#define IMX8MP_CLK_SNVS_ROOT 249 -#define IMX8MP_CLK_TRACE_ROOT 250 -#define IMX8MP_CLK_UART1_ROOT 251 -#define IMX8MP_CLK_UART2_ROOT 252 -#define IMX8MP_CLK_UART3_ROOT 253 -#define IMX8MP_CLK_UART4_ROOT 254 -#define IMX8MP_CLK_USB_ROOT 255 -#define IMX8MP_CLK_USB_PHY_ROOT 256 -#define IMX8MP_CLK_USDHC1_ROOT 257 -#define IMX8MP_CLK_USDHC2_ROOT 258 -#define IMX8MP_CLK_WDOG1_ROOT 259 -#define IMX8MP_CLK_WDOG2_ROOT 260 -#define IMX8MP_CLK_WDOG3_ROOT 261 -#define IMX8MP_CLK_VPU_G1_ROOT 262 -#define IMX8MP_CLK_GPU_ROOT 263 -#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 -#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 -#define IMX8MP_CLK_VPU_G2_ROOT 266 -#define IMX8MP_CLK_NPU_ROOT 267 -#define IMX8MP_CLK_HSIO_ROOT 268 -#define IMX8MP_CLK_MEDIA_APB_ROOT 269 -#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 -#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 -#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 -#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 -#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 -#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 -#define IMX8MP_CLK_USDHC3_ROOT 277 -#define IMX8MP_CLK_HDMI_ROOT 278 -#define IMX8MP_CLK_XTAL_ROOT 279 -#define IMX8MP_CLK_PLL_ROOT 280 -#define IMX8MP_CLK_TSENSOR_ROOT 281 -#define IMX8MP_CLK_VPU_ROOT 282 -#define IMX8MP_CLK_MRPR_ROOT 283 -#define IMX8MP_CLK_AUDIO_ROOT 284 -#define IMX8MP_CLK_DRAM_ALT_ROOT 285 -#define IMX8MP_CLK_DRAM_CORE 286 -#define IMX8MP_CLK_ARM 287 -#define IMX8MP_CLK_A53_CORE 288 - -#define IMX8MP_SYS_PLL1_40M_CG 289 -#define IMX8MP_SYS_PLL1_80M_CG 290 -#define IMX8MP_SYS_PLL1_100M_CG 291 -#define IMX8MP_SYS_PLL1_133M_CG 292 -#define IMX8MP_SYS_PLL1_160M_CG 293 -#define IMX8MP_SYS_PLL1_200M_CG 294 -#define IMX8MP_SYS_PLL1_266M_CG 295 -#define IMX8MP_SYS_PLL1_400M_CG 296 -#define IMX8MP_SYS_PLL2_50M_CG 297 -#define IMX8MP_SYS_PLL2_100M_CG 298 -#define IMX8MP_SYS_PLL2_125M_CG 299 -#define IMX8MP_SYS_PLL2_166M_CG 300 -#define IMX8MP_SYS_PLL2_200M_CG 301 -#define IMX8MP_SYS_PLL2_250M_CG 302 -#define IMX8MP_SYS_PLL2_333M_CG 303 -#define IMX8MP_SYS_PLL2_500M_CG 304 - -#define IMX8MP_CLK_M7_CORE 305 -#define IMX8MP_CLK_ML_CORE 306 -#define IMX8MP_CLK_GPU3D_CORE 307 -#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 -#define IMX8MP_CLK_GPU2D_CORE 309 -#define IMX8MP_CLK_AUDIO_AXI 310 -#define IMX8MP_CLK_HSIO_AXI 311 -#define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 -#define IMX8MP_CLK_CLKOUT1_SEL 314 -#define IMX8MP_CLK_CLKOUT1_DIV 315 -#define IMX8MP_CLK_CLKOUT1 316 -#define IMX8MP_CLK_CLKOUT2_SEL 317 -#define IMX8MP_CLK_CLKOUT2_DIV 318 -#define IMX8MP_CLK_CLKOUT2 319 -#define IMX8MP_CLK_USB_SUSP 320 -#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT -#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 -#define IMX8MP_CLK_SAI1_ROOT 322 -#define IMX8MP_CLK_SAI2_ROOT 323 -#define IMX8MP_CLK_SAI3_ROOT 324 -#define IMX8MP_CLK_SAI5_ROOT 325 -#define IMX8MP_CLK_SAI6_ROOT 326 -#define IMX8MP_CLK_SAI7_ROOT 327 -#define IMX8MP_CLK_PDM_ROOT 328 -#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 -#define IMX8MP_CLK_END 330 - -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 - -#define IMX8MP_CLK_AUDIOMIX_END 59 - -#endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h deleted file mode 100644 index afa74d7ba100..000000000000 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ /dev/null @@ -1,431 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H -#define __DT_BINDINGS_CLOCK_IMX8MQ_H - -#define IMX8MQ_CLK_DUMMY 0 -#define IMX8MQ_CLK_32K 1 -#define IMX8MQ_CLK_25M 2 -#define IMX8MQ_CLK_27M 3 -#define IMX8MQ_CLK_EXT1 4 -#define IMX8MQ_CLK_EXT2 5 -#define IMX8MQ_CLK_EXT3 6 -#define IMX8MQ_CLK_EXT4 7 - -/* ANAMIX PLL clocks */ -/* FRAC PLLs */ -/* ARM PLL */ -#define IMX8MQ_ARM_PLL_REF_SEL 8 -#define IMX8MQ_ARM_PLL_REF_DIV 9 -#define IMX8MQ_ARM_PLL 10 -#define IMX8MQ_ARM_PLL_BYPASS 11 -#define IMX8MQ_ARM_PLL_OUT 12 - -/* GPU PLL */ -#define IMX8MQ_GPU_PLL_REF_SEL 13 -#define IMX8MQ_GPU_PLL_REF_DIV 14 -#define IMX8MQ_GPU_PLL 15 -#define IMX8MQ_GPU_PLL_BYPASS 16 -#define IMX8MQ_GPU_PLL_OUT 17 - -/* VPU PLL */ -#define IMX8MQ_VPU_PLL_REF_SEL 18 -#define IMX8MQ_VPU_PLL_REF_DIV 19 -#define IMX8MQ_VPU_PLL 20 -#define IMX8MQ_VPU_PLL_BYPASS 21 -#define IMX8MQ_VPU_PLL_OUT 22 - -/* AUDIO PLL1 */ -#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 -#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 -#define IMX8MQ_AUDIO_PLL1 25 -#define IMX8MQ_AUDIO_PLL1_BYPASS 26 -#define IMX8MQ_AUDIO_PLL1_OUT 27 - -/* AUDIO PLL2 */ -#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 -#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 -#define IMX8MQ_AUDIO_PLL2 30 -#define IMX8MQ_AUDIO_PLL2_BYPASS 31 -#define IMX8MQ_AUDIO_PLL2_OUT 32 - -/* VIDEO PLL1 */ -#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 -#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 -#define IMX8MQ_VIDEO_PLL1 35 -#define IMX8MQ_VIDEO_PLL1_BYPASS 36 -#define IMX8MQ_VIDEO_PLL1_OUT 37 - -/* SYS1 PLL */ -#define IMX8MQ_SYS1_PLL1_REF_SEL 38 -#define IMX8MQ_SYS1_PLL1_REF_DIV 39 -#define IMX8MQ_SYS1_PLL1 40 -#define IMX8MQ_SYS1_PLL1_OUT 41 -#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 -#define IMX8MQ_SYS1_PLL2 43 -#define IMX8MQ_SYS1_PLL2_DIV 44 -#define IMX8MQ_SYS1_PLL2_OUT 45 - -/* SYS2 PLL */ -#define IMX8MQ_SYS2_PLL1_REF_SEL 46 -#define IMX8MQ_SYS2_PLL1_REF_DIV 47 -#define IMX8MQ_SYS2_PLL1 48 -#define IMX8MQ_SYS2_PLL1_OUT 49 -#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 -#define IMX8MQ_SYS2_PLL2 51 -#define IMX8MQ_SYS2_PLL2_DIV 52 -#define IMX8MQ_SYS2_PLL2_OUT 53 - -/* SYS3 PLL */ -#define IMX8MQ_SYS3_PLL1_REF_SEL 54 -#define IMX8MQ_SYS3_PLL1_REF_DIV 55 -#define IMX8MQ_SYS3_PLL1 56 -#define IMX8MQ_SYS3_PLL1_OUT 57 -#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 -#define IMX8MQ_SYS3_PLL2 59 -#define IMX8MQ_SYS3_PLL2_DIV 60 -#define IMX8MQ_SYS3_PLL2_OUT 61 - -/* DRAM PLL */ -#define IMX8MQ_DRAM_PLL1_REF_SEL 62 -#define IMX8MQ_DRAM_PLL1_REF_DIV 63 -#define IMX8MQ_DRAM_PLL1 64 -#define IMX8MQ_DRAM_PLL1_OUT 65 -#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 -#define IMX8MQ_DRAM_PLL2 67 -#define IMX8MQ_DRAM_PLL2_DIV 68 -#define IMX8MQ_DRAM_PLL2_OUT 69 - -/* SYS PLL DIV */ -#define IMX8MQ_SYS1_PLL_40M 70 -#define IMX8MQ_SYS1_PLL_80M 71 -#define IMX8MQ_SYS1_PLL_100M 72 -#define IMX8MQ_SYS1_PLL_133M 73 -#define IMX8MQ_SYS1_PLL_160M 74 -#define IMX8MQ_SYS1_PLL_200M 75 -#define IMX8MQ_SYS1_PLL_266M 76 -#define IMX8MQ_SYS1_PLL_400M 77 -#define IMX8MQ_SYS1_PLL_800M 78 - -#define IMX8MQ_SYS2_PLL_50M 79 -#define IMX8MQ_SYS2_PLL_100M 80 -#define IMX8MQ_SYS2_PLL_125M 81 -#define IMX8MQ_SYS2_PLL_166M 82 -#define IMX8MQ_SYS2_PLL_200M 83 -#define IMX8MQ_SYS2_PLL_250M 84 -#define IMX8MQ_SYS2_PLL_333M 85 -#define IMX8MQ_SYS2_PLL_500M 86 -#define IMX8MQ_SYS2_PLL_1000M 87 - -/* CCM ROOT clocks */ -/* A53 */ -#define IMX8MQ_CLK_A53_SRC 88 -#define IMX8MQ_CLK_A53_CG 89 -#define IMX8MQ_CLK_A53_DIV 90 -/* M4 */ -#define IMX8MQ_CLK_M4_SRC 91 -#define IMX8MQ_CLK_M4_CG 92 -#define IMX8MQ_CLK_M4_DIV 93 -/* VPU */ -#define IMX8MQ_CLK_VPU_SRC 94 -#define IMX8MQ_CLK_VPU_CG 95 -#define IMX8MQ_CLK_VPU_DIV 96 -/* GPU CORE */ -#define IMX8MQ_CLK_GPU_CORE_SRC 97 -#define IMX8MQ_CLK_GPU_CORE_CG 98 -#define IMX8MQ_CLK_GPU_CORE_DIV 99 -/* GPU SHADER */ -#define IMX8MQ_CLK_GPU_SHADER_SRC 100 -#define IMX8MQ_CLK_GPU_SHADER_CG 101 -#define IMX8MQ_CLK_GPU_SHADER_DIV 102 - -/* BUS TYPE */ -/* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI 103 -/* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI 104 -/* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS 105 -/* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS 106 -/* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI 107 -/* DISP APB */ -#define IMX8MQ_CLK_DISP_APB 108 -/* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM 109 -/* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS 110 -/* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI 111 -/* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB 112 -/* NOC */ -#define IMX8MQ_CLK_NOC 113 -/* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB 115 - -/* AHB */ -#define IMX8MQ_CLK_AHB 116 -/* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB 117 - -/* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT 118 -/* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB 119 -/* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1 120 -/* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2 121 -/* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC 122 -/* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000 123 -/* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL 124 -/* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY 125 -/* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX 126 -/* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL 127 -/* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL 128 -/* SAI1~6 */ -#define IMX8MQ_CLK_SAI1 129 - -#define IMX8MQ_CLK_SAI2 130 - -#define IMX8MQ_CLK_SAI3 131 - -#define IMX8MQ_CLK_SAI4 132 - -#define IMX8MQ_CLK_SAI5 133 - -#define IMX8MQ_CLK_SAI6 134 -/* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1 135 -/* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2 136 -/* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF 137 -/* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER 138 -/* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF 139 -/* NAND */ -#define IMX8MQ_CLK_NAND 140 -/* QSPI */ -#define IMX8MQ_CLK_QSPI 141 -/* USDHC1 */ -#define IMX8MQ_CLK_USDHC1 142 -/* USDHC2 */ -#define IMX8MQ_CLK_USDHC2 143 -/* I2C1 */ -#define IMX8MQ_CLK_I2C1 144 -/* I2C2 */ -#define IMX8MQ_CLK_I2C2 145 -/* I2C3 */ -#define IMX8MQ_CLK_I2C3 146 -/* I2C4 */ -#define IMX8MQ_CLK_I2C4 147 -/* UART1 */ -#define IMX8MQ_CLK_UART1 148 -/* UART2 */ -#define IMX8MQ_CLK_UART2 149 -/* UART3 */ -#define IMX8MQ_CLK_UART3 150 -/* UART4 */ -#define IMX8MQ_CLK_UART4 151 -/* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF 152 -/* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF 153 -/* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1 154 -/* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2 155 -/* PWM1 */ -#define IMX8MQ_CLK_PWM1 156 -/* PWM2 */ -#define IMX8MQ_CLK_PWM2 157 -/* PWM3 */ -#define IMX8MQ_CLK_PWM3 158 -/* PWM4 */ -#define IMX8MQ_CLK_PWM4 159 -/* GPT1 */ -#define IMX8MQ_CLK_GPT1 160 -/* WDOG */ -#define IMX8MQ_CLK_WDOG 161 -/* WRCLK */ -#define IMX8MQ_CLK_WRCLK 162 -/* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE 163 -/* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF 164 -/* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI 165 -/*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC 166 -/* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE 167 -/* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF 168 -/* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC 169 -/* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE 170 -/* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF 171 -/* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC 172 -/* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL 173 -/* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY 174 -/* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX 175 -/* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3 176 - -/* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 177 -#define IMX8MQ_CLK_DRAM_ROOT 178 -#define IMX8MQ_CLK_ECSPI1_ROOT 179 -#define IMX8MQ_CLK_ECSPI2_ROOT 180 -#define IMX8MQ_CLK_ECSPI3_ROOT 181 -#define IMX8MQ_CLK_ENET1_ROOT 182 -#define IMX8MQ_CLK_GPT1_ROOT 183 -#define IMX8MQ_CLK_I2C1_ROOT 184 -#define IMX8MQ_CLK_I2C2_ROOT 185 -#define IMX8MQ_CLK_I2C3_ROOT 186 -#define IMX8MQ_CLK_I2C4_ROOT 187 -#define IMX8MQ_CLK_M4_ROOT 188 -#define IMX8MQ_CLK_PCIE1_ROOT 189 -#define IMX8MQ_CLK_PCIE2_ROOT 190 -#define IMX8MQ_CLK_PWM1_ROOT 191 -#define IMX8MQ_CLK_PWM2_ROOT 192 -#define IMX8MQ_CLK_PWM3_ROOT 193 -#define IMX8MQ_CLK_PWM4_ROOT 194 -#define IMX8MQ_CLK_QSPI_ROOT 195 -#define IMX8MQ_CLK_SAI1_ROOT 196 -#define IMX8MQ_CLK_SAI2_ROOT 197 -#define IMX8MQ_CLK_SAI3_ROOT 198 -#define IMX8MQ_CLK_SAI4_ROOT 199 -#define IMX8MQ_CLK_SAI5_ROOT 200 -#define IMX8MQ_CLK_SAI6_ROOT 201 -#define IMX8MQ_CLK_UART1_ROOT 202 -#define IMX8MQ_CLK_UART2_ROOT 203 -#define IMX8MQ_CLK_UART3_ROOT 204 -#define IMX8MQ_CLK_UART4_ROOT 205 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 -#define IMX8MQ_CLK_USB1_PHY_ROOT 208 -#define IMX8MQ_CLK_USB2_PHY_ROOT 209 -#define IMX8MQ_CLK_USDHC1_ROOT 210 -#define IMX8MQ_CLK_USDHC2_ROOT 211 -#define IMX8MQ_CLK_WDOG1_ROOT 212 -#define IMX8MQ_CLK_WDOG2_ROOT 213 -#define IMX8MQ_CLK_WDOG3_ROOT 214 -#define IMX8MQ_CLK_GPU_ROOT 215 -#define IMX8MQ_CLK_HEVC_ROOT 216 -#define IMX8MQ_CLK_AVC_ROOT 217 -#define IMX8MQ_CLK_VP9_ROOT 218 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 -#define IMX8MQ_CLK_DISP_ROOT 220 -#define IMX8MQ_CLK_HDMI_ROOT 221 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 -#define IMX8MQ_CLK_VPU_DEC_ROOT 223 -#define IMX8MQ_CLK_CSI1_ROOT 224 -#define IMX8MQ_CLK_CSI2_ROOT 225 -#define IMX8MQ_CLK_RAWNAND_ROOT 226 -#define IMX8MQ_CLK_SDMA1_ROOT 227 -#define IMX8MQ_CLK_SDMA2_ROOT 228 -#define IMX8MQ_CLK_VPU_G1_ROOT 229 -#define IMX8MQ_CLK_VPU_G2_ROOT 230 - -/* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 231 -#define IMX8MQ_SYS2_PLL_OUT 232 -#define IMX8MQ_SYS3_PLL_OUT 233 -#define IMX8MQ_DRAM_PLL_OUT 234 - -#define IMX8MQ_GPT_3M_CLK 235 - -#define IMX8MQ_CLK_IPG_ROOT 236 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 -#define IMX8MQ_CLK_SAI1_IPG 238 -#define IMX8MQ_CLK_SAI2_IPG 239 -#define IMX8MQ_CLK_SAI3_IPG 240 -#define IMX8MQ_CLK_SAI4_IPG 241 -#define IMX8MQ_CLK_SAI5_IPG 242 -#define IMX8MQ_CLK_SAI6_IPG 243 - -/* DSI AHB/IPG clocks */ -/* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB 244 -/* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 245 - -#define IMX8MQ_CLK_TMU_ROOT 246 - -/* Display root clocks */ -#define IMX8MQ_CLK_DISP_AXI_ROOT 247 -#define IMX8MQ_CLK_DISP_APB_ROOT 248 -#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 - -#define IMX8MQ_CLK_OCOTP_ROOT 250 - -#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 -#define IMX8MQ_CLK_DRAM_CORE 252 - -#define IMX8MQ_CLK_MU_ROOT 253 -#define IMX8MQ_VIDEO2_PLL_OUT 254 - -#define IMX8MQ_CLK_CLKO2 255 - -#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 - -#define IMX8MQ_CLK_CLKO1 257 -#define IMX8MQ_CLK_ARM 258 - -#define IMX8MQ_CLK_GPIO1_ROOT 259 -#define IMX8MQ_CLK_GPIO2_ROOT 260 -#define IMX8MQ_CLK_GPIO3_ROOT 261 -#define IMX8MQ_CLK_GPIO4_ROOT 262 -#define IMX8MQ_CLK_GPIO5_ROOT 263 - -#define IMX8MQ_CLK_SNVS_ROOT 264 -#define IMX8MQ_CLK_GIC 265 - -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 - -#define IMX8MQ_CLK_GPU_CORE 285 -#define IMX8MQ_CLK_GPU_SHADER 286 -#define IMX8MQ_CLK_M4_CORE 287 -#define IMX8MQ_CLK_VPU_CORE 288 - -#define IMX8MQ_CLK_A53_CORE 289 - -#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 -#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 -#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 -#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 -#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 -#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 -#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 -#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 -#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 -#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 -#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 -#define IMX8MQ_CLK_MON_SEL 301 -#define IMX8MQ_CLK_MON_CLK2_OUT 302 - -#define IMX8MQ_CLK_END 303 - -#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h deleted file mode 100644 index 953ecfe8ebcc..000000000000 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H -#define __DT_BINDINGS_CLOCK_IMX8ULP_H - -#define IMX8ULP_CLK_DUMMY 0 - -/* CGC1 */ -#define IMX8ULP_CLK_SPLL2 5 -#define IMX8ULP_CLK_SPLL3 6 -#define IMX8ULP_CLK_A35_SEL 7 -#define IMX8ULP_CLK_A35_DIV 8 -#define IMX8ULP_CLK_SPLL2_PRE_SEL 9 -#define IMX8ULP_CLK_SPLL3_PRE_SEL 10 -#define IMX8ULP_CLK_SPLL3_PFD0 11 -#define IMX8ULP_CLK_SPLL3_PFD1 12 -#define IMX8ULP_CLK_SPLL3_PFD2 13 -#define IMX8ULP_CLK_SPLL3_PFD3 14 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 -#define IMX8ULP_CLK_NIC_SEL 23 -#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 -#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 -#define IMX8ULP_CLK_XBAR_SEL 26 -#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 -#define IMX8ULP_CLK_XBAR_DIVBUS 28 -#define IMX8ULP_CLK_XBAR_AD_SLOW 29 -#define IMX8ULP_CLK_SOSC_DIV1 30 -#define IMX8ULP_CLK_SOSC_DIV2 31 -#define IMX8ULP_CLK_SOSC_DIV3 32 -#define IMX8ULP_CLK_FROSC_DIV1 33 -#define IMX8ULP_CLK_FROSC_DIV2 34 -#define IMX8ULP_CLK_FROSC_DIV3 35 -#define IMX8ULP_CLK_SPLL3_VCODIV 36 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 -#define IMX8ULP_CLK_SOSC_DIV1_GATE 45 -#define IMX8ULP_CLK_SOSC_DIV2_GATE 46 -#define IMX8ULP_CLK_SOSC_DIV3_GATE 47 -#define IMX8ULP_CLK_FROSC_DIV1_GATE 48 -#define IMX8ULP_CLK_FROSC_DIV2_GATE 49 -#define IMX8ULP_CLK_FROSC_DIV3_GATE 50 -#define IMX8ULP_CLK_SAI4_SEL 51 -#define IMX8ULP_CLK_SAI5_SEL 52 -#define IMX8ULP_CLK_AUD_CLK1 53 -#define IMX8ULP_CLK_ARM 54 -#define IMX8ULP_CLK_ENET_TS_SEL 55 - -#define IMX8ULP_CLK_CGC1_END 56 - -/* CGC2 */ -#define IMX8ULP_CLK_PLL4_PRE_SEL 0 -#define IMX8ULP_CLK_PLL4 1 -#define IMX8ULP_CLK_PLL4_VCODIV 2 -#define IMX8ULP_CLK_DDR_SEL 3 -#define IMX8ULP_CLK_DDR_DIV 4 -#define IMX8ULP_CLK_LPAV_AXI_SEL 5 -#define IMX8ULP_CLK_LPAV_AXI_DIV 6 -#define IMX8ULP_CLK_LPAV_AHB_DIV 7 -#define IMX8ULP_CLK_LPAV_BUS_DIV 8 -#define IMX8ULP_CLK_PLL4_PFD0 9 -#define IMX8ULP_CLK_PLL4_PFD1 10 -#define IMX8ULP_CLK_PLL4_PFD2 11 -#define IMX8ULP_CLK_PLL4_PFD3 12 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 -#define IMX8ULP_CLK_AUD_CLK2 41 -#define IMX8ULP_CLK_SAI6_SEL 42 -#define IMX8ULP_CLK_SAI7_SEL 43 -#define IMX8ULP_CLK_SPDIF_SEL 44 -#define IMX8ULP_CLK_HIFI_SEL 45 -#define IMX8ULP_CLK_HIFI_DIVCORE 46 -#define IMX8ULP_CLK_HIFI_DIVPLAT 47 -#define IMX8ULP_CLK_DSI_PHY_REF 48 - -#define IMX8ULP_CLK_CGC2_END 49 - -/* PCC3 */ -#define IMX8ULP_CLK_WDOG3 0 -#define IMX8ULP_CLK_WDOG4 1 -#define IMX8ULP_CLK_LPIT1 2 -#define IMX8ULP_CLK_TPM4 3 -#define IMX8ULP_CLK_TPM5 4 -#define IMX8ULP_CLK_FLEXIO1 5 -#define IMX8ULP_CLK_I3C2 6 -#define IMX8ULP_CLK_LPI2C4 7 -#define IMX8ULP_CLK_LPI2C5 8 -#define IMX8ULP_CLK_LPUART4 9 -#define IMX8ULP_CLK_LPUART5 10 -#define IMX8ULP_CLK_LPSPI4 11 -#define IMX8ULP_CLK_LPSPI5 12 -#define IMX8ULP_CLK_DMA1_MP 13 -#define IMX8ULP_CLK_DMA1_CH0 14 -#define IMX8ULP_CLK_DMA1_CH1 15 -#define IMX8ULP_CLK_DMA1_CH2 16 -#define IMX8ULP_CLK_DMA1_CH3 17 -#define IMX8ULP_CLK_DMA1_CH4 18 -#define IMX8ULP_CLK_DMA1_CH5 19 -#define IMX8ULP_CLK_DMA1_CH6 20 -#define IMX8ULP_CLK_DMA1_CH7 21 -#define IMX8ULP_CLK_DMA1_CH8 22 -#define IMX8ULP_CLK_DMA1_CH9 23 -#define IMX8ULP_CLK_DMA1_CH10 24 -#define IMX8ULP_CLK_DMA1_CH11 25 -#define IMX8ULP_CLK_DMA1_CH12 26 -#define IMX8ULP_CLK_DMA1_CH13 27 -#define IMX8ULP_CLK_DMA1_CH14 28 -#define IMX8ULP_CLK_DMA1_CH15 29 -#define IMX8ULP_CLK_DMA1_CH16 30 -#define IMX8ULP_CLK_DMA1_CH17 31 -#define IMX8ULP_CLK_DMA1_CH18 32 -#define IMX8ULP_CLK_DMA1_CH19 33 -#define IMX8ULP_CLK_DMA1_CH20 34 -#define IMX8ULP_CLK_DMA1_CH21 35 -#define IMX8ULP_CLK_DMA1_CH22 36 -#define IMX8ULP_CLK_DMA1_CH23 37 -#define IMX8ULP_CLK_DMA1_CH24 38 -#define IMX8ULP_CLK_DMA1_CH25 39 -#define IMX8ULP_CLK_DMA1_CH26 40 -#define IMX8ULP_CLK_DMA1_CH27 41 -#define IMX8ULP_CLK_DMA1_CH28 42 -#define IMX8ULP_CLK_DMA1_CH29 43 -#define IMX8ULP_CLK_DMA1_CH30 44 -#define IMX8ULP_CLK_DMA1_CH31 45 -#define IMX8ULP_CLK_MU3_A 46 -#define IMX8ULP_CLK_MU0_B 47 - -#define IMX8ULP_CLK_PCC3_END 48 - -/* PCC4 */ -#define IMX8ULP_CLK_FLEXSPI2 0 -#define IMX8ULP_CLK_TPM6 1 -#define IMX8ULP_CLK_TPM7 2 -#define IMX8ULP_CLK_LPI2C6 3 -#define IMX8ULP_CLK_LPI2C7 4 -#define IMX8ULP_CLK_LPUART6 5 -#define IMX8ULP_CLK_LPUART7 6 -#define IMX8ULP_CLK_SAI4 7 -#define IMX8ULP_CLK_SAI5 8 -#define IMX8ULP_CLK_PCTLE 9 -#define IMX8ULP_CLK_PCTLF 10 -#define IMX8ULP_CLK_USDHC0 11 -#define IMX8ULP_CLK_USDHC1 12 -#define IMX8ULP_CLK_USDHC2 13 -#define IMX8ULP_CLK_USB0 14 -#define IMX8ULP_CLK_USB0_PHY 15 -#define IMX8ULP_CLK_USB1 16 -#define IMX8ULP_CLK_USB1_PHY 17 -#define IMX8ULP_CLK_USB_XBAR 18 -#define IMX8ULP_CLK_ENET 19 -#define IMX8ULP_CLK_SFA1 20 -#define IMX8ULP_CLK_RGPIOE 21 -#define IMX8ULP_CLK_RGPIOF 22 - -#define IMX8ULP_CLK_PCC4_END 23 - -/* PCC5 */ -#define IMX8ULP_CLK_TPM8 0 -#define IMX8ULP_CLK_SAI6 1 -#define IMX8ULP_CLK_SAI7 2 -#define IMX8ULP_CLK_SPDIF 3 -#define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 -#define IMX8ULP_CLK_PCTLD 6 -#define IMX8ULP_CLK_CSI 7 -#define IMX8ULP_CLK_DSI 8 -#define IMX8ULP_CLK_WDOG5 9 -#define IMX8ULP_CLK_EPDC 10 -#define IMX8ULP_CLK_PXP 11 -#define IMX8ULP_CLK_SFA2 12 -#define IMX8ULP_CLK_GPU2D 13 -#define IMX8ULP_CLK_GPU3D 14 -#define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 -#define IMX8ULP_CLK_CSI_CLK_ESC 17 -#define IMX8ULP_CLK_RGPIOD 18 -#define IMX8ULP_CLK_DMA2_MP 19 -#define IMX8ULP_CLK_DMA2_CH0 20 -#define IMX8ULP_CLK_DMA2_CH1 21 -#define IMX8ULP_CLK_DMA2_CH2 22 -#define IMX8ULP_CLK_DMA2_CH3 23 -#define IMX8ULP_CLK_DMA2_CH4 24 -#define IMX8ULP_CLK_DMA2_CH5 25 -#define IMX8ULP_CLK_DMA2_CH6 26 -#define IMX8ULP_CLK_DMA2_CH7 27 -#define IMX8ULP_CLK_DMA2_CH8 28 -#define IMX8ULP_CLK_DMA2_CH9 29 -#define IMX8ULP_CLK_DMA2_CH10 30 -#define IMX8ULP_CLK_DMA2_CH11 31 -#define IMX8ULP_CLK_DMA2_CH12 32 -#define IMX8ULP_CLK_DMA2_CH13 33 -#define IMX8ULP_CLK_DMA2_CH14 34 -#define IMX8ULP_CLK_DMA2_CH15 35 -#define IMX8ULP_CLK_DMA2_CH16 36 -#define IMX8ULP_CLK_DMA2_CH17 37 -#define IMX8ULP_CLK_DMA2_CH18 38 -#define IMX8ULP_CLK_DMA2_CH19 39 -#define IMX8ULP_CLK_DMA2_CH20 40 -#define IMX8ULP_CLK_DMA2_CH21 41 -#define IMX8ULP_CLK_DMA2_CH22 42 -#define IMX8ULP_CLK_DMA2_CH23 43 -#define IMX8ULP_CLK_DMA2_CH24 44 -#define IMX8ULP_CLK_DMA2_CH25 45 -#define IMX8ULP_CLK_DMA2_CH26 46 -#define IMX8ULP_CLK_DMA2_CH27 47 -#define IMX8ULP_CLK_DMA2_CH28 48 -#define IMX8ULP_CLK_DMA2_CH29 49 -#define IMX8ULP_CLK_DMA2_CH30 50 -#define IMX8ULP_CLK_DMA2_CH31 51 -#define IMX8ULP_CLK_MU2_B 52 -#define IMX8ULP_CLK_MU3_B 53 -#define IMX8ULP_CLK_AVD_SIM 54 -#define IMX8ULP_CLK_DSI_TX_ESC 55 - -#define IMX8ULP_CLK_PCC5_END 56 - -#endif diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h deleted file mode 100644 index 35a1f62053a5..000000000000 --- a/include/dt-bindings/clock/imx93-clock.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H -#define __DT_BINDINGS_CLOCK_IMX93_CLK_H - -#define IMX93_CLK_DUMMY 0 -#define IMX93_CLK_24M 1 -#define IMX93_CLK_EXT1 2 -#define IMX93_CLK_SYS_PLL_PFD0 3 -#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 -#define IMX93_CLK_SYS_PLL_PFD1 5 -#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 -#define IMX93_CLK_SYS_PLL_PFD2 7 -#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 -#define IMX93_CLK_AUDIO_PLL 9 -#define IMX93_CLK_VIDEO_PLL 10 -#define IMX93_CLK_A55_PERIPH 11 -#define IMX93_CLK_A55_MTR_BUS 12 -#define IMX93_CLK_A55 13 -#define IMX93_CLK_M33 14 -#define IMX93_CLK_BUS_WAKEUP 15 -#define IMX93_CLK_BUS_AON 16 -#define IMX93_CLK_WAKEUP_AXI 17 -#define IMX93_CLK_SWO_TRACE 18 -#define IMX93_CLK_M33_SYSTICK 19 -#define IMX93_CLK_FLEXIO1 20 -#define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPTMR1 24 -#define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM4 29 -#define IMX93_CLK_TPM5 30 -#define IMX93_CLK_TPM6 31 -#define IMX93_CLK_FLEXSPI1 32 -#define IMX93_CLK_CAN1 33 -#define IMX93_CLK_CAN2 34 -#define IMX93_CLK_LPUART1 35 -#define IMX93_CLK_LPUART2 36 -#define IMX93_CLK_LPUART3 37 -#define IMX93_CLK_LPUART4 38 -#define IMX93_CLK_LPUART5 39 -#define IMX93_CLK_LPUART6 40 -#define IMX93_CLK_LPUART7 41 -#define IMX93_CLK_LPUART8 42 -#define IMX93_CLK_LPI2C1 43 -#define IMX93_CLK_LPI2C2 44 -#define IMX93_CLK_LPI2C3 45 -#define IMX93_CLK_LPI2C4 46 -#define IMX93_CLK_LPI2C5 47 -#define IMX93_CLK_LPI2C6 48 -#define IMX93_CLK_LPI2C7 49 -#define IMX93_CLK_LPI2C8 50 -#define IMX93_CLK_LPSPI1 51 -#define IMX93_CLK_LPSPI2 52 -#define IMX93_CLK_LPSPI3 53 -#define IMX93_CLK_LPSPI4 54 -#define IMX93_CLK_LPSPI5 55 -#define IMX93_CLK_LPSPI6 56 -#define IMX93_CLK_LPSPI7 57 -#define IMX93_CLK_LPSPI8 58 -#define IMX93_CLK_I3C1 59 -#define IMX93_CLK_I3C2 60 -#define IMX93_CLK_USDHC1 61 -#define IMX93_CLK_USDHC2 62 -#define IMX93_CLK_USDHC3 63 -#define IMX93_CLK_SAI1 64 -#define IMX93_CLK_SAI2 65 -#define IMX93_CLK_SAI3 66 -#define IMX93_CLK_CCM_CKO1 67 -#define IMX93_CLK_CCM_CKO2 68 -#define IMX93_CLK_CCM_CKO3 69 -#define IMX93_CLK_CCM_CKO4 70 -#define IMX93_CLK_HSIO 71 -#define IMX93_CLK_HSIO_USB_TEST_60M 72 -#define IMX93_CLK_HSIO_ACSCAN_80M 73 -#define IMX93_CLK_HSIO_ACSCAN_480M 74 -#define IMX93_CLK_ML_APB 75 -#define IMX93_CLK_ML 76 -#define IMX93_CLK_MEDIA_AXI 77 -#define IMX93_CLK_MEDIA_APB 78 -#define IMX93_CLK_MEDIA_LDB 79 -#define IMX93_CLK_MEDIA_DISP_PIX 80 -#define IMX93_CLK_CAM_PIX 81 -#define IMX93_CLK_MIPI_TEST_BYTE 82 -#define IMX93_CLK_MIPI_PHY_CFG 83 -#define IMX93_CLK_ADC 84 -#define IMX93_CLK_PDM 85 -#define IMX93_CLK_TSTMR1 86 -#define IMX93_CLK_TSTMR2 87 -#define IMX93_CLK_MQS1 88 -#define IMX93_CLK_MQS2 89 -#define IMX93_CLK_AUDIO_XCVR 90 -#define IMX93_CLK_SPDIF 91 -#define IMX93_CLK_ENET 92 -#define IMX93_CLK_ENET_TIMER1 93 -#define IMX93_CLK_ENET_TIMER2 94 -#define IMX93_CLK_ENET_REF 95 -#define IMX93_CLK_ENET_REF_PHY 96 -#define IMX93_CLK_I3C1_SLOW 97 -#define IMX93_CLK_I3C2_SLOW 98 -#define IMX93_CLK_USB_PHY_BURUNIN 99 -#define IMX93_CLK_PAL_CAME_SCAN 100 -#define IMX93_CLK_A55_GATE 101 -#define IMX93_CLK_CM33_GATE 102 -#define IMX93_CLK_ADC1_GATE 103 -#define IMX93_CLK_WDOG1_GATE 104 -#define IMX93_CLK_WDOG2_GATE 105 -#define IMX93_CLK_WDOG3_GATE 106 -#define IMX93_CLK_WDOG4_GATE 107 -#define IMX93_CLK_WDOG5_GATE 108 -#define IMX93_CLK_SEMA1_GATE 109 -#define IMX93_CLK_SEMA2_GATE 110 -#define IMX93_CLK_MU_A_GATE 111 -#define IMX93_CLK_MU_B_GATE 112 -#define IMX93_CLK_EDMA1_GATE 113 -#define IMX93_CLK_EDMA2_GATE 114 -#define IMX93_CLK_FLEXSPI1_GATE 115 -#define IMX93_CLK_GPIO1_GATE 116 -#define IMX93_CLK_GPIO2_GATE 117 -#define IMX93_CLK_GPIO3_GATE 118 -#define IMX93_CLK_GPIO4_GATE 119 -#define IMX93_CLK_FLEXIO1_GATE 120 -#define IMX93_CLK_FLEXIO2_GATE 121 -#define IMX93_CLK_LPIT1_GATE 122 -#define IMX93_CLK_LPIT2_GATE 123 -#define IMX93_CLK_LPTMR1_GATE 124 -#define IMX93_CLK_LPTMR2_GATE 125 -#define IMX93_CLK_TPM1_GATE 126 -#define IMX93_CLK_TPM2_GATE 127 -#define IMX93_CLK_TPM3_GATE 128 -#define IMX93_CLK_TPM4_GATE 129 -#define IMX93_CLK_TPM5_GATE 130 -#define IMX93_CLK_TPM6_GATE 131 -#define IMX93_CLK_CAN1_GATE 132 -#define IMX93_CLK_CAN2_GATE 133 -#define IMX93_CLK_LPUART1_GATE 134 -#define IMX93_CLK_LPUART2_GATE 135 -#define IMX93_CLK_LPUART3_GATE 136 -#define IMX93_CLK_LPUART4_GATE 137 -#define IMX93_CLK_LPUART5_GATE 138 -#define IMX93_CLK_LPUART6_GATE 139 -#define IMX93_CLK_LPUART7_GATE 140 -#define IMX93_CLK_LPUART8_GATE 141 -#define IMX93_CLK_LPI2C1_GATE 142 -#define IMX93_CLK_LPI2C2_GATE 143 -#define IMX93_CLK_LPI2C3_GATE 144 -#define IMX93_CLK_LPI2C4_GATE 145 -#define IMX93_CLK_LPI2C5_GATE 146 -#define IMX93_CLK_LPI2C6_GATE 147 -#define IMX93_CLK_LPI2C7_GATE 148 -#define IMX93_CLK_LPI2C8_GATE 149 -#define IMX93_CLK_LPSPI1_GATE 150 -#define IMX93_CLK_LPSPI2_GATE 151 -#define IMX93_CLK_LPSPI3_GATE 152 -#define IMX93_CLK_LPSPI4_GATE 153 -#define IMX93_CLK_LPSPI5_GATE 154 -#define IMX93_CLK_LPSPI6_GATE 155 -#define IMX93_CLK_LPSPI7_GATE 156 -#define IMX93_CLK_LPSPI8_GATE 157 -#define IMX93_CLK_I3C1_GATE 158 -#define IMX93_CLK_I3C2_GATE 159 -#define IMX93_CLK_USDHC1_GATE 160 -#define IMX93_CLK_USDHC2_GATE 161 -#define IMX93_CLK_USDHC3_GATE 162 -#define IMX93_CLK_SAI1_GATE 163 -#define IMX93_CLK_SAI2_GATE 164 -#define IMX93_CLK_SAI3_GATE 165 -#define IMX93_CLK_MIPI_CSI_GATE 166 -#define IMX93_CLK_MIPI_DSI_GATE 167 -#define IMX93_CLK_LVDS_GATE 168 -#define IMX93_CLK_LCDIF_GATE 169 -#define IMX93_CLK_PXP_GATE 170 -#define IMX93_CLK_ISI_GATE 171 -#define IMX93_CLK_NIC_MEDIA_GATE 172 -#define IMX93_CLK_USB_CONTROLLER_GATE 173 -#define IMX93_CLK_USB_TEST_60M_GATE 174 -#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 -#define IMX93_CLK_PDM_GATE 176 -#define IMX93_CLK_MQS1_GATE 177 -#define IMX93_CLK_MQS2_GATE 178 -#define IMX93_CLK_AUD_XCVR_GATE 179 -#define IMX93_CLK_SPDIF_GATE 180 -#define IMX93_CLK_HSIO_32K_GATE 181 -#define IMX93_CLK_ENET1_GATE 182 -#define IMX93_CLK_ENET_QOS_GATE 183 -#define IMX93_CLK_SYS_CNT_GATE 184 -#define IMX93_CLK_TSTMR1_GATE 185 -#define IMX93_CLK_TSTMR2_GATE 186 -#define IMX93_CLK_TMC_GATE 187 -#define IMX93_CLK_PMRO_GATE 188 -#define IMX93_CLK_32K 189 -#define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_MU1_A_GATE 193 -#define IMX93_CLK_MU1_B_GATE 194 -#define IMX93_CLK_MU2_A_GATE 195 -#define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_NIC_AXI 197 -#define IMX93_CLK_ARM_PLL 198 -#define IMX93_CLK_A55_SEL 199 -#define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 - -#endif diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h deleted file mode 100644 index 93bef0832d16..000000000000 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright(C) 2019 - * Author(s): Giulio Benetti giulio.benetti@benettiengineering.com - */ - -#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H -#define __DT_BINDINGS_CLOCK_IMXRT1050_H - -#define IMXRT1050_CLK_DUMMY 0 -#define IMXRT1050_CLK_CKIL 1 -#define IMXRT1050_CLK_CKIH 2 -#define IMXRT1050_CLK_OSC 3 -#define IMXRT1050_CLK_PLL2_PFD0_352M 4 -#define IMXRT1050_CLK_PLL2_PFD1_594M 5 -#define IMXRT1050_CLK_PLL2_PFD2_396M 6 -#define IMXRT1050_CLK_PLL3_PFD0_720M 7 -#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 -#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 -#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 -#define IMXRT1050_CLK_PLL2_198M 11 -#define IMXRT1050_CLK_PLL3_120M 12 -#define IMXRT1050_CLK_PLL3_80M 13 -#define IMXRT1050_CLK_PLL3_60M 14 -#define IMXRT1050_CLK_PLL1_BYPASS 15 -#define IMXRT1050_CLK_PLL2_BYPASS 16 -#define IMXRT1050_CLK_PLL3_BYPASS 17 -#define IMXRT1050_CLK_PLL5_BYPASS 19 -#define IMXRT1050_CLK_PLL1_REF_SEL 20 -#define IMXRT1050_CLK_PLL2_REF_SEL 21 -#define IMXRT1050_CLK_PLL3_REF_SEL 22 -#define IMXRT1050_CLK_PLL5_REF_SEL 23 -#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 -#define IMXRT1050_CLK_PERIPH_SEL 25 -#define IMXRT1050_CLK_SEMC_ALT_SEL 26 -#define IMXRT1050_CLK_SEMC_SEL 27 -#define IMXRT1050_CLK_USDHC1_SEL 28 -#define IMXRT1050_CLK_USDHC2_SEL 29 -#define IMXRT1050_CLK_LPUART_SEL 30 -#define IMXRT1050_CLK_LCDIF_SEL 31 -#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 -#define IMXRT1050_CLK_VIDEO_DIV 33 -#define IMXRT1050_CLK_ARM_PODF 34 -#define IMXRT1050_CLK_LPUART_PODF 35 -#define IMXRT1050_CLK_USDHC1_PODF 36 -#define IMXRT1050_CLK_USDHC2_PODF 37 -#define IMXRT1050_CLK_SEMC_PODF 38 -#define IMXRT1050_CLK_AHB_PODF 39 -#define IMXRT1050_CLK_LCDIF_PRED 40 -#define IMXRT1050_CLK_LCDIF_PODF 41 -#define IMXRT1050_CLK_USDHC1 42 -#define IMXRT1050_CLK_USDHC2 43 -#define IMXRT1050_CLK_LPUART1 44 -#define IMXRT1050_CLK_SEMC 45 -#define IMXRT1050_CLK_LCDIF_APB 46 -#define IMXRT1050_CLK_PLL1_ARM 47 -#define IMXRT1050_CLK_PLL2_SYS 48 -#define IMXRT1050_CLK_PLL3_USB_OTG 49 -#define IMXRT1050_CLK_PLL4_AUDIO 50 -#define IMXRT1050_CLK_PLL5_VIDEO 51 -#define IMXRT1050_CLK_PLL6_ENET 52 -#define IMXRT1050_CLK_PLL7_USB_HOST 53 -#define IMXRT1050_CLK_LCDIF_PIX 54 -#define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_IPG_PDOF 56 -#define IMXRT1050_CLK_PER_CLK_SEL 57 -#define IMXRT1050_CLK_PER_PDOF 58 -#define IMXRT1050_CLK_DMA 59 -#define IMXRT1050_CLK_DMA_MUX 60 -#define IMXRT1050_CLK_END 61 - -#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */

Dropped in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Tested-by: Neil Armstrong neil.armstrong@linaro.org # on AML-S805X-AC Tested-by: Neil Armstrong neil.armstrong@linaro.org # on AML-S905X-CC Tested-by: Neil Armstrong neil.armstrong@linaro.org # on BPI-M2S Tested-by: Neil Armstrong neil.armstrong@linaro.org # on BPI-M5 --- .../clock/amlogic,a1-peripherals-clkc.h | 168 --------------------- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 --- include/dt-bindings/clock/axg-aoclkc.h | 31 ---- include/dt-bindings/clock/axg-audio-clkc.h | 94 ------------ include/dt-bindings/clock/axg-clkc.h | 100 ------------ include/dt-bindings/clock/g12a-aoclkc.h | 36 ----- include/dt-bindings/clock/g12a-clkc.h | 153 ------------------- include/dt-bindings/clock/gxbb-aoclkc.h | 74 --------- include/dt-bindings/clock/gxbb-clkc.h | 151 ------------------ include/dt-bindings/gpio/meson-a1-gpio.h | 73 --------- include/dt-bindings/gpio/meson-axg-gpio.h | 116 -------------- include/dt-bindings/gpio/meson-g12a-gpio.h | 114 -------------- include/dt-bindings/gpio/meson-gxbb-gpio.h | 148 ------------------ include/dt-bindings/gpio/meson-gxl-gpio.h | 125 --------------- include/dt-bindings/power/meson-a1-power.h | 32 ---- include/dt-bindings/power/meson-axg-power.h | 14 -- include/dt-bindings/power/meson-g12a-power.h | 13 -- include/dt-bindings/power/meson-gxbb-power.h | 13 -- include/dt-bindings/power/meson-sm1-power.h | 18 --- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 76 ---------- .../reset/amlogic,meson-axg-audio-arb.h | 19 --- .../dt-bindings/reset/amlogic,meson-axg-reset.h | 123 --------------- .../reset/amlogic,meson-g12a-audio-reset.h | 53 ------- .../dt-bindings/reset/amlogic,meson-g12a-reset.h | 137 ----------------- .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 161 -------------------- include/dt-bindings/reset/axg-aoclkc.h | 20 --- include/dt-bindings/reset/g12a-aoclkc.h | 18 --- include/dt-bindings/reset/gxbb-aoclkc.h | 66 -------- include/dt-bindings/sound/meson-aiu.h | 18 --- include/dt-bindings/sound/meson-g12a-toacodec.h | 10 -- include/dt-bindings/sound/meson-g12a-tohdmitx.h | 13 -- 31 files changed, 2212 deletions(-)

diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h deleted file mode 100644 index 06f198ee7623..000000000000 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu jian.hu@amlogic.com - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov ddrokosov@sberdevices.ru - */ - -#ifndef __A1_PERIPHERALS_CLKC_H -#define __A1_PERIPHERALS_CLKC_H - -#define CLKID_XTAL_IN 0 -#define CLKID_FIXPLL_IN 1 -#define CLKID_USB_PHY_IN 2 -#define CLKID_USB_CTRL_IN 3 -#define CLKID_HIFIPLL_IN 4 -#define CLKID_SYSPLL_IN 5 -#define CLKID_DDS_IN 6 -#define CLKID_SYS 7 -#define CLKID_CLKTREE 8 -#define CLKID_RESET_CTRL 9 -#define CLKID_ANALOG_CTRL 10 -#define CLKID_PWR_CTRL 11 -#define CLKID_PAD_CTRL 12 -#define CLKID_SYS_CTRL 13 -#define CLKID_TEMP_SENSOR 14 -#define CLKID_AM2AXI_DIV 15 -#define CLKID_SPICC_B 16 -#define CLKID_SPICC_A 17 -#define CLKID_MSR 18 -#define CLKID_AUDIO 19 -#define CLKID_JTAG_CTRL 20 -#define CLKID_SARADC_EN 21 -#define CLKID_PWM_EF 22 -#define CLKID_PWM_CD 23 -#define CLKID_PWM_AB 24 -#define CLKID_CEC 25 -#define CLKID_I2C_S 26 -#define CLKID_IR_CTRL 27 -#define CLKID_I2C_M_D 28 -#define CLKID_I2C_M_C 29 -#define CLKID_I2C_M_B 30 -#define CLKID_I2C_M_A 31 -#define CLKID_ACODEC 32 -#define CLKID_OTP 33 -#define CLKID_SD_EMMC_A 34 -#define CLKID_USB_PHY 35 -#define CLKID_USB_CTRL 36 -#define CLKID_SYS_DSPB 37 -#define CLKID_SYS_DSPA 38 -#define CLKID_DMA 39 -#define CLKID_IRQ_CTRL 40 -#define CLKID_NIC 41 -#define CLKID_GIC 42 -#define CLKID_UART_C 43 -#define CLKID_UART_B 44 -#define CLKID_UART_A 45 -#define CLKID_SYS_PSRAM 46 -#define CLKID_RSA 47 -#define CLKID_CORESIGHT 48 -#define CLKID_AM2AXI_VAD 49 -#define CLKID_AUDIO_VAD 50 -#define CLKID_AXI_DMC 51 -#define CLKID_AXI_PSRAM 52 -#define CLKID_RAMB 53 -#define CLKID_RAMA 54 -#define CLKID_AXI_SPIFC 55 -#define CLKID_AXI_NIC 56 -#define CLKID_AXI_DMA 57 -#define CLKID_CPU_CTRL 58 -#define CLKID_ROM 59 -#define CLKID_PROC_I2C 60 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_DSPA_EN 63 -#define CLKID_DSPA_EN_NIC 64 -#define CLKID_DSPB_EN 65 -#define CLKID_DSPB_EN_NIC 66 -#define CLKID_RTC 67 -#define CLKID_CECA_32K 68 -#define CLKID_CECB_32K 69 -#define CLKID_24M 70 -#define CLKID_12M 71 -#define CLKID_FCLK_DIV2_DIVN 72 -#define CLKID_GEN 73 -#define CLKID_SARADC_SEL 74 -#define CLKID_SARADC 75 -#define CLKID_PWM_A 76 -#define CLKID_PWM_B 77 -#define CLKID_PWM_C 78 -#define CLKID_PWM_D 79 -#define CLKID_PWM_E 80 -#define CLKID_PWM_F 81 -#define CLKID_SPICC 82 -#define CLKID_TS 83 -#define CLKID_SPIFC 84 -#define CLKID_USB_BUS 85 -#define CLKID_SD_EMMC 86 -#define CLKID_PSRAM 87 -#define CLKID_DMC 88 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_SEL 95 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_SEL 98 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_SEL 101 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_SEL 104 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECB_32K_SEL_PRE 113 -#define CLKID_CECB_32K_SEL 114 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_CECA_32K_SEL_PRE 117 -#define CLKID_CECA_32K_SEL 118 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_SEL 121 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_SEL 124 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_SEL 126 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_SEL 128 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_SEL 130 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_SEL 132 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_SEL 134 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_SD_EMMC_SEL2 147 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - -#endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h deleted file mode 100644 index 2b660c0f2c9f..000000000000 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu jian.hu@amlogic.com - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov ddrokosov@sberdevices.ru - */ - -#ifndef __A1_PLL_CLKC_H -#define __A1_PLL_CLKC_H - -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 -#define CLKID_FCLK_DIV2 6 -#define CLKID_FCLK_DIV3 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_HIFI_PLL 10 - -#endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h deleted file mode 100644 index 8ec4a269c7a6..000000000000 --- a/include/dt-bindings/clock/axg-aoclkc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_SAR_ADC 6 -#define CLKID_AO_CLK81 7 -#define CLKID_AO_SAR_ADC_SEL 8 -#define CLKID_AO_SAR_ADC_DIV 9 -#define CLKID_AO_SAR_ADC_CLK 10 -#define CLKID_AO_CTS_OSCIN 11 -#define CLKID_AO_32K_PRE 12 -#define CLKID_AO_32K_DIV 13 -#define CLKID_AO_32K_SEL 14 -#define CLKID_AO_32K 15 -#define CLKID_AO_CTS_RTC_OSCIN 16 - -#endif diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8f..000000000000 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index 93752ea107e3..000000000000 --- a/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_GEN_CLK 84 -#define CLKID_VPU_0_SEL 92 -#define CLKID_VPU_0 93 -#define CLKID_VPU_1_SEL 95 -#define CLKID_VPU_1 96 -#define CLKID_VPU 97 -#define CLKID_VAPB_0_SEL 99 -#define CLKID_VAPB_0 100 -#define CLKID_VAPB_1_SEL 102 -#define CLKID_VAPB_1 103 -#define CLKID_VAPB_SEL 104 -#define CLKID_VAPB 105 -#define CLKID_VCLK 106 -#define CLKID_VCLK2 107 -#define CLKID_VCLK_DIV1 122 -#define CLKID_VCLK_DIV2 123 -#define CLKID_VCLK_DIV4 124 -#define CLKID_VCLK_DIV6 125 -#define CLKID_VCLK_DIV12 126 -#define CLKID_VCLK2_DIV1 127 -#define CLKID_VCLK2_DIV2 128 -#define CLKID_VCLK2_DIV4 129 -#define CLKID_VCLK2_DIV6 130 -#define CLKID_VCLK2_DIV12 131 -#define CLKID_CTS_ENCL 133 -#define CLKID_VDIN_MEAS 136 - -#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h deleted file mode 100644 index e916e49ff288..000000000000 --- a/include/dt-bindings/clock/g12a-aoclkc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK - -#define CLKID_AO_AHB 0 -#define CLKID_AO_IR_IN 1 -#define CLKID_AO_I2C_M0 2 -#define CLKID_AO_I2C_S0 3 -#define CLKID_AO_UART 4 -#define CLKID_AO_PROD_I2C 5 -#define CLKID_AO_UART2 6 -#define CLKID_AO_IR_OUT 7 -#define CLKID_AO_SAR_ADC 8 -#define CLKID_AO_MAILBOX 9 -#define CLKID_AO_M3 10 -#define CLKID_AO_AHB_SRAM 11 -#define CLKID_AO_RTI 12 -#define CLKID_AO_M4_FCLK 13 -#define CLKID_AO_M4_HCLK 14 -#define CLKID_AO_CLK81 15 -#define CLKID_AO_SAR_ADC_SEL 16 -#define CLKID_AO_SAR_ADC_CLK 18 -#define CLKID_AO_CTS_OSCIN 19 -#define CLKID_AO_32K 23 -#define CLKID_AO_CEC 27 -#define CLKID_AO_CTS_RTC_OSCIN 28 - -#endif diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h deleted file mode 100644 index a93b58c5e18e..000000000000 --- a/include/dt-bindings/clock/g12a-clkc.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Meson-G12A clock tree IDs - * - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#ifndef __G12A_CLKC_H -#define __G12A_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_DOS 16 -#define CLKID_AUDIO_LOCKER 17 -#define CLKID_MIPI_DSI_HOST 18 -#define CLKID_ETH_PHY 19 -#define CLKID_ISA 20 -#define CLKID_PL301 21 -#define CLKID_PERIPHS 22 -#define CLKID_SPICC0 23 -#define CLKID_I2C 24 -#define CLKID_SANA 25 -#define CLKID_SD 26 -#define CLKID_RNG0 27 -#define CLKID_UART0 28 -#define CLKID_SPICC1 29 -#define CLKID_HIU_IFACE 30 -#define CLKID_MIPI_DSI_PHY 31 -#define CLKID_ASSIST_MISC 32 -#define CLKID_SD_EMMC_A 33 -#define CLKID_SD_EMMC_B 34 -#define CLKID_SD_EMMC_C 35 -#define CLKID_AUDIO_CODEC 36 -#define CLKID_AUDIO 37 -#define CLKID_ETH 38 -#define CLKID_DEMUX 39 -#define CLKID_AUDIO_IFIFO 40 -#define CLKID_ADC 41 -#define CLKID_UART1 42 -#define CLKID_G2D 43 -#define CLKID_RESET 44 -#define CLKID_PCIE_COMB 45 -#define CLKID_PARSER 46 -#define CLKID_USB 47 -#define CLKID_PCIE_PHY 48 -#define CLKID_AHB_ARB0 49 -#define CLKID_AHB_DATA_BUS 50 -#define CLKID_AHB_CTRL_BUS 51 -#define CLKID_HTX_HDCP22 52 -#define CLKID_HTX_PCLK 53 -#define CLKID_BT656 54 -#define CLKID_USB1_DDR_BRIDGE 55 -#define CLKID_MMC_PCLK 56 -#define CLKID_UART2 57 -#define CLKID_VPU_INTR 58 -#define CLKID_GIC 59 -#define CLKID_SD_EMMC_A_CLK0 60 -#define CLKID_SD_EMMC_B_CLK0 61 -#define CLKID_SD_EMMC_C_CLK0 62 -#define CLKID_HIFI_PLL 74 -#define CLKID_VCLK2_VENCI0 80 -#define CLKID_VCLK2_VENCI1 81 -#define CLKID_VCLK2_VENCP0 82 -#define CLKID_VCLK2_VENCP1 83 -#define CLKID_VCLK2_VENCT0 84 -#define CLKID_VCLK2_VENCT1 85 -#define CLKID_VCLK2_OTHER 86 -#define CLKID_VCLK2_ENCI 87 -#define CLKID_VCLK2_ENCP 88 -#define CLKID_DAC_CLK 89 -#define CLKID_AOCLK 90 -#define CLKID_IEC958 91 -#define CLKID_ENC480P 92 -#define CLKID_RNG1 93 -#define CLKID_VCLK2_ENCT 94 -#define CLKID_VCLK2_ENCL 95 -#define CLKID_VCLK2_VENCLMMC 96 -#define CLKID_VCLK2_VENCL 97 -#define CLKID_VCLK2_OTHER1 98 -#define CLKID_FCLK_DIV2P5 99 -#define CLKID_DMA 105 -#define CLKID_EFUSE 106 -#define CLKID_ROM_BOOT 107 -#define CLKID_RESET_SEC 108 -#define CLKID_SEC_AHB_APB3 109 -#define CLKID_VPU_0_SEL 110 -#define CLKID_VPU_0 112 -#define CLKID_VPU_1_SEL 113 -#define CLKID_VPU_1 115 -#define CLKID_VPU 116 -#define CLKID_VAPB_0_SEL 117 -#define CLKID_VAPB_0 119 -#define CLKID_VAPB_1_SEL 120 -#define CLKID_VAPB_1 122 -#define CLKID_VAPB_SEL 123 -#define CLKID_VAPB 124 -#define CLKID_HDMI_PLL 128 -#define CLKID_VID_PLL 129 -#define CLKID_VCLK 138 -#define CLKID_VCLK2 139 -#define CLKID_VCLK_DIV1 148 -#define CLKID_VCLK_DIV2 149 -#define CLKID_VCLK_DIV4 150 -#define CLKID_VCLK_DIV6 151 -#define CLKID_VCLK_DIV12 152 -#define CLKID_VCLK2_DIV1 153 -#define CLKID_VCLK2_DIV2 154 -#define CLKID_VCLK2_DIV4 155 -#define CLKID_VCLK2_DIV6 156 -#define CLKID_VCLK2_DIV12 157 -#define CLKID_CTS_ENCI 162 -#define CLKID_CTS_ENCP 163 -#define CLKID_CTS_VDAC 164 -#define CLKID_HDMI_TX 165 -#define CLKID_HDMI 168 -#define CLKID_MALI_0_SEL 169 -#define CLKID_MALI_0 171 -#define CLKID_MALI_1_SEL 172 -#define CLKID_MALI_1 174 -#define CLKID_MALI 175 -#define CLKID_MPLL_50M 177 -#define CLKID_CPU_CLK 187 -#define CLKID_PCIE_PLL 201 -#define CLKID_VDEC_1 204 -#define CLKID_VDEC_HEVC 207 -#define CLKID_VDEC_HEVCF 210 -#define CLKID_TS 212 -#define CLKID_CPUB_CLK 224 -#define CLKID_GP1_PLL 243 -#define CLKID_DSU_CLK 252 -#define CLKID_CPU1_CLK 253 -#define CLKID_CPU2_CLK 254 -#define CLKID_CPU3_CLK 255 -#define CLKID_SPICC0_SCLK 258 -#define CLKID_SPICC1_SCLK 261 -#define CLKID_NNA_AXI_CLK 264 -#define CLKID_NNA_CORE_CLK 267 -#define CLKID_MIPI_DSI_PXCLK_SEL 269 -#define CLKID_MIPI_DSI_PXCLK 270 - -#endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h deleted file mode 100644 index ec3b26319fc4..000000000000 --- a/include/dt-bindings/clock/gxbb-aoclkc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see http://www.gnu.org/licenses/. - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_CEC_32K 6 -#define CLKID_AO_CTS_OSCIN 7 -#define CLKID_AO_32K_PRE 8 -#define CLKID_AO_32K_DIV 9 -#define CLKID_AO_32K_SEL 10 -#define CLKID_AO_32K 11 -#define CLKID_AO_CTS_RTC_OSCIN 12 -#define CLKID_AO_CLK81 13 - -#endif diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h deleted file mode 100644 index 4073eb7a9da1..000000000000 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * GXBB clock tree IDs - */ - -#ifndef __GXBB_CLKC_H -#define __GXBB_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_HDMI_PLL 2 -#define CLKID_FIXED_PLL 3 -#define CLKID_FCLK_DIV2 4 -#define CLKID_FCLK_DIV3 5 -#define CLKID_FCLK_DIV4 6 -#define CLKID_FCLK_DIV5 7 -#define CLKID_FCLK_DIV7 8 -#define CLKID_GP0_PLL 9 -#define CLKID_CLK81 12 -#define CLKID_MPLL0 13 -#define CLKID_MPLL1 14 -#define CLKID_MPLL2 15 -#define CLKID_DDR 16 -#define CLKID_DOS 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC 21 -#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 -#define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 -#define CLKID_UART0 26 -#define CLKID_SDHC 27 -#define CLKID_STREAM 28 -#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 -#define CLKID_ABUF 31 -#define CLKID_HIU_IFACE 32 -#define CLKID_ASSIST_MISC 33 -#define CLKID_SPI 34 -#define CLKID_ETH 36 -#define CLKID_I2S_SPDIF 35 -#define CLKID_DEMUX 37 -#define CLKID_AIU_GLUE 38 -#define CLKID_IEC958 39 -#define CLKID_I2S_OUT 40 -#define CLKID_AMCLK 41 -#define CLKID_AIFIFO2 42 -#define CLKID_MIXER 43 -#define CLKID_MIXER_IFACE 44 -#define CLKID_ADC 45 -#define CLKID_BLKMV 46 -#define CLKID_AIU 47 -#define CLKID_UART1 48 -#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 -#define CLKID_RESET 52 -#define CLKID_NAND 53 -#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 -#define CLKID_VDIN1 56 -#define CLKID_AHB_ARB0 57 -#define CLKID_EFUSE 58 -#define CLKID_BOOT_ROM 59 -#define CLKID_AHB_DATA_BUS 60 -#define CLKID_AHB_CTRL_BUS 61 -#define CLKID_HDMI_INTR_SYNC 62 -#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 -#define CLKID_MMC_PCLK 66 -#define CLKID_DVIN 67 -#define CLKID_UART2 68 -#define CLKID_SANA 69 -#define CLKID_VPU_INTR 70 -#define CLKID_SEC_AHB_AHB3_BRIDGE 71 -#define CLKID_CLK81_A53 72 -#define CLKID_VCLK2_VENCI0 73 -#define CLKID_VCLK2_VENCI1 74 -#define CLKID_VCLK2_VENCP0 75 -#define CLKID_VCLK2_VENCP1 76 -#define CLKID_GCLK_VENCI_INT0 77 -#define CLKID_GCLK_VENCI_INT 78 -#define CLKID_DAC_CLK 79 -#define CLKID_AOCLK_GATE 80 -#define CLKID_IEC958_GATE 81 -#define CLKID_ENC480P 82 -#define CLKID_RNG1 83 -#define CLKID_GCLK_VENCI_INT1 84 -#define CLKID_VCLK2_VENCLMCC 85 -#define CLKID_VCLK2_VENCL 86 -#define CLKID_VCLK_OTHER 87 -#define CLKID_EDP 88 -#define CLKID_AO_MEDIA_CPU 89 -#define CLKID_AO_AHB_SRAM 90 -#define CLKID_AO_AHB_BUS 91 -#define CLKID_AO_IFACE 92 -#define CLKID_AO_I2C 93 -#define CLKID_SD_EMMC_A 94 -#define CLKID_SD_EMMC_B 95 -#define CLKID_SD_EMMC_C 96 -#define CLKID_SAR_ADC_CLK 97 -#define CLKID_SAR_ADC_SEL 98 -#define CLKID_MALI_0_SEL 100 -#define CLKID_MALI_0 102 -#define CLKID_MALI_1_SEL 103 -#define CLKID_MALI_1 105 -#define CLKID_MALI 106 -#define CLKID_CTS_AMCLK 107 -#define CLKID_CTS_MCLK_I958 110 -#define CLKID_CTS_I958 113 -#define CLKID_32K_CLK 114 -#define CLKID_SD_EMMC_A_CLK0 119 -#define CLKID_SD_EMMC_B_CLK0 122 -#define CLKID_SD_EMMC_C_CLK0 125 -#define CLKID_VPU_0_SEL 126 -#define CLKID_VPU_0 128 -#define CLKID_VPU_1_SEL 129 -#define CLKID_VPU_1 131 -#define CLKID_VPU 132 -#define CLKID_VAPB_0_SEL 133 -#define CLKID_VAPB_0 135 -#define CLKID_VAPB_1_SEL 136 -#define CLKID_VAPB_1 138 -#define CLKID_VAPB_SEL 139 -#define CLKID_VAPB 140 -#define CLKID_VDEC_1 153 -#define CLKID_VDEC_HEVC 156 -#define CLKID_GEN_CLK 159 -#define CLKID_VID_PLL 166 -#define CLKID_VCLK 175 -#define CLKID_VCLK2 176 -#define CLKID_VCLK_DIV1 185 -#define CLKID_VCLK_DIV2 186 -#define CLKID_VCLK_DIV4 187 -#define CLKID_VCLK_DIV6 188 -#define CLKID_VCLK_DIV12 189 -#define CLKID_VCLK2_DIV1 190 -#define CLKID_VCLK2_DIV2 191 -#define CLKID_VCLK2_DIV4 192 -#define CLKID_VCLK2_DIV6 193 -#define CLKID_VCLK2_DIV12 194 -#define CLKID_CTS_ENCI 199 -#define CLKID_CTS_ENCP 200 -#define CLKID_CTS_VDAC 201 -#define CLKID_HDMI_TX 202 -#define CLKID_HDMI 205 -#define CLKID_ACODEC 206 - -#endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1db..000000000000 --- a/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song qianggui.song@amlogic.com - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h deleted file mode 100644 index 25bb1fffa97a..000000000000 --- a/include/dt-bindings/gpio/meson-axg-gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H -#define _DT_BINDINGS_MESON_AXG_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define BOOT_0 11 -#define BOOT_1 12 -#define BOOT_2 13 -#define BOOT_3 14 -#define BOOT_4 15 -#define BOOT_5 16 -#define BOOT_6 17 -#define BOOT_7 18 -#define BOOT_8 19 -#define BOOT_9 20 -#define BOOT_10 21 -#define BOOT_11 22 -#define BOOT_12 23 -#define BOOT_13 24 -#define BOOT_14 25 -#define GPIOA_0 26 -#define GPIOA_1 27 -#define GPIOA_2 28 -#define GPIOA_3 29 -#define GPIOA_4 30 -#define GPIOA_5 31 -#define GPIOA_6 32 -#define GPIOA_7 33 -#define GPIOA_8 34 -#define GPIOA_9 35 -#define GPIOA_10 36 -#define GPIOA_11 37 -#define GPIOA_12 38 -#define GPIOA_13 39 -#define GPIOA_14 40 -#define GPIOA_15 41 -#define GPIOA_16 42 -#define GPIOA_17 43 -#define GPIOA_18 44 -#define GPIOA_19 45 -#define GPIOA_20 46 -#define GPIOX_0 47 -#define GPIOX_1 48 -#define GPIOX_2 49 -#define GPIOX_3 50 -#define GPIOX_4 51 -#define GPIOX_5 52 -#define GPIOX_6 53 -#define GPIOX_7 54 -#define GPIOX_8 55 -#define GPIOX_9 56 -#define GPIOX_10 57 -#define GPIOX_11 58 -#define GPIOX_12 59 -#define GPIOX_13 60 -#define GPIOX_14 61 -#define GPIOX_15 62 -#define GPIOX_16 63 -#define GPIOX_17 64 -#define GPIOX_18 65 -#define GPIOX_19 66 -#define GPIOX_20 67 -#define GPIOX_21 68 -#define GPIOX_22 69 -#define GPIOY_0 70 -#define GPIOY_1 71 -#define GPIOY_2 72 -#define GPIOY_3 73 -#define GPIOY_4 74 -#define GPIOY_5 75 -#define GPIOY_6 76 -#define GPIOY_7 77 -#define GPIOY_8 78 -#define GPIOY_9 79 -#define GPIOY_10 80 -#define GPIOY_11 81 -#define GPIOY_12 82 -#define GPIOY_13 83 -#define GPIOY_14 84 -#define GPIOY_15 85 - -#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h deleted file mode 100644 index f7bd69350d18..000000000000 --- a/include/dt-bindings/gpio/meson-g12a-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - */ - -#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H -#define _DT_BINDINGS_MESON_G12A_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOE_0 12 -#define GPIOE_1 13 -#define GPIOE_2 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define BOOT_0 25 -#define BOOT_1 26 -#define BOOT_2 27 -#define BOOT_3 28 -#define BOOT_4 29 -#define BOOT_5 30 -#define BOOT_6 31 -#define BOOT_7 32 -#define BOOT_8 33 -#define BOOT_9 34 -#define BOOT_10 35 -#define BOOT_11 36 -#define BOOT_12 37 -#define BOOT_13 38 -#define BOOT_14 39 -#define BOOT_15 40 -#define GPIOC_0 41 -#define GPIOC_1 42 -#define GPIOC_2 43 -#define GPIOC_3 44 -#define GPIOC_4 45 -#define GPIOC_5 46 -#define GPIOC_6 47 -#define GPIOC_7 48 -#define GPIOA_0 49 -#define GPIOA_1 50 -#define GPIOA_2 51 -#define GPIOA_3 52 -#define GPIOA_4 53 -#define GPIOA_5 54 -#define GPIOA_6 55 -#define GPIOA_7 56 -#define GPIOA_8 57 -#define GPIOA_9 58 -#define GPIOA_10 59 -#define GPIOA_11 60 -#define GPIOA_12 61 -#define GPIOA_13 62 -#define GPIOA_14 63 -#define GPIOA_15 64 -#define GPIOX_0 65 -#define GPIOX_1 66 -#define GPIOX_2 67 -#define GPIOX_3 68 -#define GPIOX_4 69 -#define GPIOX_5 70 -#define GPIOX_6 71 -#define GPIOX_7 72 -#define GPIOX_8 73 -#define GPIOX_9 74 -#define GPIOX_10 75 -#define GPIOX_11 76 -#define GPIOX_12 77 -#define GPIOX_13 78 -#define GPIOX_14 79 -#define GPIOX_15 80 -#define GPIOX_16 81 -#define GPIOX_17 82 -#define GPIOX_18 83 -#define GPIOX_19 84 - -#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h deleted file mode 100644 index 489c75b27645..000000000000 --- a/include/dt-bindings/gpio/meson-gxbb-gpio.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXBB SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione carlo@endlessm.com - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H -#define _DT_BINDINGS_MESON_GXBB_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define BOOT_0 20 -#define BOOT_1 21 -#define BOOT_2 22 -#define BOOT_3 23 -#define BOOT_4 24 -#define BOOT_5 25 -#define BOOT_6 26 -#define BOOT_7 27 -#define BOOT_8 28 -#define BOOT_9 29 -#define BOOT_10 30 -#define BOOT_11 31 -#define BOOT_12 32 -#define BOOT_13 33 -#define BOOT_14 34 -#define BOOT_15 35 -#define BOOT_16 36 -#define BOOT_17 37 -#define CARD_0 38 -#define CARD_1 39 -#define CARD_2 40 -#define CARD_3 41 -#define CARD_4 42 -#define CARD_5 43 -#define CARD_6 44 -#define GPIODV_0 45 -#define GPIODV_1 46 -#define GPIODV_2 47 -#define GPIODV_3 48 -#define GPIODV_4 49 -#define GPIODV_5 50 -#define GPIODV_6 51 -#define GPIODV_7 52 -#define GPIODV_8 53 -#define GPIODV_9 54 -#define GPIODV_10 55 -#define GPIODV_11 56 -#define GPIODV_12 57 -#define GPIODV_13 58 -#define GPIODV_14 59 -#define GPIODV_15 60 -#define GPIODV_16 61 -#define GPIODV_17 62 -#define GPIODV_18 63 -#define GPIODV_19 64 -#define GPIODV_20 65 -#define GPIODV_21 66 -#define GPIODV_22 67 -#define GPIODV_23 68 -#define GPIODV_24 69 -#define GPIODV_25 70 -#define GPIODV_26 71 -#define GPIODV_27 72 -#define GPIODV_28 73 -#define GPIODV_29 74 -#define GPIOY_0 75 -#define GPIOY_1 76 -#define GPIOY_2 77 -#define GPIOY_3 78 -#define GPIOY_4 79 -#define GPIOY_5 80 -#define GPIOY_6 81 -#define GPIOY_7 82 -#define GPIOY_8 83 -#define GPIOY_9 84 -#define GPIOY_10 85 -#define GPIOY_11 86 -#define GPIOY_12 87 -#define GPIOY_13 88 -#define GPIOY_14 89 -#define GPIOY_15 90 -#define GPIOY_16 91 -#define GPIOX_0 92 -#define GPIOX_1 93 -#define GPIOX_2 94 -#define GPIOX_3 95 -#define GPIOX_4 96 -#define GPIOX_5 97 -#define GPIOX_6 98 -#define GPIOX_7 99 -#define GPIOX_8 100 -#define GPIOX_9 101 -#define GPIOX_10 102 -#define GPIOX_11 103 -#define GPIOX_12 104 -#define GPIOX_13 105 -#define GPIOX_14 106 -#define GPIOX_15 107 -#define GPIOX_16 108 -#define GPIOX_17 109 -#define GPIOX_18 110 -#define GPIOX_19 111 -#define GPIOX_20 112 -#define GPIOX_21 113 -#define GPIOX_22 114 -#define GPIOCLK_0 115 -#define GPIOCLK_1 116 -#define GPIOCLK_2 117 -#define GPIOCLK_3 118 - -#endif diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h deleted file mode 100644 index 0a001ae48272..000000000000 --- a/include/dt-bindings/gpio/meson-gxl-gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXL SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione carlo@endlessm.com - */ - -#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H -#define _DT_BINDINGS_MESON_GXL_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIO_TEST_N 10 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define GPIOH_9 25 -#define BOOT_0 26 -#define BOOT_1 27 -#define BOOT_2 28 -#define BOOT_3 29 -#define BOOT_4 30 -#define BOOT_5 31 -#define BOOT_6 32 -#define BOOT_7 33 -#define BOOT_8 34 -#define BOOT_9 35 -#define BOOT_10 36 -#define BOOT_11 37 -#define BOOT_12 38 -#define BOOT_13 39 -#define BOOT_14 40 -#define BOOT_15 41 -#define CARD_0 42 -#define CARD_1 43 -#define CARD_2 44 -#define CARD_3 45 -#define CARD_4 46 -#define CARD_5 47 -#define CARD_6 48 -#define GPIODV_0 49 -#define GPIODV_1 50 -#define GPIODV_2 51 -#define GPIODV_3 52 -#define GPIODV_4 53 -#define GPIODV_5 54 -#define GPIODV_6 55 -#define GPIODV_7 56 -#define GPIODV_8 57 -#define GPIODV_9 58 -#define GPIODV_10 59 -#define GPIODV_11 60 -#define GPIODV_12 61 -#define GPIODV_13 62 -#define GPIODV_14 63 -#define GPIODV_15 64 -#define GPIODV_16 65 -#define GPIODV_17 66 -#define GPIODV_18 67 -#define GPIODV_19 68 -#define GPIODV_20 69 -#define GPIODV_21 70 -#define GPIODV_22 71 -#define GPIODV_23 72 -#define GPIODV_24 73 -#define GPIODV_25 74 -#define GPIODV_26 75 -#define GPIODV_27 76 -#define GPIODV_28 77 -#define GPIODV_29 78 -#define GPIOX_0 79 -#define GPIOX_1 80 -#define GPIOX_2 81 -#define GPIOX_3 82 -#define GPIOX_4 83 -#define GPIOX_5 84 -#define GPIOX_6 85 -#define GPIOX_7 86 -#define GPIOX_8 87 -#define GPIOX_9 88 -#define GPIOX_10 89 -#define GPIOX_11 90 -#define GPIOX_12 91 -#define GPIOX_13 92 -#define GPIOX_14 93 -#define GPIOX_15 94 -#define GPIOX_16 95 -#define GPIOX_17 96 -#define GPIOX_18 97 -#define GPIOCLK_0 98 -#define GPIOCLK_1 99 - -#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h deleted file mode 100644 index 8e39dfc0b62a..000000000000 --- a/include/dt-bindings/power/meson-a1-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2023 SberDevices, Inc. - * Author: Alexey Romanov avromanov@sberdevices.ru - */ - -#ifndef _DT_BINDINGS_MESON_A1_POWER_H -#define _DT_BINDINGS_MESON_A1_POWER_H - -#define PWRC_DSPA_ID 8 -#define PWRC_DSPB_ID 9 -#define PWRC_UART_ID 10 -#define PWRC_DMC_ID 11 -#define PWRC_I2C_ID 12 -#define PWRC_PSRAM_ID 13 -#define PWRC_ACODEC_ID 14 -#define PWRC_AUDIO_ID 15 -#define PWRC_OTP_ID 16 -#define PWRC_DMA_ID 17 -#define PWRC_SD_EMMC_ID 18 -#define PWRC_RAMA_ID 19 -#define PWRC_RAMB_ID 20 -#define PWRC_IR_ID 21 -#define PWRC_SPICC_ID 22 -#define PWRC_SPIFC_ID 23 -#define PWRC_USB_ID 24 -#define PWRC_NIC_ID 25 -#define PWRC_PDMIN_ID 26 -#define PWRC_RSA_ID 27 -#define PWRC_MAX_ID 28 - -#endif diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h deleted file mode 100644 index e5243884b249..000000000000 --- a/include/dt-bindings/power/meson-axg-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2020 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_AXG_POWER_H -#define _DT_BINDINGS_MESON_AXG_POWER_H - -#define PWRC_AXG_VPU_ID 0 -#define PWRC_AXG_ETHERNET_MEM_ID 1 -#define PWRC_AXG_AUDIO_ID 2 - -#endif diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h deleted file mode 100644 index bb5e67a842de..000000000000 --- a/include/dt-bindings/power/meson-g12a-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_G12A_POWER_H -#define _DT_BINDINGS_MESON_G12A_POWER_H - -#define PWRC_G12A_VPU_ID 0 -#define PWRC_G12A_ETH_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h deleted file mode 100644 index 1262dac696c0..000000000000 --- a/include/dt-bindings/power/meson-gxbb-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H -#define _DT_BINDINGS_MESON_GXBB_POWER_H - -#define PWRC_GXBB_VPU_ID 0 -#define PWRC_GXBB_ETHERNET_MEM_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h deleted file mode 100644 index a020ab00c134..000000000000 --- a/include/dt-bindings/power/meson-sm1-power.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_SM1_POWER_H -#define _DT_BINDINGS_MESON_SM1_POWER_H - -#define PWRC_SM1_VPU_ID 0 -#define PWRC_SM1_NNA_ID 1 -#define PWRC_SM1_USB_ID 2 -#define PWRC_SM1_PCIE_ID 3 -#define PWRC_SM1_GE2D_ID 4 -#define PWRC_SM1_AUDIO_ID 5 -#define PWRC_SM1_ETH_ID 6 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index 2c749c655e1e..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - * - * Copyright (c) 2023, SberDevices, Inc. - * Author: Alexey Romanov avromanov@salutedevices.com - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb8..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca4..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan yixun.lan@amlogic.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7af..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 6d487c5eba2c..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75-77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index 883bfd3bcbad..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -#define RESET_ACODEC 61 -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h deleted file mode 100644 index d342c0b6b2a7..000000000000 --- a/include/dt-bindings/reset/axg-aoclkc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h deleted file mode 100644 index bd2e2337135c..000000000000 --- a/include/dt-bindings/reset/g12a-aoclkc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK - -#define RESET_AO_IR_IN 0 -#define RESET_AO_UART 1 -#define RESET_AO_I2C_M 2 -#define RESET_AO_I2C_S 3 -#define RESET_AO_SAR_ADC 4 -#define RESET_AO_UART2 5 -#define RESET_AO_IR_OUT 6 - -#endif diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h deleted file mode 100644 index 9e3fd60c309c..000000000000 --- a/include/dt-bindings/reset/gxbb-aoclkc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see http://www.gnu.org/licenses/. - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h deleted file mode 100644 index 1051b8af298b..000000000000 --- a/include/dt-bindings/sound/meson-aiu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_AIU_H -#define __DT_MESON_AIU_H - -#define AIU_CPU 0 -#define AIU_HDMI 1 -#define AIU_ACODEC 2 - -#define CPU_I2S_FIFO 0 -#define CPU_SPDIF_FIFO 1 -#define CPU_I2S_ENCODER 2 -#define CPU_SPDIF_ENCODER 3 - -#define CTRL_I2S 0 -#define CTRL_PCM 1 -#define CTRL_OUT 2 - -#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h deleted file mode 100644 index 69d7a75592a2..000000000000 --- a/include/dt-bindings/sound/meson-g12a-toacodec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOACODEC_H -#define __DT_MESON_G12A_TOACODEC_H - -#define TOACODEC_IN_A 0 -#define TOACODEC_IN_B 1 -#define TOACODEC_IN_C 2 -#define TOACODEC_OUT 3 - -#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h deleted file mode 100644 index c5e1f48d30d0..000000000000 --- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOHDMITX_H -#define __DT_MESON_G12A_TOHDMITX_H - -#define TOHDMITX_I2S_IN_A 0 -#define TOHDMITX_I2S_IN_B 1 -#define TOHDMITX_I2S_IN_C 2 -#define TOHDMITX_I2S_OUT 3 -#define TOHDMITX_SPDIF_IN_A 4 -#define TOHDMITX_SPDIF_IN_B 5 -#define TOHDMITX_SPDIF_OUT 6 - -#endif /* __DT_MESON_G12A_TOHDMITX_H */

Drop in favour of dts/upstream.

Small driver/dts adjustments to fix compatibility.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/px30-cru.h | 389 ---------- include/dt-bindings/clock/rk3036-cru.h | 185 ----- include/dt-bindings/clock/rk3066a-cru.h | 31 - include/dt-bindings/clock/rk3128-cru.h | 273 ------- include/dt-bindings/clock/rk3188-cru-common.h | 261 ------- include/dt-bindings/clock/rk3188-cru.h | 47 -- include/dt-bindings/clock/rk3228-cru.h | 287 -------- include/dt-bindings/clock/rk3288-cru.h | 381 ---------- include/dt-bindings/clock/rk3308-cru.h | 387 ---------- include/dt-bindings/clock/rk3328-cru.h | 393 ---------- include/dt-bindings/clock/rk3368-cru.h | 381 ---------- include/dt-bindings/clock/rk3399-cru.h | 749 ------------------- include/dt-bindings/clock/rk3568-cru.h | 926 ------------------------ include/dt-bindings/clock/rockchip,rk3588-cru.h | 766 -------------------- include/dt-bindings/clock/rockchip,rk808.h | 11 - include/dt-bindings/clock/rockchip,rv1126-cru.h | 632 ---------------- 18 files changed, 2 insertions(+), 6101 deletions(-)

diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 87b173e59579..320fa824cc80 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,9 +39,9 @@ bootph-all; compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_DDRCLK>; + clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; reg = <0x0 0xffa80000 0x0 0x0800 0x0 0xffa80800 0x0 0x1800 0x0 0xffa82000 0x0 0x2000 diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 80f65a237e8e..f0ce54067f8c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1048,9 +1048,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * assigned-clocks handling won't require for vopl, so * return 0 to satisfy clk_set_defaults during device probe. */ return 0; - case SCLK_DDRCLK: + case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS: break; diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h deleted file mode 100644 index e5e59690b5f5..000000000000 --- a/include/dt-bindings/clock/px30-cru.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine zhangqing@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H -#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_NPLL 4 -#define APLL_BOOST_H 5 -#define APLL_BOOST_L 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define USB480M 14 -#define SCLK_PDM 15 -#define SCLK_I2S0_TX 16 -#define SCLK_I2S0_TX_OUT 17 -#define SCLK_I2S0_RX 18 -#define SCLK_I2S0_RX_OUT 19 -#define SCLK_I2S1 20 -#define SCLK_I2S1_OUT 21 -#define SCLK_I2S2 22 -#define SCLK_I2S2_OUT 23 -#define SCLK_UART1 24 -#define SCLK_UART2 25 -#define SCLK_UART3 26 -#define SCLK_UART4 27 -#define SCLK_UART5 28 -#define SCLK_I2C0 29 -#define SCLK_I2C1 30 -#define SCLK_I2C2 31 -#define SCLK_I2C3 32 -#define SCLK_I2C4 33 -#define SCLK_PWM0 34 -#define SCLK_PWM1 35 -#define SCLK_SPI0 36 -#define SCLK_SPI1 37 -#define SCLK_TIMER0 38 -#define SCLK_TIMER1 39 -#define SCLK_TIMER2 40 -#define SCLK_TIMER3 41 -#define SCLK_TIMER4 42 -#define SCLK_TIMER5 43 -#define SCLK_TSADC 44 -#define SCLK_SARADC 45 -#define SCLK_OTP 46 -#define SCLK_OTP_USR 47 -#define SCLK_CRYPTO 48 -#define SCLK_CRYPTO_APK 49 -#define SCLK_DDRC 50 -#define SCLK_ISP 51 -#define SCLK_CIF_OUT 52 -#define SCLK_RGA_CORE 53 -#define SCLK_VOPB_PWM 54 -#define SCLK_NANDC 55 -#define SCLK_SDIO 56 -#define SCLK_EMMC 57 -#define SCLK_SFC 58 -#define SCLK_SDMMC 59 -#define SCLK_OTG_ADP 60 -#define SCLK_GMAC_SRC 61 -#define SCLK_GMAC 62 -#define SCLK_GMAC_RX_TX 63 -#define SCLK_MAC_REF 64 -#define SCLK_MAC_REFOUT 65 -#define SCLK_MAC_OUT 66 -#define SCLK_SDMMC_DRV 67 -#define SCLK_SDMMC_SAMPLE 68 -#define SCLK_SDIO_DRV 69 -#define SCLK_SDIO_SAMPLE 70 -#define SCLK_EMMC_DRV 71 -#define SCLK_EMMC_SAMPLE 72 -#define SCLK_GPU 73 -#define SCLK_PVTM 74 -#define SCLK_CORE_VPU 75 -#define SCLK_GMAC_RMII 76 -#define SCLK_UART2_SRC 77 -#define SCLK_NANDC_DIV 78 -#define SCLK_NANDC_DIV50 79 -#define SCLK_SDIO_DIV 80 -#define SCLK_SDIO_DIV50 81 -#define SCLK_EMMC_DIV 82 -#define SCLK_EMMC_DIV50 83 - -/* dclk gates */ -#define DCLK_VOPB 150 -#define DCLK_VOPL 151 - -/* aclk gates */ -#define ACLK_GPU 170 -#define ACLK_BUS_PRE 171 -#define ACLK_CRYPTO 172 -#define ACLK_VI_PRE 173 -#define ACLK_VO_PRE 174 -#define ACLK_VPU 175 -#define ACLK_PERI_PRE 176 -#define ACLK_GMAC 178 -#define ACLK_CIF 179 -#define ACLK_ISP 180 -#define ACLK_VOPB 181 -#define ACLK_VOPL 182 -#define ACLK_RGA 183 -#define ACLK_GIC 184 -#define ACLK_DCF 186 -#define ACLK_DMAC 187 - -/* hclk gates */ -#define HCLK_BUS_PRE 240 -#define HCLK_CRYPTO 241 -#define HCLK_VI_PRE 242 -#define HCLK_VO_PRE 243 -#define HCLK_VPU 244 -#define HCLK_PERI_PRE 245 -#define HCLK_MMC_NAND 246 -#define HCLK_SDMMC 247 -#define HCLK_USB 248 -#define HCLK_CIF 249 -#define HCLK_ISP 250 -#define HCLK_VOPB 251 -#define HCLK_VOPL 252 -#define HCLK_RGA 253 -#define HCLK_NANDC 254 -#define HCLK_SDIO 255 -#define HCLK_EMMC 256 -#define HCLK_SFC 257 -#define HCLK_OTG 258 -#define HCLK_HOST 259 -#define HCLK_HOST_ARB 260 -#define HCLK_PDM 261 -#define HCLK_I2S0 262 -#define HCLK_I2S1 263 -#define HCLK_I2S2 264 - -/* pclk gates */ -#define PCLK_BUS_PRE 320 -#define PCLK_DDR 321 -#define PCLK_VO_PRE 322 -#define PCLK_GMAC 323 -#define PCLK_MIPI_DSI 324 -#define PCLK_MIPIDSIPHY 325 -#define PCLK_MIPICSIPHY 326 -#define PCLK_USB_GRF 327 -#define PCLK_DCF 328 -#define PCLK_UART1 329 -#define PCLK_UART2 330 -#define PCLK_UART3 331 -#define PCLK_UART4 332 -#define PCLK_UART5 333 -#define PCLK_I2C0 334 -#define PCLK_I2C1 335 -#define PCLK_I2C2 336 -#define PCLK_I2C3 337 -#define PCLK_I2C4 338 -#define PCLK_PWM0 339 -#define PCLK_PWM1 340 -#define PCLK_SPI0 341 -#define PCLK_SPI1 342 -#define PCLK_SARADC 343 -#define PCLK_TSADC 344 -#define PCLK_TIMER 345 -#define PCLK_OTP_NS 346 -#define PCLK_WDT_NS 347 -#define PCLK_GPIO1 348 -#define PCLK_GPIO2 349 -#define PCLK_GPIO3 350 -#define PCLK_ISP 351 -#define PCLK_CIF 352 -#define PCLK_OTP_PHY 353 - -#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) - -/* pmu-clocks indices */ - -#define PLL_GPLL 1 - -#define SCLK_RTC32K_PMU 4 -#define SCLK_WIFI_PMU 5 -#define SCLK_UART0_PMU 6 -#define SCLK_PVTM_PMU 7 -#define PCLK_PMU_PRE 8 -#define SCLK_REF24M_PMU 9 -#define SCLK_USBPHY_REF 10 -#define SCLK_MIPIDSIPHY_REF 11 - -#define XIN24M_DIV 12 - -#define PCLK_GPIO0_PMU 20 -#define PCLK_UART0_PMU 21 - -#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_GPU 18 -#define SRST_GPU_NIU 19 -#define SRST_UPCTL2 20 -#define SRST_UPCTL2_A 21 -#define SRST_UPCTL2_P 22 -#define SRST_MSCH 23 -#define SRST_MSCH_P 24 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRGRF_p 28 -#define SRST_AXI_SPLIT_A 29 -#define SRST_AXI_CMD_A 30 -#define SRST_AXI_CMD_P 31 - -#define SRST_DDRPHY 32 -#define SRST_DDRPHYDIV 33 -#define SRST_DDRPHY_P 34 -#define SRST_VPU_A 36 -#define SRST_VPU_NIU_A 37 -#define SRST_VPU_H 38 -#define SRST_VPU_NIU_H 39 -#define SRST_VI_NIU_A 40 -#define SRST_VI_NIU_H 41 -#define SRST_ISP_H 42 -#define SRST_ISP 43 -#define SRST_CIF_A 44 -#define SRST_CIF_H 45 -#define SRST_CIF_PCLKIN 46 -#define SRST_MIPICSIPHY_P 47 - -#define SRST_VO_NIU_A 48 -#define SRST_VO_NIU_H 49 -#define SRST_VO_NIU_P 50 -#define SRST_VOPB_A 51 -#define SRST_VOPB_H 52 -#define SRST_VOPB 53 -#define SRST_PWM_VOPB 54 -#define SRST_VOPL_A 55 -#define SRST_VOPL_H 56 -#define SRST_VOPL 57 -#define SRST_RGA_A 58 -#define SRST_RGA_H 59 -#define SRST_RGA 60 -#define SRST_MIPIDSI_HOST_P 61 -#define SRST_MIPIDSIPHY_P 62 -#define SRST_VPU_CORE 63 - -#define SRST_PERI_NIU_A 64 -#define SRST_USB_NIU_H 65 -#define SRST_USB2OTG_H 66 -#define SRST_USB2OTG 67 -#define SRST_USB2OTG_ADP 68 -#define SRST_USB2HOST_H 69 -#define SRST_USB2HOST_ARB_H 70 -#define SRST_USB2HOST_AUX_H 71 -#define SRST_USB2HOST_EHCI 72 -#define SRST_USB2HOST 73 -#define SRST_USBPHYPOR 74 -#define SRST_USBPHY_OTG_PORT 75 -#define SRST_USBPHY_HOST_PORT 76 -#define SRST_USBPHY_GRF 77 -#define SRST_CPU_BOOST_P 78 -#define SRST_CPU_BOOST 79 - -#define SRST_MMC_NAND_NIU_H 80 -#define SRST_SDIO_H 81 -#define SRST_EMMC_H 82 -#define SRST_SFC_H 83 -#define SRST_SFC 84 -#define SRST_SDCARD_NIU_H 85 -#define SRST_SDMMC_H 86 -#define SRST_NANDC_H 89 -#define SRST_NANDC 90 -#define SRST_GMAC_NIU_A 92 -#define SRST_GMAC_NIU_P 93 -#define SRST_GMAC_A 94 - -#define SRST_PMU_NIU_P 96 -#define SRST_PMU_SGRF_P 97 -#define SRST_PMU_GRF_P 98 -#define SRST_PMU 99 -#define SRST_PMU_MEM_P 100 -#define SRST_PMU_GPIO0_P 101 -#define SRST_PMU_UART0_P 102 -#define SRST_PMU_CRU_P 103 -#define SRST_PMU_PVTM 104 -#define SRST_PMU_UART 105 -#define SRST_PMU_NIU_H 106 -#define SRST_PMU_DDR_FAIL_SAVE 107 -#define SRST_PMU_CORE_PERF_A 108 -#define SRST_PMU_CORE_GRF_P 109 -#define SRST_PMU_GPU_PERF_A 110 -#define SRST_PMU_GPU_GRF_P 111 - -#define SRST_CRYPTO_NIU_A 112 -#define SRST_CRYPTO_NIU_H 113 -#define SRST_CRYPTO_A 114 -#define SRST_CRYPTO_H 115 -#define SRST_CRYPTO 116 -#define SRST_CRYPTO_APK 117 -#define SRST_BUS_NIU_H 120 -#define SRST_USB_NIU_P 121 -#define SRST_BUS_TOP_NIU_P 122 -#define SRST_INTMEM_A 123 -#define SRST_GIC_A 124 -#define SRST_ROM_H 126 -#define SRST_DCF_A 127 - -#define SRST_DCF_P 128 -#define SRST_PDM_H 129 -#define SRST_PDM 130 -#define SRST_I2S0_H 131 -#define SRST_I2S0_TX 132 -#define SRST_I2S1_H 133 -#define SRST_I2S1 134 -#define SRST_I2S2_H 135 -#define SRST_I2S2 136 -#define SRST_UART1_P 137 -#define SRST_UART1 138 -#define SRST_UART2_P 139 -#define SRST_UART2 140 -#define SRST_UART3_P 141 -#define SRST_UART3 142 -#define SRST_UART4_P 143 - -#define SRST_UART4 144 -#define SRST_UART5_P 145 -#define SRST_UART5 146 -#define SRST_I2C0_P 147 -#define SRST_I2C0 148 -#define SRST_I2C1_P 149 -#define SRST_I2C1 150 -#define SRST_I2C2_P 151 -#define SRST_I2C2 152 -#define SRST_I2C3_P 153 -#define SRST_I2C3 154 -#define SRST_PWM0_P 157 -#define SRST_PWM0 158 -#define SRST_PWM1_P 159 - -#define SRST_PWM1 160 -#define SRST_SPI0_P 161 -#define SRST_SPI0 162 -#define SRST_SPI1_P 163 -#define SRST_SPI1 164 -#define SRST_SARADC_P 165 -#define SRST_SARADC 166 -#define SRST_TSADC_P 167 -#define SRST_TSADC 168 -#define SRST_TIMER_P 169 -#define SRST_TIMER0 170 -#define SRST_TIMER1 171 -#define SRST_TIMER2 172 -#define SRST_TIMER3 173 -#define SRST_TIMER4 174 -#define SRST_TIMER5 175 - -#define SRST_OTP_NS_P 176 -#define SRST_OTP_NS_SBPI 177 -#define SRST_OTP_NS_USR 178 -#define SRST_OTP_PHY_P 179 -#define SRST_OTP_PHY 180 -#define SRST_WDT_NS_P 181 -#define SRST_GPIO1_P 182 -#define SRST_GPIO2_P 183 -#define SRST_GPIO3_P 184 -#define SRST_SGRF_P 185 -#define SRST_GRF_P 186 -#define SRST_I2S0_RX 191 - -#endif diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 2c0552d1a936..000000000000 --- a/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 - -#define DCLK_LCDC 190 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h deleted file mode 100644 index 014eec586689..000000000000 --- a/include/dt-bindings/clock/rk3066a-cru.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H - -#include <dt-bindings/clock/rk3188-cru-common.h> - -/* soft-reset indices */ -#define SRST_SRST1 0 -#define SRST_SRST2 1 - -#define SRST_L2MEM 18 -#define SRST_I2S0 23 -#define SRST_I2S1 24 -#define SRST_I2S2 25 -#define SRST_TIMER2 29 - -#define SRST_GPIO4 36 -#define SRST_GPIO6 38 - -#define SRST_TSADC 92 - -#define SRST_HDMI 96 -#define SRST_HDMI_APB 97 -#define SRST_CIF1 111 - -#endif diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h deleted file mode 100644 index 6a47825dac5d..000000000000 --- a/include/dt-bindings/clock/rk3128-cru.h +++ /dev/null @@ -1,273 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine zhangqing@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 -#define PLL_GPLL_DIV2 6 -#define PLL_GPLL_DIV3 7 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_SARADC 91 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_HEVC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_DDRC 144 -#define SCLK_PVTM_FUNC 145 -#define SCLK_PVTM_CORE 146 -#define SCLK_PVTM_GPU 147 -#define SCLK_MIPI_24M 148 -#define SCLK_PVTM 149 -#define SCLK_CIF_SRC 150 -#define SCLK_CIF_OUT_SRC 151 -#define SCLK_CIF_OUT 152 -#define SCLK_SFC 153 -#define SCLK_USB480M 154 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_EBC 191 - -/* aclk gates */ -#define ACLK_VIO0 192 -#define ACLK_VIO1 193 -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VEPU 196 -#define ACLK_VDPU 197 -#define ACLK_CIF 198 -#define ACLK_IEP 199 -#define ACLK_LCDC0 204 -#define ACLK_RGA 205 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_SARADC 318 -#define PCLK_WDT 319 -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_MIPI 325 -#define PCLK_EFUSE 326 -#define PCLK_HDMI 327 -#define PCLK_ACODEC 328 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_GMAC 367 -#define PCLK_PMU_PRE 368 -#define PCLK_SIM_CARD 369 - -/* hclk gates */ -#define HCLK_SPDIF 440 -#define HCLK_GPS 441 -#define HCLK_USBHOST 442 -#define HCLK_I2S_8CH 443 -#define HCLK_I2S_2CH 444 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VEPU 461 -#define HCLK_VDPU 462 -#define HCLK_LCDC0 463 -#define HCLK_EBC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_CIF 470 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_CRYPTO 476 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_STRC_SYS_A 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_AHB2APBSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S_2CH 24 -#define SRST_I2S_8CH 25 -#define SRST_GPU_PVTM 26 -#define SRST_FUNC_PVTM 27 -#define SRST_CORE_PVTM 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_MIPIPHY_P 36 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_SFC 47 - -#define SRST_PWM 48 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_CRYPTO 53 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_SYS_A 57 -#define SRST_PERIPH_SYS_H 58 -#define SRST_PERIPH_SYS_P 59 -#define SRST_SMART_CARD 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA 64 -#define SRST_GPS 67 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_TSP 92 -#define SRST_TSP_CLKIN 93 -#define SRST_HOST0_ECHI 94 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_VIO0_A 98 -#define SRST_VIO_BUS_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 -#define SRST_IEP_A 106 -#define SRST_IEP_H 107 -#define SRST_RGA_A 108 -#define SRST_RGA_H 109 -#define SRST_CIF0 110 -#define SRST_PMU 111 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC_CORE 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_PMU_NIU_P 117 -#define SRST_LCDC0_S 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 -#define SRST_EBC_A 123 -#define SRST_EBC_H 124 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_VIO_MIPI_DSI 137 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h deleted file mode 100644 index afad90680fce..000000000000 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H - -/* core clocks from */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define CORE_PERI 5 -#define CORE_L2C 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define SCLK_UART0 64 -#define SCLK_UART1 65 -#define SCLK_UART2 66 -#define SCLK_UART3 67 -#define SCLK_MAC 68 -#define SCLK_SPI0 69 -#define SCLK_SPI1 70 -#define SCLK_SARADC 71 -#define SCLK_SDMMC 72 -#define SCLK_SDIO 73 -#define SCLK_EMMC 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_SPDIF 78 -#define SCLK_CIF0 79 -#define SCLK_CIF1 80 -#define SCLK_OTGPHY0 81 -#define SCLK_OTGPHY1 82 -#define SCLK_HSADC 83 -#define SCLK_TIMER0 84 -#define SCLK_TIMER1 85 -#define SCLK_TIMER2 86 -#define SCLK_TIMER3 87 -#define SCLK_TIMER4 88 -#define SCLK_TIMER5 89 -#define SCLK_TIMER6 90 -#define SCLK_JTAG 91 -#define SCLK_SMC 92 -#define SCLK_TSADC 93 - -#define DCLK_LCDC0 190 -#define DCLK_LCDC1 191 - -/* aclk gates */ -#define ACLK_DMA1 192 -#define ACLK_DMA2 193 -#define ACLK_GPS 194 -#define ACLK_LCDC0 195 -#define ACLK_LCDC1 196 -#define ACLK_GPU 197 -#define ACLK_SMC 198 -#define ACLK_CIF1 199 -#define ACLK_IPP 200 -#define ACLK_RGA 201 -#define ACLK_CIF0 202 -#define ACLK_CPU 203 -#define ACLK_PERI 204 -#define ACLK_VEPU 205 -#define ACLK_VDPU 206 - -/* pclk gates */ -#define PCLK_GRF 320 -#define PCLK_PMU 321 -#define PCLK_TIMER0 322 -#define PCLK_TIMER1 323 -#define PCLK_TIMER2 324 -#define PCLK_TIMER3 325 -#define PCLK_PWM01 326 -#define PCLK_PWM23 327 -#define PCLK_SPI0 328 -#define PCLK_SPI1 329 -#define PCLK_SARADC 330 -#define PCLK_WDT 331 -#define PCLK_UART0 332 -#define PCLK_UART1 333 -#define PCLK_UART2 334 -#define PCLK_UART3 335 -#define PCLK_I2C0 336 -#define PCLK_I2C1 337 -#define PCLK_I2C2 338 -#define PCLK_I2C3 339 -#define PCLK_I2C4 340 -#define PCLK_GPIO0 341 -#define PCLK_GPIO1 342 -#define PCLK_GPIO2 343 -#define PCLK_GPIO3 344 -#define PCLK_GPIO4 345 -#define PCLK_GPIO6 346 -#define PCLK_EFUSE 347 -#define PCLK_TZPC 348 -#define PCLK_TSADC 349 -#define PCLK_CPU 350 -#define PCLK_PERI 351 -#define PCLK_DDRUPCTL 352 -#define PCLK_PUBL 353 - -/* hclk gates */ -#define HCLK_SDMMC 448 -#define HCLK_SDIO 449 -#define HCLK_EMMC 450 -#define HCLK_OTG0 451 -#define HCLK_EMAC 452 -#define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 -#define HCLK_OTG1 457 -#define HCLK_HSIC 458 -#define HCLK_HSADC 459 -#define HCLK_PIDF 460 -#define HCLK_LCDC0 461 -#define HCLK_LCDC1 462 -#define HCLK_ROM 463 -#define HCLK_CIF0 464 -#define HCLK_IPP 465 -#define HCLK_RGA 466 -#define HCLK_NANDC0 467 -#define HCLK_CPU 468 -#define HCLK_PERI 469 -#define HCLK_CIF1 470 -#define HCLK_VEPU 471 -#define HCLK_VDPU 472 -#define HCLK_HDMI 473 - -#define CLK_NR_CLKS (HCLK_HDMI + 1) - -/* soft-reset indices */ -#define SRST_MCORE 2 -#define SRST_CORE0 3 -#define SRST_CORE1 4 -#define SRST_MCORE_DBG 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE0_WDT 12 -#define SRST_CORE1_WDT 13 -#define SRST_STRC_SYS 14 -#define SRST_L2C 15 - -#define SRST_CPU_AHB 17 -#define SRST_AHB2APB 19 -#define SRST_DMA1 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_SPDIF 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_EFUSE 30 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 - -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_UART3 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_I2C4 47 - -#define SRST_PWM0 48 -#define SRST_PWM1 49 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU_ATB 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERI_AXI 57 -#define SRST_PERI_AHB 58 -#define SRST_PERI_APB 59 -#define SRST_PERI_NIU 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_SMC 65 -#define SRST_MAC 66 -#define SRST_NANC0 68 -#define SRST_USBOTG0 69 -#define SRST_USBPHY0 70 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_USBPHY1 73 -#define SRST_OTGC1 74 -#define SRST_HSADC 76 -#define SRST_PIDFILTER 77 -#define SRST_DDR_MSCH 79 - -#define SRST_TZPC 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_SPI1 85 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_APB 89 -#define SRST_DDRCTL 90 -#define SRST_DDRCTL_APB 91 -#define SRST_DDRPUB 93 - -#define SRST_VIO0_AXI 98 -#define SRST_VIO0_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_LCDC1_AXI 103 -#define SRST_LCDC1_AHB 104 -#define SRST_LCDC1_DCLK 105 -#define SRST_IPP_AXI 106 -#define SRST_IPP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_CIF0 110 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO1_AXI 114 -#define SRST_VCODEC_CPU 115 -#define SRST_VCODEC_NIU 116 -#define SRST_GPU 120 -#define SRST_GPU_NIU 122 -#define SRST_TFUN_ATB 125 -#define SRST_TFUN_APB 126 -#define SRST_CTI4_APB 127 - -#define SRST_TPIU_APB 128 -#define SRST_TRACE 129 -#define SRST_CORE_DBG 130 -#define SRST_DBG_APB 131 -#define SRST_CTI0 132 -#define SRST_CTI0_APB 133 -#define SRST_CTI1 134 -#define SRST_CTI1_APB 135 -#define SRST_PTM_CORE0 136 -#define SRST_PTM_CORE1 137 -#define SRST_PTM0 138 -#define SRST_PTM0_ATB 139 -#define SRST_PTM1 140 -#define SRST_PTM1_ATB 141 -#define SRST_CTM 142 -#define SRST_TS 143 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h deleted file mode 100644 index 1da306e1788c..000000000000 --- a/include/dt-bindings/clock/rk3188-cru.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H - -#include <dt-bindings/clock/rk3188-cru-common.h> - -/* soft-reset indices */ -#define SRST_PTM_CORE2 0 -#define SRST_PTM_CORE3 1 -#define SRST_CORE2 5 -#define SRST_CORE3 6 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 - -#define SRST_TIMER2 16 -#define SRST_TIMER4 23 -#define SRST_I2S0 24 -#define SRST_TIMER5 25 -#define SRST_TIMER3 29 -#define SRST_TIMER6 31 - -#define SRST_PTM3 36 -#define SRST_PTM3_ATB 37 - -#define SRST_GPS 67 -#define SRST_HSICPHY 75 -#define SRST_TIMER 78 - -#define SRST_PTM2 92 -#define SRST_CORE2_WDT 94 -#define SRST_CORE3_WDT 95 - -#define SRST_PTM2_ATB 111 - -#define SRST_HSIC 117 -#define SRST_CTI2 118 -#define SRST_CTI2_APB 119 -#define SRST_GPU_BRIDGE 121 -#define SRST_CTI3 123 -#define SRST_CTI3_APB 124 - -#endif diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h deleted file mode 100644 index de550ea56eeb..000000000000 --- a/include/dt-bindings/clock/rk3228-cru.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Rockchip Electronics Co. Ltd. - * Author: Jeffy Chen jeffy.chen@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_I2S2 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_SDIO_SRC 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_HDMI_HDCP 123 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC_EXTCLK 125 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_MAC_PHY 131 -#define SCLK_MAC_OUT 132 -#define SCLK_VDEC_CABAC 133 -#define SCLK_VDEC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_HDCP 136 -#define SCLK_HDMI_CEC 137 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_HSADC 140 -#define SCLK_WIFI 141 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_HDMI_PHY 144 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_HDMI_PHY 191 - -/* aclk gates */ -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VPU_PRE 196 -#define ACLK_RKVDEC_PRE 197 -#define ACLK_RGA_PRE 198 -#define ACLK_IEP_PRE 199 -#define ACLK_HDCP_PRE 200 -#define ACLK_VOP_PRE 201 -#define ACLK_VPU 202 -#define ACLK_RKVDEC 203 -#define ACLK_IEP 204 -#define ACLK_RGA 205 -#define ACLK_HDCP 206 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_HDCP 325 -#define PCLK_EFUSE_1024 326 -#define PCLK_EFUSE_256 327 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_HDMI_CTRL 364 -#define PCLK_HDMI_PHY 365 -#define PCLK_GMAC 367 - -/* hclk gates */ -#define HCLK_I2S0_8CH 442 -#define HCLK_I2S1_8CH 443 -#define HCLK_I2S2_2CH 444 -#define HCLK_SPDIF_8CH 445 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VPU_PRE 461 -#define HCLK_RKVDEC_PRE 462 -#define HCLK_VIO_PRE 463 -#define HCLK_VPU 464 -#define HCLK_RKVDEC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_HDCP_MMU 470 -#define HCLK_HOST0 471 -#define HCLK_HOST1 472 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_M_CRYPTO 476 -#define HCLK_S_CRYPTO 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_NOC 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_BUSSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_OTG_ADP 23 -#define SRST_I2S0 24 -#define SRST_I2S1 25 -#define SRST_I2S2 26 -#define SRST_ACODEC_P 27 -#define SRST_DFIMON 28 -#define SRST_MSCH 29 -#define SRST_EFUSE1024 30 -#define SRST_EFUSE256 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_PERIPH_NOC_A 36 -#define SRST_PERIPH_NOC_BUS_H 37 -#define SRST_PERIPH_NOC_P 38 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_PHYNOC 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 - -#define SRST_PWM 48 -#define SRST_A53_GIC 49 -#define SRST_DAP 51 -#define SRST_DAP_NOC 52 -#define SRST_CRYPTO 53 -#define SRST_SGRF 54 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_NOC_H 58 -#define SRST_MACPHY 63 - -#define SRST_DMA 64 -#define SRST_NANDC 68 -#define SRST_USBOTG 69 -#define SRST_OTGC 70 -#define SRST_USBHOST0 71 -#define SRST_HOST_CTRL0 72 -#define SRST_USBHOST1 73 -#define SRST_HOST_CTRL1 74 -#define SRST_USBHOST2 75 -#define SRST_HOST_CTRL2 76 -#define SRST_USBPOR0 77 -#define SRST_USBPOR1 78 -#define SRST_DDRMSCH 79 - -#define SRST_SMART_CARD 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_TSP_H 85 -#define SRST_TSP 86 -#define SRST_TSADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_HOST0_ECHI 92 -#define SRST_HOST1_ECHI 93 -#define SRST_HOST2_ECHI 94 -#define SRST_VOP_NOC_A 95 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_IEP_NOC_A 98 -#define SRST_VIO_NOC_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_UTMI2 105 -#define SRST_UTMI3 106 -#define SRST_RGA 107 -#define SRST_RGA_NOC_A 108 -#define SRST_RGA_A 109 -#define SRST_RGA_H 110 -#define SRST_HDCP_A 111 - -#define SRST_VPU_A 112 -#define SRST_VPU_H 113 -#define SRST_VPU_NOC_A 116 -#define SRST_VPU_NOC_H 117 -#define SRST_RKVDEC_A 118 -#define SRST_RKVDEC_NOC_A 119 -#define SRST_RKVDEC_H 120 -#define SRST_RKVDEC_NOC_H 121 -#define SRST_RKVDEC_CORE 122 -#define SRST_RKVDEC_CABAC 123 -#define SRST_IEP_A 124 -#define SRST_IEP_H 125 -#define SRST_GPU_A 126 -#define SRST_GPU_NOC_A 127 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_HDMIPHY 139 -#define SRST_VDAC 140 -#define SRST_TIMER_6CH_P 141 - -#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6b..000000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h deleted file mode 100644 index d97840f9ee2e..000000000000 --- a/include/dt-bindings/clock/rk3308-cru.h +++ /dev/null @@ -1,387 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Rockchip Electronics Co. Ltd. - * Author: Finley Xiao finley.xiao@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_VPLL0 3 -#define PLL_VPLL1 4 -#define ARMCLK 5 - -/* sclk (special clocks) */ -#define USB480M 14 -#define SCLK_RTC32K 15 -#define SCLK_PVTM_CORE 16 -#define SCLK_UART0 17 -#define SCLK_UART1 18 -#define SCLK_UART2 19 -#define SCLK_UART3 20 -#define SCLK_UART4 21 -#define SCLK_I2C0 22 -#define SCLK_I2C1 23 -#define SCLK_I2C2 24 -#define SCLK_I2C3 25 -#define SCLK_PWM0 26 -#define SCLK_SPI0 27 -#define SCLK_SPI1 28 -#define SCLK_SPI2 29 -#define SCLK_TIMER0 30 -#define SCLK_TIMER1 31 -#define SCLK_TIMER2 32 -#define SCLK_TIMER3 33 -#define SCLK_TIMER4 34 -#define SCLK_TIMER5 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_OTP 38 -#define SCLK_OTP_USR 39 -#define SCLK_CPU_BOOST 40 -#define SCLK_CRYPTO 41 -#define SCLK_CRYPTO_APK 42 -#define SCLK_NANDC_DIV 43 -#define SCLK_NANDC_DIV50 44 -#define SCLK_NANDC 45 -#define SCLK_SDMMC_DIV 46 -#define SCLK_SDMMC_DIV50 47 -#define SCLK_SDMMC 48 -#define SCLK_SDMMC_DRV 49 -#define SCLK_SDMMC_SAMPLE 50 -#define SCLK_SDIO_DIV 51 -#define SCLK_SDIO_DIV50 52 -#define SCLK_SDIO 53 -#define SCLK_SDIO_DRV 54 -#define SCLK_SDIO_SAMPLE 55 -#define SCLK_EMMC_DIV 56 -#define SCLK_EMMC_DIV50 57 -#define SCLK_EMMC 58 -#define SCLK_EMMC_DRV 59 -#define SCLK_EMMC_SAMPLE 60 -#define SCLK_SFC 61 -#define SCLK_OTG_ADP 62 -#define SCLK_MAC_SRC 63 -#define SCLK_MAC 64 -#define SCLK_MAC_REF 65 -#define SCLK_MAC_RX_TX 66 -#define SCLK_MAC_RMII 67 -#define SCLK_DDR_MON_TIMER 68 -#define SCLK_DDR_MON 69 -#define SCLK_DDRCLK 70 -#define SCLK_PMU 71 -#define SCLK_USBPHY_REF 72 -#define SCLK_WIFI 73 -#define SCLK_PVTM_PMU 74 -#define SCLK_PDM 75 -#define SCLK_I2S0_8CH_TX 76 -#define SCLK_I2S0_8CH_TX_OUT 77 -#define SCLK_I2S0_8CH_RX 78 -#define SCLK_I2S0_8CH_RX_OUT 79 -#define SCLK_I2S1_8CH_TX 80 -#define SCLK_I2S1_8CH_TX_OUT 81 -#define SCLK_I2S1_8CH_RX 82 -#define SCLK_I2S1_8CH_RX_OUT 83 -#define SCLK_I2S2_8CH_TX 84 -#define SCLK_I2S2_8CH_TX_OUT 85 -#define SCLK_I2S2_8CH_RX 86 -#define SCLK_I2S2_8CH_RX_OUT 87 -#define SCLK_I2S3_8CH_TX 88 -#define SCLK_I2S3_8CH_TX_OUT 89 -#define SCLK_I2S3_8CH_RX 90 -#define SCLK_I2S3_8CH_RX_OUT 91 -#define SCLK_I2S0_2CH 92 -#define SCLK_I2S0_2CH_OUT 93 -#define SCLK_I2S1_2CH 94 -#define SCLK_I2S1_2CH_OUT 95 -#define SCLK_SPDIF_TX_DIV 96 -#define SCLK_SPDIF_TX_DIV50 97 -#define SCLK_SPDIF_TX 98 -#define SCLK_SPDIF_RX_DIV 99 -#define SCLK_SPDIF_RX_DIV50 100 -#define SCLK_SPDIF_RX 101 -#define SCLK_I2S0_8CH_TX_MUX 102 -#define SCLK_I2S0_8CH_RX_MUX 103 -#define SCLK_I2S1_8CH_TX_MUX 104 -#define SCLK_I2S1_8CH_RX_MUX 105 -#define SCLK_I2S2_8CH_TX_MUX 106 -#define SCLK_I2S2_8CH_RX_MUX 107 -#define SCLK_I2S3_8CH_TX_MUX 108 -#define SCLK_I2S3_8CH_RX_MUX 109 -#define SCLK_I2S0_8CH_TX_SRC 110 -#define SCLK_I2S0_8CH_RX_SRC 111 -#define SCLK_I2S1_8CH_TX_SRC 112 -#define SCLK_I2S1_8CH_RX_SRC 113 -#define SCLK_I2S2_8CH_TX_SRC 114 -#define SCLK_I2S2_8CH_RX_SRC 115 -#define SCLK_I2S3_8CH_TX_SRC 116 -#define SCLK_I2S3_8CH_RX_SRC 117 -#define SCLK_I2S0_2CH_SRC 118 -#define SCLK_I2S1_2CH_SRC 119 -#define SCLK_PWM1 120 -#define SCLK_PWM2 121 -#define SCLK_OWIRE 122 - -/* dclk */ -#define DCLK_VOP 125 - -/* aclk */ -#define ACLK_BUS_SRC 130 -#define ACLK_BUS 131 -#define ACLK_PERI_SRC 132 -#define ACLK_PERI 133 -#define ACLK_MAC 134 -#define ACLK_CRYPTO 135 -#define ACLK_VOP 136 -#define ACLK_GIC 137 -#define ACLK_DMAC0 138 -#define ACLK_DMAC1 139 - -/* hclk */ -#define HCLK_BUS 150 -#define HCLK_PERI 151 -#define HCLK_AUDIO 152 -#define HCLK_NANDC 153 -#define HCLK_SDMMC 154 -#define HCLK_SDIO 155 -#define HCLK_EMMC 156 -#define HCLK_SFC 157 -#define HCLK_OTG 158 -#define HCLK_HOST 159 -#define HCLK_HOST_ARB 160 -#define HCLK_PDM 161 -#define HCLK_SPDIFTX 162 -#define HCLK_SPDIFRX 163 -#define HCLK_I2S0_8CH 164 -#define HCLK_I2S1_8CH 165 -#define HCLK_I2S2_8CH 166 -#define HCLK_I2S3_8CH 167 -#define HCLK_I2S0_2CH 168 -#define HCLK_I2S1_2CH 169 -#define HCLK_VAD 170 -#define HCLK_CRYPTO 171 -#define HCLK_VOP 172 - -/* pclk */ -#define PCLK_BUS 190 -#define PCLK_DDR 191 -#define PCLK_PERI 192 -#define PCLK_PMU 193 -#define PCLK_AUDIO 194 -#define PCLK_MAC 195 -#define PCLK_ACODEC 196 -#define PCLK_UART0 197 -#define PCLK_UART1 198 -#define PCLK_UART2 199 -#define PCLK_UART3 200 -#define PCLK_UART4 201 -#define PCLK_I2C0 202 -#define PCLK_I2C1 203 -#define PCLK_I2C2 204 -#define PCLK_I2C3 205 -#define PCLK_PWM0 206 -#define PCLK_SPI0 207 -#define PCLK_SPI1 208 -#define PCLK_SPI2 209 -#define PCLK_SARADC 210 -#define PCLK_TSADC 211 -#define PCLK_TIMER 212 -#define PCLK_OTP_NS 213 -#define PCLK_WDT 214 -#define PCLK_GPIO0 215 -#define PCLK_GPIO1 216 -#define PCLK_GPIO2 217 -#define PCLK_GPIO3 218 -#define PCLK_GPIO4 219 -#define PCLK_SGRF 220 -#define PCLK_GRF 221 -#define PCLK_USBSD_DET 222 -#define PCLK_DDR_UPCTL 223 -#define PCLK_DDR_MON 224 -#define PCLK_DDRPHY 225 -#define PCLK_DDR_STDBY 226 -#define PCLK_USB_GRF 227 -#define PCLK_CRU 228 -#define PCLK_OTP_PHY 229 -#define PCLK_CPU_BOOST 230 -#define PCLK_PWM1 231 -#define PCLK_PWM2 232 -#define PCLK_CAN 233 -#define PCLK_OWIRE 234 - -#define CLK_NR_CLKS (PCLK_OWIRE + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -/* cru_softrst_con1 */ -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_CORE_PRF 18 -#define SRST_CORE_GRF 19 -#define SRST_DDRUPCTL 20 -#define SRST_DDRUPCTL_P 22 -#define SRST_MSCH 23 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRPHY 28 -#define SRST_DDRPHY_DIV 29 -#define SRST_DDRPHY_P 30 - -/* cru_softrst_con2 */ -#define SRST_BUS_NIU_H 32 -#define SRST_USB_NIU_P 33 -#define SRST_CRYPTO_A 34 -#define SRST_CRYPTO_H 35 -#define SRST_CRYPTO 36 -#define SRST_CRYPTO_APK 37 -#define SRST_VOP_A 38 -#define SRST_VOP_H 39 -#define SRST_VOP_D 40 -#define SRST_INTMEM_A 41 -#define SRST_ROM_H 42 -#define SRST_GIC_A 43 -#define SRST_UART0_P 44 -#define SRST_UART0 45 -#define SRST_UART1_P 46 -#define SRST_UART1 47 - -/* cru_softrst_con3 */ -#define SRST_UART2_P 48 -#define SRST_UART2 49 -#define SRST_UART3_P 50 -#define SRST_UART3 51 -#define SRST_UART4_P 52 -#define SRST_UART4 53 -#define SRST_I2C0_P 54 -#define SRST_I2C0 55 -#define SRST_I2C1_P 56 -#define SRST_I2C1 57 -#define SRST_I2C2_P 58 -#define SRST_I2C2 59 -#define SRST_I2C3_P 60 -#define SRST_I2C3 61 -#define SRST_PWM0_P 62 -#define SRST_PWM0 63 - -/* cru_softrst_con4 */ -#define SRST_SPI0_P 64 -#define SRST_SPI0 65 -#define SRST_SPI1_P 66 -#define SRST_SPI1 67 -#define SRST_SPI2_P 68 -#define SRST_SPI2 69 -#define SRST_SARADC_P 70 -#define SRST_TSADC_P 71 -#define SRST_TSADC 72 -#define SRST_TIMER0_P 73 -#define SRST_TIMER0 74 -#define SRST_TIMER1 75 -#define SRST_TIMER2 76 -#define SRST_TIMER3 77 -#define SRST_TIMER4 78 -#define SRST_TIMER5 79 - -/* cru_softrst_con5 */ -#define SRST_OTP_NS_P 80 -#define SRST_OTP_NS_SBPI 81 -#define SRST_OTP_NS_USR 82 -#define SRST_OTP_PHY_P 83 -#define SRST_OTP_PHY 84 -#define SRST_GPIO0_P 86 -#define SRST_GPIO1_P 87 -#define SRST_GPIO2_P 88 -#define SRST_GPIO3_P 89 -#define SRST_GPIO4_P 90 -#define SRST_GRF_P 91 -#define SRST_USBSD_DET_P 92 -#define SRST_PMU 93 -#define SRST_PMU_PVTM 94 -#define SRST_USB_GRF_P 95 - -/* cru_softrst_con6 */ -#define SRST_CPU_BOOST 96 -#define SRST_CPU_BOOST_P 97 -#define SRST_PWM1_P 98 -#define SRST_PWM1 99 -#define SRST_PWM2_P 100 -#define SRST_PWM2 101 -#define SRST_PERI_NIU_A 104 -#define SRST_PERI_NIU_H 105 -#define SRST_PERI_NIU_p 106 -#define SRST_USB2OTG_H 107 -#define SRST_USB2OTG 108 -#define SRST_USB2OTG_ADP 109 -#define SRST_USB2HOST_H 110 -#define SRST_USB2HOST_ARB_H 111 - -/* cru_softrst_con7 */ -#define SRST_USB2HOST_AUX_H 112 -#define SRST_USB2HOST_EHCI 113 -#define SRST_USB2HOST 114 -#define SRST_USBPHYPOR 115 -#define SRST_UTMI0 116 -#define SRST_UTMI1 117 -#define SRST_SDIO_H 118 -#define SRST_EMMC_H 119 -#define SRST_SFC_H 120 -#define SRST_SFC 121 -#define SRST_SD_H 122 -#define SRST_NANDC_H 123 -#define SRST_NANDC_N 124 -#define SRST_MAC_A 125 -#define SRST_CAN_P 126 -#define SRST_OWIRE_P 127 - -/* cru_softrst_con8 */ -#define SRST_AUDIO_NIU_H 128 -#define SRST_AUDIO_NIU_P 129 -#define SRST_PDM_H 130 -#define SRST_PDM_M 131 -#define SRST_SPDIFTX_H 132 -#define SRST_SPDIFTX_M 133 -#define SRST_SPDIFRX_H 134 -#define SRST_SPDIFRX_M 135 -#define SRST_I2S0_8CH_H 136 -#define SRST_I2S0_8CH_TX_M 137 -#define SRST_I2S0_8CH_RX_M 138 -#define SRST_I2S1_8CH_H 139 -#define SRST_I2S1_8CH_TX_M 140 -#define SRST_I2S1_8CH_RX_M 141 -#define SRST_I2S2_8CH_H 142 -#define SRST_I2S2_8CH_TX_M 143 - -/* cru_softrst_con9 */ -#define SRST_I2S2_8CH_RX_M 144 -#define SRST_I2S3_8CH_H 145 -#define SRST_I2S3_8CH_TX_M 146 -#define SRST_I2S3_8CH_RX_M 147 -#define SRST_I2S0_2CH_H 148 -#define SRST_I2S0_2CH_M 149 -#define SRST_I2S1_2CH_H 150 -#define SRST_I2S1_2CH_M 151 -#define SRST_VAD_H 152 -#define SRST_ACODEC_P 153 - -#endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h deleted file mode 100644 index 555b4ff660ae..000000000000 --- a/include/dt-bindings/clock/rk3328-cru.h +++ /dev/null @@ -1,393 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Elaine zhangqing@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_RTC32K 30 -#define SCLK_SDMMC_EXT 31 -#define SCLK_SPI 32 -#define SCLK_SDMMC 33 -#define SCLK_SDIO 34 -#define SCLK_EMMC 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_UART0 38 -#define SCLK_UART1 39 -#define SCLK_UART2 40 -#define SCLK_I2S0 41 -#define SCLK_I2S1 42 -#define SCLK_I2S2 43 -#define SCLK_I2S1_OUT 44 -#define SCLK_I2S2_OUT 45 -#define SCLK_SPDIF 46 -#define SCLK_TIMER0 47 -#define SCLK_TIMER1 48 -#define SCLK_TIMER2 49 -#define SCLK_TIMER3 50 -#define SCLK_TIMER4 51 -#define SCLK_TIMER5 52 -#define SCLK_WIFI 53 -#define SCLK_CIF_OUT 54 -#define SCLK_I2C0 55 -#define SCLK_I2C1 56 -#define SCLK_I2C2 57 -#define SCLK_I2C3 58 -#define SCLK_CRYPTO 59 -#define SCLK_PWM 60 -#define SCLK_PDM 61 -#define SCLK_EFUSE 62 -#define SCLK_OTP 63 -#define SCLK_DDRCLK 64 -#define SCLK_VDEC_CABAC 65 -#define SCLK_VDEC_CORE 66 -#define SCLK_VENC_DSP 67 -#define SCLK_VENC_CORE 68 -#define SCLK_RGA 69 -#define SCLK_HDMI_SFC 70 -#define SCLK_HDMI_CEC 71 -#define SCLK_USB3_REF 72 -#define SCLK_USB3_SUSPEND 73 -#define SCLK_SDMMC_DRV 74 -#define SCLK_SDIO_DRV 75 -#define SCLK_EMMC_DRV 76 -#define SCLK_SDMMC_EXT_DRV 77 -#define SCLK_SDMMC_SAMPLE 78 -#define SCLK_SDIO_SAMPLE 79 -#define SCLK_EMMC_SAMPLE 80 -#define SCLK_SDMMC_EXT_SAMPLE 81 -#define SCLK_VOP 82 -#define SCLK_MAC2PHY_RXTX 83 -#define SCLK_MAC2PHY_SRC 84 -#define SCLK_MAC2PHY_REF 85 -#define SCLK_MAC2PHY_OUT 86 -#define SCLK_MAC2IO_RX 87 -#define SCLK_MAC2IO_TX 88 -#define SCLK_MAC2IO_REFOUT 89 -#define SCLK_MAC2IO_REF 90 -#define SCLK_MAC2IO_OUT 91 -#define SCLK_TSP 92 -#define SCLK_HSADC_TSP 93 -#define SCLK_USB3PHY_REF 94 -#define SCLK_REF_USB3OTG 95 -#define SCLK_USB3OTG_REF 96 -#define SCLK_USB3OTG_SUSPEND 97 -#define SCLK_REF_USB3OTG_SRC 98 -#define SCLK_MAC2IO_SRC 99 -#define SCLK_MAC2IO 100 -#define SCLK_MAC2PHY 101 -#define SCLK_MAC2IO_EXT 102 - -/* dclk gates */ -#define DCLK_LCDC 120 -#define DCLK_HDMIPHY 121 -#define HDMIPHY 122 -#define USB480M 123 -#define DCLK_LCDC_SRC 124 - -/* aclk gates */ -#define ACLK_AXISRAM 130 -#define ACLK_VOP_PRE 131 -#define ACLK_USB3OTG 132 -#define ACLK_RGA_PRE 133 -#define ACLK_DMAC 134 -#define ACLK_GPU 135 -#define ACLK_BUS_PRE 136 -#define ACLK_PERI_PRE 137 -#define ACLK_RKVDEC_PRE 138 -#define ACLK_RKVDEC 139 -#define ACLK_RKVENC 140 -#define ACLK_VPU_PRE 141 -#define ACLK_VIO_PRE 142 -#define ACLK_VPU 143 -#define ACLK_VIO 144 -#define ACLK_VOP 145 -#define ACLK_GMAC 146 -#define ACLK_H265 147 -#define ACLK_H264 148 -#define ACLK_MAC2PHY 149 -#define ACLK_MAC2IO 150 -#define ACLK_DCF 151 -#define ACLK_TSP 152 -#define ACLK_PERI 153 -#define ACLK_RGA 154 -#define ACLK_IEP 155 -#define ACLK_CIF 156 -#define ACLK_HDCP 157 - -/* pclk gates */ -#define PCLK_GPIO0 200 -#define PCLK_GPIO1 201 -#define PCLK_GPIO2 202 -#define PCLK_GPIO3 203 -#define PCLK_GRF 204 -#define PCLK_I2C0 205 -#define PCLK_I2C1 206 -#define PCLK_I2C2 207 -#define PCLK_I2C3 208 -#define PCLK_SPI 209 -#define PCLK_UART0 210 -#define PCLK_UART1 211 -#define PCLK_UART2 212 -#define PCLK_TSADC 213 -#define PCLK_PWM 214 -#define PCLK_TIMER 215 -#define PCLK_BUS_PRE 216 -#define PCLK_PERI_PRE 217 -#define PCLK_HDMI_CTRL 218 -#define PCLK_HDMI_PHY 219 -#define PCLK_GMAC 220 -#define PCLK_H265 221 -#define PCLK_MAC2PHY 222 -#define PCLK_MAC2IO 223 -#define PCLK_USB3PHY_OTG 224 -#define PCLK_USB3PHY_PIPE 225 -#define PCLK_USB3_GRF 226 -#define PCLK_USB2_GRF 227 -#define PCLK_HDMIPHY 228 -#define PCLK_DDR 229 -#define PCLK_PERI 230 -#define PCLK_HDMI 231 -#define PCLK_HDCP 232 -#define PCLK_DCF 233 -#define PCLK_SARADC 234 -#define PCLK_ACODECPHY 235 -#define PCLK_WDT 236 - -/* hclk gates */ -#define HCLK_PERI 308 -#define HCLK_TSP 309 -#define HCLK_GMAC 310 -#define HCLK_I2S0_8CH 311 -#define HCLK_I2S1_8CH 312 -#define HCLK_I2S2_2CH 313 -#define HCLK_SPDIF_8CH 314 -#define HCLK_VOP 315 -#define HCLK_NANDC 316 -#define HCLK_SDMMC 317 -#define HCLK_SDIO 318 -#define HCLK_EMMC 319 -#define HCLK_SDMMC_EXT 320 -#define HCLK_RKVDEC_PRE 321 -#define HCLK_RKVDEC 322 -#define HCLK_RKVENC 323 -#define HCLK_VPU_PRE 324 -#define HCLK_VIO_PRE 325 -#define HCLK_VPU 326 -#define HCLK_BUS_PRE 328 -#define HCLK_PERI_PRE 329 -#define HCLK_H264 330 -#define HCLK_CIF 331 -#define HCLK_OTG_PMU 332 -#define HCLK_OTG 333 -#define HCLK_HOST0 334 -#define HCLK_HOST0_ARB 335 -#define HCLK_CRYPTO_MST 336 -#define HCLK_CRYPTO_SLV 337 -#define HCLK_PDM 338 -#define HCLK_IEP 339 -#define HCLK_RGA 340 -#define HCLK_HDCP 341 - -#define CLK_NR_CLKS (HCLK_HDCP + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NIU 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_A53_GIC 18 -#define SRST_DAP 19 -#define SRST_PMU_P 21 -#define SRST_EFUSE 22 -#define SRST_BUSSYS_H 23 -#define SRST_BUSSYS_P 24 -#define SRST_SPDIF 25 -#define SRST_INTMEM 26 -#define SRST_ROM 27 -#define SRST_GPIO0 28 -#define SRST_GPIO1 29 -#define SRST_GPIO2 30 -#define SRST_GPIO3 31 - -#define SRST_I2S0 32 -#define SRST_I2S1 33 -#define SRST_I2S2 34 -#define SRST_I2S0_H 35 -#define SRST_I2S1_H 36 -#define SRST_I2S2_H 37 -#define SRST_UART0 38 -#define SRST_UART1 39 -#define SRST_UART2 40 -#define SRST_UART0_P 41 -#define SRST_UART1_P 42 -#define SRST_UART2_P 43 -#define SRST_I2C0 44 -#define SRST_I2C1 45 -#define SRST_I2C2 46 -#define SRST_I2C3 47 - -#define SRST_I2C0_P 48 -#define SRST_I2C1_P 49 -#define SRST_I2C2_P 50 -#define SRST_I2C3_P 51 -#define SRST_EFUSE_SE_P 52 -#define SRST_EFUSE_NS_P 53 -#define SRST_PWM0 54 -#define SRST_PWM0_P 55 -#define SRST_DMA 56 -#define SRST_TSP_A 57 -#define SRST_TSP_H 58 -#define SRST_TSP 59 -#define SRST_TSP_HSADC 60 -#define SRST_DCF_A 61 -#define SRST_DCF_P 62 - -#define SRST_SCR 64 -#define SRST_SPI 65 -#define SRST_TSADC 66 -#define SRST_TSADC_P 67 -#define SRST_CRYPTO 68 -#define SRST_SGRF 69 -#define SRST_GRF 70 -#define SRST_USB_GRF 71 -#define SRST_TIMER_6CH_P 72 -#define SRST_TIMER0 73 -#define SRST_TIMER1 74 -#define SRST_TIMER2 75 -#define SRST_TIMER3 76 -#define SRST_TIMER4 77 -#define SRST_TIMER5 78 -#define SRST_USB3GRF 79 - -#define SRST_PHYNIU 80 -#define SRST_HDMIPHY 81 -#define SRST_VDAC 82 -#define SRST_ACODEC_p 83 -#define SRST_SARADC 85 -#define SRST_SARADC_P 86 -#define SRST_GRF_DDR 87 -#define SRST_DFIMON 88 -#define SRST_MSCH 89 -#define SRST_DDRMSCH 91 -#define SRST_DDRCTRL 92 -#define SRST_DDRCTRL_P 93 -#define SRST_DDRPHY 94 -#define SRST_DDRPHY_P 95 - -#define SRST_GMAC_NIU_A 96 -#define SRST_GMAC_NIU_P 97 -#define SRST_GMAC2PHY_A 98 -#define SRST_GMAC2IO_A 99 -#define SRST_MACPHY 100 -#define SRST_OTP_PHY 101 -#define SRST_GPU_A 102 -#define SRST_GPU_NIU_A 103 -#define SRST_SDMMCEXT 104 -#define SRST_PERIPH_NIU_A 105 -#define SRST_PERIHP_NIU_H 106 -#define SRST_PERIHP_P 107 -#define SRST_PERIPHSYS_H 108 -#define SRST_MMC0 109 -#define SRST_SDIO 110 -#define SRST_EMMC 111 - -#define SRST_USB2OTG_H 112 -#define SRST_USB2OTG 113 -#define SRST_USB2OTG_ADP 114 -#define SRST_USB2HOST_H 115 -#define SRST_USB2HOST_ARB 116 -#define SRST_USB2HOST_AUX 117 -#define SRST_USB2HOST_EHCIPHY 118 -#define SRST_USB2HOST_UTMI 119 -#define SRST_USB3OTG 120 -#define SRST_USBPOR 121 -#define SRST_USB2OTG_UTMI 122 -#define SRST_USB2HOST_PHY_UTMI 123 -#define SRST_USB3OTG_UTMI 124 -#define SRST_USB3PHY_U2 125 -#define SRST_USB3PHY_U3 126 -#define SRST_USB3PHY_PIPE 127 - -#define SRST_VIO_A 128 -#define SRST_VIO_BUS_H 129 -#define SRST_VIO_H2P_H 130 -#define SRST_VIO_ARBI_H 131 -#define SRST_VOP_NIU_A 132 -#define SRST_VOP_A 133 -#define SRST_VOP_H 134 -#define SRST_VOP_D 135 -#define SRST_RGA 136 -#define SRST_RGA_NIU_A 137 -#define SRST_RGA_A 138 -#define SRST_RGA_H 139 -#define SRST_IEP_A 140 -#define SRST_IEP_H 141 -#define SRST_HDMI 142 -#define SRST_HDMI_P 143 - -#define SRST_HDCP_A 144 -#define SRST_HDCP 145 -#define SRST_HDCP_H 146 -#define SRST_CIF_A 147 -#define SRST_CIF_H 148 -#define SRST_CIF_P 149 -#define SRST_OTP_P 150 -#define SRST_OTP_SBPI 151 -#define SRST_OTP_USER 152 -#define SRST_DDRCTRL_A 153 -#define SRST_DDRSTDY_P 154 -#define SRST_DDRSTDY 155 -#define SRST_PDM_H 156 -#define SRST_PDM 157 -#define SRST_USB3PHY_OTG_P 158 -#define SRST_USB3PHY_PIPE_P 159 - -#define SRST_VCODEC_A 160 -#define SRST_VCODEC_NIU_A 161 -#define SRST_VCODEC_H 162 -#define SRST_VCODEC_NIU_H 163 -#define SRST_VDEC_A 164 -#define SRST_VDEC_NIU_A 165 -#define SRST_VDEC_H 166 -#define SRST_VDEC_NIU_H 167 -#define SRST_VDEC_CORE 168 -#define SRST_VDEC_CABAC 169 -#define SRST_DDRPHYDIV 175 - -#define SRST_RKVENC_NIU_A 176 -#define SRST_RKVENC_NIU_H 177 -#define SRST_RKVENC_H265_A 178 -#define SRST_RKVENC_H265_P 179 -#define SRST_RKVENC_H265_CORE 180 -#define SRST_RKVENC_H265_DSP 181 -#define SRST_RKVENC_H264_A 182 -#define SRST_RKVENC_H264_H 183 -#define SRST_RKVENC_INTMEM 184 - -#endif diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h deleted file mode 100644 index 0a06c5f514d7..000000000000 --- a/include/dt-bindings/clock/rk3368-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Heiko Stuebner heiko@sntech.de - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H - -/* core clocks */ -#define PLL_APLLB 1 -#define PLL_APLLL 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define ARMCLKB 7 -#define ARMCLKL 8 - -/* sclk gates (special clocks) */ -#define SCLK_GPU_CORE 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_NANDC0 75 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S_8CH 82 -#define SCLK_SPDIF_8CH 83 -#define SCLK_I2S_2CH 84 -#define SCLK_TIMER00 85 -#define SCLK_TIMER01 86 -#define SCLK_TIMER02 87 -#define SCLK_TIMER03 88 -#define SCLK_TIMER04 89 -#define SCLK_TIMER05 90 -#define SCLK_OTGPHY0 93 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_VOP0_PWM 100 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_HDCP 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S_8CH_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_PMU 125 -#define SCLK_SFC 126 -#define SCLK_MAC 127 -#define SCLK_MACREF_OUT 128 -#define SCLK_TIMER10 133 -#define SCLK_TIMER11 134 -#define SCLK_TIMER12 135 -#define SCLK_TIMER13 136 -#define SCLK_TIMER14 137 -#define SCLK_TIMER15 138 - -#define DCLK_VOP 190 -#define MCLK_CRYPTO 191 - -/* aclk gates */ -#define ACLK_GPU_MEM 192 -#define ACLK_GPU_CFG 193 -#define ACLK_DMAC_BUS 194 -#define ACLK_DMAC_PERI 195 -#define ACLK_PERI_MMU 196 -#define ACLK_GMAC 197 -#define ACLK_VOP 198 -#define ACLK_VOP_IEP 199 -#define ACLK_RGA 200 -#define ACLK_HDCP 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NOC 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NOC 206 -#define ACLK_VIDEO 208 -#define ACLK_BUS 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_PMUGRF 324 -#define PCLK_MAILBOX 325 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM0 350 -#define PCLK_PWM1 351 -#define PCLK_TIMER0 353 -#define PCLK_TIMER1 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_CSI 358 -#define PCLK_HDCP 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO_H2P 361 -#define PCLK_BUS 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_DDRPHY 365 -#define PCLK_ISP 366 -#define PCLK_VIP 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 - -/* hclk gates */ -#define HCLK_SFC 448 -#define HCLK_OTG0 449 -#define HCLK_HOST0 450 -#define HCLK_HOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S_2CH 462 -#define HCLK_I2S_8CH 463 -#define HCLK_SPDIF 464 -#define HCLK_VOP 465 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NOC 472 -#define HCLK_VIP 473 -#define HCLK_VIO_H2P 474 -#define HCLK_VIO_HDCPMMU 475 -#define HCLK_VIDEO 476 -#define HCLK_BUS 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE_B0 0 -#define SRST_CORE_B1 1 -#define SRST_CORE_B2 2 -#define SRST_CORE_B3 3 -#define SRST_CORE_B0_PO 4 -#define SRST_CORE_B1_PO 5 -#define SRST_CORE_B2_PO 6 -#define SRST_CORE_B3_PO 7 -#define SRST_L2_B 8 -#define SRST_ADB_B 9 -#define SRST_PD_CORE_B_NIU 10 -#define SRST_PDBUS_STRSYS 11 -#define SRST_SOCDBG_B 14 -#define SRST_CORE_B_DBG 15 - -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_I2S8CH 23 -#define SRST_MAILBOX 24 -#define SRST_I2S2CH 25 -#define SRST_EFUSE_256 26 -#define SRST_MCU_SYS 28 -#define SRST_MCU_PO 29 -#define SRST_MCU_NOC 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_PMUGRF 41 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_SFC 79 - -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP_24M 111 - -#define SRST_VIDEO_AXI 112 -#define SRST_VIDEO_AHB 113 -#define SRST_MIPIDPHYTX 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDPHYRX 116 -#define SRST_MIPICSI 117 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_EDP 122 -#define SRST_PMU_PVTM 123 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 -#define SRST_GPU_SYS 126 -#define SRST_GPU_MEM_NIU 127 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBOTG_UTMI 138 -#define SRST_USBHOST1_UTMI 139 -#define SRST_USB_ADP 141 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_RGA_H2P_BRG 153 -#define SRST_VIDEO 154 -#define SRST_GPU_CFG_NIU 157 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_VIDEO_NIU 165 -#define SRST_VIDEO_NIU_AHB 167 -#define SRST_DDRMSCH0 170 -#define SRST_PDBUS_AHB 173 -#define SRST_CRYPTO 174 - -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 - -#define SRST_CORE_L0 192 -#define SRST_CORE_L1 193 -#define SRST_CORE_L2 194 -#define SRST_CORE_L3 195 -#define SRST_CORE_L0_PO 195 -#define SRST_CORE_L1_PO 197 -#define SRST_CORE_L2_PO 198 -#define SRST_CORE_L3_PO 199 -#define SRST_L2_L 200 -#define SRST_ADB_L 201 -#define SRST_PD_CORE_L_NIU 202 -#define SRST_CCI_SYS 203 -#define SRST_CCI_DDR 204 -#define SRST_CCI 205 -#define SRST_SOCDBG_L 206 -#define SRST_CORE_L_DBG 207 - -#define SRST_CORE_B0_NC 208 -#define SRST_CORE_B0_PO_NC 209 -#define SRST_L2_B_NC 210 -#define SRST_ADB_B_NC 211 -#define SRST_PD_CORE_B_NIU_NC 212 -#define SRST_PDBUS_STRSYS_NC 213 -#define SRST_CORE_L0_NC 214 -#define SRST_CORE_L0_PO_NC 215 -#define SRST_L2_L_NC 216 -#define SRST_ADB_L_NC 217 -#define SRST_PD_CORE_L_NIU_NC 218 -#define SRST_CCI_SYS_NC 219 -#define SRST_CCI_DDR_NC 220 -#define SRST_CCI_NC 221 -#define SRST_TRACE_NC 222 - -#define SRST_TIMER00 224 -#define SRST_TIMER01 225 -#define SRST_TIMER02 226 -#define SRST_TIMER03 227 -#define SRST_TIMER04 228 -#define SRST_TIMER05 229 -#define SRST_TIMER10 230 -#define SRST_TIMER11 231 -#define SRST_TIMER12 232 -#define SRST_TIMER13 233 -#define SRST_TIMER14 234 -#define SRST_TIMER15 235 -#define SRST_TIMER0_APB 236 -#define SRST_TIMER1_APB 237 - -#endif diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h deleted file mode 100644 index 211faf8fa891..000000000000 --- a/include/dt-bindings/clock/rk3399-cru.h +++ /dev/null @@ -1,749 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H - -/* core clocks */ -#define PLL_APLLL 1 -#define PLL_APLLB 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define PLL_VPLL 7 -#define ARMCLKL 8 -#define ARMCLKB 9 - -/* sclk gates (special clocks) */ -#define SCLK_I2C1 65 -#define SCLK_I2C2 66 -#define SCLK_I2C3 67 -#define SCLK_I2C5 68 -#define SCLK_I2C6 69 -#define SCLK_I2C7 70 -#define SCLK_SPI0 71 -#define SCLK_SPI1 72 -#define SCLK_SPI2 73 -#define SCLK_SPI4 74 -#define SCLK_SPI5 75 -#define SCLK_SDMMC 76 -#define SCLK_SDIO 77 -#define SCLK_EMMC 78 -#define SCLK_TSADC 79 -#define SCLK_SARADC 80 -#define SCLK_UART0 81 -#define SCLK_UART1 82 -#define SCLK_UART2 83 -#define SCLK_UART3 84 -#define SCLK_SPDIF_8CH 85 -#define SCLK_I2S0_8CH 86 -#define SCLK_I2S1_8CH 87 -#define SCLK_I2S2_8CH 88 -#define SCLK_I2S_8CH_OUT 89 -#define SCLK_TIMER00 90 -#define SCLK_TIMER01 91 -#define SCLK_TIMER02 92 -#define SCLK_TIMER03 93 -#define SCLK_TIMER04 94 -#define SCLK_TIMER05 95 -#define SCLK_TIMER06 96 -#define SCLK_TIMER07 97 -#define SCLK_TIMER08 98 -#define SCLK_TIMER09 99 -#define SCLK_TIMER10 100 -#define SCLK_TIMER11 101 -#define SCLK_MACREF 102 -#define SCLK_MAC_RX 103 -#define SCLK_MAC_TX 104 -#define SCLK_MAC 105 -#define SCLK_MACREF_OUT 106 -#define SCLK_VOP0_PWM 107 -#define SCLK_VOP1_PWM 108 -#define SCLK_RGA_CORE 109 -#define SCLK_ISP0 110 -#define SCLK_ISP1 111 -#define SCLK_HDMI_CEC 112 -#define SCLK_HDMI_SFR 113 -#define SCLK_DP_CORE 114 -#define SCLK_PVTM_CORE_L 115 -#define SCLK_PVTM_CORE_B 116 -#define SCLK_PVTM_GPU 117 -#define SCLK_PVTM_DDR 118 -#define SCLK_MIPIDPHY_REF 119 -#define SCLK_MIPIDPHY_CFG 120 -#define SCLK_HSICPHY 121 -#define SCLK_USBPHY480M 122 -#define SCLK_USB2PHY0_REF 123 -#define SCLK_USB2PHY1_REF 124 -#define SCLK_UPHY0_TCPDPHY_REF 125 -#define SCLK_UPHY0_TCPDCORE 126 -#define SCLK_UPHY1_TCPDPHY_REF 127 -#define SCLK_UPHY1_TCPDCORE 128 -#define SCLK_USB3OTG0_REF 129 -#define SCLK_USB3OTG1_REF 130 -#define SCLK_USB3OTG0_SUSPEND 131 -#define SCLK_USB3OTG1_SUSPEND 132 -#define SCLK_CRYPTO0 133 -#define SCLK_CRYPTO1 134 -#define SCLK_CCI_TRACE 135 -#define SCLK_CS 136 -#define SCLK_CIF_OUT 137 -#define SCLK_PCIEPHY_REF 138 -#define SCLK_PCIE_CORE 139 -#define SCLK_M0_PERILP 140 -#define SCLK_M0_PERILP_DEC 141 -#define SCLK_CM0S 142 -#define SCLK_DBG_NOC 143 -#define SCLK_DBG_PD_CORE_B 144 -#define SCLK_DBG_PD_CORE_L 145 -#define SCLK_DFIMON0_TIMER 146 -#define SCLK_DFIMON1_TIMER 147 -#define SCLK_INTMEM0 148 -#define SCLK_INTMEM1 149 -#define SCLK_INTMEM2 150 -#define SCLK_INTMEM3 151 -#define SCLK_INTMEM4 152 -#define SCLK_INTMEM5 153 -#define SCLK_SDMMC_DRV 154 -#define SCLK_SDMMC_SAMPLE 155 -#define SCLK_SDIO_DRV 156 -#define SCLK_SDIO_SAMPLE 157 -#define SCLK_VDU_CORE 158 -#define SCLK_VDU_CA 159 -#define SCLK_PCIE_PM 160 -#define SCLK_SPDIF_REC_DPTX 161 -#define SCLK_DPHY_PLL 162 -#define SCLK_DPHY_TX0_CFG 163 -#define SCLK_DPHY_TX1RX1_CFG 164 -#define SCLK_DPHY_RX0_CFG 165 -#define SCLK_RMII_SRC 166 -#define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 - -#define DCLK_VOP0 180 -#define DCLK_VOP1 181 -#define DCLK_VOP0_DIV 182 -#define DCLK_VOP1_DIV 183 -#define DCLK_M0_PERILP 184 - -#define FCLK_CM0S 190 - -/* aclk gates */ -#define ACLK_PERIHP 192 -#define ACLK_PERIHP_NOC 193 -#define ACLK_PERILP0 194 -#define ACLK_PERILP0_NOC 195 -#define ACLK_PERF_PCIE 196 -#define ACLK_PCIE 197 -#define ACLK_INTMEM 198 -#define ACLK_TZMA 199 -#define ACLK_DCF 200 -#define ACLK_CCI 201 -#define ACLK_CCI_NOC0 202 -#define ACLK_CCI_NOC1 203 -#define ACLK_CCI_GRF 204 -#define ACLK_CENTER 205 -#define ACLK_CENTER_MAIN_NOC 206 -#define ACLK_CENTER_PERI_NOC 207 -#define ACLK_GPU 208 -#define ACLK_PERF_GPU 209 -#define ACLK_GPU_GRF 210 -#define ACLK_DMAC0_PERILP 211 -#define ACLK_DMAC1_PERILP 212 -#define ACLK_GMAC 213 -#define ACLK_GMAC_NOC 214 -#define ACLK_PERF_GMAC 215 -#define ACLK_VOP0_NOC 216 -#define ACLK_VOP0 217 -#define ACLK_VOP1_NOC 218 -#define ACLK_VOP1 219 -#define ACLK_RGA 220 -#define ACLK_RGA_NOC 221 -#define ACLK_HDCP 222 -#define ACLK_HDCP_NOC 223 -#define ACLK_HDCP22 224 -#define ACLK_IEP 225 -#define ACLK_IEP_NOC 226 -#define ACLK_VIO 227 -#define ACLK_VIO_NOC 228 -#define ACLK_ISP0 229 -#define ACLK_ISP1 230 -#define ACLK_ISP0_NOC 231 -#define ACLK_ISP1_NOC 232 -#define ACLK_ISP0_WRAPPER 233 -#define ACLK_ISP1_WRAPPER 234 -#define ACLK_VCODEC 235 -#define ACLK_VCODEC_NOC 236 -#define ACLK_VDU 237 -#define ACLK_VDU_NOC 238 -#define ACLK_PERI 239 -#define ACLK_EMMC 240 -#define ACLK_EMMC_CORE 241 -#define ACLK_EMMC_NOC 242 -#define ACLK_EMMC_GRF 243 -#define ACLK_USB3 244 -#define ACLK_USB3_NOC 245 -#define ACLK_USB3OTG0 246 -#define ACLK_USB3OTG1 247 -#define ACLK_USB3_RKSOC_AXI_PERF 248 -#define ACLK_USB3_GRF 249 -#define ACLK_GIC 250 -#define ACLK_GIC_NOC 251 -#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 -#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 -#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 -#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 -#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 -#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 -#define ACLK_ADB400M_PD_CORE_L 258 -#define ACLK_ADB400M_PD_CORE_B 259 -#define ACLK_PERF_CORE_L 260 -#define ACLK_PERF_CORE_B 261 -#define ACLK_GIC_PRE 262 -#define ACLK_VOP0_PRE 263 -#define ACLK_VOP1_PRE 264 - -/* pclk gates */ -#define PCLK_PERIHP 320 -#define PCLK_PERIHP_NOC 321 -#define PCLK_PERILP0 322 -#define PCLK_PERILP1 323 -#define PCLK_PERILP1_NOC 324 -#define PCLK_PERILP_SGRF 325 -#define PCLK_PERIHP_GRF 326 -#define PCLK_PCIE 327 -#define PCLK_SGRF 328 -#define PCLK_INTR_ARB 329 -#define PCLK_CENTER_MAIN_NOC 330 -#define PCLK_CIC 331 -#define PCLK_COREDBG_B 332 -#define PCLK_COREDBG_L 333 -#define PCLK_DBG_CXCS_PD_CORE_B 334 -#define PCLK_DCF 335 -#define PCLK_GPIO2 336 -#define PCLK_GPIO3 337 -#define PCLK_GPIO4 338 -#define PCLK_GRF 339 -#define PCLK_HSICPHY 340 -#define PCLK_I2C1 341 -#define PCLK_I2C2 342 -#define PCLK_I2C3 343 -#define PCLK_I2C5 344 -#define PCLK_I2C6 345 -#define PCLK_I2C7 346 -#define PCLK_SPI0 347 -#define PCLK_SPI1 348 -#define PCLK_SPI2 349 -#define PCLK_SPI4 350 -#define PCLK_SPI5 351 -#define PCLK_UART0 352 -#define PCLK_UART1 353 -#define PCLK_UART2 354 -#define PCLK_UART3 355 -#define PCLK_TSADC 356 -#define PCLK_SARADC 357 -#define PCLK_GMAC 358 -#define PCLK_GMAC_NOC 359 -#define PCLK_TIMER0 360 -#define PCLK_TIMER1 361 -#define PCLK_EDP 362 -#define PCLK_EDP_NOC 363 -#define PCLK_EDP_CTRL 364 -#define PCLK_VIO 365 -#define PCLK_VIO_NOC 366 -#define PCLK_VIO_GRF 367 -#define PCLK_MIPI_DSI0 368 -#define PCLK_MIPI_DSI1 369 -#define PCLK_HDCP 370 -#define PCLK_HDCP_NOC 371 -#define PCLK_HDMI_CTRL 372 -#define PCLK_DP_CTRL 373 -#define PCLK_HDCP22 374 -#define PCLK_GASKET 375 -#define PCLK_DDR 376 -#define PCLK_DDR_MON 377 -#define PCLK_DDR_SGRF 378 -#define PCLK_ISP1_WRAPPER 379 -#define PCLK_WDT 380 -#define PCLK_EFUSE1024NS 381 -#define PCLK_EFUSE1024S 382 -#define PCLK_PMU_INTR_ARB 383 -#define PCLK_MAILBOX0 384 -#define PCLK_USBPHY_MUX_G 385 -#define PCLK_UPHY0_TCPHY_G 386 -#define PCLK_UPHY0_TCPD_G 387 -#define PCLK_UPHY1_TCPHY_G 388 -#define PCLK_UPHY1_TCPD_G 389 -#define PCLK_ALIVE 390 - -/* hclk gates */ -#define HCLK_PERIHP 448 -#define HCLK_PERILP0 449 -#define HCLK_PERILP1 450 -#define HCLK_PERILP0_NOC 451 -#define HCLK_PERILP1_NOC 452 -#define HCLK_M0_PERILP 453 -#define HCLK_M0_PERILP_NOC 454 -#define HCLK_AHB1TOM 455 -#define HCLK_HOST0 456 -#define HCLK_HOST0_ARB 457 -#define HCLK_HOST1 458 -#define HCLK_HOST1_ARB 459 -#define HCLK_HSIC 460 -#define HCLK_SD 461 -#define HCLK_SDMMC 462 -#define HCLK_SDMMC_NOC 463 -#define HCLK_M_CRYPTO0 464 -#define HCLK_M_CRYPTO1 465 -#define HCLK_S_CRYPTO0 466 -#define HCLK_S_CRYPTO1 467 -#define HCLK_I2S0_8CH 468 -#define HCLK_I2S1_8CH 469 -#define HCLK_I2S2_8CH 470 -#define HCLK_SPDIF 471 -#define HCLK_VOP0_NOC 472 -#define HCLK_VOP0 473 -#define HCLK_VOP1_NOC 474 -#define HCLK_VOP1 475 -#define HCLK_ROM 476 -#define HCLK_IEP 477 -#define HCLK_IEP_NOC 478 -#define HCLK_ISP0 479 -#define HCLK_ISP1 480 -#define HCLK_ISP0_NOC 481 -#define HCLK_ISP1_NOC 482 -#define HCLK_ISP0_WRAPPER 483 -#define HCLK_ISP1_WRAPPER 484 -#define HCLK_RGA 485 -#define HCLK_RGA_NOC 486 -#define HCLK_HDCP 487 -#define HCLK_HDCP_NOC 488 -#define HCLK_HDCP22 489 -#define HCLK_VCODEC 490 -#define HCLK_VCODEC_NOC 491 -#define HCLK_VDU 492 -#define HCLK_VDU_NOC 493 -#define HCLK_SDIO 494 -#define HCLK_SDIO_NOC 495 -#define HCLK_SDIOAUDIO_NOC 496 - -#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) - -/* pmu-clocks indices */ - -#define PLL_PPLL 1 - -#define SCLK_32K_SUSPEND_PMU 2 -#define SCLK_SPI3_PMU 3 -#define SCLK_TIMER12_PMU 4 -#define SCLK_TIMER13_PMU 5 -#define SCLK_UART4_PMU 6 -#define SCLK_PVTM_PMU 7 -#define SCLK_WIFI_PMU 8 -#define SCLK_I2C0_PMU 9 -#define SCLK_I2C4_PMU 10 -#define SCLK_I2C8_PMU 11 - -#define PCLK_SRC_PMU 19 -#define PCLK_PMU 20 -#define PCLK_PMUGRF_PMU 21 -#define PCLK_INTMEM1_PMU 22 -#define PCLK_GPIO0_PMU 23 -#define PCLK_GPIO1_PMU 24 -#define PCLK_SGRF_PMU 25 -#define PCLK_NOC_PMU 26 -#define PCLK_I2C0_PMU 27 -#define PCLK_I2C4_PMU 28 -#define PCLK_I2C8_PMU 29 -#define PCLK_RKPWM_PMU 30 -#define PCLK_SPI3_PMU 31 -#define PCLK_TIMER_PMU 32 -#define PCLK_MAILBOX_PMU 33 -#define PCLK_UART4_PMU 34 -#define PCLK_WDT_M0_PMU 35 - -#define FCLK_CM0S_SRC_PMU 44 -#define FCLK_CM0S_PMU 45 -#define SCLK_CM0S_PMU 46 -#define HCLK_CM0S_PMU 47 -#define DCLK_CM0S_PMU 48 -#define PCLK_INTR_ARB_PMU 49 -#define HCLK_NOC_PMU 50 - -#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE_L0 0 -#define SRST_CORE_B0 1 -#define SRST_CORE_PO_L0 2 -#define SRST_CORE_PO_B0 3 -#define SRST_L2_L 4 -#define SRST_L2_B 5 -#define SRST_ADB_L 6 -#define SRST_ADB_B 7 -#define SRST_A_CCI 8 -#define SRST_A_CCIM0_NOC 9 -#define SRST_A_CCIM1_NOC 10 -#define SRST_DBG_NOC 11 - -/* cru_softrst_con1 */ -#define SRST_CORE_L0_T 16 -#define SRST_CORE_L1 17 -#define SRST_CORE_L2 18 -#define SRST_CORE_L3 19 -#define SRST_CORE_PO_L0_T 20 -#define SRST_CORE_PO_L1 21 -#define SRST_CORE_PO_L2 22 -#define SRST_CORE_PO_L3 23 -#define SRST_A_ADB400_GIC2COREL 24 -#define SRST_A_ADB400_COREL2GIC 25 -#define SRST_P_DBG_L 26 -#define SRST_L2_L_T 28 -#define SRST_ADB_L_T 29 -#define SRST_A_RKPERF_L 30 -#define SRST_PVTM_CORE_L 31 - -/* cru_softrst_con2 */ -#define SRST_CORE_B0_T 32 -#define SRST_CORE_B1 33 -#define SRST_CORE_PO_B0_T 36 -#define SRST_CORE_PO_B1 37 -#define SRST_A_ADB400_GIC2COREB 40 -#define SRST_A_ADB400_COREB2GIC 41 -#define SRST_P_DBG_B 42 -#define SRST_L2_B_T 43 -#define SRST_ADB_B_T 45 -#define SRST_A_RKPERF_B 46 -#define SRST_PVTM_CORE_B 47 - -/* cru_softrst_con3 */ -#define SRST_A_CCI_T 50 -#define SRST_A_CCIM0_NOC_T 51 -#define SRST_A_CCIM1_NOC_T 52 -#define SRST_A_ADB400M_PD_CORE_B_T 53 -#define SRST_A_ADB400M_PD_CORE_L_T 54 -#define SRST_DBG_NOC_T 55 -#define SRST_DBG_CXCS 56 -#define SRST_CCI_TRACE 57 -#define SRST_P_CCI_GRF 58 - -/* cru_softrst_con4 */ -#define SRST_A_CENTER_MAIN_NOC 64 -#define SRST_A_CENTER_PERI_NOC 65 -#define SRST_P_CENTER_MAIN 66 -#define SRST_P_DDRMON 67 -#define SRST_P_CIC 68 -#define SRST_P_CENTER_SGRF 69 -#define SRST_DDR0_MSCH 70 -#define SRST_DDRCFG0_MSCH 71 -#define SRST_DDR0 72 -#define SRST_DDRPHY0 73 -#define SRST_DDR1_MSCH 74 -#define SRST_DDRCFG1_MSCH 75 -#define SRST_DDR1 76 -#define SRST_DDRPHY1 77 -#define SRST_DDR_CIC 78 -#define SRST_PVTM_DDR 79 - -/* cru_softrst_con5 */ -#define SRST_A_VCODEC_NOC 80 -#define SRST_A_VCODEC 81 -#define SRST_H_VCODEC_NOC 82 -#define SRST_H_VCODEC 83 -#define SRST_A_VDU_NOC 88 -#define SRST_A_VDU 89 -#define SRST_H_VDU_NOC 90 -#define SRST_H_VDU 91 -#define SRST_VDU_CORE 92 -#define SRST_VDU_CA 93 - -/* cru_softrst_con6 */ -#define SRST_A_IEP_NOC 96 -#define SRST_A_VOP_IEP 97 -#define SRST_A_IEP 98 -#define SRST_H_IEP_NOC 99 -#define SRST_H_IEP 100 -#define SRST_A_RGA_NOC 102 -#define SRST_A_RGA 103 -#define SRST_H_RGA_NOC 104 -#define SRST_H_RGA 105 -#define SRST_RGA_CORE 106 -#define SRST_EMMC_NOC 108 -#define SRST_EMMC 109 -#define SRST_EMMC_GRF 110 - -/* cru_softrst_con7 */ -#define SRST_A_PERIHP_NOC 112 -#define SRST_P_PERIHP_GRF 113 -#define SRST_H_PERIHP_NOC 114 -#define SRST_USBHOST0 115 -#define SRST_HOSTC0_AUX 116 -#define SRST_HOST0_ARB 117 -#define SRST_USBHOST1 118 -#define SRST_HOSTC1_AUX 119 -#define SRST_HOST1_ARB 120 -#define SRST_SDIO0 121 -#define SRST_SDMMC 122 -#define SRST_HSIC 123 -#define SRST_HSIC_AUX 124 -#define SRST_AHB1TOM 125 -#define SRST_P_PERIHP_NOC 126 -#define SRST_HSICPHY 127 - -/* cru_softrst_con8 */ -#define SRST_A_PCIE 128 -#define SRST_P_PCIE 129 -#define SRST_PCIE_CORE 130 -#define SRST_PCIE_MGMT 131 -#define SRST_PCIE_MGMT_STICKY 132 -#define SRST_PCIE_PIPE 133 -#define SRST_PCIE_PM 134 -#define SRST_PCIEPHY 135 -#define SRST_A_GMAC_NOC 136 -#define SRST_A_GMAC 137 -#define SRST_P_GMAC_NOC 138 -#define SRST_P_GMAC_GRF 140 -#define SRST_HSICPHY_POR 142 -#define SRST_HSICPHY_UTMI 143 - -/* cru_softrst_con9 */ -#define SRST_USB2PHY0_POR 144 -#define SRST_USB2PHY0_UTMI_PORT0 145 -#define SRST_USB2PHY0_UTMI_PORT1 146 -#define SRST_USB2PHY0_EHCIPHY 147 -#define SRST_UPHY0_PIPE_L00 148 -#define SRST_UPHY0 149 -#define SRST_UPHY0_TCPDPWRUP 150 -#define SRST_USB2PHY1_POR 152 -#define SRST_USB2PHY1_UTMI_PORT0 153 -#define SRST_USB2PHY1_UTMI_PORT1 154 -#define SRST_USB2PHY1_EHCIPHY 155 -#define SRST_UPHY1_PIPE_L00 156 -#define SRST_UPHY1 157 -#define SRST_UPHY1_TCPDPWRUP 158 - -/* cru_softrst_con10 */ -#define SRST_A_PERILP0_NOC 160 -#define SRST_A_DCF 161 -#define SRST_GIC500 162 -#define SRST_DMAC0_PERILP0 163 -#define SRST_DMAC1_PERILP0 164 -#define SRST_TZMA 165 -#define SRST_INTMEM 166 -#define SRST_ADB400_MST0 167 -#define SRST_ADB400_MST1 168 -#define SRST_ADB400_SLV0 169 -#define SRST_ADB400_SLV1 170 -#define SRST_H_PERILP0 171 -#define SRST_H_PERILP0_NOC 172 -#define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 - -/* cru_softrst_con11 */ -#define SRST_P_DCF 176 -#define SRST_CM0S_NOC 177 -#define SRST_CM0S 178 -#define SRST_CM0S_DBG 179 -#define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 -#define SRST_P_PERILP1_SGRF 182 -#define SRST_P_PERILP1_GRF 183 -#define SRST_CRYPTO1_S 184 -#define SRST_CRYPTO1_M 185 -#define SRST_CRYPTO1 186 -#define SRST_GIC_NOC 188 -#define SRST_SD_NOC 189 -#define SRST_SDIOAUDIO_BRG 190 - -/* cru_softrst_con12 */ -#define SRST_H_PERILP1 192 -#define SRST_H_PERILP1_NOC 193 -#define SRST_H_I2S0_8CH 194 -#define SRST_H_I2S1_8CH 195 -#define SRST_H_I2S2_8CH 196 -#define SRST_H_SPDIF_8CH 197 -#define SRST_P_PERILP1_NOC 198 -#define SRST_P_EFUSE_1024 199 -#define SRST_P_EFUSE_1024S 200 -#define SRST_P_I2C0 201 -#define SRST_P_I2C1 202 -#define SRST_P_I2C2 203 -#define SRST_P_I2C3 204 -#define SRST_P_I2C4 205 -#define SRST_P_I2C5 206 -#define SRST_P_MAILBOX0 207 - -/* cru_softrst_con13 */ -#define SRST_P_UART0 208 -#define SRST_P_UART1 209 -#define SRST_P_UART2 210 -#define SRST_P_UART3 211 -#define SRST_P_SARADC 212 -#define SRST_P_TSADC 213 -#define SRST_P_SPI0 214 -#define SRST_P_SPI1 215 -#define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 -#define SRST_SPI0 219 -#define SRST_SPI1 220 -#define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 - -/* cru_softrst_con14 */ -#define SRST_I2S0_8CH 224 -#define SRST_I2S1_8CH 225 -#define SRST_I2S2_8CH 226 -#define SRST_SPDIF_8CH 227 -#define SRST_UART0 228 -#define SRST_UART1 229 -#define SRST_UART2 230 -#define SRST_UART3 231 -#define SRST_TSADC 232 -#define SRST_I2C0 233 -#define SRST_I2C1 234 -#define SRST_I2C2 235 -#define SRST_I2C3 236 -#define SRST_I2C4 237 -#define SRST_I2C5 238 -#define SRST_SDIOAUDIO_NOC 239 - -/* cru_softrst_con15 */ -#define SRST_A_VIO_NOC 240 -#define SRST_A_HDCP_NOC 241 -#define SRST_A_HDCP 242 -#define SRST_H_HDCP_NOC 243 -#define SRST_H_HDCP 244 -#define SRST_P_HDCP_NOC 245 -#define SRST_P_HDCP 246 -#define SRST_P_HDMI_CTRL 247 -#define SRST_P_DP_CTRL 248 -#define SRST_S_DP_CTRL 249 -#define SRST_C_DP_CTRL 250 -#define SRST_P_MIPI_DSI0 251 -#define SRST_P_MIPI_DSI1 252 -#define SRST_DP_CORE 253 -#define SRST_DP_I2S 254 - -/* cru_softrst_con16 */ -#define SRST_GASKET 256 -#define SRST_VIO_GRF 258 -#define SRST_DPTX_SPDIF_REC 259 -#define SRST_HDMI_CTRL 260 -#define SRST_HDCP_CTRL 261 -#define SRST_A_ISP0_NOC 262 -#define SRST_A_ISP1_NOC 263 -#define SRST_H_ISP0_NOC 266 -#define SRST_H_ISP1_NOC 267 -#define SRST_H_ISP0 268 -#define SRST_H_ISP1 269 -#define SRST_ISP0 270 -#define SRST_ISP1 271 - -/* cru_softrst_con17 */ -#define SRST_A_VOP0_NOC 272 -#define SRST_A_VOP1_NOC 273 -#define SRST_A_VOP0 274 -#define SRST_A_VOP1 275 -#define SRST_H_VOP0_NOC 276 -#define SRST_H_VOP1_NOC 277 -#define SRST_H_VOP0 278 -#define SRST_H_VOP1 279 -#define SRST_D_VOP0 280 -#define SRST_D_VOP1 281 -#define SRST_VOP0_PWM 282 -#define SRST_VOP1_PWM 283 -#define SRST_P_EDP_NOC 284 -#define SRST_P_EDP_CTRL 285 - -/* cru_softrst_con18 */ -#define SRST_A_GPU 288 -#define SRST_A_GPU_NOC 289 -#define SRST_A_GPU_GRF 290 -#define SRST_PVTM_GPU 291 -#define SRST_A_USB3_NOC 292 -#define SRST_A_USB3_OTG0 293 -#define SRST_A_USB3_OTG1 294 -#define SRST_A_USB3_GRF 295 -#define SRST_PMU 296 - -/* cru_softrst_con19 */ -#define SRST_P_TIMER0_5 304 -#define SRST_TIMER0 305 -#define SRST_TIMER1 306 -#define SRST_TIMER2 307 -#define SRST_TIMER3 308 -#define SRST_TIMER4 309 -#define SRST_TIMER5 310 -#define SRST_P_TIMER6_11 311 -#define SRST_TIMER6 312 -#define SRST_TIMER7 313 -#define SRST_TIMER8 314 -#define SRST_TIMER9 315 -#define SRST_TIMER10 316 -#define SRST_TIMER11 317 -#define SRST_P_INTR_ARB_PMU 318 -#define SRST_P_ALIVE_SGRF 319 - -/* cru_softrst_con20 */ -#define SRST_P_GPIO2 320 -#define SRST_P_GPIO3 321 -#define SRST_P_GPIO4 322 -#define SRST_P_GRF 323 -#define SRST_P_ALIVE_NOC 324 -#define SRST_P_WDT0 325 -#define SRST_P_WDT1 326 -#define SRST_P_INTR_ARB 327 -#define SRST_P_UPHY0_DPTX 328 -#define SRST_P_UPHY0_APB 330 -#define SRST_P_UPHY0_TCPHY 332 -#define SRST_P_UPHY1_TCPHY 333 -#define SRST_P_UPHY0_TCPDCTRL 334 -#define SRST_P_UPHY1_TCPDCTRL 335 - -/* pmu soft-reset indices */ - -/* pmu_cru_softrst_con0 */ -#define SRST_P_NOC 0 -#define SRST_P_INTMEM 1 -#define SRST_H_CM0S 2 -#define SRST_H_CM0S_NOC 3 -#define SRST_DBG_CM0S 4 -#define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 -#define SRST_P_TIMER_0_1 8 -#define SRST_P_TIMER_0 9 -#define SRST_P_TIMER_1 10 -#define SRST_P_UART4 11 -#define SRST_UART4 12 -#define SRST_P_WDT 13 - -/* pmu_cru_softrst_con1 */ -#define SRST_P_I2C6 16 -#define SRST_P_I2C7 17 -#define SRST_P_I2C8 18 -#define SRST_P_MAILBOX 19 -#define SRST_P_RKPWM 20 -#define SRST_P_PMUGRF 21 -#define SRST_P_SGRF 22 -#define SRST_P_GPIO0 23 -#define SRST_P_GPIO1 24 -#define SRST_P_CRU 25 -#define SRST_P_INTR 26 -#define SRST_PVTM 27 -#define SRST_I2C6 28 -#define SRST_I2C7 29 -#define SRST_I2C8 30 - -#endif diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h deleted file mode 100644 index d29890865150..000000000000 --- a/include/dt-bindings/clock/rk3568-cru.h +++ /dev/null @@ -1,926 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang zhangqing@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H - -/* pmucru-clocks indices */ - -/* pmucru plls */ -#define PLL_PPLL 1 -#define PLL_HPLL 2 - -/* pmucru clocks */ -#define XIN_OSC0_DIV 4 -#define CLK_RTC_32K 5 -#define CLK_PMU 6 -#define CLK_I2C0 7 -#define CLK_RTC32K_FRAC 8 -#define CLK_UART0_DIV 9 -#define CLK_UART0_FRAC 10 -#define SCLK_UART0 11 -#define DBCLK_GPIO0 12 -#define CLK_PWM0 13 -#define CLK_CAPTURE_PWM0_NDFT 14 -#define CLK_PMUPVTM 15 -#define CLK_CORE_PMUPVTM 16 -#define CLK_REF24M 17 -#define XIN_OSC0_USBPHY0_G 18 -#define CLK_USBPHY0_REF 19 -#define XIN_OSC0_USBPHY1_G 20 -#define CLK_USBPHY1_REF 21 -#define XIN_OSC0_MIPIDSIPHY0_G 22 -#define CLK_MIPIDSIPHY0_REF 23 -#define XIN_OSC0_MIPIDSIPHY1_G 24 -#define CLK_MIPIDSIPHY1_REF 25 -#define CLK_WIFI_DIV 26 -#define CLK_WIFI_OSC0 27 -#define CLK_WIFI 28 -#define CLK_PCIEPHY0_DIV 29 -#define CLK_PCIEPHY0_OSC0 30 -#define CLK_PCIEPHY0_REF 31 -#define CLK_PCIEPHY1_DIV 32 -#define CLK_PCIEPHY1_OSC0 33 -#define CLK_PCIEPHY1_REF 34 -#define CLK_PCIEPHY2_DIV 35 -#define CLK_PCIEPHY2_OSC0 36 -#define CLK_PCIEPHY2_REF 37 -#define CLK_PCIE30PHY_REF_M 38 -#define CLK_PCIE30PHY_REF_N 39 -#define CLK_HDMI_REF 40 -#define XIN_OSC0_EDPPHY_G 41 -#define PCLK_PDPMU 42 -#define PCLK_PMU 43 -#define PCLK_UART0 44 -#define PCLK_I2C0 45 -#define PCLK_GPIO0 46 -#define PCLK_PMUPVTM 47 -#define PCLK_PWM0 48 -#define CLK_PDPMU 49 -#define SCLK_32K_IOE 50 - -#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) - -/* cru-clocks indices */ - -/* cru plls */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_VPLL 5 -#define PLL_NPLL 6 - -/* cru clocks */ -#define CPLL_333M 9 -#define ARMCLK 10 -#define USB480M 11 -#define ACLK_CORE_NIU2BUS 18 -#define CLK_CORE_PVTM 19 -#define CLK_CORE_PVTM_CORE 20 -#define CLK_CORE_PVTPLL 21 -#define CLK_GPU_SRC 22 -#define CLK_GPU_PRE_NDFT 23 -#define CLK_GPU_PRE_MUX 24 -#define ACLK_GPU_PRE 25 -#define PCLK_GPU_PRE 26 -#define CLK_GPU 27 -#define CLK_GPU_NP5 28 -#define PCLK_GPU_PVTM 29 -#define CLK_GPU_PVTM 30 -#define CLK_GPU_PVTM_CORE 31 -#define CLK_GPU_PVTPLL 32 -#define CLK_NPU_SRC 33 -#define CLK_NPU_PRE_NDFT 34 -#define CLK_NPU 35 -#define CLK_NPU_NP5 36 -#define HCLK_NPU_PRE 37 -#define PCLK_NPU_PRE 38 -#define ACLK_NPU_PRE 39 -#define ACLK_NPU 40 -#define HCLK_NPU 41 -#define PCLK_NPU_PVTM 42 -#define CLK_NPU_PVTM 43 -#define CLK_NPU_PVTM_CORE 44 -#define CLK_NPU_PVTPLL 45 -#define CLK_DDRPHY1X_SRC 46 -#define CLK_DDRPHY1X_HWFFC_SRC 47 -#define CLK_DDR1X 48 -#define CLK_MSCH 49 -#define CLK24_DDRMON 50 -#define ACLK_GIC_AUDIO 51 -#define HCLK_GIC_AUDIO 52 -#define HCLK_SDMMC_BUFFER 53 -#define DCLK_SDMMC_BUFFER 54 -#define ACLK_GIC600 55 -#define ACLK_SPINLOCK 56 -#define HCLK_I2S0_8CH 57 -#define HCLK_I2S1_8CH 58 -#define HCLK_I2S2_2CH 59 -#define HCLK_I2S3_2CH 60 -#define CLK_I2S0_8CH_TX_SRC 61 -#define CLK_I2S0_8CH_TX_FRAC 62 -#define MCLK_I2S0_8CH_TX 63 -#define I2S0_MCLKOUT_TX 64 -#define CLK_I2S0_8CH_RX_SRC 65 -#define CLK_I2S0_8CH_RX_FRAC 66 -#define MCLK_I2S0_8CH_RX 67 -#define I2S0_MCLKOUT_RX 68 -#define CLK_I2S1_8CH_TX_SRC 69 -#define CLK_I2S1_8CH_TX_FRAC 70 -#define MCLK_I2S1_8CH_TX 71 -#define I2S1_MCLKOUT_TX 72 -#define CLK_I2S1_8CH_RX_SRC 73 -#define CLK_I2S1_8CH_RX_FRAC 74 -#define MCLK_I2S1_8CH_RX 75 -#define I2S1_MCLKOUT_RX 76 -#define CLK_I2S2_2CH_SRC 77 -#define CLK_I2S2_2CH_FRAC 78 -#define MCLK_I2S2_2CH 79 -#define I2S2_MCLKOUT 80 -#define CLK_I2S3_2CH_TX_SRC 81 -#define CLK_I2S3_2CH_TX_FRAC 82 -#define MCLK_I2S3_2CH_TX 83 -#define I2S3_MCLKOUT_TX 84 -#define CLK_I2S3_2CH_RX_SRC 85 -#define CLK_I2S3_2CH_RX_FRAC 86 -#define MCLK_I2S3_2CH_RX 87 -#define I2S3_MCLKOUT_RX 88 -#define HCLK_PDM 89 -#define MCLK_PDM 90 -#define HCLK_VAD 91 -#define HCLK_SPDIF_8CH 92 -#define MCLK_SPDIF_8CH_SRC 93 -#define MCLK_SPDIF_8CH_FRAC 94 -#define MCLK_SPDIF_8CH 95 -#define HCLK_AUDPWM 96 -#define SCLK_AUDPWM_SRC 97 -#define SCLK_AUDPWM_FRAC 98 -#define SCLK_AUDPWM 99 -#define HCLK_ACDCDIG 100 -#define CLK_ACDCDIG_I2C 101 -#define CLK_ACDCDIG_DAC 102 -#define CLK_ACDCDIG_ADC 103 -#define ACLK_SECURE_FLASH 104 -#define HCLK_SECURE_FLASH 105 -#define ACLK_CRYPTO_NS 106 -#define HCLK_CRYPTO_NS 107 -#define CLK_CRYPTO_NS_CORE 108 -#define CLK_CRYPTO_NS_PKA 109 -#define CLK_CRYPTO_NS_RNG 110 -#define HCLK_TRNG_NS 111 -#define CLK_TRNG_NS 112 -#define PCLK_OTPC_NS 113 -#define CLK_OTPC_NS_SBPI 114 -#define CLK_OTPC_NS_USR 115 -#define HCLK_NANDC 116 -#define NCLK_NANDC 117 -#define HCLK_SFC 118 -#define HCLK_SFC_XIP 119 -#define SCLK_SFC 120 -#define ACLK_EMMC 121 -#define HCLK_EMMC 122 -#define BCLK_EMMC 123 -#define CCLK_EMMC 124 -#define TCLK_EMMC 125 -#define ACLK_PIPE 126 -#define PCLK_PIPE 127 -#define PCLK_PIPE_GRF 128 -#define ACLK_PCIE20_MST 129 -#define ACLK_PCIE20_SLV 130 -#define ACLK_PCIE20_DBI 131 -#define PCLK_PCIE20 132 -#define CLK_PCIE20_AUX_NDFT 133 -#define CLK_PCIE20_AUX_DFT 134 -#define CLK_PCIE20_PIPE_DFT 135 -#define ACLK_PCIE30X1_MST 136 -#define ACLK_PCIE30X1_SLV 137 -#define ACLK_PCIE30X1_DBI 138 -#define PCLK_PCIE30X1 139 -#define CLK_PCIE30X1_AUX_NDFT 140 -#define CLK_PCIE30X1_AUX_DFT 141 -#define CLK_PCIE30X1_PIPE_DFT 142 -#define ACLK_PCIE30X2_MST 143 -#define ACLK_PCIE30X2_SLV 144 -#define ACLK_PCIE30X2_DBI 145 -#define PCLK_PCIE30X2 146 -#define CLK_PCIE30X2_AUX_NDFT 147 -#define CLK_PCIE30X2_AUX_DFT 148 -#define CLK_PCIE30X2_PIPE_DFT 149 -#define ACLK_SATA0 150 -#define CLK_SATA0_PMALIVE 151 -#define CLK_SATA0_RXOOB 152 -#define CLK_SATA0_PIPE_NDFT 153 -#define CLK_SATA0_PIPE_DFT 154 -#define ACLK_SATA1 155 -#define CLK_SATA1_PMALIVE 156 -#define CLK_SATA1_RXOOB 157 -#define CLK_SATA1_PIPE_NDFT 158 -#define CLK_SATA1_PIPE_DFT 159 -#define ACLK_SATA2 160 -#define CLK_SATA2_PMALIVE 161 -#define CLK_SATA2_RXOOB 162 -#define CLK_SATA2_PIPE_NDFT 163 -#define CLK_SATA2_PIPE_DFT 164 -#define ACLK_USB3OTG0 165 -#define CLK_USB3OTG0_REF 166 -#define CLK_USB3OTG0_SUSPEND 167 -#define ACLK_USB3OTG1 168 -#define CLK_USB3OTG1_REF 169 -#define CLK_USB3OTG1_SUSPEND 170 -#define CLK_XPCS_EEE 171 -#define PCLK_XPCS 172 -#define ACLK_PHP 173 -#define HCLK_PHP 174 -#define PCLK_PHP 175 -#define HCLK_SDMMC0 176 -#define CLK_SDMMC0 177 -#define HCLK_SDMMC1 178 -#define CLK_SDMMC1 179 -#define ACLK_GMAC0 180 -#define PCLK_GMAC0 181 -#define CLK_MAC0_2TOP 182 -#define CLK_MAC0_OUT 183 -#define CLK_MAC0_REFOUT 184 -#define CLK_GMAC0_PTP_REF 185 -#define ACLK_USB 186 -#define HCLK_USB 187 -#define PCLK_USB 188 -#define HCLK_USB2HOST0 189 -#define HCLK_USB2HOST0_ARB 190 -#define HCLK_USB2HOST1 191 -#define HCLK_USB2HOST1_ARB 192 -#define HCLK_SDMMC2 193 -#define CLK_SDMMC2 194 -#define ACLK_GMAC1 195 -#define PCLK_GMAC1 196 -#define CLK_MAC1_2TOP 197 -#define CLK_MAC1_OUT 198 -#define CLK_MAC1_REFOUT 199 -#define CLK_GMAC1_PTP_REF 200 -#define ACLK_PERIMID 201 -#define HCLK_PERIMID 202 -#define ACLK_VI 203 -#define HCLK_VI 204 -#define PCLK_VI 205 -#define ACLK_VICAP 206 -#define HCLK_VICAP 207 -#define DCLK_VICAP 208 -#define ICLK_VICAP_G 209 -#define ACLK_ISP 210 -#define HCLK_ISP 211 -#define CLK_ISP 212 -#define PCLK_CSI2HOST1 213 -#define CLK_CIF_OUT 214 -#define CLK_CAM0_OUT 215 -#define CLK_CAM1_OUT 216 -#define ACLK_VO 217 -#define HCLK_VO 218 -#define PCLK_VO 219 -#define ACLK_VOP_PRE 220 -#define ACLK_VOP 221 -#define HCLK_VOP 222 -#define DCLK_VOP0 223 -#define DCLK_VOP1 224 -#define DCLK_VOP2 225 -#define CLK_VOP_PWM 226 -#define ACLK_HDCP 227 -#define HCLK_HDCP 228 -#define PCLK_HDCP 229 -#define PCLK_HDMI_HOST 230 -#define CLK_HDMI_SFR 231 -#define PCLK_DSITX_0 232 -#define PCLK_DSITX_1 233 -#define PCLK_EDP_CTRL 234 -#define CLK_EDP_200M 235 -#define ACLK_VPU_PRE 236 -#define HCLK_VPU_PRE 237 -#define ACLK_VPU 238 -#define HCLK_VPU 239 -#define ACLK_RGA_PRE 240 -#define HCLK_RGA_PRE 241 -#define PCLK_RGA_PRE 242 -#define ACLK_RGA 243 -#define HCLK_RGA 244 -#define CLK_RGA_CORE 245 -#define ACLK_IEP 246 -#define HCLK_IEP 247 -#define CLK_IEP_CORE 248 -#define HCLK_EBC 249 -#define DCLK_EBC 250 -#define ACLK_JDEC 251 -#define HCLK_JDEC 252 -#define ACLK_JENC 253 -#define HCLK_JENC 254 -#define PCLK_EINK 255 -#define HCLK_EINK 256 -#define ACLK_RKVENC_PRE 257 -#define HCLK_RKVENC_PRE 258 -#define ACLK_RKVENC 259 -#define HCLK_RKVENC 260 -#define CLK_RKVENC_CORE 261 -#define ACLK_RKVDEC_PRE 262 -#define HCLK_RKVDEC_PRE 263 -#define ACLK_RKVDEC 264 -#define HCLK_RKVDEC 265 -#define CLK_RKVDEC_CA 266 -#define CLK_RKVDEC_CORE 267 -#define CLK_RKVDEC_HEVC_CA 268 -#define ACLK_BUS 269 -#define PCLK_BUS 270 -#define PCLK_TSADC 271 -#define CLK_TSADC_TSEN 272 -#define CLK_TSADC 273 -#define PCLK_SARADC 274 -#define CLK_SARADC 275 -#define PCLK_SCR 276 -#define PCLK_WDT_NS 277 -#define TCLK_WDT_NS 278 -#define ACLK_DMAC0 279 -#define ACLK_DMAC1 280 -#define ACLK_MCU 281 -#define PCLK_INTMUX 282 -#define PCLK_MAILBOX 283 -#define PCLK_UART1 284 -#define CLK_UART1_SRC 285 -#define CLK_UART1_FRAC 286 -#define SCLK_UART1 287 -#define PCLK_UART2 288 -#define CLK_UART2_SRC 289 -#define CLK_UART2_FRAC 290 -#define SCLK_UART2 291 -#define PCLK_UART3 292 -#define CLK_UART3_SRC 293 -#define CLK_UART3_FRAC 294 -#define SCLK_UART3 295 -#define PCLK_UART4 296 -#define CLK_UART4_SRC 297 -#define CLK_UART4_FRAC 298 -#define SCLK_UART4 299 -#define PCLK_UART5 300 -#define CLK_UART5_SRC 301 -#define CLK_UART5_FRAC 302 -#define SCLK_UART5 303 -#define PCLK_UART6 304 -#define CLK_UART6_SRC 305 -#define CLK_UART6_FRAC 306 -#define SCLK_UART6 307 -#define PCLK_UART7 308 -#define CLK_UART7_SRC 309 -#define CLK_UART7_FRAC 310 -#define SCLK_UART7 311 -#define PCLK_UART8 312 -#define CLK_UART8_SRC 313 -#define CLK_UART8_FRAC 314 -#define SCLK_UART8 315 -#define PCLK_UART9 316 -#define CLK_UART9_SRC 317 -#define CLK_UART9_FRAC 318 -#define SCLK_UART9 319 -#define PCLK_CAN0 320 -#define CLK_CAN0 321 -#define PCLK_CAN1 322 -#define CLK_CAN1 323 -#define PCLK_CAN2 324 -#define CLK_CAN2 325 -#define CLK_I2C 326 -#define PCLK_I2C1 327 -#define CLK_I2C1 328 -#define PCLK_I2C2 329 -#define CLK_I2C2 330 -#define PCLK_I2C3 331 -#define CLK_I2C3 332 -#define PCLK_I2C4 333 -#define CLK_I2C4 334 -#define PCLK_I2C5 335 -#define CLK_I2C5 336 -#define PCLK_SPI0 337 -#define CLK_SPI0 338 -#define PCLK_SPI1 339 -#define CLK_SPI1 340 -#define PCLK_SPI2 341 -#define CLK_SPI2 342 -#define PCLK_SPI3 343 -#define CLK_SPI3 344 -#define PCLK_PWM1 345 -#define CLK_PWM1 346 -#define CLK_PWM1_CAPTURE 347 -#define PCLK_PWM2 348 -#define CLK_PWM2 349 -#define CLK_PWM2_CAPTURE 350 -#define PCLK_PWM3 351 -#define CLK_PWM3 352 -#define CLK_PWM3_CAPTURE 353 -#define DBCLK_GPIO 354 -#define PCLK_GPIO1 355 -#define DBCLK_GPIO1 356 -#define PCLK_GPIO2 357 -#define DBCLK_GPIO2 358 -#define PCLK_GPIO3 359 -#define DBCLK_GPIO3 360 -#define PCLK_GPIO4 361 -#define DBCLK_GPIO4 362 -#define OCC_SCAN_CLK_GPIO 363 -#define PCLK_TIMER 364 -#define CLK_TIMER0 365 -#define CLK_TIMER1 366 -#define CLK_TIMER2 367 -#define CLK_TIMER3 368 -#define CLK_TIMER4 369 -#define CLK_TIMER5 370 -#define ACLK_TOP_HIGH 371 -#define ACLK_TOP_LOW 372 -#define HCLK_TOP 373 -#define PCLK_TOP 374 -#define PCLK_PCIE30PHY 375 -#define CLK_OPTC_ARB 376 -#define PCLK_MIPICSIPHY 377 -#define PCLK_MIPIDSIPHY0 378 -#define PCLK_MIPIDSIPHY1 379 -#define PCLK_PIPEPHY0 380 -#define PCLK_PIPEPHY1 381 -#define PCLK_PIPEPHY2 382 -#define PCLK_CPU_BOOST 383 -#define CLK_CPU_BOOST 384 -#define PCLK_OTPPHY 385 -#define SCLK_GMAC0 386 -#define SCLK_GMAC0_RGMII_SPEED 387 -#define SCLK_GMAC0_RMII_SPEED 388 -#define SCLK_GMAC0_RX_TX 389 -#define SCLK_GMAC1 390 -#define SCLK_GMAC1_RGMII_SPEED 391 -#define SCLK_GMAC1_RMII_SPEED 392 -#define SCLK_GMAC1_RX_TX 393 -#define SCLK_SDMMC0_DRV 394 -#define SCLK_SDMMC0_SAMPLE 395 -#define SCLK_SDMMC1_DRV 396 -#define SCLK_SDMMC1_SAMPLE 397 -#define SCLK_SDMMC2_DRV 398 -#define SCLK_SDMMC2_SAMPLE 399 -#define SCLK_EMMC_DRV 400 -#define SCLK_EMMC_SAMPLE 401 -#define PCLK_EDPPHY_GRF 402 -#define CLK_HDMI_CEC 403 -#define CLK_I2S0_8CH_TX 404 -#define CLK_I2S0_8CH_RX 405 -#define CLK_I2S1_8CH_TX 406 -#define CLK_I2S1_8CH_RX 407 -#define CLK_I2S2_2CH 408 -#define CLK_I2S3_2CH_TX 409 -#define CLK_I2S3_2CH_RX 410 -#define CPLL_500M 411 -#define CPLL_250M 412 -#define CPLL_125M 413 -#define CPLL_62P5M 414 -#define CPLL_50M 415 -#define CPLL_25M 416 -#define CPLL_100M 417 -#define SCLK_DDRCLK 418 - -#define PCLK_CORE_PVTM 450 - -#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) - -/* pmu soft-reset indices */ -/* pmucru_softrst_con0 */ -#define SRST_P_PDPMU_NIU 0 -#define SRST_P_PMUCRU 1 -#define SRST_P_PMUGRF 2 -#define SRST_P_I2C0 3 -#define SRST_I2C0 4 -#define SRST_P_UART0 5 -#define SRST_S_UART0 6 -#define SRST_P_PWM0 7 -#define SRST_PWM0 8 -#define SRST_P_GPIO0 9 -#define SRST_GPIO0 10 -#define SRST_P_PMUPVTM 11 -#define SRST_PMUPVTM 12 - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_NCORERESET0 0 -#define SRST_NCORERESET1 1 -#define SRST_NCORERESET2 2 -#define SRST_NCORERESET3 3 -#define SRST_NCPUPORESET0 4 -#define SRST_NCPUPORESET1 5 -#define SRST_NCPUPORESET2 6 -#define SRST_NCPUPORESET3 7 -#define SRST_NSRESET 8 -#define SRST_NSPORESET 9 -#define SRST_NATRESET 10 -#define SRST_NGICRESET 11 -#define SRST_NPRESET 12 -#define SRST_NPERIPHRESET 13 - -/* cru_softrst_con1 */ -#define SRST_A_CORE_NIU2DDR 16 -#define SRST_A_CORE_NIU2BUS 17 -#define SRST_P_DBG_NIU 18 -#define SRST_P_DBG 19 -#define SRST_P_DBG_DAPLITE 20 -#define SRST_DAP 21 -#define SRST_A_ADB400_CORE2GIC 22 -#define SRST_A_ADB400_GIC2CORE 23 -#define SRST_P_CORE_GRF 24 -#define SRST_P_CORE_PVTM 25 -#define SRST_CORE_PVTM 26 -#define SRST_CORE_PVTPLL 27 - -/* cru_softrst_con2 */ -#define SRST_GPU 32 -#define SRST_A_GPU_NIU 33 -#define SRST_P_GPU_NIU 34 -#define SRST_P_GPU_PVTM 35 -#define SRST_GPU_PVTM 36 -#define SRST_GPU_PVTPLL 37 -#define SRST_A_NPU_NIU 40 -#define SRST_H_NPU_NIU 41 -#define SRST_P_NPU_NIU 42 -#define SRST_A_NPU 43 -#define SRST_H_NPU 44 -#define SRST_P_NPU_PVTM 45 -#define SRST_NPU_PVTM 46 -#define SRST_NPU_PVTPLL 47 - -/* cru_softrst_con3 */ -#define SRST_A_MSCH 51 -#define SRST_HWFFC_CTRL 52 -#define SRST_DDR_ALWAYSON 53 -#define SRST_A_DDRSPLIT 54 -#define SRST_DDRDFI_CTL 55 -#define SRST_A_DMA2DDR 57 - -/* cru_softrst_con4 */ -#define SRST_A_PERIMID_NIU 64 -#define SRST_H_PERIMID_NIU 65 -#define SRST_A_GIC_AUDIO_NIU 66 -#define SRST_H_GIC_AUDIO_NIU 67 -#define SRST_A_GIC600 68 -#define SRST_A_GIC600_DEBUG 69 -#define SRST_A_GICADB_CORE2GIC 70 -#define SRST_A_GICADB_GIC2CORE 71 -#define SRST_A_SPINLOCK 72 -#define SRST_H_SDMMC_BUFFER 73 -#define SRST_D_SDMMC_BUFFER 74 -#define SRST_H_I2S0_8CH 75 -#define SRST_H_I2S1_8CH 76 -#define SRST_H_I2S2_2CH 77 -#define SRST_H_I2S3_2CH 78 - -/* cru_softrst_con5 */ -#define SRST_M_I2S0_8CH_TX 80 -#define SRST_M_I2S0_8CH_RX 81 -#define SRST_M_I2S1_8CH_TX 82 -#define SRST_M_I2S1_8CH_RX 83 -#define SRST_M_I2S2_2CH 84 -#define SRST_M_I2S3_2CH_TX 85 -#define SRST_M_I2S3_2CH_RX 86 -#define SRST_H_PDM 87 -#define SRST_M_PDM 88 -#define SRST_H_VAD 89 -#define SRST_H_SPDIF_8CH 90 -#define SRST_M_SPDIF_8CH 91 -#define SRST_H_AUDPWM 92 -#define SRST_S_AUDPWM 93 -#define SRST_H_ACDCDIG 94 -#define SRST_ACDCDIG 95 - -/* cru_softrst_con6 */ -#define SRST_A_SECURE_FLASH_NIU 96 -#define SRST_H_SECURE_FLASH_NIU 97 -#define SRST_A_CRYPTO_NS 103 -#define SRST_H_CRYPTO_NS 104 -#define SRST_CRYPTO_NS_CORE 105 -#define SRST_CRYPTO_NS_PKA 106 -#define SRST_CRYPTO_NS_RNG 107 -#define SRST_H_TRNG_NS 108 -#define SRST_TRNG_NS 109 - -/* cru_softrst_con7 */ -#define SRST_H_NANDC 112 -#define SRST_N_NANDC 113 -#define SRST_H_SFC 114 -#define SRST_H_SFC_XIP 115 -#define SRST_S_SFC 116 -#define SRST_A_EMMC 117 -#define SRST_H_EMMC 118 -#define SRST_B_EMMC 119 -#define SRST_C_EMMC 120 -#define SRST_T_EMMC 121 - -/* cru_softrst_con8 */ -#define SRST_A_PIPE_NIU 128 -#define SRST_P_PIPE_NIU 130 -#define SRST_P_PIPE_GRF 133 -#define SRST_A_SATA0 134 -#define SRST_SATA0_PIPE 135 -#define SRST_SATA0_PMALIVE 136 -#define SRST_SATA0_RXOOB 137 -#define SRST_A_SATA1 138 -#define SRST_SATA1_PIPE 139 -#define SRST_SATA1_PMALIVE 140 -#define SRST_SATA1_RXOOB 141 - -/* cru_softrst_con9 */ -#define SRST_A_SATA2 144 -#define SRST_SATA2_PIPE 145 -#define SRST_SATA2_PMALIVE 146 -#define SRST_SATA2_RXOOB 147 -#define SRST_USB3OTG0 148 -#define SRST_USB3OTG1 149 -#define SRST_XPCS 150 -#define SRST_XPCS_TX_DIV10 151 -#define SRST_XPCS_RX_DIV10 152 -#define SRST_XPCS_XGXS_RX 153 - -/* cru_softrst_con10 */ -#define SRST_P_PCIE20 160 -#define SRST_PCIE20_POWERUP 161 -#define SRST_MSTR_ARESET_PCIE20 162 -#define SRST_SLV_ARESET_PCIE20 163 -#define SRST_DBI_ARESET_PCIE20 164 -#define SRST_BRESET_PCIE20 165 -#define SRST_PERST_PCIE20 166 -#define SRST_CORE_RST_PCIE20 167 -#define SRST_NSTICKY_RST_PCIE20 168 -#define SRST_STICKY_RST_PCIE20 169 -#define SRST_PWR_RST_PCIE20 170 - -/* cru_softrst_con11 */ -#define SRST_P_PCIE30X1 176 -#define SRST_PCIE30X1_POWERUP 177 -#define SRST_M_ARESET_PCIE30X1 178 -#define SRST_S_ARESET_PCIE30X1 179 -#define SRST_D_ARESET_PCIE30X1 180 -#define SRST_BRESET_PCIE30X1 181 -#define SRST_PERST_PCIE30X1 182 -#define SRST_CORE_RST_PCIE30X1 183 -#define SRST_NSTC_RST_PCIE30X1 184 -#define SRST_STC_RST_PCIE30X1 185 -#define SRST_PWR_RST_PCIE30X1 186 - -/* cru_softrst_con12 */ -#define SRST_P_PCIE30X2 192 -#define SRST_PCIE30X2_POWERUP 193 -#define SRST_M_ARESET_PCIE30X2 194 -#define SRST_S_ARESET_PCIE30X2 195 -#define SRST_D_ARESET_PCIE30X2 196 -#define SRST_BRESET_PCIE30X2 197 -#define SRST_PERST_PCIE30X2 198 -#define SRST_CORE_RST_PCIE30X2 199 -#define SRST_NSTC_RST_PCIE30X2 200 -#define SRST_STC_RST_PCIE30X2 201 -#define SRST_PWR_RST_PCIE30X2 202 - -/* cru_softrst_con13 */ -#define SRST_A_PHP_NIU 208 -#define SRST_H_PHP_NIU 209 -#define SRST_P_PHP_NIU 210 -#define SRST_H_SDMMC0 211 -#define SRST_SDMMC0 212 -#define SRST_H_SDMMC1 213 -#define SRST_SDMMC1 214 -#define SRST_A_GMAC0 215 -#define SRST_GMAC0_TIMESTAMP 216 - -/* cru_softrst_con14 */ -#define SRST_A_USB_NIU 224 -#define SRST_H_USB_NIU 225 -#define SRST_P_USB_NIU 226 -#define SRST_P_USB_GRF 227 -#define SRST_H_USB2HOST0 228 -#define SRST_H_USB2HOST0_ARB 229 -#define SRST_USB2HOST0_UTMI 230 -#define SRST_H_USB2HOST1 231 -#define SRST_H_USB2HOST1_ARB 232 -#define SRST_USB2HOST1_UTMI 233 -#define SRST_H_SDMMC2 234 -#define SRST_SDMMC2 235 -#define SRST_A_GMAC1 236 -#define SRST_GMAC1_TIMESTAMP 237 - -/* cru_softrst_con15 */ -#define SRST_A_VI_NIU 240 -#define SRST_H_VI_NIU 241 -#define SRST_P_VI_NIU 242 -#define SRST_A_VICAP 247 -#define SRST_H_VICAP 248 -#define SRST_D_VICAP 249 -#define SRST_I_VICAP 250 -#define SRST_P_VICAP 251 -#define SRST_H_ISP 252 -#define SRST_ISP 253 -#define SRST_P_CSI2HOST1 255 - -/* cru_softrst_con16 */ -#define SRST_A_VO_NIU 256 -#define SRST_H_VO_NIU 257 -#define SRST_P_VO_NIU 258 -#define SRST_A_VOP_NIU 259 -#define SRST_A_VOP 260 -#define SRST_H_VOP 261 -#define SRST_VOP0 262 -#define SRST_VOP1 263 -#define SRST_VOP2 264 -#define SRST_VOP_PWM 265 -#define SRST_A_HDCP 266 -#define SRST_H_HDCP 267 -#define SRST_P_HDCP 268 -#define SRST_P_HDMI_HOST 270 -#define SRST_HDMI_HOST 271 - -/* cru_softrst_con17 */ -#define SRST_P_DSITX_0 272 -#define SRST_P_DSITX_1 273 -#define SRST_P_EDP_CTRL 274 -#define SRST_EDP_24M 275 -#define SRST_A_VPU_NIU 280 -#define SRST_H_VPU_NIU 281 -#define SRST_A_VPU 282 -#define SRST_H_VPU 283 -#define SRST_H_EINK 286 -#define SRST_P_EINK 287 - -/* cru_softrst_con18 */ -#define SRST_A_RGA_NIU 288 -#define SRST_H_RGA_NIU 289 -#define SRST_P_RGA_NIU 290 -#define SRST_A_RGA 292 -#define SRST_H_RGA 293 -#define SRST_RGA_CORE 294 -#define SRST_A_IEP 295 -#define SRST_H_IEP 296 -#define SRST_IEP_CORE 297 -#define SRST_H_EBC 298 -#define SRST_D_EBC 299 -#define SRST_A_JDEC 300 -#define SRST_H_JDEC 301 -#define SRST_A_JENC 302 -#define SRST_H_JENC 303 - -/* cru_softrst_con19 */ -#define SRST_A_VENC_NIU 304 -#define SRST_H_VENC_NIU 305 -#define SRST_A_RKVENC 307 -#define SRST_H_RKVENC 308 -#define SRST_RKVENC_CORE 309 - -/* cru_softrst_con20 */ -#define SRST_A_RKVDEC_NIU 320 -#define SRST_H_RKVDEC_NIU 321 -#define SRST_A_RKVDEC 322 -#define SRST_H_RKVDEC 323 -#define SRST_RKVDEC_CA 324 -#define SRST_RKVDEC_CORE 325 -#define SRST_RKVDEC_HEVC_CA 326 - -/* cru_softrst_con21 */ -#define SRST_A_BUS_NIU 336 -#define SRST_P_BUS_NIU 338 -#define SRST_P_CAN0 340 -#define SRST_CAN0 341 -#define SRST_P_CAN1 342 -#define SRST_CAN1 343 -#define SRST_P_CAN2 344 -#define SRST_CAN2 345 -#define SRST_P_GPIO1 346 -#define SRST_GPIO1 347 -#define SRST_P_GPIO2 348 -#define SRST_GPIO2 349 -#define SRST_P_GPIO3 350 -#define SRST_GPIO3 351 - -/* cru_softrst_con22 */ -#define SRST_P_GPIO4 352 -#define SRST_GPIO4 353 -#define SRST_P_I2C1 354 -#define SRST_I2C1 355 -#define SRST_P_I2C2 356 -#define SRST_I2C2 357 -#define SRST_P_I2C3 358 -#define SRST_I2C3 359 -#define SRST_P_I2C4 360 -#define SRST_I2C4 361 -#define SRST_P_I2C5 362 -#define SRST_I2C5 363 -#define SRST_P_OTPC_NS 364 -#define SRST_OTPC_NS_SBPI 365 -#define SRST_OTPC_NS_USR 366 - -/* cru_softrst_con23 */ -#define SRST_P_PWM1 368 -#define SRST_PWM1 369 -#define SRST_P_PWM2 370 -#define SRST_PWM2 371 -#define SRST_P_PWM3 372 -#define SRST_PWM3 373 -#define SRST_P_SPI0 374 -#define SRST_SPI0 375 -#define SRST_P_SPI1 376 -#define SRST_SPI1 377 -#define SRST_P_SPI2 378 -#define SRST_SPI2 379 -#define SRST_P_SPI3 380 -#define SRST_SPI3 381 - -/* cru_softrst_con24 */ -#define SRST_P_SARADC 384 -#define SRST_P_TSADC 385 -#define SRST_TSADC 386 -#define SRST_P_TIMER 387 -#define SRST_TIMER0 388 -#define SRST_TIMER1 389 -#define SRST_TIMER2 390 -#define SRST_TIMER3 391 -#define SRST_TIMER4 392 -#define SRST_TIMER5 393 -#define SRST_P_UART1 394 -#define SRST_S_UART1 395 - -/* cru_softrst_con25 */ -#define SRST_P_UART2 400 -#define SRST_S_UART2 401 -#define SRST_P_UART3 402 -#define SRST_S_UART3 403 -#define SRST_P_UART4 404 -#define SRST_S_UART4 405 -#define SRST_P_UART5 406 -#define SRST_S_UART5 407 -#define SRST_P_UART6 408 -#define SRST_S_UART6 409 -#define SRST_P_UART7 410 -#define SRST_S_UART7 411 -#define SRST_P_UART8 412 -#define SRST_S_UART8 413 -#define SRST_P_UART9 414 -#define SRST_S_UART9 415 - -/* cru_softrst_con26 */ -#define SRST_P_GRF 416 -#define SRST_P_GRF_VCCIO12 417 -#define SRST_P_GRF_VCCIO34 418 -#define SRST_P_GRF_VCCIO567 419 -#define SRST_P_SCR 420 -#define SRST_P_WDT_NS 421 -#define SRST_T_WDT_NS 422 -#define SRST_P_DFT2APB 423 -#define SRST_A_MCU 426 -#define SRST_P_INTMUX 427 -#define SRST_P_MAILBOX 428 - -/* cru_softrst_con27 */ -#define SRST_A_TOP_HIGH_NIU 432 -#define SRST_A_TOP_LOW_NIU 433 -#define SRST_H_TOP_NIU 434 -#define SRST_P_TOP_NIU 435 -#define SRST_P_TOP_CRU 438 -#define SRST_P_DDRPHY 439 -#define SRST_DDRPHY 440 -#define SRST_P_MIPICSIPHY 442 -#define SRST_P_MIPIDSIPHY0 443 -#define SRST_P_MIPIDSIPHY1 444 -#define SRST_P_PCIE30PHY 445 -#define SRST_PCIE30PHY 446 -#define SRST_P_PCIE30PHY_GRF 447 - -/* cru_softrst_con28 */ -#define SRST_P_APB2ASB_LEFT 448 -#define SRST_P_APB2ASB_BOTTOM 449 -#define SRST_P_ASB2APB_LEFT 450 -#define SRST_P_ASB2APB_BOTTOM 451 -#define SRST_P_PIPEPHY0 452 -#define SRST_PIPEPHY0 453 -#define SRST_P_PIPEPHY1 454 -#define SRST_PIPEPHY1 455 -#define SRST_P_PIPEPHY2 456 -#define SRST_PIPEPHY2 457 -#define SRST_P_USB2PHY0_GRF 458 -#define SRST_P_USB2PHY1_GRF 459 -#define SRST_P_CPU_BOOST 460 -#define SRST_CPU_BOOST 461 -#define SRST_P_OTPPHY 462 -#define SRST_OTPPHY 463 - -/* cru_softrst_con29 */ -#define SRST_USB2PHY0_POR 464 -#define SRST_USB2PHY0_USB3OTG0 465 -#define SRST_USB2PHY0_USB3OTG1 466 -#define SRST_USB2PHY1_POR 467 -#define SRST_USB2PHY1_USB2HOST0 468 -#define SRST_USB2PHY1_USB2HOST1 469 -#define SRST_P_EDPPHY_GRF 470 -#define SRST_TSADCPHY 471 -#define SRST_GMAC0_DELAYLINE 472 -#define SRST_GMAC1_DELAYLINE 473 -#define SRST_OTPC_ARB 474 -#define SRST_P_PIPEPHY0_GRF 475 -#define SRST_P_PIPEPHY1_GRF 476 -#define SRST_P_PIPEPHY2_GRF 477 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h deleted file mode 100644 index b5616bca7b44..000000000000 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ /dev/null @@ -1,766 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang zhangqing@rock-chips.com - * Author: Sebastian Reichel sebastian.reichel@collabora.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H - -/* cru-clocks indices */ - -#define PLL_B0PLL 0 -#define PLL_B1PLL 1 -#define PLL_LPLL 2 -#define PLL_V0PLL 3 -#define PLL_AUPLL 4 -#define PLL_CPLL 5 -#define PLL_GPLL 6 -#define PLL_NPLL 7 -#define PLL_PPLL 8 -#define ARMCLK_L 9 -#define ARMCLK_B01 10 -#define ARMCLK_B23 11 -#define PCLK_BIGCORE0_ROOT 12 -#define PCLK_BIGCORE0_PVTM 13 -#define PCLK_BIGCORE1_ROOT 14 -#define PCLK_BIGCORE1_PVTM 15 -#define PCLK_DSU_S_ROOT 16 -#define PCLK_DSU_ROOT 17 -#define PCLK_DSU_NS_ROOT 18 -#define PCLK_LITCORE_PVTM 19 -#define PCLK_DBG 20 -#define PCLK_DSU 21 -#define PCLK_S_DAPLITE 22 -#define PCLK_M_DAPLITE 23 -#define MBIST_MCLK_PDM1 24 -#define MBIST_CLK_ACDCDIG 25 -#define HCLK_I2S2_2CH 26 -#define HCLK_I2S3_2CH 27 -#define CLK_I2S2_2CH_SRC 28 -#define CLK_I2S2_2CH_FRAC 29 -#define CLK_I2S2_2CH 30 -#define MCLK_I2S2_2CH 31 -#define I2S2_2CH_MCLKOUT 32 -#define CLK_DAC_ACDCDIG 33 -#define CLK_I2S3_2CH_SRC 34 -#define CLK_I2S3_2CH_FRAC 35 -#define CLK_I2S3_2CH 36 -#define MCLK_I2S3_2CH 37 -#define I2S3_2CH_MCLKOUT 38 -#define PCLK_ACDCDIG 39 -#define HCLK_I2S0_8CH 40 -#define CLK_I2S0_8CH_TX_SRC 41 -#define CLK_I2S0_8CH_TX_FRAC 42 -#define MCLK_I2S0_8CH_TX 43 -#define CLK_I2S0_8CH_TX 44 -#define CLK_I2S0_8CH_RX_SRC 45 -#define CLK_I2S0_8CH_RX_FRAC 46 -#define MCLK_I2S0_8CH_RX 47 -#define CLK_I2S0_8CH_RX 48 -#define I2S0_8CH_MCLKOUT 49 -#define HCLK_PDM1 50 -#define MCLK_PDM1 51 -#define HCLK_AUDIO_ROOT 52 -#define PCLK_AUDIO_ROOT 53 -#define HCLK_SPDIF0 54 -#define CLK_SPDIF0_SRC 55 -#define CLK_SPDIF0_FRAC 56 -#define MCLK_SPDIF0 57 -#define CLK_SPDIF0 58 -#define CLK_SPDIF1 59 -#define HCLK_SPDIF1 60 -#define CLK_SPDIF1_SRC 61 -#define CLK_SPDIF1_FRAC 62 -#define MCLK_SPDIF1 63 -#define ACLK_AV1_ROOT 64 -#define ACLK_AV1 65 -#define PCLK_AV1_ROOT 66 -#define PCLK_AV1 67 -#define PCLK_MAILBOX0 68 -#define PCLK_MAILBOX1 69 -#define PCLK_MAILBOX2 70 -#define PCLK_PMU2 71 -#define PCLK_PMUCM0_INTMUX 72 -#define PCLK_DDRCM0_INTMUX 73 -#define PCLK_TOP 74 -#define PCLK_PWM1 75 -#define CLK_PWM1 76 -#define CLK_PWM1_CAPTURE 77 -#define PCLK_PWM2 78 -#define CLK_PWM2 79 -#define CLK_PWM2_CAPTURE 80 -#define PCLK_PWM3 81 -#define CLK_PWM3 82 -#define CLK_PWM3_CAPTURE 83 -#define PCLK_BUSTIMER0 84 -#define PCLK_BUSTIMER1 85 -#define CLK_BUS_TIMER_ROOT 86 -#define CLK_BUSTIMER0 87 -#define CLK_BUSTIMER1 88 -#define CLK_BUSTIMER2 89 -#define CLK_BUSTIMER3 90 -#define CLK_BUSTIMER4 91 -#define CLK_BUSTIMER5 92 -#define CLK_BUSTIMER6 93 -#define CLK_BUSTIMER7 94 -#define CLK_BUSTIMER8 95 -#define CLK_BUSTIMER9 96 -#define CLK_BUSTIMER10 97 -#define CLK_BUSTIMER11 98 -#define PCLK_WDT0 99 -#define TCLK_WDT0 100 -#define PCLK_CAN0 101 -#define CLK_CAN0 102 -#define PCLK_CAN1 103 -#define CLK_CAN1 104 -#define PCLK_CAN2 105 -#define CLK_CAN2 106 -#define ACLK_DECOM 107 -#define PCLK_DECOM 108 -#define DCLK_DECOM 109 -#define ACLK_DMAC0 110 -#define ACLK_DMAC1 111 -#define ACLK_DMAC2 112 -#define ACLK_BUS_ROOT 113 -#define ACLK_GIC 114 -#define PCLK_GPIO1 115 -#define DBCLK_GPIO1 116 -#define PCLK_GPIO2 117 -#define DBCLK_GPIO2 118 -#define PCLK_GPIO3 119 -#define DBCLK_GPIO3 120 -#define PCLK_GPIO4 121 -#define DBCLK_GPIO4 122 -#define PCLK_I2C1 123 -#define PCLK_I2C2 124 -#define PCLK_I2C3 125 -#define PCLK_I2C4 126 -#define PCLK_I2C5 127 -#define PCLK_I2C6 128 -#define PCLK_I2C7 129 -#define PCLK_I2C8 130 -#define CLK_I2C1 131 -#define CLK_I2C2 132 -#define CLK_I2C3 133 -#define CLK_I2C4 134 -#define CLK_I2C5 135 -#define CLK_I2C6 136 -#define CLK_I2C7 137 -#define CLK_I2C8 138 -#define PCLK_OTPC_NS 139 -#define CLK_OTPC_NS 140 -#define CLK_OTPC_ARB 141 -#define CLK_OTPC_AUTO_RD_G 142 -#define CLK_OTP_PHY_G 143 -#define PCLK_SARADC 144 -#define CLK_SARADC 145 -#define PCLK_SPI0 146 -#define PCLK_SPI1 147 -#define PCLK_SPI2 148 -#define PCLK_SPI3 149 -#define PCLK_SPI4 150 -#define CLK_SPI0 151 -#define CLK_SPI1 152 -#define CLK_SPI2 153 -#define CLK_SPI3 154 -#define CLK_SPI4 155 -#define ACLK_SPINLOCK 156 -#define PCLK_TSADC 157 -#define CLK_TSADC 158 -#define PCLK_UART1 159 -#define PCLK_UART2 160 -#define PCLK_UART3 161 -#define PCLK_UART4 162 -#define PCLK_UART5 163 -#define PCLK_UART6 164 -#define PCLK_UART7 165 -#define PCLK_UART8 166 -#define PCLK_UART9 167 -#define CLK_UART1_SRC 168 -#define CLK_UART1_FRAC 169 -#define CLK_UART1 170 -#define SCLK_UART1 171 -#define CLK_UART2_SRC 172 -#define CLK_UART2_FRAC 173 -#define CLK_UART2 174 -#define SCLK_UART2 175 -#define CLK_UART3_SRC 176 -#define CLK_UART3_FRAC 177 -#define CLK_UART3 178 -#define SCLK_UART3 179 -#define CLK_UART4_SRC 180 -#define CLK_UART4_FRAC 181 -#define CLK_UART4 182 -#define SCLK_UART4 183 -#define CLK_UART5_SRC 184 -#define CLK_UART5_FRAC 185 -#define CLK_UART5 186 -#define SCLK_UART5 187 -#define CLK_UART6_SRC 188 -#define CLK_UART6_FRAC 189 -#define CLK_UART6 190 -#define SCLK_UART6 191 -#define CLK_UART7_SRC 192 -#define CLK_UART7_FRAC 193 -#define CLK_UART7 194 -#define SCLK_UART7 195 -#define CLK_UART8_SRC 196 -#define CLK_UART8_FRAC 197 -#define CLK_UART8 198 -#define SCLK_UART8 199 -#define CLK_UART9_SRC 200 -#define CLK_UART9_FRAC 201 -#define CLK_UART9 202 -#define SCLK_UART9 203 -#define ACLK_CENTER_ROOT 204 -#define ACLK_CENTER_LOW_ROOT 205 -#define HCLK_CENTER_ROOT 206 -#define PCLK_CENTER_ROOT 207 -#define ACLK_DMA2DDR 208 -#define ACLK_DDR_SHAREMEM 209 -#define ACLK_CENTER_S200_ROOT 210 -#define ACLK_CENTER_S400_ROOT 211 -#define FCLK_DDR_CM0_CORE 212 -#define CLK_DDR_TIMER_ROOT 213 -#define CLK_DDR_TIMER0 214 -#define CLK_DDR_TIMER1 215 -#define TCLK_WDT_DDR 216 -#define CLK_DDR_CM0_RTC 217 -#define PCLK_WDT 218 -#define PCLK_TIMER 219 -#define PCLK_DMA2DDR 220 -#define PCLK_SHAREMEM 221 -#define CLK_50M_SRC 222 -#define CLK_100M_SRC 223 -#define CLK_150M_SRC 224 -#define CLK_200M_SRC 225 -#define CLK_250M_SRC 226 -#define CLK_300M_SRC 227 -#define CLK_350M_SRC 228 -#define CLK_400M_SRC 229 -#define CLK_450M_SRC 230 -#define CLK_500M_SRC 231 -#define CLK_600M_SRC 232 -#define CLK_650M_SRC 233 -#define CLK_700M_SRC 234 -#define CLK_800M_SRC 235 -#define CLK_1000M_SRC 236 -#define CLK_1200M_SRC 237 -#define ACLK_TOP_M300_ROOT 238 -#define ACLK_TOP_M500_ROOT 239 -#define ACLK_TOP_M400_ROOT 240 -#define ACLK_TOP_S200_ROOT 241 -#define ACLK_TOP_S400_ROOT 242 -#define CLK_MIPI_CAMARAOUT_M0 243 -#define CLK_MIPI_CAMARAOUT_M1 244 -#define CLK_MIPI_CAMARAOUT_M2 245 -#define CLK_MIPI_CAMARAOUT_M3 246 -#define CLK_MIPI_CAMARAOUT_M4 247 -#define MCLK_GMAC0_OUT 248 -#define REFCLKO25M_ETH0_OUT 249 -#define REFCLKO25M_ETH1_OUT 250 -#define CLK_CIFOUT_OUT 251 -#define PCLK_MIPI_DCPHY0 252 -#define PCLK_MIPI_DCPHY1 253 -#define PCLK_CSIPHY0 254 -#define PCLK_CSIPHY1 255 -#define ACLK_TOP_ROOT 256 -#define PCLK_TOP_ROOT 257 -#define ACLK_LOW_TOP_ROOT 258 -#define PCLK_CRU 259 -#define PCLK_GPU_ROOT 260 -#define CLK_GPU_SRC 261 -#define CLK_GPU 262 -#define CLK_GPU_COREGROUP 263 -#define CLK_GPU_STACKS 264 -#define PCLK_GPU_PVTM 265 -#define CLK_GPU_PVTM 266 -#define CLK_CORE_GPU_PVTM 267 -#define PCLK_GPU_GRF 268 -#define ACLK_ISP1_ROOT 269 -#define HCLK_ISP1_ROOT 270 -#define CLK_ISP1_CORE 271 -#define CLK_ISP1_CORE_MARVIN 272 -#define CLK_ISP1_CORE_VICAP 273 -#define ACLK_ISP1 274 -#define HCLK_ISP1 275 -#define ACLK_NPU1 276 -#define HCLK_NPU1 277 -#define ACLK_NPU2 278 -#define HCLK_NPU2 279 -#define HCLK_NPU_CM0_ROOT 280 -#define FCLK_NPU_CM0_CORE 281 -#define CLK_NPU_CM0_RTC 282 -#define PCLK_NPU_PVTM 283 -#define PCLK_NPU_GRF 284 -#define CLK_NPU_PVTM 285 -#define CLK_CORE_NPU_PVTM 286 -#define ACLK_NPU0 287 -#define HCLK_NPU0 288 -#define HCLK_NPU_ROOT 289 -#define CLK_NPU_DSU0 290 -#define PCLK_NPU_ROOT 291 -#define PCLK_NPU_TIMER 292 -#define CLK_NPUTIMER_ROOT 293 -#define CLK_NPUTIMER0 294 -#define CLK_NPUTIMER1 295 -#define PCLK_NPU_WDT 296 -#define TCLK_NPU_WDT 297 -#define HCLK_EMMC 298 -#define ACLK_EMMC 299 -#define CCLK_EMMC 300 -#define BCLK_EMMC 301 -#define TMCLK_EMMC 302 -#define SCLK_SFC 303 -#define HCLK_SFC 304 -#define HCLK_SFC_XIP 305 -#define HCLK_NVM_ROOT 306 -#define ACLK_NVM_ROOT 307 -#define CLK_GMAC0_PTP_REF 308 -#define CLK_GMAC1_PTP_REF 309 -#define CLK_GMAC_125M 310 -#define CLK_GMAC_50M 311 -#define ACLK_PHP_GIC_ITS 312 -#define ACLK_MMU_PCIE 313 -#define ACLK_MMU_PHP 314 -#define ACLK_PCIE_4L_DBI 315 -#define ACLK_PCIE_2L_DBI 316 -#define ACLK_PCIE_1L0_DBI 317 -#define ACLK_PCIE_1L1_DBI 318 -#define ACLK_PCIE_1L2_DBI 319 -#define ACLK_PCIE_4L_MSTR 320 -#define ACLK_PCIE_2L_MSTR 321 -#define ACLK_PCIE_1L0_MSTR 322 -#define ACLK_PCIE_1L1_MSTR 323 -#define ACLK_PCIE_1L2_MSTR 324 -#define ACLK_PCIE_4L_SLV 325 -#define ACLK_PCIE_2L_SLV 326 -#define ACLK_PCIE_1L0_SLV 327 -#define ACLK_PCIE_1L1_SLV 328 -#define ACLK_PCIE_1L2_SLV 329 -#define PCLK_PCIE_4L 330 -#define PCLK_PCIE_2L 331 -#define PCLK_PCIE_1L0 332 -#define PCLK_PCIE_1L1 333 -#define PCLK_PCIE_1L2 334 -#define CLK_PCIE_AUX0 335 -#define CLK_PCIE_AUX1 336 -#define CLK_PCIE_AUX2 337 -#define CLK_PCIE_AUX3 338 -#define CLK_PCIE_AUX4 339 -#define CLK_PIPEPHY0_REF 340 -#define CLK_PIPEPHY1_REF 341 -#define CLK_PIPEPHY2_REF 342 -#define PCLK_PHP_ROOT 343 -#define PCLK_GMAC0 344 -#define PCLK_GMAC1 345 -#define ACLK_PCIE_ROOT 346 -#define ACLK_PHP_ROOT 347 -#define ACLK_PCIE_BRIDGE 348 -#define ACLK_GMAC0 349 -#define ACLK_GMAC1 350 -#define CLK_PMALIVE0 351 -#define CLK_PMALIVE1 352 -#define CLK_PMALIVE2 353 -#define ACLK_SATA0 354 -#define ACLK_SATA1 355 -#define ACLK_SATA2 356 -#define CLK_RXOOB0 357 -#define CLK_RXOOB1 358 -#define CLK_RXOOB2 359 -#define ACLK_USB3OTG2 360 -#define SUSPEND_CLK_USB3OTG2 361 -#define REF_CLK_USB3OTG2 362 -#define CLK_UTMI_OTG2 363 -#define CLK_PIPEPHY0_PIPE_G 364 -#define CLK_PIPEPHY1_PIPE_G 365 -#define CLK_PIPEPHY2_PIPE_G 366 -#define CLK_PIPEPHY0_PIPE_ASIC_G 367 -#define CLK_PIPEPHY1_PIPE_ASIC_G 368 -#define CLK_PIPEPHY2_PIPE_ASIC_G 369 -#define CLK_PIPEPHY2_PIPE_U3_G 370 -#define CLK_PCIE1L2_PIPE 371 -#define CLK_PCIE4L_PIPE 372 -#define CLK_PCIE2L_PIPE 373 -#define PCLK_PCIE_COMBO_PIPE_PHY0 374 -#define PCLK_PCIE_COMBO_PIPE_PHY1 375 -#define PCLK_PCIE_COMBO_PIPE_PHY2 376 -#define PCLK_PCIE_COMBO_PIPE_PHY 377 -#define HCLK_RGA3_1 378 -#define ACLK_RGA3_1 379 -#define CLK_RGA3_1_CORE 380 -#define ACLK_RGA3_ROOT 381 -#define HCLK_RGA3_ROOT 382 -#define ACLK_RKVDEC_CCU 383 -#define HCLK_RKVDEC0 384 -#define ACLK_RKVDEC0 385 -#define CLK_RKVDEC0_CA 386 -#define CLK_RKVDEC0_HEVC_CA 387 -#define CLK_RKVDEC0_CORE 388 -#define HCLK_RKVDEC1 389 -#define ACLK_RKVDEC1 390 -#define CLK_RKVDEC1_CA 391 -#define CLK_RKVDEC1_HEVC_CA 392 -#define CLK_RKVDEC1_CORE 393 -#define HCLK_SDIO 394 -#define CCLK_SRC_SDIO 395 -#define ACLK_USB_ROOT 396 -#define HCLK_USB_ROOT 397 -#define HCLK_HOST0 398 -#define HCLK_HOST_ARB0 399 -#define HCLK_HOST1 400 -#define HCLK_HOST_ARB1 401 -#define ACLK_USB3OTG0 402 -#define SUSPEND_CLK_USB3OTG0 403 -#define REF_CLK_USB3OTG0 404 -#define ACLK_USB3OTG1 405 -#define SUSPEND_CLK_USB3OTG1 406 -#define REF_CLK_USB3OTG1 407 -#define UTMI_OHCI_CLK48_HOST0 408 -#define UTMI_OHCI_CLK48_HOST1 409 -#define HCLK_IEP2P0 410 -#define ACLK_IEP2P0 411 -#define CLK_IEP2P0_CORE 412 -#define ACLK_JPEG_ENCODER0 413 -#define HCLK_JPEG_ENCODER0 414 -#define ACLK_JPEG_ENCODER1 415 -#define HCLK_JPEG_ENCODER1 416 -#define ACLK_JPEG_ENCODER2 417 -#define HCLK_JPEG_ENCODER2 418 -#define ACLK_JPEG_ENCODER3 419 -#define HCLK_JPEG_ENCODER3 420 -#define ACLK_JPEG_DECODER 421 -#define HCLK_JPEG_DECODER 422 -#define HCLK_RGA2 423 -#define ACLK_RGA2 424 -#define CLK_RGA2_CORE 425 -#define HCLK_RGA3_0 426 -#define ACLK_RGA3_0 427 -#define CLK_RGA3_0_CORE 428 -#define ACLK_VDPU_ROOT 429 -#define ACLK_VDPU_LOW_ROOT 430 -#define HCLK_VDPU_ROOT 431 -#define ACLK_JPEG_DECODER_ROOT 432 -#define ACLK_VPU 433 -#define HCLK_VPU 434 -#define HCLK_RKVENC0_ROOT 435 -#define ACLK_RKVENC0_ROOT 436 -#define HCLK_RKVENC0 437 -#define ACLK_RKVENC0 438 -#define CLK_RKVENC0_CORE 439 -#define HCLK_RKVENC1_ROOT 440 -#define ACLK_RKVENC1_ROOT 441 -#define HCLK_RKVENC1 442 -#define ACLK_RKVENC1 443 -#define CLK_RKVENC1_CORE 444 -#define ICLK_CSIHOST01 445 -#define ICLK_CSIHOST0 446 -#define ICLK_CSIHOST1 447 -#define PCLK_CSI_HOST_0 448 -#define PCLK_CSI_HOST_1 449 -#define PCLK_CSI_HOST_2 450 -#define PCLK_CSI_HOST_3 451 -#define PCLK_CSI_HOST_4 452 -#define PCLK_CSI_HOST_5 453 -#define ACLK_FISHEYE0 454 -#define HCLK_FISHEYE0 455 -#define CLK_FISHEYE0_CORE 456 -#define ACLK_FISHEYE1 457 -#define HCLK_FISHEYE1 458 -#define CLK_FISHEYE1_CORE 459 -#define CLK_ISP0_CORE 460 -#define CLK_ISP0_CORE_MARVIN 461 -#define CLK_ISP0_CORE_VICAP 462 -#define ACLK_ISP0 463 -#define HCLK_ISP0 464 -#define ACLK_VI_ROOT 465 -#define HCLK_VI_ROOT 466 -#define PCLK_VI_ROOT 467 -#define DCLK_VICAP 468 -#define ACLK_VICAP 469 -#define HCLK_VICAP 470 -#define PCLK_DP0 471 -#define PCLK_DP1 472 -#define PCLK_S_DP0 473 -#define PCLK_S_DP1 474 -#define CLK_DP0 475 -#define CLK_DP1 476 -#define HCLK_HDCP_KEY0 477 -#define ACLK_HDCP0 478 -#define HCLK_HDCP0 479 -#define PCLK_HDCP0 480 -#define HCLK_I2S4_8CH 481 -#define ACLK_TRNG0 482 -#define PCLK_TRNG0 483 -#define ACLK_VO0_ROOT 484 -#define HCLK_VO0_ROOT 485 -#define HCLK_VO0_S_ROOT 486 -#define PCLK_VO0_ROOT 487 -#define PCLK_VO0_S_ROOT 488 -#define PCLK_VO0GRF 489 -#define CLK_I2S4_8CH_TX_SRC 490 -#define CLK_I2S4_8CH_TX_FRAC 491 -#define MCLK_I2S4_8CH_TX 492 -#define CLK_I2S4_8CH_TX 493 -#define HCLK_I2S8_8CH 494 -#define CLK_I2S8_8CH_TX_SRC 495 -#define CLK_I2S8_8CH_TX_FRAC 496 -#define MCLK_I2S8_8CH_TX 497 -#define CLK_I2S8_8CH_TX 498 -#define HCLK_SPDIF2_DP0 499 -#define CLK_SPDIF2_DP0_SRC 500 -#define CLK_SPDIF2_DP0_FRAC 501 -#define MCLK_SPDIF2_DP0 502 -#define CLK_SPDIF2_DP0 503 -#define MCLK_SPDIF2 504 -#define HCLK_SPDIF5_DP1 505 -#define CLK_SPDIF5_DP1_SRC 506 -#define CLK_SPDIF5_DP1_FRAC 507 -#define MCLK_SPDIF5_DP1 508 -#define CLK_SPDIF5_DP1 509 -#define MCLK_SPDIF5 510 -#define PCLK_EDP0 511 -#define CLK_EDP0_24M 512 -#define CLK_EDP0_200M 513 -#define PCLK_EDP1 514 -#define CLK_EDP1_24M 515 -#define CLK_EDP1_200M 516 -#define HCLK_HDCP_KEY1 517 -#define ACLK_HDCP1 518 -#define HCLK_HDCP1 519 -#define PCLK_HDCP1 520 -#define ACLK_HDMIRX 521 -#define PCLK_HDMIRX 522 -#define CLK_HDMIRX_REF 523 -#define CLK_HDMIRX_AUD_SRC 524 -#define CLK_HDMIRX_AUD_FRAC 525 -#define CLK_HDMIRX_AUD 526 -#define CLK_HDMIRX_AUD_P_MUX 527 -#define PCLK_HDMITX0 528 -#define CLK_HDMITX0_EARC 529 -#define CLK_HDMITX0_REF 530 -#define PCLK_HDMITX1 531 -#define CLK_HDMITX1_EARC 532 -#define CLK_HDMITX1_REF 533 -#define CLK_HDMITRX_REFSRC 534 -#define ACLK_TRNG1 535 -#define PCLK_TRNG1 536 -#define ACLK_HDCP1_ROOT 537 -#define ACLK_HDMIRX_ROOT 538 -#define HCLK_VO1_ROOT 539 -#define HCLK_VO1_S_ROOT 540 -#define PCLK_VO1_ROOT 541 -#define PCLK_VO1_S_ROOT 542 -#define PCLK_S_EDP0 543 -#define PCLK_S_EDP1 544 -#define PCLK_S_HDMIRX 545 -#define HCLK_I2S10_8CH 546 -#define CLK_I2S10_8CH_RX_SRC 547 -#define CLK_I2S10_8CH_RX_FRAC 548 -#define CLK_I2S10_8CH_RX 549 -#define MCLK_I2S10_8CH_RX 550 -#define HCLK_I2S7_8CH 551 -#define CLK_I2S7_8CH_RX_SRC 552 -#define CLK_I2S7_8CH_RX_FRAC 553 -#define CLK_I2S7_8CH_RX 554 -#define MCLK_I2S7_8CH_RX 555 -#define HCLK_I2S9_8CH 556 -#define CLK_I2S9_8CH_RX_SRC 557 -#define CLK_I2S9_8CH_RX_FRAC 558 -#define CLK_I2S9_8CH_RX 559 -#define MCLK_I2S9_8CH_RX 560 -#define CLK_I2S5_8CH_TX_SRC 561 -#define CLK_I2S5_8CH_TX_FRAC 562 -#define CLK_I2S5_8CH_TX 563 -#define MCLK_I2S5_8CH_TX 564 -#define HCLK_I2S5_8CH 565 -#define CLK_I2S6_8CH_TX_SRC 566 -#define CLK_I2S6_8CH_TX_FRAC 567 -#define CLK_I2S6_8CH_TX 568 -#define MCLK_I2S6_8CH_TX 569 -#define CLK_I2S6_8CH_RX_SRC 570 -#define CLK_I2S6_8CH_RX_FRAC 571 -#define CLK_I2S6_8CH_RX 572 -#define MCLK_I2S6_8CH_RX 573 -#define I2S6_8CH_MCLKOUT 574 -#define HCLK_I2S6_8CH 575 -#define HCLK_SPDIF3 576 -#define CLK_SPDIF3_SRC 577 -#define CLK_SPDIF3_FRAC 578 -#define CLK_SPDIF3 579 -#define MCLK_SPDIF3 580 -#define HCLK_SPDIF4 581 -#define CLK_SPDIF4_SRC 582 -#define CLK_SPDIF4_FRAC 583 -#define CLK_SPDIF4 584 -#define MCLK_SPDIF4 585 -#define HCLK_SPDIFRX0 586 -#define MCLK_SPDIFRX0 587 -#define HCLK_SPDIFRX1 588 -#define MCLK_SPDIFRX1 589 -#define HCLK_SPDIFRX2 590 -#define MCLK_SPDIFRX2 591 -#define ACLK_VO1USB_TOP_ROOT 592 -#define HCLK_VO1USB_TOP_ROOT 593 -#define CLK_HDMIHDP0 594 -#define CLK_HDMIHDP1 595 -#define PCLK_HDPTX0 596 -#define PCLK_HDPTX1 597 -#define PCLK_USBDPPHY0 598 -#define PCLK_USBDPPHY1 599 -#define ACLK_VOP_ROOT 600 -#define ACLK_VOP_LOW_ROOT 601 -#define HCLK_VOP_ROOT 602 -#define PCLK_VOP_ROOT 603 -#define HCLK_VOP 604 -#define ACLK_VOP 605 -#define DCLK_VOP0_SRC 606 -#define DCLK_VOP1_SRC 607 -#define DCLK_VOP2_SRC 608 -#define DCLK_VOP0 609 -#define DCLK_VOP1 610 -#define DCLK_VOP2 611 -#define DCLK_VOP3 612 -#define PCLK_DSIHOST0 613 -#define PCLK_DSIHOST1 614 -#define CLK_DSIHOST0 615 -#define CLK_DSIHOST1 616 -#define CLK_VOP_PMU 617 -#define ACLK_VOP_DOBY 618 -#define ACLK_VOP_SUB_SRC 619 -#define CLK_USBDP_PHY0_IMMORTAL 620 -#define CLK_USBDP_PHY1_IMMORTAL 621 -#define CLK_PMU0 622 -#define PCLK_PMU0 623 -#define PCLK_PMU0IOC 624 -#define PCLK_GPIO0 625 -#define DBCLK_GPIO0 626 -#define PCLK_I2C0 627 -#define CLK_I2C0 628 -#define HCLK_I2S1_8CH 629 -#define CLK_I2S1_8CH_TX_SRC 630 -#define CLK_I2S1_8CH_TX_FRAC 631 -#define CLK_I2S1_8CH_TX 632 -#define MCLK_I2S1_8CH_TX 633 -#define CLK_I2S1_8CH_RX_SRC 634 -#define CLK_I2S1_8CH_RX_FRAC 635 -#define CLK_I2S1_8CH_RX 636 -#define MCLK_I2S1_8CH_RX 637 -#define I2S1_8CH_MCLKOUT 638 -#define CLK_PMU1_50M_SRC 639 -#define CLK_PMU1_100M_SRC 640 -#define CLK_PMU1_200M_SRC 641 -#define CLK_PMU1_300M_SRC 642 -#define CLK_PMU1_400M_SRC 643 -#define HCLK_PMU1_ROOT 644 -#define PCLK_PMU1_ROOT 645 -#define PCLK_PMU0_ROOT 646 -#define HCLK_PMU_CM0_ROOT 647 -#define PCLK_PMU1 648 -#define CLK_DDR_FAIL_SAFE 649 -#define CLK_PMU1 650 -#define HCLK_PDM0 651 -#define MCLK_PDM0 652 -#define HCLK_VAD 653 -#define FCLK_PMU_CM0_CORE 654 -#define CLK_PMU_CM0_RTC 655 -#define PCLK_PMU1_IOC 656 -#define PCLK_PMU1PWM 657 -#define CLK_PMU1PWM 658 -#define CLK_PMU1PWM_CAPTURE 659 -#define PCLK_PMU1TIMER 660 -#define CLK_PMU1TIMER_ROOT 661 -#define CLK_PMU1TIMER0 662 -#define CLK_PMU1TIMER1 663 -#define CLK_UART0_SRC 664 -#define CLK_UART0_FRAC 665 -#define CLK_UART0 666 -#define SCLK_UART0 667 -#define PCLK_UART0 668 -#define PCLK_PMU1WDT 669 -#define TCLK_PMU1WDT 670 -#define CLK_CR_PARA 671 -#define CLK_USB2PHY_HDPTXRXPHY_REF 672 -#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 -#define CLK_REF_PIPE_PHY0_OSC_SRC 674 -#define CLK_REF_PIPE_PHY1_OSC_SRC 675 -#define CLK_REF_PIPE_PHY2_OSC_SRC 676 -#define CLK_REF_PIPE_PHY0_PLL_SRC 677 -#define CLK_REF_PIPE_PHY1_PLL_SRC 678 -#define CLK_REF_PIPE_PHY2_PLL_SRC 679 -#define CLK_REF_PIPE_PHY0 680 -#define CLK_REF_PIPE_PHY1 681 -#define CLK_REF_PIPE_PHY2 682 -#define SCLK_SDIO_DRV 683 -#define SCLK_SDIO_SAMPLE 684 -#define SCLK_SDMMC_DRV 685 -#define SCLK_SDMMC_SAMPLE 686 -#define CLK_PCIE1L0_PIPE 687 -#define CLK_PCIE1L1_PIPE 688 -#define CLK_BIGCORE0_PVTM 689 -#define CLK_CORE_BIGCORE0_PVTM 690 -#define CLK_BIGCORE1_PVTM 691 -#define CLK_CORE_BIGCORE1_PVTM 692 -#define CLK_LITCORE_PVTM 693 -#define CLK_CORE_LITCORE_PVTM 694 -#define CLK_AUX16M_0 695 -#define CLK_AUX16M_1 696 -#define CLK_PHY0_REF_ALT_P 697 -#define CLK_PHY0_REF_ALT_M 698 -#define CLK_PHY1_REF_ALT_P 699 -#define CLK_PHY1_REF_ALT_M 700 -#define ACLK_ISP1_PRE 701 -#define HCLK_ISP1_PRE 702 -#define HCLK_NVM 703 -#define ACLK_USB 704 -#define HCLK_USB 705 -#define ACLK_JPEG_DECODER_PRE 706 -#define ACLK_VDPU_LOW_PRE 707 -#define ACLK_RKVENC1_PRE 708 -#define HCLK_RKVENC1_PRE 709 -#define HCLK_RKVDEC0_PRE 710 -#define ACLK_RKVDEC0_PRE 711 -#define HCLK_RKVDEC1_PRE 712 -#define ACLK_RKVDEC1_PRE 713 -#define ACLK_HDCP0_PRE 714 -#define HCLK_VO0 715 -#define ACLK_HDCP1_PRE 716 -#define HCLK_VO1 717 -#define ACLK_AV1_PRE 718 -#define PCLK_AV1_PRE 719 -#define HCLK_SDIO_PRE 720 - -#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) - -/* scmi-clocks indices */ - -#define SCMI_CLK_CPUL 0 -#define SCMI_CLK_DSU 1 -#define SCMI_CLK_CPUB01 2 -#define SCMI_CLK_CPUB23 3 -#define SCMI_CLK_DDR 4 -#define SCMI_CLK_GPU 5 -#define SCMI_CLK_NPU 6 -#define SCMI_CLK_SBUS 7 -#define SCMI_PCLK_SBUS 8 -#define SCMI_CCLK_SD 9 -#define SCMI_DCLK_SD 10 -#define SCMI_ACLK_SECURE_NS 11 -#define SCMI_HCLK_SECURE_NS 12 -#define SCMI_TCLK_WDT 13 -#define SCMI_KEYLADDER_CORE 14 -#define SCMI_KEYLADDER_RNG 15 -#define SCMI_ACLK_SECURE_S 16 -#define SCMI_HCLK_SECURE_S 17 -#define SCMI_PCLK_SECURE_S 18 -#define SCMI_CRYPTO_RNG 19 -#define SCMI_CRYPTO_CORE 20 -#define SCMI_CRYPTO_PKA 21 -#define SCMI_SPLL 22 -#define SCMI_HCLK_SD 23 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a873432f965..000000000000 --- a/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h b/include/dt-bindings/clock/rockchip,rv1126-cru.h deleted file mode 100644 index e89a3a5a4a34..000000000000 --- a/include/dt-bindings/clock/rockchip,rv1126-cru.h +++ /dev/null @@ -1,632 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Rockchip Electronics Co. Ltd. - * Author: Finley Xiao finley.xiao@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H - -/* pmucru-clocks indices */ - -/* pll clocks */ -#define PLL_GPLL 1 - -/* sclk (special clocks) */ -#define CLK_OSC0_DIV32K 2 -#define CLK_RTC32K 3 -#define CLK_WIFI_DIV 4 -#define CLK_WIFI_OSC0 5 -#define CLK_WIFI 6 -#define CLK_PMU 7 -#define SCLK_UART1_DIV 8 -#define SCLK_UART1_FRACDIV 9 -#define SCLK_UART1_MUX 10 -#define SCLK_UART1 11 -#define CLK_I2C0 12 -#define CLK_I2C2 13 -#define CLK_CAPTURE_PWM0 14 -#define CLK_PWM0 15 -#define CLK_CAPTURE_PWM1 16 -#define CLK_PWM1 17 -#define CLK_SPI0 18 -#define DBCLK_GPIO0 19 -#define CLK_PMUPVTM 20 -#define CLK_CORE_PMUPVTM 21 -#define CLK_REF12M 22 -#define CLK_USBPHY_OTG_REF 23 -#define CLK_USBPHY_HOST_REF 24 -#define CLK_REF24M 25 -#define CLK_MIPIDSIPHY_REF 26 - -/* pclk */ -#define PCLK_PDPMU 30 -#define PCLK_PMU 31 -#define PCLK_UART1 32 -#define PCLK_I2C0 33 -#define PCLK_I2C2 34 -#define PCLK_PWM0 35 -#define PCLK_PWM1 36 -#define PCLK_SPI0 37 -#define PCLK_GPIO0 38 -#define PCLK_PMUSGRF 39 -#define PCLK_PMUGRF 40 -#define PCLK_PMUCRU 41 -#define PCLK_CHIPVEROTP 42 -#define PCLK_PDPMU_NIU 43 -#define PCLK_PMUPVTM 44 -#define PCLK_SCRKEYGEN 45 - -#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) - -/* cru-clocks indices */ - -/* pll clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_HPLL 4 - -/* sclk (special clocks) */ -#define ARMCLK 5 -#define USB480M 6 -#define CLK_CORE_CPUPVTM 7 -#define CLK_CPUPVTM 8 -#define CLK_SCR1 9 -#define CLK_SCR1_CORE 10 -#define CLK_SCR1_RTC 11 -#define CLK_SCR1_JTAG 12 -#define SCLK_UART0_DIV 13 -#define SCLK_UART0_FRAC 14 -#define SCLK_UART0_MUX 15 -#define SCLK_UART0 16 -#define SCLK_UART2_DIV 17 -#define SCLK_UART2_FRAC 18 -#define SCLK_UART2_MUX 19 -#define SCLK_UART2 20 -#define SCLK_UART3_DIV 21 -#define SCLK_UART3_FRAC 22 -#define SCLK_UART3_MUX 23 -#define SCLK_UART3 24 -#define SCLK_UART4_DIV 25 -#define SCLK_UART4_FRAC 26 -#define SCLK_UART4_MUX 27 -#define SCLK_UART4 28 -#define SCLK_UART5_DIV 29 -#define SCLK_UART5_FRAC 30 -#define SCLK_UART5_MUX 31 -#define SCLK_UART5 32 -#define CLK_I2C1 33 -#define CLK_I2C3 34 -#define CLK_I2C4 35 -#define CLK_I2C5 36 -#define CLK_SPI1 37 -#define CLK_CAPTURE_PWM2 38 -#define CLK_PWM2 39 -#define DBCLK_GPIO1 40 -#define DBCLK_GPIO2 41 -#define DBCLK_GPIO3 42 -#define DBCLK_GPIO4 43 -#define CLK_SARADC 44 -#define CLK_TIMER0 45 -#define CLK_TIMER1 46 -#define CLK_TIMER2 47 -#define CLK_TIMER3 48 -#define CLK_TIMER4 49 -#define CLK_TIMER5 50 -#define CLK_CAN 51 -#define CLK_NPU_TSADC 52 -#define CLK_NPU_TSADCPHY 53 -#define CLK_CPU_TSADC 54 -#define CLK_CPU_TSADCPHY 55 -#define CLK_CRYPTO_CORE 56 -#define CLK_CRYPTO_PKA 57 -#define MCLK_I2S0_TX_DIV 58 -#define MCLK_I2S0_TX_FRACDIV 59 -#define MCLK_I2S0_TX_MUX 60 -#define MCLK_I2S0_TX 61 -#define MCLK_I2S0_RX_DIV 62 -#define MCLK_I2S0_RX_FRACDIV 63 -#define MCLK_I2S0_RX_MUX 64 -#define MCLK_I2S0_RX 65 -#define MCLK_I2S0_TX_OUT2IO 66 -#define MCLK_I2S0_RX_OUT2IO 67 -#define MCLK_I2S1_DIV 68 -#define MCLK_I2S1_FRACDIV 69 -#define MCLK_I2S1_MUX 70 -#define MCLK_I2S1 71 -#define MCLK_I2S1_OUT2IO 72 -#define MCLK_I2S2_DIV 73 -#define MCLK_I2S2_FRACDIV 74 -#define MCLK_I2S2_MUX 75 -#define MCLK_I2S2 76 -#define MCLK_I2S2_OUT2IO 77 -#define MCLK_PDM 78 -#define SCLK_ADUPWM_DIV 79 -#define SCLK_AUDPWM_FRACDIV 80 -#define SCLK_AUDPWM_MUX 81 -#define SCLK_AUDPWM 82 -#define CLK_ACDCDIG_ADC 83 -#define CLK_ACDCDIG_DAC 84 -#define CLK_ACDCDIG_I2C 85 -#define CLK_VENC_CORE 86 -#define CLK_VDEC_CORE 87 -#define CLK_VDEC_CA 88 -#define CLK_VDEC_HEVC_CA 89 -#define CLK_RGA_CORE 90 -#define CLK_IEP_CORE 91 -#define CLK_ISP_DIV 92 -#define CLK_ISP_NP5 93 -#define CLK_ISP_NUX 94 -#define CLK_ISP 95 -#define CLK_CIF_OUT_DIV 96 -#define CLK_CIF_OUT_FRACDIV 97 -#define CLK_CIF_OUT_MUX 98 -#define CLK_CIF_OUT 99 -#define CLK_MIPICSI_OUT_DIV 100 -#define CLK_MIPICSI_OUT_FRACDIV 101 -#define CLK_MIPICSI_OUT_MUX 102 -#define CLK_MIPICSI_OUT 103 -#define CLK_ISPP_DIV 104 -#define CLK_ISPP_NP5 105 -#define CLK_ISPP_NUX 106 -#define CLK_ISPP 107 -#define CLK_SDMMC 108 -#define SCLK_SDMMC_DRV 109 -#define SCLK_SDMMC_SAMPLE 110 -#define CLK_SDIO 111 -#define SCLK_SDIO_DRV 112 -#define SCLK_SDIO_SAMPLE 113 -#define CLK_EMMC 114 -#define SCLK_EMMC_DRV 115 -#define SCLK_EMMC_SAMPLE 116 -#define CLK_NANDC 117 -#define SCLK_SFC 118 -#define CLK_USBHOST_UTMI_OHCI 119 -#define CLK_USBOTG_REF 120 -#define CLK_GMAC_DIV 121 -#define CLK_GMAC_RGMII_M0 122 -#define CLK_GMAC_SRC_M0 123 -#define CLK_GMAC_RGMII_M1 124 -#define CLK_GMAC_SRC_M1 125 -#define CLK_GMAC_SRC 126 -#define CLK_GMAC_REF 127 -#define CLK_GMAC_TX_SRC 128 -#define CLK_GMAC_TX_DIV5 129 -#define CLK_GMAC_TX_DIV50 130 -#define RGMII_MODE_CLK 131 -#define CLK_GMAC_RX_SRC 132 -#define CLK_GMAC_RX_DIV2 133 -#define CLK_GMAC_RX_DIV20 134 -#define RMII_MODE_CLK 135 -#define CLK_GMAC_TX_RX 136 -#define CLK_GMAC_PTPREF 137 -#define CLK_GMAC_ETHERNET_OUT 138 -#define CLK_DDRPHY 139 -#define CLK_DDR_MON 140 -#define TMCLK_DDR_MON 141 -#define CLK_NPU_DIV 142 -#define CLK_NPU_NP5 143 -#define CLK_CORE_NPU 144 -#define CLK_CORE_NPUPVTM 145 -#define CLK_NPUPVTM 146 -#define SCLK_DDRCLK 147 -#define CLK_OTP 148 - -/* dclk */ -#define DCLK_DECOM 150 -#define DCLK_VOP_DIV 151 -#define DCLK_VOP_FRACDIV 152 -#define DCLK_VOP_MUX 153 -#define DCLK_VOP 154 -#define DCLK_CIF 155 -#define DCLK_CIFLITE 156 - -/* aclk */ -#define ACLK_PDBUS 160 -#define ACLK_DMAC 161 -#define ACLK_DCF 162 -#define ACLK_SPINLOCK 163 -#define ACLK_DECOM 164 -#define ACLK_PDCRYPTO 165 -#define ACLK_CRYPTO 166 -#define ACLK_PDVEPU 167 -#define ACLK_VENC 168 -#define ACLK_PDVDEC 169 -#define ACLK_PDJPEG 170 -#define ACLK_VDEC 171 -#define ACLK_JPEG 172 -#define ACLK_PDVO 173 -#define ACLK_RGA 174 -#define ACLK_VOP 175 -#define ACLK_IEP 176 -#define ACLK_PDVI_DIV 177 -#define ACLK_PDVI_NP5 178 -#define ACLK_PDVI 179 -#define ACLK_ISP 180 -#define ACLK_CIF 181 -#define ACLK_CIFLITE 182 -#define ACLK_PDISPP_DIV 183 -#define ACLK_PDISPP_NP5 184 -#define ACLK_PDISPP 185 -#define ACLK_ISPP 186 -#define ACLK_PDPHP 187 -#define ACLK_PDUSB 188 -#define ACLK_USBOTG 189 -#define ACLK_PDGMAC 190 -#define ACLK_GMAC 191 -#define ACLK_PDNPU_DIV 192 -#define ACLK_PDNPU_NP5 193 -#define ACLK_PDNPU 194 -#define ACLK_NPU 195 - -/* hclk */ -#define HCLK_PDCORE_NIU 200 -#define HCLK_PDUSB 201 -#define HCLK_PDCRYPTO 202 -#define HCLK_CRYPTO 203 -#define HCLK_PDAUDIO 204 -#define HCLK_I2S0 205 -#define HCLK_I2S1 206 -#define HCLK_I2S2 207 -#define HCLK_PDM 208 -#define HCLK_AUDPWM 209 -#define HCLK_PDVEPU 210 -#define HCLK_VENC 211 -#define HCLK_PDVDEC 212 -#define HCLK_PDJPEG 213 -#define HCLK_VDEC 214 -#define HCLK_JPEG 215 -#define HCLK_PDVO 216 -#define HCLK_RGA 217 -#define HCLK_VOP 218 -#define HCLK_IEP 219 -#define HCLK_PDVI 220 -#define HCLK_ISP 221 -#define HCLK_CIF 222 -#define HCLK_CIFLITE 223 -#define HCLK_PDISPP 224 -#define HCLK_ISPP 225 -#define HCLK_PDPHP 226 -#define HCLK_PDSDMMC 227 -#define HCLK_SDMMC 228 -#define HCLK_PDSDIO 229 -#define HCLK_SDIO 230 -#define HCLK_PDNVM 231 -#define HCLK_EMMC 232 -#define HCLK_NANDC 233 -#define HCLK_SFC 234 -#define HCLK_SFCXIP 235 -#define HCLK_PDBUS 236 -#define HCLK_USBHOST 237 -#define HCLK_USBHOST_ARB 238 -#define HCLK_PDNPU 239 -#define HCLK_NPU 240 - -/* pclk */ -#define PCLK_CPUPVTM 245 -#define PCLK_PDBUS 246 -#define PCLK_DCF 247 -#define PCLK_WDT 248 -#define PCLK_MAILBOX 249 -#define PCLK_UART0 250 -#define PCLK_UART2 251 -#define PCLK_UART3 252 -#define PCLK_UART4 253 -#define PCLK_UART5 254 -#define PCLK_I2C1 255 -#define PCLK_I2C3 256 -#define PCLK_I2C4 257 -#define PCLK_I2C5 258 -#define PCLK_SPI1 259 -#define PCLK_PWM2 261 -#define PCLK_GPIO1 262 -#define PCLK_GPIO2 263 -#define PCLK_GPIO3 264 -#define PCLK_GPIO4 265 -#define PCLK_SARADC 266 -#define PCLK_TIMER 267 -#define PCLK_DECOM 268 -#define PCLK_CAN 269 -#define PCLK_NPU_TSADC 270 -#define PCLK_CPU_TSADC 271 -#define PCLK_ACDCDIG 272 -#define PCLK_PDVO 273 -#define PCLK_DSIHOST 274 -#define PCLK_PDVI 275 -#define PCLK_CSIHOST 276 -#define PCLK_PDGMAC 277 -#define PCLK_GMAC 278 -#define PCLK_PDDDR 279 -#define PCLK_DDR_MON 280 -#define PCLK_PDNPU 281 -#define PCLK_NPUPVTM 282 -#define PCLK_PDTOP 283 -#define PCLK_TOPCRU 284 -#define PCLK_TOPGRF 285 -#define PCLK_CPUEMADET 286 -#define PCLK_DDRPHY 287 -#define PCLK_DSIPHY 289 -#define PCLK_CSIPHY0 290 -#define PCLK_CSIPHY1 291 -#define PCLK_USBPHY_HOST 292 -#define PCLK_USBPHY_OTG 293 -#define PCLK_OTP 294 - -#define CLK_NR_CLKS (PCLK_OTP + 1) - -/* pmu soft-reset indices */ - -/* pmu_cru_softrst_con0 */ -#define SRST_PDPMU_NIU_P 0 -#define SRST_PMU_SGRF_P 1 -#define SRST_PMU_SGRF_REMAP_P 2 -#define SRST_I2C0_P 3 -#define SRST_I2C0 4 -#define SRST_I2C2_P 7 -#define SRST_I2C2 8 -#define SRST_UART1_P 9 -#define SRST_UART1 10 -#define SRST_PWM0_P 11 -#define SRST_PWM0 12 -#define SRST_PWM1_P 13 -#define SRST_PWM1 14 -#define SRST_DDR_FAIL_SAFE 15 - -/* pmu_cru_softrst_con1 */ -#define SRST_GPIO0_P 17 -#define SRST_GPIO0_DB 18 -#define SRST_SPI0_P 19 -#define SRST_SPI0 20 -#define SRST_PMUGRF_P 21 -#define SRST_CHIPVEROTP_P 22 -#define SRST_PMUPVTM 24 -#define SRST_PMUPVTM_P 25 -#define SRST_PMUCRU_P 30 - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_NL2 12 -#define SRST_CORE_NIU_A 13 -#define SRST_DBG_DAPLITE_P 14 -#define SRST_DAPLITE_P 15 - -/* cru_softrst_con1 */ -#define SRST_PDBUS_NIU1_A 16 -#define SRST_PDBUS_NIU1_H 17 -#define SRST_PDBUS_NIU1_P 18 -#define SRST_PDBUS_NIU2_A 19 -#define SRST_PDBUS_NIU2_H 20 -#define SRST_PDBUS_NIU3_A 21 -#define SRST_PDBUS_NIU3_H 22 -#define SRST_PDBUS_HOLD_NIU1_A 23 -#define SRST_DBG_NIU_P 24 -#define SRST_PDCORE_NIIU_H 25 -#define SRST_MUC_NIU 26 -#define SRST_DCF_A 29 -#define SRST_DCF_P 30 -#define SRST_SYSTEM_SRAM_A 31 - -/* cru_softrst_con2 */ -#define SRST_I2C1_P 32 -#define SRST_I2C1 33 -#define SRST_I2C3_P 34 -#define SRST_I2C3 35 -#define SRST_I2C4_P 36 -#define SRST_I2C4 37 -#define SRST_I2C5_P 38 -#define SRST_I2C5 39 -#define SRST_SPI1_P 40 -#define SRST_SPI1 41 -#define SRST_MCU_CORE 42 -#define SRST_PWM2_P 44 -#define SRST_PWM2 45 -#define SRST_SPINLOCK_A 46 - -/* cru_softrst_con3 */ -#define SRST_UART0_P 48 -#define SRST_UART0 49 -#define SRST_UART2_P 50 -#define SRST_UART2 51 -#define SRST_UART3_P 52 -#define SRST_UART3 53 -#define SRST_UART4_P 54 -#define SRST_UART4 55 -#define SRST_UART5_P 56 -#define SRST_UART5 57 -#define SRST_WDT_P 58 -#define SRST_SARADC_P 59 -#define SRST_GRF_P 61 -#define SRST_TIMER_P 62 -#define SRST_MAILBOX_P 63 - -/* cru_softrst_con4 */ -#define SRST_TIMER0 64 -#define SRST_TIMER1 65 -#define SRST_TIMER2 66 -#define SRST_TIMER3 67 -#define SRST_TIMER4 68 -#define SRST_TIMER5 69 -#define SRST_INTMUX_P 70 -#define SRST_GPIO1_P 72 -#define SRST_GPIO1_DB 73 -#define SRST_GPIO2_P 74 -#define SRST_GPIO2_DB 75 -#define SRST_GPIO3_P 76 -#define SRST_GPIO3_DB 77 -#define SRST_GPIO4_P 78 -#define SRST_GPIO4_DB 79 - -/* cru_softrst_con5 */ -#define SRST_CAN_P 80 -#define SRST_CAN 81 -#define SRST_DECOM_A 85 -#define SRST_DECOM_P 86 -#define SRST_DECOM_D 87 -#define SRST_PDCRYPTO_NIU_A 88 -#define SRST_PDCRYPTO_NIU_H 89 -#define SRST_CRYPTO_A 90 -#define SRST_CRYPTO_H 91 -#define SRST_CRYPTO_CORE 92 -#define SRST_CRYPTO_PKA 93 -#define SRST_SGRF_P 95 - -/* cru_softrst_con6 */ -#define SRST_PDAUDIO_NIU_H 96 -#define SRST_PDAUDIO_NIU_P 97 -#define SRST_I2S0_H 98 -#define SRST_I2S0_TX_M 99 -#define SRST_I2S0_RX_M 100 -#define SRST_I2S1_H 101 -#define SRST_I2S1_M 102 -#define SRST_I2S2_H 103 -#define SRST_I2S2_M 104 -#define SRST_PDM_H 105 -#define SRST_PDM_M 106 -#define SRST_AUDPWM_H 107 -#define SRST_AUDPWM 108 -#define SRST_ACDCDIG_P 109 -#define SRST_ACDCDIG 110 - -/* cru_softrst_con7 */ -#define SRST_PDVEPU_NIU_A 112 -#define SRST_PDVEPU_NIU_H 113 -#define SRST_VENC_A 114 -#define SRST_VENC_H 115 -#define SRST_VENC_CORE 116 -#define SRST_PDVDEC_NIU_A 117 -#define SRST_PDVDEC_NIU_H 118 -#define SRST_VDEC_A 119 -#define SRST_VDEC_H 120 -#define SRST_VDEC_CORE 121 -#define SRST_VDEC_CA 122 -#define SRST_VDEC_HEVC_CA 123 -#define SRST_PDJPEG_NIU_A 124 -#define SRST_PDJPEG_NIU_H 125 -#define SRST_JPEG_A 126 -#define SRST_JPEG_H 127 - -/* cru_softrst_con8 */ -#define SRST_PDVO_NIU_A 128 -#define SRST_PDVO_NIU_H 129 -#define SRST_PDVO_NIU_P 130 -#define SRST_RGA_A 131 -#define SRST_RGA_H 132 -#define SRST_RGA_CORE 133 -#define SRST_VOP_A 134 -#define SRST_VOP_H 135 -#define SRST_VOP_D 136 -#define SRST_TXBYTEHS_DSIHOST 137 -#define SRST_DSIHOST_P 138 -#define SRST_IEP_A 139 -#define SRST_IEP_H 140 -#define SRST_IEP_CORE 141 -#define SRST_ISP_RX_P 142 - -/* cru_softrst_con9 */ -#define SRST_PDVI_NIU_A 144 -#define SRST_PDVI_NIU_H 145 -#define SRST_PDVI_NIU_P 146 -#define SRST_ISP 147 -#define SRST_CIF_A 148 -#define SRST_CIF_H 149 -#define SRST_CIF_D 150 -#define SRST_CIF_P 151 -#define SRST_CIF_I 152 -#define SRST_CIF_RX_P 153 -#define SRST_PDISPP_NIU_A 154 -#define SRST_PDISPP_NIU_H 155 -#define SRST_ISPP_A 156 -#define SRST_ISPP_H 157 -#define SRST_ISPP 158 -#define SRST_CSIHOST_P 159 - -/* cru_softrst_con10 */ -#define SRST_PDPHPMID_NIU_A 160 -#define SRST_PDPHPMID_NIU_H 161 -#define SRST_PDNVM_NIU_H 163 -#define SRST_SDMMC_H 164 -#define SRST_SDIO_H 165 -#define SRST_EMMC_H 166 -#define SRST_SFC_H 167 -#define SRST_SFCXIP_H 168 -#define SRST_SFC 169 -#define SRST_NANDC_H 170 -#define SRST_NANDC 171 -#define SRST_PDSDMMC_H 173 -#define SRST_PDSDIO_H 174 - -/* cru_softrst_con11 */ -#define SRST_PDUSB_NIU_A 176 -#define SRST_PDUSB_NIU_H 177 -#define SRST_USBHOST_H 178 -#define SRST_USBHOST_ARB_H 179 -#define SRST_USBHOST_UTMI 180 -#define SRST_USBOTG_A 181 -#define SRST_USBPHY_OTG_P 182 -#define SRST_USBPHY_HOST_P 183 -#define SRST_USBPHYPOR_OTG 184 -#define SRST_USBPHYPOR_HOST 185 -#define SRST_PDGMAC_NIU_A 188 -#define SRST_PDGMAC_NIU_P 189 -#define SRST_GMAC_A 190 - -/* cru_softrst_con12 */ -#define SRST_DDR_DFICTL_P 193 -#define SRST_DDR_MON_P 194 -#define SRST_DDR_STANDBY_P 195 -#define SRST_DDR_GRF_P 196 -#define SRST_DDR_MSCH_P 197 -#define SRST_DDR_SPLIT_A 198 -#define SRST_DDR_MSCH 199 -#define SRST_DDR_DFICTL 202 -#define SRST_DDR_STANDBY 203 -#define SRST_NPUMCU_NIU 205 -#define SRST_DDRPHY_P 206 -#define SRST_DDRPHY 207 - -/* cru_softrst_con13 */ -#define SRST_PDNPU_NIU_A 208 -#define SRST_PDNPU_NIU_H 209 -#define SRST_PDNPU_NIU_P 210 -#define SRST_NPU_A 211 -#define SRST_NPU_H 212 -#define SRST_NPU 213 -#define SRST_NPUPVTM_P 214 -#define SRST_NPUPVTM 215 -#define SRST_NPU_TSADC_P 216 -#define SRST_NPU_TSADC 217 -#define SRST_NPU_TSADCPHY 218 -#define SRST_CIFLITE_A 220 -#define SRST_CIFLITE_H 221 -#define SRST_CIFLITE_D 222 -#define SRST_CIFLITE_RX_P 223 - -/* cru_softrst_con14 */ -#define SRST_TOPNIU_P 224 -#define SRST_TOPCRU_P 225 -#define SRST_TOPGRF_P 226 -#define SRST_CPUEMADET_P 227 -#define SRST_CSIPHY0_P 228 -#define SRST_CSIPHY1_P 229 -#define SRST_DSIPHY_P 230 -#define SRST_CPU_TSADC_P 232 -#define SRST_CPU_TSADC 233 -#define SRST_CPU_TSADCPHY 234 -#define SRST_CPUPVTM_P 235 -#define SRST_CPUPVTM 236 - -#endif

Drop in favour of dts/upstream.

Small driver and DTS adjustments to use upstream headers.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/exynos7420.dtsi | 2 +- drivers/clk/exynos/clk-exynos7420.c | 2 +- include/dt-bindings/clock/exynos7420-clk.h | 207 ---------------- include/dt-bindings/clock/exynos850.h | 337 --------------------------- include/dt-bindings/soc/samsung,exynos-usi.h | 17 -- 5 files changed, 2 insertions(+), 563 deletions(-)

diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi index 373f48cf2eca..ba9666f3de01 100644 --- a/arch/arm/dts/exynos7420.dtsi +++ b/arch/arm/dts/exynos7420.dtsi @@ -7,9 +7,9 @@ */

/dts-v1/; #include "skeleton.dtsi" -#include <dt-bindings/clock/exynos7420-clk.h> +#include <dt-bindings/clock/exynos7-clk.h> / { compatible = "samsung,exynos7420";

fin_pll: xxti { diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 9caa932e12fb..cd6d67a0752b 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -10,9 +10,9 @@ #include <errno.h> #include <clk-uclass.h> #include <asm/io.h> #include <div64.h> -#include <dt-bindings/clock/exynos7420-clk.h> +#include <dt-bindings/clock/exynos7-clk.h>

#define PLL145X_MDIV_SHIFT 16 #define PLL145X_MDIV_MASK 0x3ff #define PLL145X_PDIV_SHIFT 8 diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h deleted file mode 100644 index 10c558611085..000000000000 --- a/include/dt-bindings/clock/exynos7420-clk.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Naveen Krishna Ch naveenkrishna.ch@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H -#define _DT_BINDINGS_CLOCK_EXYNOS7_H - -/* TOPC */ -#define DOUT_ACLK_PERIS 1 -#define DOUT_SCLK_BUS0_PLL 2 -#define DOUT_SCLK_BUS1_PLL 3 -#define DOUT_SCLK_CC_PLL 4 -#define DOUT_SCLK_MFC_PLL 5 -#define DOUT_ACLK_CCORE_133 6 -#define DOUT_ACLK_MSCL_532 7 -#define ACLK_MSCL_532 8 -#define DOUT_SCLK_AUD_PLL 9 -#define FOUT_AUD_PLL 10 -#define SCLK_AUD_PLL 11 -#define SCLK_MFC_PLL_B 12 -#define SCLK_MFC_PLL_A 13 -#define SCLK_BUS1_PLL_B 14 -#define SCLK_BUS1_PLL_A 15 -#define SCLK_BUS0_PLL_B 16 -#define SCLK_BUS0_PLL_A 17 -#define SCLK_CC_PLL_B 18 -#define SCLK_CC_PLL_A 19 -#define ACLK_CCORE_133 20 -#define ACLK_PERIS_66 21 -#define TOPC_NR_CLK 22 - -/* TOP0 */ -#define DOUT_ACLK_PERIC1 1 -#define DOUT_ACLK_PERIC0 2 -#define CLK_SCLK_UART0 3 -#define CLK_SCLK_UART1 4 -#define CLK_SCLK_UART2 5 -#define CLK_SCLK_UART3 6 -#define CLK_SCLK_SPI0 7 -#define CLK_SCLK_SPI1 8 -#define CLK_SCLK_SPI2 9 -#define CLK_SCLK_SPI3 10 -#define CLK_SCLK_SPI4 11 -#define CLK_SCLK_SPDIF 12 -#define CLK_SCLK_PCM1 13 -#define CLK_SCLK_I2S1 14 -#define CLK_ACLK_PERIC0_66 15 -#define CLK_ACLK_PERIC1_66 16 -#define TOP0_NR_CLK 17 - -/* TOP1 */ -#define DOUT_ACLK_FSYS1_200 1 -#define DOUT_ACLK_FSYS0_200 2 -#define DOUT_SCLK_MMC2 3 -#define DOUT_SCLK_MMC1 4 -#define DOUT_SCLK_MMC0 5 -#define CLK_SCLK_MMC2 6 -#define CLK_SCLK_MMC1 7 -#define CLK_SCLK_MMC0 8 -#define CLK_ACLK_FSYS0_200 9 -#define CLK_ACLK_FSYS1_200 10 -#define CLK_SCLK_PHY_FSYS1 11 -#define CLK_SCLK_PHY_FSYS1_26M 12 -#define MOUT_SCLK_UFSUNIPRO20 13 -#define DOUT_SCLK_UFSUNIPRO20 14 -#define CLK_SCLK_UFSUNIPRO20 15 -#define DOUT_SCLK_PHY_FSYS1 16 -#define DOUT_SCLK_PHY_FSYS1_26M 17 -#define TOP1_NR_CLK 18 - -/* CCORE */ -#define PCLK_RTC 1 -#define CCORE_NR_CLK 2 - -/* PERIC0 */ -#define PCLK_UART0 1 -#define SCLK_UART0 2 -#define PCLK_HSI2C0 3 -#define PCLK_HSI2C1 4 -#define PCLK_HSI2C4 5 -#define PCLK_HSI2C5 6 -#define PCLK_HSI2C9 7 -#define PCLK_HSI2C10 8 -#define PCLK_HSI2C11 9 -#define PCLK_PWM 10 -#define SCLK_PWM 11 -#define PCLK_ADCIF 12 -#define PERIC0_NR_CLK 13 - -/* PERIC1 */ -#define PCLK_UART1 1 -#define PCLK_UART2 2 -#define PCLK_UART3 3 -#define SCLK_UART1 4 -#define SCLK_UART2 5 -#define SCLK_UART3 6 -#define PCLK_HSI2C2 7 -#define PCLK_HSI2C3 8 -#define PCLK_HSI2C6 9 -#define PCLK_HSI2C7 10 -#define PCLK_HSI2C8 11 -#define PCLK_SPI0 12 -#define PCLK_SPI1 13 -#define PCLK_SPI2 14 -#define PCLK_SPI3 15 -#define PCLK_SPI4 16 -#define SCLK_SPI0 17 -#define SCLK_SPI1 18 -#define SCLK_SPI2 19 -#define SCLK_SPI3 20 -#define SCLK_SPI4 21 -#define PCLK_I2S1 22 -#define PCLK_PCM1 23 -#define PCLK_SPDIF 24 -#define SCLK_I2S1 25 -#define SCLK_PCM1 26 -#define SCLK_SPDIF 27 -#define PERIC1_NR_CLK 28 - -/* PERIS */ -#define PCLK_CHIPID 1 -#define SCLK_CHIPID 2 -#define PCLK_WDT 3 -#define PCLK_TMU 4 -#define SCLK_TMU 5 -#define PERIS_NR_CLK 6 - -/* FSYS0 */ -#define ACLK_MMC2 1 -#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 -#define ACLK_USBDRD300 3 -#define SCLK_USBDRD300_SUSPENDCLK 4 -#define SCLK_USBDRD300_REFCLK 5 -#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 -#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 -#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 -#define ACLK_PDMA0 9 -#define ACLK_PDMA1 10 -#define FSYS0_NR_CLK 11 - -/* FSYS1 */ -#define ACLK_MMC1 1 -#define ACLK_MMC0 2 -#define PHYCLK_UFS20_TX0_SYMBOL 3 -#define PHYCLK_UFS20_RX0_SYMBOL 4 -#define PHYCLK_UFS20_RX1_SYMBOL 5 -#define ACLK_UFS20_LINK 6 -#define SCLK_UFSUNIPRO20_USER 7 -#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 -#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 -#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 -#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 -#define SCLK_COMBO_PHY_EMBEDDED_26M 12 -#define DOUT_PCLK_FSYS1 13 -#define PCLK_GPIO_FSYS1 14 -#define MOUT_FSYS1_PHYCLK_SEL1 15 -#define FSYS1_NR_CLK 16 - -/* MSCL */ -#define USERMUX_ACLK_MSCL_532 1 -#define DOUT_PCLK_MSCL 2 -#define ACLK_MSCL_0 3 -#define ACLK_MSCL_1 4 -#define ACLK_JPEG 5 -#define ACLK_G2D 6 -#define ACLK_LH_ASYNC_SI_MSCL_0 7 -#define ACLK_LH_ASYNC_SI_MSCL_1 8 -#define ACLK_AXI2ACEL_BRIDGE 9 -#define ACLK_XIU_MSCLX_0 10 -#define ACLK_XIU_MSCLX_1 11 -#define ACLK_QE_MSCL_0 12 -#define ACLK_QE_MSCL_1 13 -#define ACLK_QE_JPEG 14 -#define ACLK_QE_G2D 15 -#define ACLK_PPMU_MSCL_0 16 -#define ACLK_PPMU_MSCL_1 17 -#define ACLK_MSCLNP_133 18 -#define ACLK_AHB2APB_MSCL0P 19 -#define ACLK_AHB2APB_MSCL1P 20 - -#define PCLK_MSCL_0 21 -#define PCLK_MSCL_1 22 -#define PCLK_JPEG 23 -#define PCLK_G2D 24 -#define PCLK_QE_MSCL_0 25 -#define PCLK_QE_MSCL_1 26 -#define PCLK_QE_JPEG 27 -#define PCLK_QE_G2D 28 -#define PCLK_PPMU_MSCL_0 29 -#define PCLK_PPMU_MSCL_1 30 -#define PCLK_AXI2ACEL_BRIDGE 31 -#define PCLK_PMU_MSCL 32 -#define MSCL_NR_CLK 33 - -/* AUD */ -#define SCLK_I2S 1 -#define SCLK_PCM 2 -#define PCLK_I2S 3 -#define PCLK_PCM 4 -#define ACLK_ADMA 5 -#define AUD_NR_CLK 6 -#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h deleted file mode 100644 index 3090e09c9a55..000000000000 --- a/include/dt-bindings/clock/exynos850.h +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2021 Linaro Ltd. - * Author: Sam Protsenko semen.protsenko@linaro.org - * - * Device Tree binding constants for Exynos850 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H -#define _DT_BINDINGS_CLOCK_EXYNOS_850_H - -/* CMU_TOP */ -#define CLK_FOUT_SHARED0_PLL 1 -#define CLK_FOUT_SHARED1_PLL 2 -#define CLK_FOUT_MMC_PLL 3 -#define CLK_MOUT_SHARED0_PLL 4 -#define CLK_MOUT_SHARED1_PLL 5 -#define CLK_MOUT_MMC_PLL 6 -#define CLK_MOUT_CORE_BUS 7 -#define CLK_MOUT_CORE_CCI 8 -#define CLK_MOUT_CORE_MMC_EMBD 9 -#define CLK_MOUT_CORE_SSS 10 -#define CLK_MOUT_DPU 11 -#define CLK_MOUT_HSI_BUS 12 -#define CLK_MOUT_HSI_MMC_CARD 13 -#define CLK_MOUT_HSI_USB20DRD 14 -#define CLK_MOUT_PERI_BUS 15 -#define CLK_MOUT_PERI_UART 16 -#define CLK_MOUT_PERI_IP 17 -#define CLK_DOUT_SHARED0_DIV3 18 -#define CLK_DOUT_SHARED0_DIV2 19 -#define CLK_DOUT_SHARED1_DIV3 20 -#define CLK_DOUT_SHARED1_DIV2 21 -#define CLK_DOUT_SHARED0_DIV4 22 -#define CLK_DOUT_SHARED1_DIV4 23 -#define CLK_DOUT_CORE_BUS 24 -#define CLK_DOUT_CORE_CCI 25 -#define CLK_DOUT_CORE_MMC_EMBD 26 -#define CLK_DOUT_CORE_SSS 27 -#define CLK_DOUT_DPU 28 -#define CLK_DOUT_HSI_BUS 29 -#define CLK_DOUT_HSI_MMC_CARD 30 -#define CLK_DOUT_HSI_USB20DRD 31 -#define CLK_DOUT_PERI_BUS 32 -#define CLK_DOUT_PERI_UART 33 -#define CLK_DOUT_PERI_IP 34 -#define CLK_GOUT_CORE_BUS 35 -#define CLK_GOUT_CORE_CCI 36 -#define CLK_GOUT_CORE_MMC_EMBD 37 -#define CLK_GOUT_CORE_SSS 38 -#define CLK_GOUT_DPU 39 -#define CLK_GOUT_HSI_BUS 40 -#define CLK_GOUT_HSI_MMC_CARD 41 -#define CLK_GOUT_HSI_USB20DRD 42 -#define CLK_GOUT_PERI_BUS 43 -#define CLK_GOUT_PERI_UART 44 -#define CLK_GOUT_PERI_IP 45 -#define CLK_MOUT_CLKCMU_APM_BUS 46 -#define CLK_DOUT_CLKCMU_APM_BUS 47 -#define CLK_GOUT_CLKCMU_APM_BUS 48 -#define CLK_MOUT_AUD 49 -#define CLK_GOUT_AUD 50 -#define CLK_DOUT_AUD 51 -#define CLK_MOUT_IS_BUS 52 -#define CLK_MOUT_IS_ITP 53 -#define CLK_MOUT_IS_VRA 54 -#define CLK_MOUT_IS_GDC 55 -#define CLK_GOUT_IS_BUS 56 -#define CLK_GOUT_IS_ITP 57 -#define CLK_GOUT_IS_VRA 58 -#define CLK_GOUT_IS_GDC 59 -#define CLK_DOUT_IS_BUS 60 -#define CLK_DOUT_IS_ITP 61 -#define CLK_DOUT_IS_VRA 62 -#define CLK_DOUT_IS_GDC 63 -#define CLK_MOUT_MFCMSCL_MFC 64 -#define CLK_MOUT_MFCMSCL_M2M 65 -#define CLK_MOUT_MFCMSCL_MCSC 66 -#define CLK_MOUT_MFCMSCL_JPEG 67 -#define CLK_GOUT_MFCMSCL_MFC 68 -#define CLK_GOUT_MFCMSCL_M2M 69 -#define CLK_GOUT_MFCMSCL_MCSC 70 -#define CLK_GOUT_MFCMSCL_JPEG 71 -#define CLK_DOUT_MFCMSCL_MFC 72 -#define CLK_DOUT_MFCMSCL_M2M 73 -#define CLK_DOUT_MFCMSCL_MCSC 74 -#define CLK_DOUT_MFCMSCL_JPEG 75 -#define CLK_MOUT_G3D_SWITCH 76 -#define CLK_GOUT_G3D_SWITCH 77 -#define CLK_DOUT_G3D_SWITCH 78 - -/* CMU_APM */ -#define CLK_RCO_I3C_PMIC 1 -#define OSCCLK_RCO_APM 2 -#define CLK_RCO_APM__ALV 3 -#define CLK_DLL_DCO 4 -#define CLK_MOUT_APM_BUS_USER 5 -#define CLK_MOUT_RCO_APM_I3C_USER 6 -#define CLK_MOUT_RCO_APM_USER 7 -#define CLK_MOUT_DLL_USER 8 -#define CLK_MOUT_CLKCMU_CHUB_BUS 9 -#define CLK_MOUT_APM_BUS 10 -#define CLK_MOUT_APM_I3C 11 -#define CLK_DOUT_CLKCMU_CHUB_BUS 12 -#define CLK_DOUT_APM_BUS 13 -#define CLK_DOUT_APM_I3C 14 -#define CLK_GOUT_CLKCMU_CMGP_BUS 15 -#define CLK_GOUT_CLKCMU_CHUB_BUS 16 -#define CLK_GOUT_RTC_PCLK 17 -#define CLK_GOUT_TOP_RTC_PCLK 18 -#define CLK_GOUT_I3C_PCLK 19 -#define CLK_GOUT_I3C_SCLK 20 -#define CLK_GOUT_SPEEDY_PCLK 21 -#define CLK_GOUT_GPIO_ALIVE_PCLK 22 -#define CLK_GOUT_PMU_ALIVE_PCLK 23 -#define CLK_GOUT_SYSREG_APM_PCLK 24 - -/* CMU_AUD */ -#define CLK_DOUT_AUD_AUDIF 1 -#define CLK_DOUT_AUD_BUSD 2 -#define CLK_DOUT_AUD_BUSP 3 -#define CLK_DOUT_AUD_CNT 4 -#define CLK_DOUT_AUD_CPU 5 -#define CLK_DOUT_AUD_CPU_ACLK 6 -#define CLK_DOUT_AUD_CPU_PCLKDBG 7 -#define CLK_DOUT_AUD_FM 8 -#define CLK_DOUT_AUD_FM_SPDY 9 -#define CLK_DOUT_AUD_MCLK 10 -#define CLK_DOUT_AUD_UAIF0 11 -#define CLK_DOUT_AUD_UAIF1 12 -#define CLK_DOUT_AUD_UAIF2 13 -#define CLK_DOUT_AUD_UAIF3 14 -#define CLK_DOUT_AUD_UAIF4 15 -#define CLK_DOUT_AUD_UAIF5 16 -#define CLK_DOUT_AUD_UAIF6 17 -#define CLK_FOUT_AUD_PLL 18 -#define CLK_GOUT_AUD_ABOX_ACLK 19 -#define CLK_GOUT_AUD_ASB_CCLK 20 -#define CLK_GOUT_AUD_CA32_CCLK 21 -#define CLK_GOUT_AUD_CNT_BCLK 22 -#define CLK_GOUT_AUD_CODEC_MCLK 23 -#define CLK_GOUT_AUD_DAP_CCLK 24 -#define CLK_GOUT_AUD_GPIO_PCLK 25 -#define CLK_GOUT_AUD_PPMU_ACLK 26 -#define CLK_GOUT_AUD_PPMU_PCLK 27 -#define CLK_GOUT_AUD_SPDY_BCLK 28 -#define CLK_GOUT_AUD_SYSMMU_CLK 29 -#define CLK_GOUT_AUD_SYSREG_PCLK 30 -#define CLK_GOUT_AUD_TZPC_PCLK 31 -#define CLK_GOUT_AUD_UAIF0_BCLK 32 -#define CLK_GOUT_AUD_UAIF1_BCLK 33 -#define CLK_GOUT_AUD_UAIF2_BCLK 34 -#define CLK_GOUT_AUD_UAIF3_BCLK 35 -#define CLK_GOUT_AUD_UAIF4_BCLK 36 -#define CLK_GOUT_AUD_UAIF5_BCLK 37 -#define CLK_GOUT_AUD_UAIF6_BCLK 38 -#define CLK_GOUT_AUD_WDT_PCLK 39 -#define CLK_MOUT_AUD_CPU 40 -#define CLK_MOUT_AUD_CPU_HCH 41 -#define CLK_MOUT_AUD_CPU_USER 42 -#define CLK_MOUT_AUD_FM 43 -#define CLK_MOUT_AUD_PLL 44 -#define CLK_MOUT_AUD_TICK_USB_USER 45 -#define CLK_MOUT_AUD_UAIF0 46 -#define CLK_MOUT_AUD_UAIF1 47 -#define CLK_MOUT_AUD_UAIF2 48 -#define CLK_MOUT_AUD_UAIF3 49 -#define CLK_MOUT_AUD_UAIF4 50 -#define CLK_MOUT_AUD_UAIF5 51 -#define CLK_MOUT_AUD_UAIF6 52 -#define IOCLK_AUDIOCDCLK0 53 -#define IOCLK_AUDIOCDCLK1 54 -#define IOCLK_AUDIOCDCLK2 55 -#define IOCLK_AUDIOCDCLK3 56 -#define IOCLK_AUDIOCDCLK4 57 -#define IOCLK_AUDIOCDCLK5 58 -#define IOCLK_AUDIOCDCLK6 59 -#define TICK_USB 60 -#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 - -/* CMU_CMGP */ -#define CLK_RCO_CMGP 1 -#define CLK_MOUT_CMGP_ADC 2 -#define CLK_MOUT_CMGP_USI0 3 -#define CLK_MOUT_CMGP_USI1 4 -#define CLK_DOUT_CMGP_ADC 5 -#define CLK_DOUT_CMGP_USI0 6 -#define CLK_DOUT_CMGP_USI1 7 -#define CLK_GOUT_CMGP_ADC_S0_PCLK 8 -#define CLK_GOUT_CMGP_ADC_S1_PCLK 9 -#define CLK_GOUT_CMGP_GPIO_PCLK 10 -#define CLK_GOUT_CMGP_USI0_IPCLK 11 -#define CLK_GOUT_CMGP_USI0_PCLK 12 -#define CLK_GOUT_CMGP_USI1_IPCLK 13 -#define CLK_GOUT_CMGP_USI1_PCLK 14 -#define CLK_GOUT_SYSREG_CMGP_PCLK 15 - -/* CMU_G3D */ -#define CLK_FOUT_G3D_PLL 1 -#define CLK_MOUT_G3D_PLL 2 -#define CLK_MOUT_G3D_SWITCH_USER 3 -#define CLK_MOUT_G3D_BUSD 4 -#define CLK_DOUT_G3D_BUSP 5 -#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 -#define CLK_GOUT_G3D_GPU_CLK 7 -#define CLK_GOUT_G3D_TZPC_PCLK 8 -#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 -#define CLK_GOUT_G3D_BUSD_CLK 10 -#define CLK_GOUT_G3D_BUSP_CLK 11 -#define CLK_GOUT_G3D_SYSREG_PCLK 12 - -/* CMU_HSI */ -#define CLK_MOUT_HSI_BUS_USER 1 -#define CLK_MOUT_HSI_MMC_CARD_USER 2 -#define CLK_MOUT_HSI_USB20DRD_USER 3 -#define CLK_MOUT_HSI_RTC 4 -#define CLK_GOUT_USB_RTC_CLK 5 -#define CLK_GOUT_USB_REF_CLK 6 -#define CLK_GOUT_USB_PHY_REF_CLK 7 -#define CLK_GOUT_USB_PHY_ACLK 8 -#define CLK_GOUT_USB_BUS_EARLY_CLK 9 -#define CLK_GOUT_GPIO_HSI_PCLK 10 -#define CLK_GOUT_MMC_CARD_ACLK 11 -#define CLK_GOUT_MMC_CARD_SDCLKIN 12 -#define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define CLK_GOUT_HSI_PPMU_ACLK 14 -#define CLK_GOUT_HSI_PPMU_PCLK 15 -#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 - -/* CMU_IS */ -#define CLK_MOUT_IS_BUS_USER 1 -#define CLK_MOUT_IS_ITP_USER 2 -#define CLK_MOUT_IS_VRA_USER 3 -#define CLK_MOUT_IS_GDC_USER 4 -#define CLK_DOUT_IS_BUSP 5 -#define CLK_GOUT_IS_CMU_IS_PCLK 6 -#define CLK_GOUT_IS_CSIS0_ACLK 7 -#define CLK_GOUT_IS_CSIS1_ACLK 8 -#define CLK_GOUT_IS_CSIS2_ACLK 9 -#define CLK_GOUT_IS_TZPC_PCLK 10 -#define CLK_GOUT_IS_CSIS_DMA_CLK 11 -#define CLK_GOUT_IS_GDC_CLK 12 -#define CLK_GOUT_IS_IPP_CLK 13 -#define CLK_GOUT_IS_ITP_CLK 14 -#define CLK_GOUT_IS_MCSC_CLK 15 -#define CLK_GOUT_IS_VRA_CLK 16 -#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 -#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 -#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 -#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 -#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 -#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 -#define CLK_GOUT_IS_SYSREG_PCLK 23 - -/* CMU_MFCMSCL */ -#define CLK_MOUT_MFCMSCL_MFC_USER 1 -#define CLK_MOUT_MFCMSCL_M2M_USER 2 -#define CLK_MOUT_MFCMSCL_MCSC_USER 3 -#define CLK_MOUT_MFCMSCL_JPEG_USER 4 -#define CLK_DOUT_MFCMSCL_BUSP 5 -#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 -#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 -#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 -#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 -#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 -#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 -#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 -#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 -#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 -#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 - -/* CMU_PERI */ -#define CLK_MOUT_PERI_BUS_USER 1 -#define CLK_MOUT_PERI_UART_USER 2 -#define CLK_MOUT_PERI_HSI2C_USER 3 -#define CLK_MOUT_PERI_SPI_USER 4 -#define CLK_DOUT_PERI_HSI2C0 5 -#define CLK_DOUT_PERI_HSI2C1 6 -#define CLK_DOUT_PERI_HSI2C2 7 -#define CLK_DOUT_PERI_SPI0 8 -#define CLK_GOUT_PERI_HSI2C0 9 -#define CLK_GOUT_PERI_HSI2C1 10 -#define CLK_GOUT_PERI_HSI2C2 11 -#define CLK_GOUT_GPIO_PERI_PCLK 12 -#define CLK_GOUT_HSI2C0_IPCLK 13 -#define CLK_GOUT_HSI2C0_PCLK 14 -#define CLK_GOUT_HSI2C1_IPCLK 15 -#define CLK_GOUT_HSI2C1_PCLK 16 -#define CLK_GOUT_HSI2C2_IPCLK 17 -#define CLK_GOUT_HSI2C2_PCLK 18 -#define CLK_GOUT_I2C0_PCLK 19 -#define CLK_GOUT_I2C1_PCLK 20 -#define CLK_GOUT_I2C2_PCLK 21 -#define CLK_GOUT_I2C3_PCLK 22 -#define CLK_GOUT_I2C4_PCLK 23 -#define CLK_GOUT_I2C5_PCLK 24 -#define CLK_GOUT_I2C6_PCLK 25 -#define CLK_GOUT_MCT_PCLK 26 -#define CLK_GOUT_PWM_MOTOR_PCLK 27 -#define CLK_GOUT_SPI0_IPCLK 28 -#define CLK_GOUT_SPI0_PCLK 29 -#define CLK_GOUT_SYSREG_PERI_PCLK 30 -#define CLK_GOUT_UART_IPCLK 31 -#define CLK_GOUT_UART_PCLK 32 -#define CLK_GOUT_WDT0_PCLK 33 -#define CLK_GOUT_WDT1_PCLK 34 - -/* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_MMC_EMBD_USER 3 -#define CLK_MOUT_CORE_SSS_USER 4 -#define CLK_MOUT_CORE_GIC 5 -#define CLK_DOUT_CORE_BUSP 6 -#define CLK_GOUT_CCI_ACLK 7 -#define CLK_GOUT_GIC_CLK 8 -#define CLK_GOUT_MMC_EMBD_ACLK 9 -#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 -#define CLK_GOUT_SSS_ACLK 11 -#define CLK_GOUT_SSS_PCLK 12 -#define CLK_GOUT_GPIO_CORE_PCLK 13 -#define CLK_GOUT_SYSREG_CORE_PCLK 14 - -/* CMU_DPU */ -#define CLK_MOUT_DPU_USER 1 -#define CLK_DOUT_DPU_BUSP 2 -#define CLK_GOUT_DPU_CMU_DPU_PCLK 3 -#define CLK_GOUT_DPU_DECON0_ACLK 4 -#define CLK_GOUT_DPU_DMA_ACLK 5 -#define CLK_GOUT_DPU_DPP_ACLK 6 -#define CLK_GOUT_DPU_PPMU_ACLK 7 -#define CLK_GOUT_DPU_PPMU_PCLK 8 -#define CLK_GOUT_DPU_SMMU_CLK 9 -#define CLK_GOUT_DPU_SYSREG_PCLK 10 -#define DPU_NR_CLK 11 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h deleted file mode 100644 index a01af169d249..000000000000 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 Linaro Ltd. - * Author: Sam Protsenko semen.protsenko@linaro.org - * - * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). - */ - -#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H -#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H - -#define USI_V2_NONE 0 -#define USI_V2_UART 1 -#define USI_V2_SPI 2 -#define USI_V2_I2C 3 - -#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/net/phy/dp83869.c | 2 + include/dt-bindings/bus/ti-sysc.h | 28 ---- include/dt-bindings/clk/ti-dra7-atl.h | 40 ----- include/dt-bindings/clock/am3.h | 227 ----------------------------- include/dt-bindings/clock/omap4.h | 149 ------------------- include/dt-bindings/clock/omap5.h | 129 ---------------- include/dt-bindings/media/omap3-isp.h | 22 --- include/dt-bindings/mux/ti-serdes.h | 190 ------------------------ include/dt-bindings/net/ti-dp83867.h | 53 ------- include/dt-bindings/net/ti-dp83869.h | 60 -------- include/dt-bindings/phy/phy-ti.h | 21 --- include/dt-bindings/pinctrl/am33xx.h | 172 ---------------------- include/dt-bindings/pinctrl/am43xx.h | 39 ----- include/dt-bindings/pinctrl/omap.h | 91 ------------ include/dt-bindings/reset/ti-syscon.h | 38 ----- include/dt-bindings/soc/ti,sci_pm_domain.h | 9 -- 16 files changed, 2 insertions(+), 1268 deletions(-)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index f9d4782580e9..fa6be1f3ecde 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -105,8 +105,10 @@ #define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6) #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \ GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT) +/* Special flag to indicate clock should be off */ +#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF

/* CFG3 bits */ #define DP83869_CFG3_PORT_MIRROR_EN BIT(0)

diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h deleted file mode 100644 index eae427454374..000000000000 --- a/include/dt-bindings/bus/ti-sysc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* TI sysc interconnect target module defines */ - -/* Generic sysc found on omap2 and later, also known as type1 */ -#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) -#define SYSC_OMAP2_EMUFREE (1 << 5) -#define SYSC_OMAP2_ENAWAKEUP (1 << 2) -#define SYSC_OMAP2_SOFTRESET (1 << 1) -#define SYSC_OMAP2_AUTOIDLE (1 << 0) - -/* Generic sysc found on omap4 and later, also known as type2 */ -#define SYSC_OMAP4_DMADISABLE (1 << 16) -#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ -#define SYSC_OMAP4_SOFTRESET (1 << 0) - -/* SmartReflex sysc found on 36xx and later */ -#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) - -#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) - -/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ -#define SYSC_PRUSS_SUB_MWAIT (1 << 5) -#define SYSC_PRUSS_STANDBY_INIT (1 << 4) - -/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ -#define SYSC_IDLE_FORCE 0 -#define SYSC_IDLE_NO 1 -#define SYSC_IDLE_SMART 2 -#define SYSC_IDLE_SMART_WKUP 3 diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h deleted file mode 100644 index 42dd4164f6f4..000000000000 --- a/include/dt-bindings/clk/ti-dra7-atl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This header provides constants for DRA7 ATL (Audio Tracking Logic) - * - * The constants defined in this header are used in dts files - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * Peter Ujfalusi peter.ujfalusi@ti.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H -#define _DT_BINDINGS_CLK_DRA7_ATL_H - -#define DRA7_ATL_WS_MCASP1_FSR 0 -#define DRA7_ATL_WS_MCASP1_FSX 1 -#define DRA7_ATL_WS_MCASP2_FSR 2 -#define DRA7_ATL_WS_MCASP2_FSX 3 -#define DRA7_ATL_WS_MCASP3_FSX 4 -#define DRA7_ATL_WS_MCASP4_FSX 5 -#define DRA7_ATL_WS_MCASP5_FSX 6 -#define DRA7_ATL_WS_MCASP6_FSX 7 -#define DRA7_ATL_WS_MCASP7_FSX 8 -#define DRA7_ATL_WS_MCASP8_FSX 9 -#define DRA7_ATL_WS_MCASP8_AHCLKX 10 -#define DRA7_ATL_WS_XREF_CLK3 11 -#define DRA7_ATL_WS_XREF_CLK0 12 -#define DRA7_ATL_WS_XREF_CLK1 13 -#define DRA7_ATL_WS_XREF_CLK2 14 -#define DRA7_ATL_WS_OSC1_X1 15 - -#endif diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h deleted file mode 100644 index 86a8806e2140..000000000000 --- a/include/dt-bindings/clock/am3.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2017 Texas Instruments, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_CLK_AM3_H -#define __DT_BINDINGS_CLK_AM3_H - -#define AM3_CLKCTRL_OFFSET 0x0 -#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - -/* l4ls clocks */ -#define AM3_L4LS_CLKCTRL_OFFSET 0x38 -#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) -#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) -#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) -#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) -#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) -#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) -#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) -#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) -#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) -#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) -#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) -#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) -#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) -#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) -#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) -#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) -#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) -#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) -#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) -#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) -#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) -#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) -#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) -#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) -#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) -#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) -#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) -#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) -#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) -#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) -#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) - -/* l3s clocks */ -#define AM3_L3S_CLKCTRL_OFFSET 0x1c -#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) -#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) -#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) -#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) -#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) -#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) - -/* l3 clocks */ -#define AM3_L3_CLKCTRL_OFFSET 0x24 -#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) -#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) -#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) -#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) -#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) -#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) -#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) -#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) -#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) -#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) -#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) - -/* l4hs clocks */ -#define AM3_L4HS_CLKCTRL_OFFSET 0x120 -#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) -#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) - -/* pruss_ocp clocks */ -#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 -#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) - -/* cpsw_125mhz clocks */ -#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) - -/* lcdc clocks */ -#define AM3_LCDC_CLKCTRL_OFFSET 0x18 -#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) -#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) - -/* clk_24mhz clocks */ -#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c -#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) -#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) -#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) -#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) -#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) -#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) -#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) -#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) -#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) -#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) - -/* l3_aon clocks */ -#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 -#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) -#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) - -/* l4_wkup_aon clocks */ -#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 -#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) - -/* mpu clocks */ -#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h deleted file mode 100644 index 88d73be84b94..000000000000 --- a/include/dt-bindings/clock/omap4.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP4_H -#define __DT_BINDINGS_CLK_OMAP4_H - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) - -/* mpuss clocks */ -#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* tesla clocks */ -#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) - -/* l4_ao clocks */ -#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* l3_1 clocks */ -#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_2 clocks */ -#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* ducati clocks */ -#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_dma clocks */ -#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_emif clocks */ -#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* d2d clocks */ -#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l4_cfg clocks */ -#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* l3_instr clocks */ -#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) - -/* ivahd clocks */ -#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* iss clocks */ -#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* l3_dss clocks */ -#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_gfx clocks */ -#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_init clocks */ -#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) -#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) - -/* l4_per clocks */ -#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) -#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) -#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) -#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) -#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) -#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) -#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) -#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) -#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) -#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) -#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) -#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) -#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) -#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) -#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) -#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) -#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) -#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) -#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) - -/* l4_secure clocks */ -#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* l4_wkup clocks */ -#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) - -/* emu_sys clocks */ -#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h deleted file mode 100644 index 41775272fd27..000000000000 --- a/include/dt-bindings/clock/omap5.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP5_H -#define __DT_BINDINGS_CLK_OMAP5_H - -#define OMAP5_CLKCTRL_OFFSET 0x20 -#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) - -/* mpu clocks */ -#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dsp clocks */ -#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) - -/* l3main1 clocks */ -#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3main2 clocks */ -#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) - -/* l4cfg clocks */ -#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) - -/* l3instr clocks */ -#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* l4per clocks */ -#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) -#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) -#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) -#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) -#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) -#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) -#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) -#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) -#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) -#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) -#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) -#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) -#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) -#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) -#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) -#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) -#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) -#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) -#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) -#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) -#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) -#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) -#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) - -/* l4_secure clocks */ -#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* iva clocks */ -#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* gpu clocks */ -#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) -#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) -#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) -#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) - -/* wkupaon clocks */ -#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) - -#endif diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h deleted file mode 100644 index 4e4208462142..000000000000 --- a/include/dt-bindings/media/omap3-isp.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * include/dt-bindings/media/omap3-isp.h - * - * Copyright (C) 2015 Sakari Ailus - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __DT_BINDINGS_OMAP3_ISP_H__ -#define __DT_BINDINGS_OMAP3_ISP_H__ - -#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 -#define OMAP3ISP_PHY_TYPE_CSIPHY 1 - -#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h deleted file mode 100644 index b0b1091aad6d..000000000000 --- a/include/dt-bindings/mux/ti-serdes.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for SERDES MUX for TI SoCs - */ - -#ifndef _DT_BINDINGS_MUX_TI_SERDES -#define _DT_BINDINGS_MUX_TI_SERDES - -/* - * These bindings are deprecated, because they do not match the actual - * concept of bindings but rather contain pure constants values used only - * in DTS board files. - * Instead include the header in the DTS source directory. - */ -#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." - -/* J721E */ - -#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 -#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 -#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 -#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 -#define J721E_SERDES0_LANE1_USB3_0 0x2 -#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 -#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 -#define J721E_SERDES1_LANE1_USB3_1 0x2 -#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 -#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 -#define J721E_SERDES2_LANE1_USB3_1 0x2 -#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 -#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 -#define J721E_SERDES3_LANE1_USB3_0 0x2 -#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 -#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 -#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 -#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 -#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 -#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 -#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 -#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 -#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 - -/* J7200 */ - -#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 -#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 -#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 -#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 -#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J7200_SERDES0_LANE3_USB 0x2 -#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* AM64 */ - -#define AM64_SERDES0_LANE0_PCIE0 0x0 -#define AM64_SERDES0_LANE0_USB 0x1 - -/* J721S2 */ - -#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 -#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 -#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J721S2_SERDES0_LANE1_USB 0x2 -#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 -#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 -#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J721S2_SERDES0_LANE3_USB 0x2 -#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* J784S4 */ - -#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 -#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 -#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J784S4_SERDES0_LANE3_USB 0x2 -#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 -#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 -#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 -#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 -#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 -#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 -#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 -#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 -#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 -#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 -#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 -#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 -#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 -#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 -#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 - -#endif /* _DT_BINDINGS_MUX_TI_SERDES */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h deleted file mode 100644 index 6fc4b445d3a1..000000000000 --- a/include/dt-bindings/net/ti-dp83867.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Texas Instruments DP83867 PHY - * - * Author: Dan Murphy dmurphy@ti.com - * - * Copyright: (C) 2015 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DP83867_H -#define _DT_BINDINGS_TI_DP83867_H - -/* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83867_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF -#endif diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h deleted file mode 100644 index b3a5ac4a17b3..000000000000 --- a/include/dt-bindings/net/ti-dp83869.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * TI DP83869 PHY drivers - * - */ - -#ifndef _DT_BINDINGS_TI_DP83869_H -#define _DT_BINDINGS_TI_DP83869_H - -/* PHY CTRL bits */ -#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83869_RGMIIDCTL_250_PS 0x0 -#define DP83869_RGMIIDCTL_500_PS 0x1 -#define DP83869_RGMIIDCTL_750_PS 0x2 -#define DP83869_RGMIIDCTL_1_NS 0x3 -#define DP83869_RGMIIDCTL_1_25_NS 0x4 -#define DP83869_RGMIIDCTL_1_50_NS 0x5 -#define DP83869_RGMIIDCTL_1_75_NS 0x6 -#define DP83869_RGMIIDCTL_2_00_NS 0x7 -#define DP83869_RGMIIDCTL_2_25_NS 0x8 -#define DP83869_RGMIIDCTL_2_50_NS 0x9 -#define DP83869_RGMIIDCTL_2_75_NS 0xa -#define DP83869_RGMIIDCTL_3_00_NS 0xb -#define DP83869_RGMIIDCTL_3_25_NS 0xc -#define DP83869_RGMIIDCTL_3_50_NS 0xd -#define DP83869_RGMIIDCTL_3_75_NS 0xe -#define DP83869_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83869_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF - -/* OPMODE - Operation mode */ -#define DP83869_RGMII_COPPER_ETHERNET 0x00 -#define DP83869_RGMII_1000_BASE 0x01 -#define DP83869_RGMII_100_BASE 0x02 -#define DP83869_RGMII_SGMII_BRIDGE 0x03 -#define DP83869_1000M_MEDIA_CONVERT 0x04 -#define DP83869_100M_MEDIA_CONVERT 0x05 -#define DP83869_SGMII_COPPER_ETHERNET 0x06 - -#endif diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h deleted file mode 100644 index ad955d3a56b4..000000000000 --- a/include/dt-bindings/phy/phy-ti.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for TI SERDES. - */ - -#ifndef _DT_BINDINGS_TI_SERDES -#define _DT_BINDINGS_TI_SERDES - -/* Clock index for output clocks from WIZ */ - -/* MUX Clocks */ -#define TI_WIZ_PLL0_REFCLK 0 -#define TI_WIZ_PLL1_REFCLK 1 -#define TI_WIZ_REFCLK_DIG 2 - -/* Reserve index here for future additions */ - -/* MISC Clocks */ -#define TI_WIZ_PHY_EN_REFCLK 16 - -#endif /* _DT_BINDINGS_TI_SERDES */ diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h deleted file mode 100644 index 17877e85980b..000000000000 --- a/include/dt-bindings/pinctrl/am33xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to AM33XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H -#define _DT_BINDINGS_PINCTRL_AM33XX_H - -#include <dt-bindings/pinctrl/omap.h> - -/* am33xx specific mux bit defines */ -#undef PULL_ENA -#undef INPUT_EN - -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_SLOW (1 << 6) -#define SLEWCTRL_FAST 0 - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#define AM335X_PIN_OFFSET_MIN 0x0800U - -#define AM335X_PIN_GPMC_AD0 0x800 -#define AM335X_PIN_GPMC_AD1 0x804 -#define AM335X_PIN_GPMC_AD2 0x808 -#define AM335X_PIN_GPMC_AD3 0x80c -#define AM335X_PIN_GPMC_AD4 0x810 -#define AM335X_PIN_GPMC_AD5 0x814 -#define AM335X_PIN_GPMC_AD6 0x818 -#define AM335X_PIN_GPMC_AD7 0x81c -#define AM335X_PIN_GPMC_AD8 0x820 -#define AM335X_PIN_GPMC_AD9 0x824 -#define AM335X_PIN_GPMC_AD10 0x828 -#define AM335X_PIN_GPMC_AD11 0x82c -#define AM335X_PIN_GPMC_AD12 0x830 -#define AM335X_PIN_GPMC_AD13 0x834 -#define AM335X_PIN_GPMC_AD14 0x838 -#define AM335X_PIN_GPMC_AD15 0x83c -#define AM335X_PIN_GPMC_A0 0x840 -#define AM335X_PIN_GPMC_A1 0x844 -#define AM335X_PIN_GPMC_A2 0x848 -#define AM335X_PIN_GPMC_A3 0x84c -#define AM335X_PIN_GPMC_A4 0x850 -#define AM335X_PIN_GPMC_A5 0x854 -#define AM335X_PIN_GPMC_A6 0x858 -#define AM335X_PIN_GPMC_A7 0x85c -#define AM335X_PIN_GPMC_A8 0x860 -#define AM335X_PIN_GPMC_A9 0x864 -#define AM335X_PIN_GPMC_A10 0x868 -#define AM335X_PIN_GPMC_A11 0x86c -#define AM335X_PIN_GPMC_WAIT0 0x870 -#define AM335X_PIN_GPMC_WPN 0x874 -#define AM335X_PIN_GPMC_BEN1 0x878 -#define AM335X_PIN_GPMC_CSN0 0x87c -#define AM335X_PIN_GPMC_CSN1 0x880 -#define AM335X_PIN_GPMC_CSN2 0x884 -#define AM335X_PIN_GPMC_CSN3 0x888 -#define AM335X_PIN_GPMC_CLK 0x88c -#define AM335X_PIN_GPMC_ADVN_ALE 0x890 -#define AM335X_PIN_GPMC_OEN_REN 0x894 -#define AM335X_PIN_GPMC_WEN 0x898 -#define AM335X_PIN_GPMC_BEN0_CLE 0x89c -#define AM335X_PIN_LCD_DATA0 0x8a0 -#define AM335X_PIN_LCD_DATA1 0x8a4 -#define AM335X_PIN_LCD_DATA2 0x8a8 -#define AM335X_PIN_LCD_DATA3 0x8ac -#define AM335X_PIN_LCD_DATA4 0x8b0 -#define AM335X_PIN_LCD_DATA5 0x8b4 -#define AM335X_PIN_LCD_DATA6 0x8b8 -#define AM335X_PIN_LCD_DATA7 0x8bc -#define AM335X_PIN_LCD_DATA8 0x8c0 -#define AM335X_PIN_LCD_DATA9 0x8c4 -#define AM335X_PIN_LCD_DATA10 0x8c8 -#define AM335X_PIN_LCD_DATA11 0x8cc -#define AM335X_PIN_LCD_DATA12 0x8d0 -#define AM335X_PIN_LCD_DATA13 0x8d4 -#define AM335X_PIN_LCD_DATA14 0x8d8 -#define AM335X_PIN_LCD_DATA15 0x8dc -#define AM335X_PIN_LCD_VSYNC 0x8e0 -#define AM335X_PIN_LCD_HSYNC 0x8e4 -#define AM335X_PIN_LCD_PCLK 0x8e8 -#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec -#define AM335X_PIN_MMC0_DAT3 0x8f0 -#define AM335X_PIN_MMC0_DAT2 0x8f4 -#define AM335X_PIN_MMC0_DAT1 0x8f8 -#define AM335X_PIN_MMC0_DAT0 0x8fc -#define AM335X_PIN_MMC0_CLK 0x900 -#define AM335X_PIN_MMC0_CMD 0x904 -#define AM335X_PIN_MII1_COL 0x908 -#define AM335X_PIN_MII1_CRS 0x90c -#define AM335X_PIN_MII1_RX_ER 0x910 -#define AM335X_PIN_MII1_TX_EN 0x914 -#define AM335X_PIN_MII1_RX_DV 0x918 -#define AM335X_PIN_MII1_TXD3 0x91c -#define AM335X_PIN_MII1_TXD2 0x920 -#define AM335X_PIN_MII1_TXD1 0x924 -#define AM335X_PIN_MII1_TXD0 0x928 -#define AM335X_PIN_MII1_TX_CLK 0x92c -#define AM335X_PIN_MII1_RX_CLK 0x930 -#define AM335X_PIN_MII1_RXD3 0x934 -#define AM335X_PIN_MII1_RXD2 0x938 -#define AM335X_PIN_MII1_RXD1 0x93c -#define AM335X_PIN_MII1_RXD0 0x940 -#define AM335X_PIN_RMII1_REF_CLK 0x944 -#define AM335X_PIN_MDIO 0x948 -#define AM335X_PIN_MDC 0x94c -#define AM335X_PIN_SPI0_SCLK 0x950 -#define AM335X_PIN_SPI0_D0 0x954 -#define AM335X_PIN_SPI0_D1 0x958 -#define AM335X_PIN_SPI0_CS0 0x95c -#define AM335X_PIN_SPI0_CS1 0x960 -#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 -#define AM335X_PIN_UART0_CTSN 0x968 -#define AM335X_PIN_UART0_RTSN 0x96c -#define AM335X_PIN_UART0_RXD 0x970 -#define AM335X_PIN_UART0_TXD 0x974 -#define AM335X_PIN_UART1_CTSN 0x978 -#define AM335X_PIN_UART1_RTSN 0x97c -#define AM335X_PIN_UART1_RXD 0x980 -#define AM335X_PIN_UART1_TXD 0x984 -#define AM335X_PIN_I2C0_SDA 0x988 -#define AM335X_PIN_I2C0_SCL 0x98c -#define AM335X_PIN_MCASP0_ACLKX 0x990 -#define AM335X_PIN_MCASP0_FSX 0x994 -#define AM335X_PIN_MCASP0_AXR0 0x998 -#define AM335X_PIN_MCASP0_AHCLKR 0x99c -#define AM335X_PIN_MCASP0_ACLKR 0x9a0 -#define AM335X_PIN_MCASP0_FSR 0x9a4 -#define AM335X_PIN_MCASP0_AXR1 0x9a8 -#define AM335X_PIN_MCASP0_AHCLKX 0x9ac -#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 -#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 -#define AM335X_PIN_WARMRSTN 0x9b8 -#define AM335X_PIN_NNMI 0x9c0 -#define AM335X_PIN_TMS 0x9d0 -#define AM335X_PIN_TDI 0x9d4 -#define AM335X_PIN_TDO 0x9d8 -#define AM335X_PIN_TCK 0x9dc -#define AM335X_PIN_TRSTN 0x9e0 -#define AM335X_PIN_EMU0 0x9e4 -#define AM335X_PIN_EMU1 0x9e8 -#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 -#define AM335X_PIN_PMIC_POWER_EN 0x9fc -#define AM335X_PIN_EXT_WAKEUP 0xa00 -#define AM335X_PIN_USB0_DRVVBUS 0xa1c -#define AM335X_PIN_USB1_DRVVBUS 0xa34 - -#define AM335X_PIN_OFFSET_MAX 0x0a34U - -#endif diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h deleted file mode 100644 index 292c2ebf58dd..000000000000 --- a/include/dt-bindings/pinctrl/am43xx.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This header provides constants specific to AM43XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H -#define _DT_BINDINGS_PINCTRL_AM43XX_H - -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE8 8 - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_SLOW (1 << 19) -#define SLEWCTRL_FAST 0 -#define DS0_PULL_UP_DOWN_EN (1 << 27) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) - -#endif diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h deleted file mode 100644 index 4c060ee0e0ad..000000000000 --- a/include/dt-bindings/pinctrl/omap.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for OMAP pinctrl bindings. - * - * Copyright (C) 2009 Nokia - * Copyright (C) 2009-2010 Texas Instruments - */ - -#ifndef _DT_BINDINGS_PINCTRL_OMAP_H -#define _DT_BINDINGS_PINCTRL_OMAP_H - -/* 34xx mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) - -/* omap3/4/5 specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) -#define WAKEUP_EVENT (1 << 15) - -/* Active pin states */ -#define PIN_OUTPUT 0 -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* Off mode states */ -#define PIN_OFF_NONE 0 -#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) -#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) -#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) -#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) -#define PIN_OFF_WAKEUPENABLE WAKEUP_EN - -/* - * Macros to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) - -#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) -#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) -#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) -#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) -#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) -#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) - -/* - * Macros to allow using the offset from the padconf physical address - * instead of the offset from padconf base. - */ -#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) - -#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) -#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) - -/* - * Define some commonly used pins configured by the boards. - * Note that some boards use alternative pins, so check - * the schematics before using these. - */ -#define OMAP3_UART1_RX 0x152 -#define OMAP3_UART2_RX 0x14a -#define OMAP3_UART3_RX 0x16e -#define OMAP4_UART2_RX 0xdc -#define OMAP4_UART3_RX 0x104 -#define OMAP4_UART4_RX 0x11c - -#endif diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h deleted file mode 100644 index 1427ff140f11..000000000000 --- a/include/dt-bindings/reset/ti-syscon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * TI Syscon Reset definitions - * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ -#define __DT_BINDINGS_RESET_TI_SYSCON_H__ - -/* - * The reset does not support the feature and corresponding - * values are not valid - */ -#define ASSERT_NONE (1 << 0) -#define DEASSERT_NONE (1 << 1) -#define STATUS_NONE (1 << 2) - -/* When set this function is activated by setting(vs clearing) this bit */ -#define ASSERT_SET (1 << 3) -#define DEASSERT_SET (1 << 4) -#define STATUS_SET (1 << 5) - -/* The following are the inverse of the above and are added for consistency */ -#define ASSERT_CLEAR (0 << 3) -#define DEASSERT_CLEAR (0 << 4) -#define STATUS_CLEAR (0 << 5) - -#endif diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h deleted file mode 100644 index 8f2a7360b65e..000000000000 --- a/include/dt-bindings/soc/ti,sci_pm_domain.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H -#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H - -#define TI_SCI_PD_EXCLUSIVE 1 -#define TI_SCI_PD_SHARED 0 - -#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */

Drop in favour of dts/upstream.

Small driver adjustment to fix compatibility.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/tegra186.dtsi | 2 +- drivers/mailbox/tegra-hsp.c | 2 +- include/dt-bindings/gpio/tegra-gpio.h | 51 ------ include/dt-bindings/mailbox/tegra186-hsp.h | 19 --- include/dt-bindings/memory/tegra114-mc.h | 25 --- include/dt-bindings/memory/tegra124-mc.h | 31 ---- include/dt-bindings/memory/tegra210-mc.h | 36 ---- include/dt-bindings/memory/tegra30-mc.h | 24 --- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 - include/dt-bindings/pinctrl/pinctrl-tegra.h | 37 ---- include/dt-bindings/power/tegra186-powergate.h | 28 ---- include/dt-bindings/reset/tegra124-car.h | 12 -- include/dt-bindings/reset/tegra186-reset.h | 205 ----------------------- include/dt-bindings/thermal/tegra124-soctherm.h | 14 -- 14 files changed, 2 insertions(+), 491 deletions(-)

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index edcb7aacb8ee..58dadc944888 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -313,9 +313,9 @@ };

bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + mboxes = <&hsp TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; /* * In theory, these references, and the configuration in the * node these reference point at, are board-specific, since * they depend on the BCT's memory carve-out setup, the diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 08c51c40f141..e5a3d8243780 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -62,9 +62,9 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,

static int tegra_hsp_db_id(ulong chan_id) { switch (chan_id) { - case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP: + case (TEGRA_HSP_MBOX_TYPE_DB << 16) | TEGRA_HSP_DB_MASTER_BPMP: return TEGRA_HSP_DB_ID_BPMP; default: debug("Invalid channel ID\n"); return -EINVAL; diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h deleted file mode 100644 index a1c09e88e80b..000000000000 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra*-gpio. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H - -#include <dt-bindings/gpio/gpio.h> - -#define TEGRA_GPIO_PORT_A 0 -#define TEGRA_GPIO_PORT_B 1 -#define TEGRA_GPIO_PORT_C 2 -#define TEGRA_GPIO_PORT_D 3 -#define TEGRA_GPIO_PORT_E 4 -#define TEGRA_GPIO_PORT_F 5 -#define TEGRA_GPIO_PORT_G 6 -#define TEGRA_GPIO_PORT_H 7 -#define TEGRA_GPIO_PORT_I 8 -#define TEGRA_GPIO_PORT_J 9 -#define TEGRA_GPIO_PORT_K 10 -#define TEGRA_GPIO_PORT_L 11 -#define TEGRA_GPIO_PORT_M 12 -#define TEGRA_GPIO_PORT_N 13 -#define TEGRA_GPIO_PORT_O 14 -#define TEGRA_GPIO_PORT_P 15 -#define TEGRA_GPIO_PORT_Q 16 -#define TEGRA_GPIO_PORT_R 17 -#define TEGRA_GPIO_PORT_S 18 -#define TEGRA_GPIO_PORT_T 19 -#define TEGRA_GPIO_PORT_U 20 -#define TEGRA_GPIO_PORT_V 21 -#define TEGRA_GPIO_PORT_W 22 -#define TEGRA_GPIO_PORT_X 23 -#define TEGRA_GPIO_PORT_Y 24 -#define TEGRA_GPIO_PORT_Z 25 -#define TEGRA_GPIO_PORT_AA 26 -#define TEGRA_GPIO_PORT_BB 27 -#define TEGRA_GPIO_PORT_CC 28 -#define TEGRA_GPIO_PORT_DD 29 -#define TEGRA_GPIO_PORT_EE 30 -#define TEGRA_GPIO_PORT_FF 31 - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h deleted file mode 100644 index b4864325d74b..000000000000 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - * - * The number with HSP_DB_MASTER prefix indicates the bit that is - * associated with a master ID in the doorbell registers. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -#define HSP_MBOX_TYPE_DB 0x0 -#define HSP_MBOX_TYPE_SM 0x1 -#define HSP_MBOX_TYPE_SS 0x2 -#define HSP_MBOX_TYPE_AS 0x3 - -#define HSP_DB_MASTER_CCPLEX 17 -#define HSP_DB_MASTER_BPMP 19 - -#endif diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h deleted file mode 100644 index 8f48985a3139..000000000000 --- a/include/dt-bindings/memory/tegra114-mc.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H -#define DT_BINDINGS_MEMORY_TEGRA114_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_AVPC 5 -#define TEGRA_SWGROUP_NV 6 -#define TEGRA_SWGROUP_HDA 7 -#define TEGRA_SWGROUP_HC 8 -#define TEGRA_SWGROUP_MSENC 9 -#define TEGRA_SWGROUP_PPCS 10 -#define TEGRA_SWGROUP_VDE 11 -#define TEGRA_SWGROUP_MPCORELP 12 -#define TEGRA_SWGROUP_MPCORE 13 -#define TEGRA_SWGROUP_VI 14 -#define TEGRA_SWGROUP_ISP 15 -#define TEGRA_SWGROUP_XUSB_HOST 16 -#define TEGRA_SWGROUP_XUSB_DEV 17 -#define TEGRA_SWGROUP_EMUCIF 18 -#define TEGRA_SWGROUP_TSEC 19 - -#endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h deleted file mode 100644 index 7d8ee798f34e..000000000000 --- a/include/dt-bindings/memory/tegra124-mc.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H -#define DT_BINDINGS_MEMORY_TEGRA124_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_MSENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_VDE 10 -#define TEGRA_SWGROUP_MPCORELP 11 -#define TEGRA_SWGROUP_MPCORE 12 -#define TEGRA_SWGROUP_ISP2 13 -#define TEGRA_SWGROUP_XUSB_HOST 14 -#define TEGRA_SWGROUP_XUSB_DEV 15 -#define TEGRA_SWGROUP_ISP2B 16 -#define TEGRA_SWGROUP_TSEC 17 -#define TEGRA_SWGROUP_A9AVP 18 -#define TEGRA_SWGROUP_GPU 19 -#define TEGRA_SWGROUP_SDMMC1A 20 -#define TEGRA_SWGROUP_SDMMC2A 21 -#define TEGRA_SWGROUP_SDMMC3A 22 -#define TEGRA_SWGROUP_SDMMC4A 23 -#define TEGRA_SWGROUP_VIC 24 -#define TEGRA_SWGROUP_VI 25 - -#endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h deleted file mode 100644 index d1731bc14dbc..000000000000 --- a/include/dt-bindings/memory/tegra210-mc.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H -#define DT_BINDINGS_MEMORY_TEGRA210_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_NVENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_MPCORE 10 -#define TEGRA_SWGROUP_ISP2 11 -#define TEGRA_SWGROUP_XUSB_HOST 12 -#define TEGRA_SWGROUP_XUSB_DEV 13 -#define TEGRA_SWGROUP_ISP2B 14 -#define TEGRA_SWGROUP_TSEC 15 -#define TEGRA_SWGROUP_A9AVP 16 -#define TEGRA_SWGROUP_GPU 17 -#define TEGRA_SWGROUP_SDMMC1A 18 -#define TEGRA_SWGROUP_SDMMC2A 19 -#define TEGRA_SWGROUP_SDMMC3A 20 -#define TEGRA_SWGROUP_SDMMC4A 21 -#define TEGRA_SWGROUP_VIC 22 -#define TEGRA_SWGROUP_VI 23 -#define TEGRA_SWGROUP_NVDEC 24 -#define TEGRA_SWGROUP_APE 25 -#define TEGRA_SWGROUP_NVJPG 26 -#define TEGRA_SWGROUP_SE 27 -#define TEGRA_SWGROUP_AXIAP 28 -#define TEGRA_SWGROUP_ETR 29 -#define TEGRA_SWGROUP_TSECB 30 - -#endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h deleted file mode 100644 index 502beb03d777..000000000000 --- a/include/dt-bindings/memory/tegra30-mc.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H -#define DT_BINDINGS_MEMORY_TEGRA30_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_MPE 5 -#define TEGRA_SWGROUP_VI 6 -#define TEGRA_SWGROUP_AFI 7 -#define TEGRA_SWGROUP_AVPC 8 -#define TEGRA_SWGROUP_NV 9 -#define TEGRA_SWGROUP_NV2 10 -#define TEGRA_SWGROUP_HDA 11 -#define TEGRA_SWGROUP_HC 12 -#define TEGRA_SWGROUP_PPCS 13 -#define TEGRA_SWGROUP_SATA 14 -#define TEGRA_SWGROUP_VDE 15 -#define TEGRA_SWGROUP_MPCORELP 16 -#define TEGRA_SWGROUP_MPCORE 17 -#define TEGRA_SWGROUP_ISP 18 - -#endif diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h deleted file mode 100644 index 914d56da9324..000000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H -#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 - -#define TEGRA_XUSB_PADCTL_PCIE 0 -#define TEGRA_XUSB_PADCTL_SATA 1 - -#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h deleted file mode 100644 index c9b57408de68..000000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for Tegra pinctrl bindings. - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * Author: Laxman Dewangan ldewangan@nvidia.com - */ - -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H -#define _DT_BINDINGS_PINCTRL_TEGRA_H - -/* - * Enable/disable for diffeent dt properties. This is applicable for - * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, - * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. - */ -#define TEGRA_PIN_DISABLE 0 -#define TEGRA_PIN_ENABLE 1 - -#define TEGRA_PIN_PULL_NONE 0 -#define TEGRA_PIN_PULL_DOWN 1 -#define TEGRA_PIN_PULL_UP 2 - -/* Low power mode driver */ -#define TEGRA_PIN_LP_DRIVE_DIV_8 0 -#define TEGRA_PIN_LP_DRIVE_DIV_4 1 -#define TEGRA_PIN_LP_DRIVE_DIV_2 2 -#define TEGRA_PIN_LP_DRIVE_DIV_1 3 - -/* Rising/Falling slew rate */ -#define TEGRA_PIN_SLEW_RATE_FASTEST 0 -#define TEGRA_PIN_SLEW_RATE_FAST 1 -#define TEGRA_PIN_SLEW_RATE_SLOW 2 -#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 - -#endif diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h deleted file mode 100644 index 17e75498563c..000000000000 --- a/include/dt-bindings/power/tegra186-powergate.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. - */ - -#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H -#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H - -#define TEGRA186_POWER_DOMAIN_AUD 0 -#define TEGRA186_POWER_DOMAIN_DFD 1 -#define TEGRA186_POWER_DOMAIN_DISP 2 -#define TEGRA186_POWER_DOMAIN_DISPB 3 -#define TEGRA186_POWER_DOMAIN_DISPC 4 -#define TEGRA186_POWER_DOMAIN_ISPA 5 -#define TEGRA186_POWER_DOMAIN_NVDEC 6 -#define TEGRA186_POWER_DOMAIN_NVJPG 7 -#define TEGRA186_POWER_DOMAIN_MPE 8 -#define TEGRA186_POWER_DOMAIN_PCX 9 -#define TEGRA186_POWER_DOMAIN_SAX 10 -#define TEGRA186_POWER_DOMAIN_VE 11 -#define TEGRA186_POWER_DOMAIN_VIC 12 -#define TEGRA186_POWER_DOMAIN_XUSBA 13 -#define TEGRA186_POWER_DOMAIN_XUSBB 14 -#define TEGRA186_POWER_DOMAIN_XUSBC 15 -#define TEGRA186_POWER_DOMAIN_GPU 43 -#define TEGRA186_POWER_DOMAIN_MAX 44 - -#endif diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h deleted file mode 100644 index 070e4f6e7486..000000000000 --- a/include/dt-bindings/reset/tegra124-car.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H -#define _DT_BINDINGS_RESET_TEGRA124_CAR_H - -#define TEGRA124_RESET(x) (6 * 32 + (x)) -#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) - -#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h deleted file mode 100644 index 7efec9200532..000000000000 --- a/include/dt-bindings/reset/tegra186-reset.h +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. - */ - -#ifndef _ABI_MACH_T186_RESET_T186_H_ -#define _ABI_MACH_T186_RESET_T186_H_ - -#define TEGRA186_RESET_ACTMON 0 -#define TEGRA186_RESET_AFI 1 -#define TEGRA186_RESET_CEC 2 -#define TEGRA186_RESET_CSITE 3 -#define TEGRA186_RESET_DP2 4 -#define TEGRA186_RESET_DPAUX 5 -#define TEGRA186_RESET_DSI 6 -#define TEGRA186_RESET_DSIB 7 -#define TEGRA186_RESET_DTV 8 -#define TEGRA186_RESET_DVFS 9 -#define TEGRA186_RESET_ENTROPY 10 -#define TEGRA186_RESET_EXTPERIPH1 11 -#define TEGRA186_RESET_EXTPERIPH2 12 -#define TEGRA186_RESET_EXTPERIPH3 13 -#define TEGRA186_RESET_GPU 14 -#define TEGRA186_RESET_HDA 15 -#define TEGRA186_RESET_HDA2CODEC_2X 16 -#define TEGRA186_RESET_HDA2HDMICODEC 17 -#define TEGRA186_RESET_HOST1X 18 -#define TEGRA186_RESET_I2C1 19 -#define TEGRA186_RESET_I2C2 20 -#define TEGRA186_RESET_I2C3 21 -#define TEGRA186_RESET_I2C4 22 -#define TEGRA186_RESET_I2C5 23 -#define TEGRA186_RESET_I2C6 24 -#define TEGRA186_RESET_ISP 25 -#define TEGRA186_RESET_KFUSE 26 -#define TEGRA186_RESET_LA 27 -#define TEGRA186_RESET_MIPI_CAL 28 -#define TEGRA186_RESET_PCIE 29 -#define TEGRA186_RESET_PCIEXCLK 30 -#define TEGRA186_RESET_SATA 31 -#define TEGRA186_RESET_SATACOLD 32 -#define TEGRA186_RESET_SDMMC1 33 -#define TEGRA186_RESET_SDMMC2 34 -#define TEGRA186_RESET_SDMMC3 35 -#define TEGRA186_RESET_SDMMC4 36 -#define TEGRA186_RESET_SE 37 -#define TEGRA186_RESET_SOC_THERM 38 -#define TEGRA186_RESET_SOR0 39 -#define TEGRA186_RESET_SPI1 40 -#define TEGRA186_RESET_SPI2 41 -#define TEGRA186_RESET_SPI3 42 -#define TEGRA186_RESET_SPI4 43 -#define TEGRA186_RESET_TMR 44 -#define TEGRA186_RESET_TRIG_SYS 45 -#define TEGRA186_RESET_TSEC 46 -#define TEGRA186_RESET_UARTA 47 -#define TEGRA186_RESET_UARTB 48 -#define TEGRA186_RESET_UARTC 49 -#define TEGRA186_RESET_UARTD 50 -#define TEGRA186_RESET_VI 51 -#define TEGRA186_RESET_VIC 52 -#define TEGRA186_RESET_XUSB_DEV 53 -#define TEGRA186_RESET_XUSB_HOST 54 -#define TEGRA186_RESET_XUSB_PADCTL 55 -#define TEGRA186_RESET_XUSB_SS 56 -#define TEGRA186_RESET_AON_APB 57 -#define TEGRA186_RESET_AXI_CBB 58 -#define TEGRA186_RESET_BPMP_APB 59 -#define TEGRA186_RESET_CAN1 60 -#define TEGRA186_RESET_CAN2 61 -#define TEGRA186_RESET_DMIC5 62 -#define TEGRA186_RESET_DSIC 63 -#define TEGRA186_RESET_DSID 64 -#define TEGRA186_RESET_EMC_EMC 65 -#define TEGRA186_RESET_EMC_MEM 66 -#define TEGRA186_RESET_EMCSB_EMC 67 -#define TEGRA186_RESET_EMCSB_MEM 68 -#define TEGRA186_RESET_EQOS 69 -#define TEGRA186_RESET_GPCDMA 70 -#define TEGRA186_RESET_GPIO_CTL0 71 -#define TEGRA186_RESET_GPIO_CTL1 72 -#define TEGRA186_RESET_GPIO_CTL2 73 -#define TEGRA186_RESET_GPIO_CTL3 74 -#define TEGRA186_RESET_GPIO_CTL4 75 -#define TEGRA186_RESET_GPIO_CTL5 76 -#define TEGRA186_RESET_I2C10 77 -#define TEGRA186_RESET_I2C12 78 -#define TEGRA186_RESET_I2C13 79 -#define TEGRA186_RESET_I2C14 80 -#define TEGRA186_RESET_I2C7 81 -#define TEGRA186_RESET_I2C8 82 -#define TEGRA186_RESET_I2C9 83 -#define TEGRA186_RESET_JTAG2AXI 84 -#define TEGRA186_RESET_MPHY_IOBIST 85 -#define TEGRA186_RESET_MPHY_L0_RX 86 -#define TEGRA186_RESET_MPHY_L0_TX 87 -#define TEGRA186_RESET_NVCSI 88 -#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 -#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 -#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 -#define TEGRA186_RESET_NVDISPLAY0_MISC 92 -#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 -#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 -#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 -#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 -#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 -#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 -#define TEGRA186_RESET_PWM1 99 -#define TEGRA186_RESET_PWM2 100 -#define TEGRA186_RESET_PWM3 101 -#define TEGRA186_RESET_PWM4 102 -#define TEGRA186_RESET_PWM5 103 -#define TEGRA186_RESET_PWM6 104 -#define TEGRA186_RESET_PWM7 105 -#define TEGRA186_RESET_PWM8 106 -#define TEGRA186_RESET_SCE_APB 107 -#define TEGRA186_RESET_SOR1 108 -#define TEGRA186_RESET_TACH 109 -#define TEGRA186_RESET_TSC 110 -#define TEGRA186_RESET_UARTF 111 -#define TEGRA186_RESET_UARTG 112 -#define TEGRA186_RESET_UFSHC 113 -#define TEGRA186_RESET_UFSHC_AXI_M 114 -#define TEGRA186_RESET_UPHY 115 -#define TEGRA186_RESET_ADSP 116 -#define TEGRA186_RESET_ADSPDBG 117 -#define TEGRA186_RESET_ADSPINTF 118 -#define TEGRA186_RESET_ADSPNEON 119 -#define TEGRA186_RESET_ADSPPERIPH 120 -#define TEGRA186_RESET_ADSPSCU 121 -#define TEGRA186_RESET_ADSPWDT 122 -#define TEGRA186_RESET_APE 123 -#define TEGRA186_RESET_DPAUX1 124 -#define TEGRA186_RESET_NVDEC 125 -#define TEGRA186_RESET_NVENC 126 -#define TEGRA186_RESET_NVJPG 127 -#define TEGRA186_RESET_PEX_USB_UPHY 128 -#define TEGRA186_RESET_QSPI 129 -#define TEGRA186_RESET_TSECB 130 -#define TEGRA186_RESET_VI_I2C 131 -#define TEGRA186_RESET_UARTE 132 -#define TEGRA186_RESET_TOP_GTE 133 -#define TEGRA186_RESET_SHSP 134 -#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 -#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 -#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 -#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 -#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 -#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 -#define TEGRA186_RESET_TSCTNVI 143 -#define TEGRA186_RESET_EXTPERIPH4 144 -#define TEGRA186_RESET_DSIPADCTL 145 -#define TEGRA186_RESET_AUD_MCLK 146 -#define TEGRA186_RESET_MPHY_CLK_CTL 147 -#define TEGRA186_RESET_MPHY_L1_RX 148 -#define TEGRA186_RESET_MPHY_L1_TX 149 -#define TEGRA186_RESET_UFSHC_LP 150 -#define TEGRA186_RESET_BPMP_NIC 151 -#define TEGRA186_RESET_BPMP_NSYSPORESET 152 -#define TEGRA186_RESET_BPMP_NRESET 153 -#define TEGRA186_RESET_BPMP_DBGRESETN 154 -#define TEGRA186_RESET_BPMP_PRESETDBGN 155 -#define TEGRA186_RESET_BPMP_PM 156 -#define TEGRA186_RESET_BPMP_CVC 157 -#define TEGRA186_RESET_BPMP_DMA 158 -#define TEGRA186_RESET_BPMP_HSP 159 -#define TEGRA186_RESET_TSCTNBPMP 160 -#define TEGRA186_RESET_BPMP_TKE 161 -#define TEGRA186_RESET_BPMP_GTE 162 -#define TEGRA186_RESET_BPMP_PM_ACTMON 163 -#define TEGRA186_RESET_AON_NIC 164 -#define TEGRA186_RESET_AON_NSYSPORESET 165 -#define TEGRA186_RESET_AON_NRESET 166 -#define TEGRA186_RESET_AON_DBGRESETN 167 -#define TEGRA186_RESET_AON_PRESETDBGN 168 -#define TEGRA186_RESET_AON_ACTMON 169 -#define TEGRA186_RESET_AOPM 170 -#define TEGRA186_RESET_AOVC 171 -#define TEGRA186_RESET_AON_DMA 172 -#define TEGRA186_RESET_AON_GPIO 173 -#define TEGRA186_RESET_AON_HSP 174 -#define TEGRA186_RESET_TSCTNAON 175 -#define TEGRA186_RESET_AON_TKE 176 -#define TEGRA186_RESET_AON_GTE 177 -#define TEGRA186_RESET_SCE_NIC 178 -#define TEGRA186_RESET_SCE_NSYSPORESET 179 -#define TEGRA186_RESET_SCE_NRESET 180 -#define TEGRA186_RESET_SCE_DBGRESETN 181 -#define TEGRA186_RESET_SCE_PRESETDBGN 182 -#define TEGRA186_RESET_SCE_ACTMON 183 -#define TEGRA186_RESET_SCE_PM 184 -#define TEGRA186_RESET_SCE_DMA 185 -#define TEGRA186_RESET_SCE_HSP 186 -#define TEGRA186_RESET_TSCTNSCE 187 -#define TEGRA186_RESET_SCE_TKE 188 -#define TEGRA186_RESET_SCE_GTE 189 -#define TEGRA186_RESET_SCE_CFG 190 -#define TEGRA186_RESET_ADSP_ALL 191 -/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ -#define TEGRA186_RESET_UFSHC_LP_SEQ 192 -#define TEGRA186_RESET_SIZE 193 - -#endif diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h deleted file mode 100644 index 729ab9fc325e..000000000000 --- a/include/dt-bindings/thermal/tegra124-soctherm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra124-soctherm. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H -#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H - -#define TEGRA124_SOCTHERM_SENSOR_CPU 0 -#define TEGRA124_SOCTHERM_SENSOR_MEM 1 -#define TEGRA124_SOCTHERM_SENSOR_GPU 2 -#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 -#define TEGRA124_SOCTHERM_SENSOR_NUM 4 - -#endif

Drop in favour of dts/upstream

Adjust header include path naming for mpfs clock.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/riscv/dts/mpfs.dtsi | 2 +- drivers/clk/microchip/mpfs_clk.c | 2 +- drivers/clk/microchip/mpfs_clk_cfg.c | 2 +- drivers/clk/microchip/mpfs_clk_msspll.c | 2 +- drivers/clk/microchip/mpfs_clk_periph.c | 2 +- include/dt-bindings/clock/at91.h | 23 -------- include/dt-bindings/clock/microchip-mpfs-clock.h | 71 ------------------------ include/dt-bindings/dma/at91.h | 52 ----------------- include/dt-bindings/mfd/at91-usart.h | 17 ------ include/dt-bindings/net/microchip-lan78xx.h | 21 ------- include/dt-bindings/pinctrl/at91.h | 49 ---------------- include/dt-bindings/sound/microchip,pdmc.h | 13 ----- 12 files changed, 5 insertions(+), 251 deletions(-)

diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi index 6012a2850703..5827d5c5d19b 100644 --- a/arch/riscv/dts/mpfs.dtsi +++ b/arch/riscv/dts/mpfs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */

-#include "dt-bindings/clock/microchip-mpfs-clock.h" +#include <dt-bindings/clock/microchip,mpfs-clock.h>

/ { #address-cells = <2>; #size-cells = <2>; diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 08f8bfcecbed..44ac4306eace 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -10,9 +10,9 @@ #include <log.h> #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> -#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <dt-bindings/clock/microchip,mpfs-clock.h> #include <linux/err.h>

#include "mpfs_clk.h"

diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c index 5739fd66e8df..953e88e283ed 100644 --- a/drivers/clk/microchip/mpfs_clk_cfg.c +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -9,9 +9,9 @@ #include <asm/io.h> #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> -#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <dt-bindings/clock/microchip,mpfs-clock.h> #include <linux/err.h>

#include "mpfs_clk.h"

diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c index f37c0d86047c..7b5020404549 100644 --- a/drivers/clk/microchip/mpfs_clk_msspll.c +++ b/drivers/clk/microchip/mpfs_clk_msspll.c @@ -8,9 +8,9 @@ #include <asm/io.h> #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> -#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <dt-bindings/clock/microchip,mpfs-clock.h> #include <linux/err.h>

#include "mpfs_clk.h"

diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index ddeccb914575..16823402def3 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -9,9 +9,9 @@ #include <asm/io.h> #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> -#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <dt-bindings/clock/microchip,mpfs-clock.h> #include <linux/err.h>

#include "mpfs_clk.h"

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h deleted file mode 100644 index ab3ee241d10c..000000000000 --- a/include/dt-bindings/clock/at91.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This header provides constants for AT91 pmc status. - * - * The constants defined in this header are being used in dts. - * - * Licensed under GPLv2 or later. - */ - -#ifndef _DT_BINDINGS_CLK_AT91_H -#define _DT_BINDINGS_CLK_AT91_H - -#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -#define AT91_PMC_LOCKA 1 /* PLLA Lock */ -#define AT91_PMC_LOCKB 2 /* PLLB Lock */ -#define AT91_PMC_MCKRDY 3 /* Master Clock */ -#define AT91_PMC_LOCKU 6 /* UPLL Lock */ -#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ -#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ -#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ -#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ -#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ - -#endif diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h deleted file mode 100644 index 79775a5134ca..000000000000 --- a/include/dt-bindings/clock/microchip-mpfs-clock.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Daire McNamara,daire.mcnamara@microchip.com - * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ -#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ - -#define CLK_CPU 0 -#define CLK_AXI 1 -#define CLK_AHB 2 - -#define CLK_ENVM 3 -#define CLK_MAC0 4 -#define CLK_MAC1 5 -#define CLK_MMC 6 -#define CLK_TIMER 7 -#define CLK_MMUART0 8 -#define CLK_MMUART1 9 -#define CLK_MMUART2 10 -#define CLK_MMUART3 11 -#define CLK_MMUART4 12 -#define CLK_SPI0 13 -#define CLK_SPI1 14 -#define CLK_I2C0 15 -#define CLK_I2C1 16 -#define CLK_CAN0 17 -#define CLK_CAN1 18 -#define CLK_USB 19 -#define CLK_RESERVED 20 -#define CLK_RTC 21 -#define CLK_QSPI 22 -#define CLK_GPIO0 23 -#define CLK_GPIO1 24 -#define CLK_GPIO2 25 -#define CLK_DDRC 26 -#define CLK_FIC0 27 -#define CLK_FIC1 28 -#define CLK_FIC2 29 -#define CLK_FIC3 30 -#define CLK_ATHENA 31 -#define CLK_CFM 32 - -#define CLK_RTCREF 33 -#define CLK_MSSPLL 34 - -/* Clock Conditioning Circuitry Clock IDs */ - -#define CLK_CCC_PLL0 0 -#define CLK_CCC_PLL1 1 -#define CLK_CCC_DLL0 2 -#define CLK_CCC_DLL1 3 - -#define CLK_CCC_PLL0_OUT0 4 -#define CLK_CCC_PLL0_OUT1 5 -#define CLK_CCC_PLL0_OUT2 6 -#define CLK_CCC_PLL0_OUT3 7 - -#define CLK_CCC_PLL1_OUT0 8 -#define CLK_CCC_PLL1_OUT1 9 -#define CLK_CCC_PLL1_OUT2 10 -#define CLK_CCC_PLL1_OUT3 11 - -#define CLK_CCC_DLL0_OUT0 12 -#define CLK_CCC_DLL0_OUT1 13 - -#define CLK_CCC_DLL1_OUT0 14 -#define CLK_CCC_DLL1_OUT1 15 - -#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h deleted file mode 100644 index ab6cbba45401..000000000000 --- a/include/dt-bindings/dma/at91.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This header provides macros for at91 dma bindings. - * - * Copyright (C) 2013 Ludovic Desroches ludovic.desroches@atmel.com - * - * GPLv2 only - */ - -#ifndef __DT_BINDINGS_AT91_DMA_H__ -#define __DT_BINDINGS_AT91_DMA_H__ - -/* ---------- HDMAC ---------- */ - -/* - * Source and/or destination peripheral ID - */ -#define AT91_DMA_CFG_PER_ID_MASK (0xff) -#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) - -/* - * FIFO configuration: it defines when a request is serviced. - */ -#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) -#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) -#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ -#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ -#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ - - -/* ---------- XDMAC ---------- */ -#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) -#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) -#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ - << AT91_XDMAC_DT_MEM_IF_OFFSET) -#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ - & AT91_XDMAC_DT_MEM_IF_MASK) - -#define AT91_XDMAC_DT_PER_IF_MASK (0x1) -#define AT91_XDMAC_DT_PER_IF_OFFSET (14) -#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ - << AT91_XDMAC_DT_PER_IF_OFFSET) -#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ - & AT91_XDMAC_DT_PER_IF_MASK) - -#define AT91_XDMAC_DT_PERID_MASK (0x7f) -#define AT91_XDMAC_DT_PERID_OFFSET (24) -#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ - << AT91_XDMAC_DT_PERID_OFFSET) -#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ - & AT91_XDMAC_DT_PERID_MASK) - -#endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h deleted file mode 100644 index 2de5bc312e1e..000000000000 --- a/include/dt-bindings/mfd/at91-usart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for AT91 USART DT bindings. - * - * Copyright (C) 2018 Microchip Technology - * - * Author: Radu Pirea radu.pirea@microchip.com - * - */ - -#ifndef __DT_BINDINGS_AT91_USART_H__ -#define __DT_BINDINGS_AT91_USART_H__ - -#define AT91_USART_MODE_SERIAL 0 -#define AT91_USART_MODE_SPI 1 - -#endif /* __DT_BINDINGS_AT91_USART_H__ */ diff --git a/include/dt-bindings/net/microchip-lan78xx.h b/include/dt-bindings/net/microchip-lan78xx.h deleted file mode 100644 index 0742ff075307..000000000000 --- a/include/dt-bindings/net/microchip-lan78xx.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H -#define _DT_BINDINGS_MICROCHIP_LAN78XX_H - -/* LED modes for LAN7800/LAN7850 embedded PHY */ - -#define LAN78XX_LINK_ACTIVITY 0 -#define LAN78XX_LINK_1000_ACTIVITY 1 -#define LAN78XX_LINK_100_ACTIVITY 2 -#define LAN78XX_LINK_10_ACTIVITY 3 -#define LAN78XX_LINK_100_1000_ACTIVITY 4 -#define LAN78XX_LINK_10_1000_ACTIVITY 5 -#define LAN78XX_LINK_10_100_ACTIVITY 6 -#define LAN78XX_DUPLEX_COLLISION 8 -#define LAN78XX_COLLISION 9 -#define LAN78XX_ACTIVITY 10 -#define LAN78XX_AUTONEG_FAULT 12 -#define LAN78XX_FORCE_LED_OFF 14 -#define LAN78XX_FORCE_LED_ON 15 - -#endif diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h deleted file mode 100644 index 3831f91fb3ba..000000000000 --- a/include/dt-bindings/pinctrl/at91.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for most at91 pinctrl bindings. - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com - */ - -#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ -#define __DT_BINDINGS_AT91_PINCTRL_H__ - -#define AT91_PINCTRL_NONE (0 << 0) -#define AT91_PINCTRL_PULL_UP (1 << 0) -#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) -#define AT91_PINCTRL_DEGLITCH (1 << 2) -#define AT91_PINCTRL_PULL_DOWN (1 << 3) -#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) -#define AT91_PINCTRL_OUTPUT (1 << 7) -#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) -#define AT91_PINCTRL_SLEWRATE (1 << 9) -#define AT91_PINCTRL_DEBOUNCE (1 << 16) -#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) - -#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) - -#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) - -#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) -#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) - -#define AT91_PIOA 0 -#define AT91_PIOB 1 -#define AT91_PIOC 2 -#define AT91_PIOD 3 -#define AT91_PIOE 4 - -#define AT91_PERIPH_GPIO 0 -#define AT91_PERIPH_A 1 -#define AT91_PERIPH_B 2 -#define AT91_PERIPH_C 3 -#define AT91_PERIPH_D 4 - -#define ATMEL_PIO_DRVSTR_LO 1 -#define ATMEL_PIO_DRVSTR_ME 2 -#define ATMEL_PIO_DRVSTR_HI 3 - -#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h deleted file mode 100644 index 96cde94ce74f..000000000000 --- a/include/dt-bindings/sound/microchip,pdmc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ -#define __DT_BINDINGS_MICROCHIP_PDMC_H__ - -/* PDM microphone's pin placement */ -#define MCHP_PDMC_DS0 0 -#define MCHP_PDMC_DS1 1 - -/* PDM microphone clock edge sampling */ -#define MCHP_PDMC_CLK_POSITIVE 0 -#define MCHP_PDMC_CLK_NEGATIVE 1 - -#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */

Drop in favour of dts/upstream.

Small driver/dts change to fix compatibility.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 26 +++++++++++++------------- drivers/clk/sifive/fu540-prci.c | 8 ++++---- include/dt-bindings/clock/sifive-fu540-prci.h | 18 ------------------ include/dt-bindings/clock/sifive-fu740-prci.h | 24 ------------------------ 4 files changed, 17 insertions(+), 59 deletions(-)

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 360679a1781a..0f8181436410 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -6,42 +6,42 @@ #include <dt-bindings/reset/sifive-fu540-prci.h>

/ { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_COREPLL>; assigned-clock-rates = <1000000000>; bootph-pre-ram; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; status = "okay"; cpu0_intc: interrupt-controller { bootph-pre-ram; }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu1_intc: interrupt-controller { bootph-pre-ram; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu2_intc: interrupt-controller { bootph-pre-ram; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu3_intc: interrupt-controller { bootph-pre-ram; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu4_intc: interrupt-controller { bootph-pre-ram; }; @@ -66,22 +66,22 @@ bootph-pre-ram; }; prci: clock-controller@10000000 { #reset-cells = <1>; - resets = <&prci PRCI_RST_DDR_CTRL_N>, - <&prci PRCI_RST_DDR_AXI_N>, - <&prci PRCI_RST_DDR_AHB_N>, - <&prci PRCI_RST_DDR_PHY_N>, - <&prci PRCI_RST_GEMGXL_N>; + resets = <&prci FU540_PRCI_RST_DDR_CTRL_N>, + <&prci FU540_PRCI_RST_DDR_AXI_N>, + <&prci FU540_PRCI_RST_DDR_AHB_N>, + <&prci FU540_PRCI_RST_DDR_PHY_N>, + <&prci FU540_PRCI_RST_GEMGXL_N>; reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", "ddr_phy", "gemgxl_reset"; }; dmc: dmc@100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU540_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; bootph-pre-ram; }; }; @@ -99,9 +99,9 @@ bootph-pre-ram; };

&eth0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; };

&l2cache { diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0da..b019f682ac49 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,27 +58,27 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { };

/* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h deleted file mode 100644 index 6a0b70a37d78..000000000000 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018-2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h deleted file mode 100644 index 672bdadbf6c0..000000000000 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - * Zong Li - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define FU740_PRCI_CLK_COREPLL 0 -#define FU740_PRCI_CLK_DDRPLL 1 -#define FU740_PRCI_CLK_GEMGXLPLL 2 -#define FU740_PRCI_CLK_DVFSCOREPLL 3 -#define FU740_PRCI_CLK_HFPCLKPLL 4 -#define FU740_PRCI_CLK_CLTXPLL 5 -#define FU740_PRCI_CLK_TLCLK 6 -#define FU740_PRCI_CLK_PCLK 7 -#define FU740_PRCI_CLK_PCIE_AUX 8 - -#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */

Drop in favour of dts/upstream.

Remaining device headers for small vendors

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/arm/coresight-cti-dt.h | 37 ----- include/dt-bindings/arm/ux500_pm_domains.h | 15 -- include/dt-bindings/bus/moxtet.h | 16 -- include/dt-bindings/display/tda998x.h | 8 - include/dt-bindings/gpio/aspeed-gpio.h | 51 ------ include/dt-bindings/gpio/uniphier-gpio.h | 18 -- .../dt-bindings/interrupt-controller/apple-aic.h | 15 -- include/dt-bindings/interrupt-controller/arm-gic.h | 23 --- include/dt-bindings/interrupt-controller/irq-st.h | 30 ---- .../dt-bindings/interrupt-controller/irqc-rzg2l.h | 25 --- .../dt-bindings/interrupt-controller/mips-gic.h | 9 - include/dt-bindings/leds/leds-netxbig.h | 18 -- include/dt-bindings/leds/leds-ns2.h | 9 - include/dt-bindings/leds/leds-pca9532.h | 18 -- include/dt-bindings/media/tda1997x.h | 74 --------- include/dt-bindings/media/video-interfaces.h | 16 -- include/dt-bindings/mfd/atmel-flexcom.h | 15 -- include/dt-bindings/mfd/dbx500-prcmu.h | 84 ---------- include/dt-bindings/net/mscc-phy-vsc8531.h | 31 ---- include/dt-bindings/net/qca-ar803x.h | 13 -- include/dt-bindings/phy/phy-am654-serdes.h | 13 -- include/dt-bindings/phy/phy-cadence.h | 24 --- include/dt-bindings/pinctrl/apple.h | 13 -- include/dt-bindings/pinctrl/dra.h | 79 --------- include/dt-bindings/power/owl-s700-powergate.h | 19 --- include/dt-bindings/power/raspberrypi-power.h | 41 ----- .../dt-bindings/regulator/dlg,da9063-regulator.h | 16 -- include/dt-bindings/regulator/maxim,max77802.h | 18 -- include/dt-bindings/reset/actions,s700-reset.h | 34 ---- include/dt-bindings/reset/actions,s900-reset.h | 65 -------- include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 ------------- include/dt-bindings/reset/altr,rst-mgr-s10.h | 96 ----------- include/dt-bindings/reset/altr,rst-mgr.h | 82 --------- include/dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 ---------- .../dt-bindings/reset/raspberrypi,firmware-reset.h | 13 -- include/dt-bindings/reset/sama7g5-reset.h | 10 -- include/dt-bindings/reset/snps,hsdk-reset.h | 17 -- include/dt-bindings/reset/starfive,jh7110-crg.h | 183 --------------------- include/dt-bindings/sound/apq8016-lpass.h | 9 - include/dt-bindings/sound/tlv320aic31xx.h | 14 -- 40 files changed, 1472 deletions(-)

diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h deleted file mode 100644 index 61e7bdf8ea6e..000000000000 --- a/include/dt-bindings/arm/coresight-cti-dt.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the defined trigger signal - * types on CoreSight CTI. - */ - -#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H -#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H - -#define GEN_IO 0 -#define GEN_INTREQ 1 -#define GEN_INTACK 2 -#define GEN_HALTREQ 3 -#define GEN_RESTARTREQ 4 -#define PE_EDBGREQ 5 -#define PE_DBGRESTART 6 -#define PE_CTIIRQ 7 -#define PE_PMUIRQ 8 -#define PE_DBGTRIGGER 9 -#define ETM_EXTOUT 10 -#define ETM_EXTIN 11 -#define SNK_FULL 12 -#define SNK_ACQCOMP 13 -#define SNK_FLUSHCOMP 14 -#define SNK_FLUSHIN 15 -#define SNK_TRIGIN 16 -#define STM_ASYNCOUT 17 -#define STM_TOUT_SPTE 18 -#define STM_TOUT_SW 19 -#define STM_TOUT_HETE 20 -#define STM_HWEVENT 21 -#define ELA_TSTART 22 -#define ELA_TSTOP 23 -#define ELA_DBGREQ 24 -#define CTI_TRIG_MAX 25 - -#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/arm/ux500_pm_domains.h b/include/dt-bindings/arm/ux500_pm_domains.h deleted file mode 100644 index 9bd764f0c9e6..000000000000 --- a/include/dt-bindings/arm/ux500_pm_domains.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Linaro Ltd. - * - * Author: Ulf Hansson ulf.hansson@linaro.org - */ -#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H -#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H - -#define DOMAIN_VAPE 0 - -/* Number of PM domains. */ -#define NR_DOMAINS (DOMAIN_VAPE + 1) - -#endif diff --git a/include/dt-bindings/bus/moxtet.h b/include/dt-bindings/bus/moxtet.h deleted file mode 100644 index 10528de7b3ef..000000000000 --- a/include/dt-bindings/bus/moxtet.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Constant for device tree bindings for Turris Mox module configuration bus - * - * Copyright (C) 2019 Marek Behún kabel@kernel.org - */ - -#ifndef _DT_BINDINGS_BUS_MOXTET_H -#define _DT_BINDINGS_BUS_MOXTET_H - -#define MOXTET_IRQ_PCI 0 -#define MOXTET_IRQ_USB3 4 -#define MOXTET_IRQ_PERIDOT(n) (8 + (n)) -#define MOXTET_IRQ_TOPAZ 12 - -#endif /* _DT_BINDINGS_BUS_MOXTET_H */ diff --git a/include/dt-bindings/display/tda998x.h b/include/dt-bindings/display/tda998x.h deleted file mode 100644 index 746831ff396c..000000000000 --- a/include/dt-bindings/display/tda998x.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_TDA998X_H -#define _DT_BINDINGS_TDA998X_H - -#define TDA998x_SPDIF 1 -#define TDA998x_I2S 2 - -#endif /*_DT_BINDINGS_TDA998X_H */ diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h deleted file mode 100644 index a49f5d5b5af0..000000000000 --- a/include/dt-bindings/gpio/aspeed-gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2022 IBM Corp. - * - * This header provides constants for binding aspeed,*-gpio. - * - * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H -#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H - -#include <dt-bindings/gpio/gpio.h> - -#define ASPEED_GPIO_PORT_A 0 -#define ASPEED_GPIO_PORT_B 1 -#define ASPEED_GPIO_PORT_C 2 -#define ASPEED_GPIO_PORT_D 3 -#define ASPEED_GPIO_PORT_E 4 -#define ASPEED_GPIO_PORT_F 5 -#define ASPEED_GPIO_PORT_G 6 -#define ASPEED_GPIO_PORT_H 7 -#define ASPEED_GPIO_PORT_I 8 -#define ASPEED_GPIO_PORT_J 9 -#define ASPEED_GPIO_PORT_K 10 -#define ASPEED_GPIO_PORT_L 11 -#define ASPEED_GPIO_PORT_M 12 -#define ASPEED_GPIO_PORT_N 13 -#define ASPEED_GPIO_PORT_O 14 -#define ASPEED_GPIO_PORT_P 15 -#define ASPEED_GPIO_PORT_Q 16 -#define ASPEED_GPIO_PORT_R 17 -#define ASPEED_GPIO_PORT_S 18 -#define ASPEED_GPIO_PORT_T 19 -#define ASPEED_GPIO_PORT_U 20 -#define ASPEED_GPIO_PORT_V 21 -#define ASPEED_GPIO_PORT_W 22 -#define ASPEED_GPIO_PORT_X 23 -#define ASPEED_GPIO_PORT_Y 24 -#define ASPEED_GPIO_PORT_Z 25 -#define ASPEED_GPIO_PORT_AA 26 -#define ASPEED_GPIO_PORT_AB 27 -#define ASPEED_GPIO_PORT_AC 28 - -#define ASPEED_GPIO(port, offset) \ - ((ASPEED_GPIO_PORT_##port * 8) + (offset)) - -#endif diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h deleted file mode 100644 index 9f0ad174f61c..000000000000 --- a/include/dt-bindings/gpio/uniphier-gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada yamada.masahiro@socionext.com - */ - -#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H -#define _DT_BINDINGS_GPIO_UNIPHIER_H - -#define UNIPHIER_GPIO_LINES_PER_BANK 8 - -#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) - -#define UNIPHIER_GPIO_PORT(bank, line) \ - ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) - -#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) - -#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h deleted file mode 100644 index 9ac56a7e6d3f..000000000000 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H - -#include <dt-bindings/interrupt-controller/irq.h> - -#define AIC_IRQ 0 -#define AIC_FIQ 1 - -#define AIC_TMR_HV_PHYS 0 -#define AIC_TMR_HV_VIRT 1 -#define AIC_TMR_GUEST_PHYS 2 -#define AIC_TMR_GUEST_VIRT 3 - -#endif diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h deleted file mode 100644 index 35b6f69b7db6..000000000000 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for the ARM GIC. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H - -#include <dt-bindings/interrupt-controller/irq.h> - -/* interrupt specifier cell 0 */ - -#define GIC_SPI 0 -#define GIC_PPI 1 - -/* - * Interrupt specifier cell 2. - * The flags in irq.h are valid, plus those below. - */ -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -#endif diff --git a/include/dt-bindings/interrupt-controller/irq-st.h b/include/dt-bindings/interrupt-controller/irq-st.h deleted file mode 100644 index 6baa9ad2644c..000000000000 --- a/include/dt-bindings/interrupt-controller/irq-st.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * include/linux/irqchip/irq-st.h - * - * Copyright (C) 2014 STMicroelectronics All Rights Reserved - * - * Author: Lee Jones lee.jones@linaro.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H - -#define ST_IRQ_SYSCFG_EXT_0 0 -#define ST_IRQ_SYSCFG_EXT_1 1 -#define ST_IRQ_SYSCFG_EXT_2 2 -#define ST_IRQ_SYSCFG_CTI_0 3 -#define ST_IRQ_SYSCFG_CTI_1 4 -#define ST_IRQ_SYSCFG_PMU_0 5 -#define ST_IRQ_SYSCFG_PMU_1 6 -#define ST_IRQ_SYSCFG_pl310_L2 7 -#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF - -#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 -#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 -#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 - -#endif diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h deleted file mode 100644 index 34ce778885a1..000000000000 --- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * This header provides constants for Renesas RZ/G2L family IRQC bindings. - * - * Copyright (C) 2022 Renesas Electronics Corp. - * - */ - -#ifndef __DT_BINDINGS_IRQC_RZG2L_H -#define __DT_BINDINGS_IRQC_RZG2L_H - -/* NMI maps to SPI0 */ -#define RZG2L_NMI 0 - -/* IRQ0-7 map to SPI1-8 */ -#define RZG2L_IRQ0 1 -#define RZG2L_IRQ1 2 -#define RZG2L_IRQ2 3 -#define RZG2L_IRQ3 4 -#define RZG2L_IRQ4 5 -#define RZG2L_IRQ5 6 -#define RZG2L_IRQ6 7 -#define RZG2L_IRQ7 8 - -#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h deleted file mode 100644 index cf35a577e371..000000000000 --- a/include/dt-bindings/interrupt-controller/mips-gic.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H - -#include <dt-bindings/interrupt-controller/irq.h> - -#define GIC_SHARED 0 -#define GIC_LOCAL 1 - -#endif diff --git a/include/dt-bindings/leds/leds-netxbig.h b/include/dt-bindings/leds/leds-netxbig.h deleted file mode 100644 index 92658b0310b2..000000000000 --- a/include/dt-bindings/leds/leds-netxbig.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for netxbig LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_NETXBIG_H -#define _DT_BINDINGS_LEDS_NETXBIG_H - -#define NETXBIG_LED_OFF 0 -#define NETXBIG_LED_ON 1 -#define NETXBIG_LED_SATA 2 -#define NETXBIG_LED_TIMER1 3 -#define NETXBIG_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */ diff --git a/include/dt-bindings/leds/leds-ns2.h b/include/dt-bindings/leds/leds-ns2.h deleted file mode 100644 index fd615749e703..000000000000 --- a/include/dt-bindings/leds/leds-ns2.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_LEDS_NS2_H -#define _DT_BINDINGS_LEDS_NS2_H - -#define NS_V2_LED_OFF 0 -#define NS_V2_LED_ON 1 -#define NS_V2_LED_SATA 2 - -#endif diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h deleted file mode 100644 index 4d917aab7e1e..000000000000 --- a/include/dt-bindings/leds/leds-pca9532.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for pca9532 LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_PCA9532_H -#define _DT_BINDINGS_LEDS_PCA9532_H - -#define PCA9532_TYPE_NONE 0 -#define PCA9532_TYPE_LED 1 -#define PCA9532_TYPE_N2100_BEEP 2 -#define PCA9532_TYPE_GPIO 3 -#define PCA9532_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h deleted file mode 100644 index bd9fbd718ec9..000000000000 --- a/include/dt-bindings/media/tda1997x.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2017 Gateworks Corporation - */ -#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H -#define _DT_BINDINGS_MEDIA_TDA1997X_H - -/* TDA19973 36bit Video Port control registers */ -#define TDA1997X_VP36_35_32 0 -#define TDA1997X_VP36_31_28 1 -#define TDA1997X_VP36_27_24 2 -#define TDA1997X_VP36_23_20 3 -#define TDA1997X_VP36_19_16 4 -#define TDA1997X_VP36_15_12 5 -#define TDA1997X_VP36_11_08 6 -#define TDA1997X_VP36_07_04 7 -#define TDA1997X_VP36_03_00 8 - -/* TDA19971 24bit Video Port control registers */ -#define TDA1997X_VP24_V23_20 0 -#define TDA1997X_VP24_V19_16 1 -#define TDA1997X_VP24_V15_12 3 -#define TDA1997X_VP24_V11_08 4 -#define TDA1997X_VP24_V07_04 6 -#define TDA1997X_VP24_V03_00 7 - -/* Pin groups */ -#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ -#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ -#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ -#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -/* pinswapped groups */ -#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) - -/* Audio bus DAI format */ -#define TDA1997X_I2S16 1 /* I2S 16bit */ -#define TDA1997X_I2S32 2 /* I2S 32bit */ -#define TDA1997X_SPDIF 3 /* SPDIF */ -#define TDA1997X_OBA 4 /* One Bit Audio */ -#define TDA1997X_DST 5 /* Direct Stream Transfer */ -#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ -#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ -#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ -#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ - -/* Audio bus channel layout */ -#define TDA1997X_LAYOUT0 0 /* 2-channel */ -#define TDA1997X_LAYOUT1 1 /* 8-channel */ - -/* Audio bus clock */ -#define TDA1997X_ACLK_16FS 0 -#define TDA1997X_ACLK_32FS 1 -#define TDA1997X_ACLK_64FS 2 -#define TDA1997X_ACLK_128FS 3 -#define TDA1997X_ACLK_256FS 4 -#define TDA1997X_ACLK_512FS 5 - -#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h deleted file mode 100644 index 68ac4e05e37f..000000000000 --- a/include/dt-bindings/media/video-interfaces.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (C) 2022 Laurent Pinchart laurent.pinchart@ideasonboard.com - */ - -#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ -#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ - -#define MEDIA_BUS_TYPE_CSI2_CPHY 1 -#define MEDIA_BUS_TYPE_CSI1 2 -#define MEDIA_BUS_TYPE_CCP2 3 -#define MEDIA_BUS_TYPE_CSI2_DPHY 4 -#define MEDIA_BUS_TYPE_PARALLEL 5 -#define MEDIA_BUS_TYPE_BT656 6 - -#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/include/dt-bindings/mfd/atmel-flexcom.h b/include/dt-bindings/mfd/atmel-flexcom.h deleted file mode 100644 index 4e2fc3236394..000000000000 --- a/include/dt-bindings/mfd/atmel-flexcom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for Atmel Flexcom DT bindings. - * - * Copyright (C) 2015 Cyrille Pitchen cyrille.pitchen@atmel.com - */ - -#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ -#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ - -#define ATMEL_FLEXCOM_MODE_USART 1 -#define ATMEL_FLEXCOM_MODE_SPI 2 -#define ATMEL_FLEXCOM_MODE_TWI 3 - -#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h deleted file mode 100644 index 7266ae67b03a..000000000000 --- a/include/dt-bindings/mfd/dbx500-prcmu.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the PRCMU bindings. - * - */ - -#ifndef _DT_BINDINGS_MFD_PRCMU_H -#define _DT_BINDINGS_MFD_PRCMU_H - -/* - * Clock identifiers. - */ -#define ARMCLK 0 -#define PRCMU_ACLK 1 -#define PRCMU_SVAMMCSPCLK 2 -#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ -#define PRCMU_SIACLK 3 -#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ -#define PRCMU_SGACLK 4 -#define PRCMU_UARTCLK 5 -#define PRCMU_MSP02CLK 6 -#define PRCMU_MSP1CLK 7 -#define PRCMU_I2CCLK 8 -#define PRCMU_SDMMCCLK 9 -#define PRCMU_SLIMCLK 10 -#define PRCMU_CAMCLK 10 /* DBx540 only. */ -#define PRCMU_PER1CLK 11 -#define PRCMU_PER2CLK 12 -#define PRCMU_PER3CLK 13 -#define PRCMU_PER5CLK 14 -#define PRCMU_PER6CLK 15 -#define PRCMU_PER7CLK 16 -#define PRCMU_LCDCLK 17 -#define PRCMU_BMLCLK 18 -#define PRCMU_HSITXCLK 19 -#define PRCMU_HSIRXCLK 20 -#define PRCMU_HDMICLK 21 -#define PRCMU_APEATCLK 22 -#define PRCMU_APETRACECLK 23 -#define PRCMU_MCDECLK 24 -#define PRCMU_IPI2CCLK 25 -#define PRCMU_DSIALTCLK 26 -#define PRCMU_DMACLK 27 -#define PRCMU_B2R2CLK 28 -#define PRCMU_TVCLK 29 -#define SPARE_UNIPROCLK 30 -#define PRCMU_SSPCLK 31 -#define PRCMU_RNGCLK 32 -#define PRCMU_UICCCLK 33 -#define PRCMU_G1CLK 34 /* DBx540 only. */ -#define PRCMU_HVACLK 35 /* DBx540 only. */ -#define PRCMU_SPARE1CLK 36 -#define PRCMU_SPARE2CLK 37 - -#define PRCMU_NUM_REG_CLOCKS 38 - -#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS -#define PRCMU_SYSCLK 39 -#define PRCMU_CDCLK 40 -#define PRCMU_TIMCLK 41 -#define PRCMU_PLLSOC0 42 -#define PRCMU_PLLSOC1 43 -#define PRCMU_ARMSS 44 -#define PRCMU_PLLDDR 45 - -/* DSI Clocks */ -#define PRCMU_PLLDSI 46 -#define PRCMU_DSI0CLK 47 -#define PRCMU_DSI1CLK 48 -#define PRCMU_DSI0ESCCLK 49 -#define PRCMU_DSI1ESCCLK 50 -#define PRCMU_DSI2ESCCLK 51 - -/* LCD DSI PLL - Ux540 only */ -#define PRCMU_PLLDSI_LCD 52 -#define PRCMU_DSI0CLK_LCD 53 -#define PRCMU_DSI1CLK_LCD 54 -#define PRCMU_DSI0ESCCLK_LCD 55 -#define PRCMU_DSI1ESCCLK_LCD 56 -#define PRCMU_DSI2ESCCLK_LCD 57 - -#define PRCMU_NUM_CLKS 58 - -#endif diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h deleted file mode 100644 index c340437414fb..000000000000 --- a/include/dt-bindings/net/mscc-phy-vsc8531.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Device Tree constants for Microsemi VSC8531 PHY - * - * Author: Nagaraju Lakkaraju - * - * Copyright (c) 2017 Microsemi Corporation - */ - -#ifndef _DT_BINDINGS_MSCC_VSC8531_H -#define _DT_BINDINGS_MSCC_VSC8531_H - -/* PHY LED Modes */ -#define VSC8531_LINK_ACTIVITY 0 -#define VSC8531_LINK_1000_ACTIVITY 1 -#define VSC8531_LINK_100_ACTIVITY 2 -#define VSC8531_LINK_10_ACTIVITY 3 -#define VSC8531_LINK_100_1000_ACTIVITY 4 -#define VSC8531_LINK_10_1000_ACTIVITY 5 -#define VSC8531_LINK_10_100_ACTIVITY 6 -#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 -#define VSC8531_DUPLEX_COLLISION 8 -#define VSC8531_COLLISION 9 -#define VSC8531_ACTIVITY 10 -#define VSC8584_100FX_1000X_ACTIVITY 11 -#define VSC8531_AUTONEG_FAULT 12 -#define VSC8531_SERIAL_MODE 13 -#define VSC8531_FORCE_LED_OFF 14 -#define VSC8531_FORCE_LED_ON 15 - -#endif diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h deleted file mode 100644 index 9c046c7242ed..000000000000 --- a/include/dt-bindings/net/qca-ar803x.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Qualcomm Atheros AR803x PHYs - */ - -#ifndef _DT_BINDINGS_QCA_AR803X_H -#define _DT_BINDINGS_QCA_AR803X_H - -#define AR803X_STRENGTH_FULL 0 -#define AR803X_STRENGTH_HALF 1 -#define AR803X_STRENGTH_QUARTER 2 - -#endif diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h deleted file mode 100644 index e8d901729ed9..000000000000 --- a/include/dt-bindings/phy/phy-am654-serdes.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for AM654 SERDES. - */ - -#ifndef _DT_BINDINGS_AM654_SERDES -#define _DT_BINDINGS_AM654_SERDES - -#define AM654_SERDES_CMU_REFCLK 0 -#define AM654_SERDES_LO_REFCLK 1 -#define AM654_SERDES_RO_REFCLK 2 - -#endif /* _DT_BINDINGS_AM654_SERDES */ diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h deleted file mode 100644 index 0122c6067b17..000000000000 --- a/include/dt-bindings/phy/phy-cadence.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for Cadence SERDES. - */ - -#ifndef _DT_BINDINGS_CADENCE_SERDES_H -#define _DT_BINDINGS_CADENCE_SERDES_H - -/* Torrent */ -#define TORRENT_SERDES_NO_SSC 0 -#define TORRENT_SERDES_EXTERNAL_SSC 1 -#define TORRENT_SERDES_INTERNAL_SSC 2 - -#define CDNS_TORRENT_REFCLK_DRIVER 0 - -/* Sierra */ -#define CDNS_SIERRA_PLL_CMNLC 0 -#define CDNS_SIERRA_PLL_CMNLC1 1 - -#define SIERRA_SERDES_NO_SSC 0 -#define SIERRA_SERDES_EXTERNAL_SSC 1 -#define SIERRA_SERDES_INTERNAL_SSC 2 - -#endif /* _DT_BINDINGS_CADENCE_SERDES_H */ diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h deleted file mode 100644 index ea0a6f466592..000000000000 --- a/include/dt-bindings/pinctrl/apple.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * This header provides constants for Apple pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_APPLE_H -#define _DT_BINDINGS_PINCTRL_APPLE_H - -#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) -#define APPLE_PIN(pinmux) ((pinmux) & 0xffff) -#define APPLE_FUNC(pinmux) ((pinmux) >> 16) - -#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h deleted file mode 100644 index 765c385f7b2c..000000000000 --- a/include/dt-bindings/pinctrl/dra.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This header provides constants for DRA pinctrl bindings. - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * Author: Rajendra Nayak rnayak@ti.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_PINCTRL_DRA_H -#define _DT_BINDINGS_PINCTRL_DRA_H - -/* DRA7 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0x0 -#define MUX_MODE1 0x1 -#define MUX_MODE2 0x2 -#define MUX_MODE3 0x3 -#define MUX_MODE4 0x4 -#define MUX_MODE5 0x5 -#define MUX_MODE6 0x6 -#define MUX_MODE7 0x7 -#define MUX_MODE8 0x8 -#define MUX_MODE9 0x9 -#define MUX_MODE10 0xa -#define MUX_MODE11 0xb -#define MUX_MODE12 0xc -#define MUX_MODE13 0xd -#define MUX_MODE14 0xe -#define MUX_MODE15 0xf - -/* Certain pins need virtual mode, but note: they may glitch */ -#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) -#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) -#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) -#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) -#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) -#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) -#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) -#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) -#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) -#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) -#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) -#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) -#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) -#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) -#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) -#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) - -#define MODE_SELECT (1 << 8) - -#define PULL_ENA (0 << 16) -#define PULL_DIS (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCONTROL (1 << 19) -#define WAKEUP_EN (1 << 24) -#define WAKEUP_EVENT (1 << 25) - -/* Active pin states */ -#define PIN_OUTPUT (0 | PULL_DIS) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN (0) -#define PIN_INPUT (INPUT_EN | PULL_DIS) -#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) - -/* DRA7 IODELAY configuration parameters */ -#define A_DELAY_PS(val) ((val) & 0xffff) -#define G_DELAY_PS(val) ((val) & 0xffff) -#endif diff --git a/include/dt-bindings/power/owl-s700-powergate.h b/include/dt-bindings/power/owl-s700-powergate.h deleted file mode 100644 index 4cf1aefbf09c..000000000000 --- a/include/dt-bindings/power/owl-s700-powergate.h +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Actions Semi S700 SPS - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H -#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H - -#define S700_PD_VDE 0 -#define S700_PD_VCE_SI 1 -#define S700_PD_USB2_1 2 -#define S700_PD_HDE 3 -#define S700_PD_DMA 4 -#define S700_PD_DS 5 -#define S700_PD_USB3 6 -#define S700_PD_USB2_0 7 - -#endif diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h deleted file mode 100644 index b3ff8e09a78f..000000000000 --- a/include/dt-bindings/power/raspberrypi-power.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H -#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H - -/* These power domain indices are the firmware interface's indices - * minus one. - */ -#define RPI_POWER_DOMAIN_I2C0 0 -#define RPI_POWER_DOMAIN_I2C1 1 -#define RPI_POWER_DOMAIN_I2C2 2 -#define RPI_POWER_DOMAIN_VIDEO_SCALER 3 -#define RPI_POWER_DOMAIN_VPU1 4 -#define RPI_POWER_DOMAIN_HDMI 5 -#define RPI_POWER_DOMAIN_USB 6 -#define RPI_POWER_DOMAIN_VEC 7 -#define RPI_POWER_DOMAIN_JPEG 8 -#define RPI_POWER_DOMAIN_H264 9 -#define RPI_POWER_DOMAIN_V3D 10 -#define RPI_POWER_DOMAIN_ISP 11 -#define RPI_POWER_DOMAIN_UNICAM0 12 -#define RPI_POWER_DOMAIN_UNICAM1 13 -#define RPI_POWER_DOMAIN_CCP2RX 14 -#define RPI_POWER_DOMAIN_CSI2 15 -#define RPI_POWER_DOMAIN_CPI 16 -#define RPI_POWER_DOMAIN_DSI0 17 -#define RPI_POWER_DOMAIN_DSI1 18 -#define RPI_POWER_DOMAIN_TRANSPOSER 19 -#define RPI_POWER_DOMAIN_CCP2TX 20 -#define RPI_POWER_DOMAIN_CDP 21 -#define RPI_POWER_DOMAIN_ARM 22 - -#define RPI_POWER_DOMAIN_COUNT 23 - -#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */ diff --git a/include/dt-bindings/regulator/dlg,da9063-regulator.h b/include/dt-bindings/regulator/dlg,da9063-regulator.h deleted file mode 100644 index 1de710dd0899..000000000000 --- a/include/dt-bindings/regulator/dlg,da9063-regulator.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H -#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H - -/* - * These buck mode constants may be used to specify values in device tree - * properties (e.g. regulator-initial-mode). - * A description of the following modes is in the manufacturers datasheet. - */ - -#define DA9063_BUCK_MODE_SLEEP 1 -#define DA9063_BUCK_MODE_SYNC 2 -#define DA9063_BUCK_MODE_AUTO 3 - -#endif diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h deleted file mode 100644 index cf28631d7109..000000000000 --- a/include/dt-bindings/regulator/maxim,max77802.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for the Maxim 77802 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H -#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H - -/* Regulator operating modes */ -#define MAX77802_OPMODE_LP 1 -#define MAX77802_OPMODE_NORMAL 3 - -#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h deleted file mode 100644 index 5e3b16b8ef53..000000000000 --- a/include/dt-bindings/reset/actions,s700-reset.h +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S700 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H -#define __DT_BINDINGS_ACTIONS_S700_RESET_H - -#define RESET_AUDIO 0 -#define RESET_CSI 1 -#define RESET_DE 2 -#define RESET_DSI 3 -#define RESET_GPIO 4 -#define RESET_I2C0 5 -#define RESET_I2C1 6 -#define RESET_I2C2 7 -#define RESET_I2C3 8 -#define RESET_KEY 9 -#define RESET_LCD0 10 -#define RESET_SI 11 -#define RESET_SPI0 12 -#define RESET_SPI1 13 -#define RESET_SPI2 14 -#define RESET_SPI3 15 -#define RESET_UART0 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_UART3 19 -#define RESET_UART4 20 -#define RESET_UART5 21 -#define RESET_UART6 22 - -#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h deleted file mode 100644 index 42c19d02e43b..000000000000 --- a/include/dt-bindings/reset/actions,s900-reset.h +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S900 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H -#define __DT_BINDINGS_ACTIONS_S900_RESET_H - -#define RESET_CHIPID 0 -#define RESET_CPU_SCNT 1 -#define RESET_SRAMI 2 -#define RESET_DDR_CTL_PHY 3 -#define RESET_DMAC 4 -#define RESET_GPIO 5 -#define RESET_BISP_AXI 6 -#define RESET_CSI0 7 -#define RESET_CSI1 8 -#define RESET_DE 9 -#define RESET_DSI 10 -#define RESET_GPU3D_PA 11 -#define RESET_GPU3D_PB 12 -#define RESET_HDE 13 -#define RESET_I2C0 14 -#define RESET_I2C1 15 -#define RESET_I2C2 16 -#define RESET_I2C3 17 -#define RESET_I2C4 18 -#define RESET_I2C5 19 -#define RESET_IMX 20 -#define RESET_NANDC0 21 -#define RESET_NANDC1 22 -#define RESET_SD0 23 -#define RESET_SD1 24 -#define RESET_SD2 25 -#define RESET_SD3 26 -#define RESET_SPI0 27 -#define RESET_SPI1 28 -#define RESET_SPI2 29 -#define RESET_SPI3 30 -#define RESET_UART0 31 -#define RESET_UART1 32 -#define RESET_UART2 33 -#define RESET_UART3 34 -#define RESET_UART4 35 -#define RESET_UART5 36 -#define RESET_UART6 37 -#define RESET_HDMI 38 -#define RESET_LVDS 39 -#define RESET_EDP 40 -#define RESET_USB2HUB 41 -#define RESET_USB2HSIC 42 -#define RESET_USB3 43 -#define RESET_PCM1 44 -#define RESET_AUDIO 45 -#define RESET_PCM0 46 -#define RESET_SE 47 -#define RESET_GIC 48 -#define RESET_DDR_CTL_PHY_AXI 49 -#define RESET_CMU_DDR 50 -#define RESET_DMM 51 -#define RESET_HDCP2TX 52 -#define RESET_ETHERNET 53 - -#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h deleted file mode 100644 index acb0bbf4f9f5..000000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-a10.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2014, Steffen Trumtrar s.trumtrar@pengutronix.de - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -#define QSPI_RESET 38 -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -#define QSPI_OCP_RESET 46 -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define L4WD0_RESET 64 -#define L4WD1_RESET 65 -#define L4SYSTIMER0_RESET 66 -#define L4SYSTIMER1_RESET 67 -#define SPTIMER0_RESET 68 -#define SPTIMER1_RESET 69 -/* 70-71 is reserved */ -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is reserved */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is reserved */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 -#define GPIO2_RESET 90 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* SYSMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -/* 130 is reserved */ -#define FPGAMGR_RESET 131 -#define S2F_RESET 132 -#define SYSDBG_RESET 133 -#define OCRAM_OCP_RESET 134 - -/* COLDMODRST */ -#define CLKMGRCOLD_RESET 160 -/* 161-162 is reserved */ -#define S2FCOLD_RESET 163 -#define TIMESTAMPCOLD_RESET 164 -#define TAPCOLD_RESET 165 -#define HMCCOLD_RESET 166 -#define IOMGRCOLD_RESET 167 - -/* NRSTMODRST */ -#define NRSTPINOE_RESET 192 - -/* DBGMODRST */ -#define DBG_RESET 224 -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h deleted file mode 100644 index 1fdcf8ae1531..000000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016-2018 Intel Corporation. All rights reserved - * Copyright (C) 2016 Altera Corporation. All rights reserved - * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define CPU2_RESET 2 -#define CPU3_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -/* 38 is empty */ -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -/* 46 is empty */ -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define WATCHDOG0_RESET 64 -#define WATCHDOG1_RESET 65 -#define WATCHDOG2_RESET 66 -#define WATCHDOG3_RESET 67 -#define L4SYSTIMER0_RESET 68 -#define L4SYSTIMER1_RESET 69 -#define SPTIMER0_RESET 70 -#define SPTIMER1_RESET 71 -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is empty */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is empty */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 - -/* BRGMODRST */ -#define SOC2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2SOC_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* COLDMODRST */ -#define CPUPO0_RESET 160 -#define CPUPO1_RESET 161 -#define CPUPO2_RESET 162 -#define CPUPO3_RESET 163 -/* 164-167 is empty */ -#define L2_RESET 168 - -/* DBGMODRST */ -#define DBG_RESET 224 -#define CSDAP_RESET 225 - -/* TAPMODRST */ -#define TAP_RESET 256 - -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 5b7ad7396524..000000000000 --- a/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014, Steffen Trumtrar s.trumtrar@pengutronix.de - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h deleted file mode 100644 index 757f5e34c814..000000000000 --- a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (c) 2020 Nuvoton Technology corporation. - -#ifndef _DT_BINDINGS_NPCM7XX_RESET_H -#define _DT_BINDINGS_NPCM7XX_RESET_H - -#define NPCM7XX_RESET_IPSRST1 0x20 -#define NPCM7XX_RESET_IPSRST2 0x24 -#define NPCM7XX_RESET_IPSRST3 0x34 - -/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ -#define NPCM7XX_RESET_FIU3 1 -#define NPCM7XX_RESET_UDC1 5 -#define NPCM7XX_RESET_EMC1 6 -#define NPCM7XX_RESET_UART_2_3 7 -#define NPCM7XX_RESET_UDC2 8 -#define NPCM7XX_RESET_PECI 9 -#define NPCM7XX_RESET_AES 10 -#define NPCM7XX_RESET_UART_0_1 11 -#define NPCM7XX_RESET_MC 12 -#define NPCM7XX_RESET_SMB2 13 -#define NPCM7XX_RESET_SMB3 14 -#define NPCM7XX_RESET_SMB4 15 -#define NPCM7XX_RESET_SMB5 16 -#define NPCM7XX_RESET_PWM_M0 18 -#define NPCM7XX_RESET_TIMER_0_4 19 -#define NPCM7XX_RESET_TIMER_5_9 20 -#define NPCM7XX_RESET_EMC2 21 -#define NPCM7XX_RESET_UDC4 22 -#define NPCM7XX_RESET_UDC5 23 -#define NPCM7XX_RESET_UDC6 24 -#define NPCM7XX_RESET_UDC3 25 -#define NPCM7XX_RESET_ADC 27 -#define NPCM7XX_RESET_SMB6 28 -#define NPCM7XX_RESET_SMB7 29 -#define NPCM7XX_RESET_SMB0 30 -#define NPCM7XX_RESET_SMB1 31 - -/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ -#define NPCM7XX_RESET_MFT0 0 -#define NPCM7XX_RESET_MFT1 1 -#define NPCM7XX_RESET_MFT2 2 -#define NPCM7XX_RESET_MFT3 3 -#define NPCM7XX_RESET_MFT4 4 -#define NPCM7XX_RESET_MFT5 5 -#define NPCM7XX_RESET_MFT6 6 -#define NPCM7XX_RESET_MFT7 7 -#define NPCM7XX_RESET_MMC 8 -#define NPCM7XX_RESET_SDHC 9 -#define NPCM7XX_RESET_GFX_SYS 10 -#define NPCM7XX_RESET_AHB_PCIBRG 11 -#define NPCM7XX_RESET_VDMA 12 -#define NPCM7XX_RESET_ECE 13 -#define NPCM7XX_RESET_VCD 14 -#define NPCM7XX_RESET_OTP 16 -#define NPCM7XX_RESET_SIOX1 18 -#define NPCM7XX_RESET_SIOX2 19 -#define NPCM7XX_RESET_3DES 21 -#define NPCM7XX_RESET_PSPI1 22 -#define NPCM7XX_RESET_PSPI2 23 -#define NPCM7XX_RESET_GMAC2 25 -#define NPCM7XX_RESET_USB_HOST 26 -#define NPCM7XX_RESET_GMAC1 28 -#define NPCM7XX_RESET_CP 31 - -/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ -#define NPCM7XX_RESET_PWM_M1 0 -#define NPCM7XX_RESET_SMB12 1 -#define NPCM7XX_RESET_SPIX 2 -#define NPCM7XX_RESET_SMB13 3 -#define NPCM7XX_RESET_UDC0 4 -#define NPCM7XX_RESET_UDC7 5 -#define NPCM7XX_RESET_UDC8 6 -#define NPCM7XX_RESET_UDC9 7 -#define NPCM7XX_RESET_PCI_MAILBOX 9 -#define NPCM7XX_RESET_SMB14 12 -#define NPCM7XX_RESET_SHA 13 -#define NPCM7XX_RESET_SEC_ECC 14 -#define NPCM7XX_RESET_PCIE_RC 15 -#define NPCM7XX_RESET_TIMER_10_14 16 -#define NPCM7XX_RESET_RNG 17 -#define NPCM7XX_RESET_SMB15 18 -#define NPCM7XX_RESET_SMB8 19 -#define NPCM7XX_RESET_SMB9 20 -#define NPCM7XX_RESET_SMB10 21 -#define NPCM7XX_RESET_SMB11 22 -#define NPCM7XX_RESET_ESPI 23 -#define NPCM7XX_RESET_USB_PHY_1 24 -#define NPCM7XX_RESET_USB_PHY_2 25 - -#endif diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h deleted file mode 100644 index 1a4f4c792723..000000000000 --- a/include/dt-bindings/reset/raspberrypi,firmware-reset.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Nicolas Saenz Julienne - * Author: Nicolas Saenz Julienne nsaenzjulienne@suse.com - */ - -#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H -#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H - -#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 -#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 - -#endif diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h deleted file mode 100644 index 2116f41d04e0..000000000000 --- a/include/dt-bindings/reset/sama7g5-reset.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef __DT_BINDINGS_RESET_SAMA7G5_H -#define __DT_BINDINGS_RESET_SAMA7G5_H - -#define SAMA7G5_RESET_USB_PHY1 4 -#define SAMA7G5_RESET_USB_PHY2 5 -#define SAMA7G5_RESET_USB_PHY3 6 - -#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ diff --git a/include/dt-bindings/reset/snps,hsdk-reset.h b/include/dt-bindings/reset/snps,hsdk-reset.h deleted file mode 100644 index e1a643e4bc91..000000000000 --- a/include/dt-bindings/reset/snps,hsdk-reset.h +++ /dev/null @@ -1,17 +0,0 @@ -/** - * This header provides index for the HSDK reset controller. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK -#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK - -#define HSDK_APB_RESET 0 -#define HSDK_AXI_RESET 1 -#define HSDK_ETH_RESET 2 -#define HSDK_USB_RESET 3 -#define HSDK_SDIO_RESET 4 -#define HSDK_HDMI_RESET 5 -#define HSDK_GFX_RESET 6 -#define HSDK_DMAC_RESET 7 -#define HSDK_EBI_RESET 8 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da7b..000000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang yanhong.wang@starfivetech.com - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h deleted file mode 100644 index dc605c4bc224..000000000000 --- a/include/dt-bindings/sound/apq8016-lpass.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_APQ8016_LPASS_H -#define __DT_APQ8016_LPASS_H - -#include <dt-bindings/sound/qcom,lpass.h> - -/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ - -#endif /* __DT_APQ8016_LPASS_H */ diff --git a/include/dt-bindings/sound/tlv320aic31xx.h b/include/dt-bindings/sound/tlv320aic31xx.h deleted file mode 100644 index 4a80238ab250..000000000000 --- a/include/dt-bindings/sound/tlv320aic31xx.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_TLV320AIC31XX_H -#define __DT_TLV320AIC31XX_H - -#define MICBIAS_2_0V 1 -#define MICBIAS_2_5V 2 -#define MICBIAS_AVDDV 3 - -#define PLL_CLKIN_MCLK 0x00 -#define PLL_CLKIN_BCLK 0x01 -#define PLL_CLKIN_GPIO1 0x02 -#define PLL_CLKIN_DIN 0x03 - -#endif /* __DT_TLV320AIC31XX_H */

This adjusts OF_UPSTREAM to behave more like the kernel by allowing for all the devicetree files for a given vendor to be compiled. This is useful for Qualcomm in particular as most boards are supported by a single U-Boot build just provided with a different DT.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- dts/Kconfig | 24 ++++++++++++++++++++++++ scripts/Makefile.dts | 13 +++++++++++++ 2 files changed, 37 insertions(+)

diff --git a/dts/Kconfig b/dts/Kconfig index b9b6367154ef..6883a000a052 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -100,8 +100,32 @@ config OF_UPSTREAM However, newer boards whose devicetree source files haven't landed in the dts/upstream subtree, they can override this option to have the DT build from existing U-Boot tree location instead.

+config OF_UPSTREAM_BUILD_VENDOR + bool "Build all devicetree files for a particular vendor" + depends on OF_UPSTREAM + help + Enable building all devicetree files for a particular vendor. This + is useful for generic U-Boot configurations where many boards can + be supported with a single binary. + + This is only available for platforms using upstream devicetree. + +config OF_UPSTREAM_VENDOR + string "Vendor to build all upstream devicetree files for" + depends on OF_UPSTREAM_BUILD_VENDOR + default "qcom" if ARCH_SNAPDRAGON + default "rockchip" if ARCH_ROCKCHIP + default "amlogic" if ARCH_MESON + default "allwinner" if ARCH_SUNXI + default "mediatek" if ARCH_MEDIATEK + default "marvell" if ARCH_MVEBU || ARCH_KIRKWOOD + default "xilinx" if ARCH_VERSAL || ARCH_ZYNQ + default "nvidia" if ARCH_TEGRA + help + Select the vendor to build all devicetree files for. + choice prompt "Provider of DTB for DT control" depends on OF_CONTROL

diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 5e2429c6170c..790f3c508f19 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -1,3 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+

dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST))) + +ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := $(srctree)/dts/upstream/src/arm64 +else +dt_dir := $(srctree)/dts/upstream/src/$(ARCH) +endif + +dtb-vendor_dts := $(patsubst %.dts,%.dtb,$(wildcard $(dt_dir)/$(subst ",,$(CONFIG_OF_UPSTREAM_VENDOR))/*.dts)) + +dtb-y += $(subst $(dt_dir)/,,$(dtb-vendor_dts)) + +endif