Use C structs for registers, and use readl/writel instead of custom accessors.

Acked-by: Michael Brandt michael.brandt@stericsson.com Signed-off-by: Rabin Vincent rabin.vincent@stericsson.com --- drivers/serial/serial_pl01x.c | 56 ++++++++++++++++++++++------------------ drivers/serial/serial_pl01x.h | 41 ++++++++++++++++-------------- 2 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index c645cef..d2609d6 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -29,12 +29,10 @@

#include <common.h> #include <watchdog.h> +#include <asm/io.h>

#include "serial_pl01x.h"

-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - /* * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 @@ -49,16 +47,22 @@ static void pl01x_putc (int portnum, char c); static int pl01x_getc (int portnum); static int pl01x_tstc (int portnum);

+static struct pl01x_regs *pl01x_get_regs(int portnum) +{ + return (struct pl01x_regs *) port[portnum]; +} + #ifdef CONFIG_PL010_SERIAL

int serial_init (void) { + struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); unsigned int divisor;

/* ** First, disable everything. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + writel(0, &regs->pl010_cr);

/* ** Set baud rate @@ -89,20 +93,18 @@ int serial_init (void) divisor = UART_PL010_BAUD_38400; }

- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, - ((divisor & 0xf00) >> 8)); - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm); + writel(divisor & 0xff, &regs->pl010_lcrl);

/* ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, - (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);

/* ** Finally, enable the UART */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);

return 0; } @@ -113,6 +115,7 @@ int serial_init (void)

int serial_init (void) { + struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); unsigned int temp; unsigned int divider; unsigned int remainder; @@ -121,7 +124,7 @@ int serial_init (void) /* ** First, disable everything. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + writel(0, &regs->pl011_cr);

/* ** Set baud rate @@ -135,21 +138,20 @@ int serial_init (void) temp = (8 * remainder) / baudRate; fraction = (temp >> 1) + (temp & 1);

- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + writel(divider, &regs->pl011_ibrd); + writel(fraction, &regs->pl011_fbrd);

/* ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, - (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, + &regs->pl011_lcrh);

/* ** Finally, enable the UART */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, - (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | - UART_PL011_CR_RXE)); + writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, + &regs->pl011_cr);

return 0; } @@ -187,28 +189,31 @@ void serial_setbrg (void)

static void pl01x_putc (int portnum, char c) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); + /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) + while (readl(&regs->fr) & UART_PL01x_FR_TXFF) WATCHDOG_RESET();

/* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); + writel(c, &regs->dr); }

static int pl01x_getc (int portnum) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); unsigned int data;

/* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) + while (readl(&regs->fr) & UART_PL01x_FR_RXFE) WATCHDOG_RESET();

- data = IO_READ (port[portnum] + UART_PL01x_DR); + data = readl(&regs->dr);

/* Check for an error flag */ if (data & 0xFFFFFF00) { /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + writel(0xFFFFFFFF, &regs->ecr); return -1; }

@@ -217,7 +222,8 @@ static int pl01x_getc (int portnum)

static int pl01x_tstc (int portnum) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); + WATCHDOG_RESET(); - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); + return !(readl(&regs->fr) & UART_PL01x_FR_RXFE); } diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index 5f20fdd..b670c24 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -29,10 +29,28 @@ * Definitions common to both PL010 & PL011 * */ -#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ -#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ -#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ -#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#ifndef __ASSEMBLY__ +/* + * We can use a combined structure for PL010 and PL011, because they overlap + * only in common registers. + */ +struct pl01x_regs { + u32 dr; /* 0x00 Data register */ + u32 ecr; /* 0x04 Error clear register (Write) */ + u32 pl010_lcrh; /* 0x08 Line control register, high byte */ + u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ + u32 pl010_lcrl; /* 0x10 Line control register, low byte */ + u32 pl010_cr; /* 0x14 Control register */ + u32 fr; /* 0x18 Flag register (Read only) */ + u32 reserved; + u32 ilpr; /* 0x20 IrDA low-power counter register */ + u32 pl011_ibrd; /* 0x24 Integer baud rate register */ + u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ + u32 pl011_lcrh; /* 0x2C Line control register */ + u32 pl011_cr; /* 0x30 Control register */ +}; +#endif

#define UART_PL01x_RSR_OE 0x08 #define UART_PL01x_RSR_BE 0x04 @@ -50,14 +68,6 @@ * PL010 definitions * */ -#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ -#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ -#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ -#define UART_PL010_CR 0x14 /* Control register. */ -#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ -#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ -#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ - #define UART_PL010_CR_LPE (1 << 7) #define UART_PL010_CR_RTIE (1 << 6) #define UART_PL010_CR_TIE (1 << 5) @@ -93,13 +103,6 @@ * PL011 definitions * */ -#define UART_PL011_IBRD 0x24 -#define UART_PL011_FBRD 0x28 -#define UART_PL011_LCRH 0x2C -#define UART_PL011_CR 0x30 -#define UART_PL011_IMSC 0x38 -#define UART_PL011_PERIPH_ID0 0xFE0 - #define UART_PL011_LCRH_SPS (1 << 7) #define UART_PL011_LCRH_WLEN_8 (3 << 5) #define UART_PL011_LCRH_WLEN_7 (2 << 5)