Add StarFive JH7110 SoC to support RISC-V arch.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com Reviewed-by: Rick Chen rick@andestech.com --- arch/riscv/cpu/jh7110/Makefile | 10 ++++ arch/riscv/cpu/jh7110/cpu.c | 23 ++++++++ arch/riscv/cpu/jh7110/dram.c | 38 ++++++++++++++ arch/riscv/cpu/jh7110/spl.c | 64 +++++++++++++++++++++++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 +++++++ arch/riscv/include/asm/arch-jh7110/spl.h | 12 +++++ 6 files changed, 166 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c create mode 100644 arch/riscv/cpu/jh7110/dram.c create mode 100644 arch/riscv/cpu/jh7110/spl.c create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h

diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile new file mode 100644 index 0000000000..951c95631e --- /dev/null +++ b/arch/riscv/cpu/jh7110/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else +obj-y += cpu.o +obj-y += dram.o +endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c new file mode 100644 index 0000000000..1d7c026584 --- /dev/null +++ b/arch/riscv/cpu/jh7110/cpu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <asm/cache.h> +#include <irq_func.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c new file mode 100644 index 0000000000..2ad3f2044a --- /dev/null +++ b/arch/riscv/cpu/jh7110/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G) + return SZ_4G; + + return gd->ram_top; +} diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c new file mode 100644 index 0000000000..104f0fe949 --- /dev/null +++ b/arch/riscv/cpu/jh7110/spl.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + */ + +#include <asm/csr.h> +#include <asm/sections.h> +#include <dm.h> +#include <log.h> + +#define CSR_U74_FEATURE_DISABLE 0x7c1 +#define L2_LIM_MEM_END 0x81FFFFFUL + +int spl_soc_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} + +void harts_early_init(void) +{ + ulong *ptr; + u8 *tmp; + ulong len, remain; + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); + + /* clear L2 LIM memory + * set __bss_end to 0x81FFFFF region to zero + * The L2 Cache Controller supports ECC. ECC is applied to SRAM. + * If it is not cleared, the ECC part is invalid, and an ECC error + * will be reported when reading data. + */ + ptr = (ulong *)&__bss_end; + len = L2_LIM_MEM_END - (ulong)&__bss_end; + remain = len % sizeof(ulong); + len /= sizeof(ulong); + + while (len--) + *ptr++ = 0; + + /* clear the remain bytes */ + if (remain) { + tmp = (u8 *)ptr; + while (remain--) + *tmp++ = 0; + } +} diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h b/arch/riscv/include/asm/arch-jh7110/regs.h new file mode 100644 index 0000000000..05026870a0 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/regs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#ifndef __STARFIVE_JH7110_REGS_H +#define __STARFIVE_JH7110_REGS_H + +#define JH7110_SYS_CRG 0x13020000 +#define JH7110_SYS_SYSCON 0x13030000 +#define JH7110_SYS_IOMUX 0x13040000 +#define JH7110_AON_CRG 0x17000000 +#define JH7110_AON_SYSCON 0x17010000 + +#define JH7110_BOOT_MODE_SELECT_REG 0x1702002c +#define JH7110_BOOT_MODE_SELECT_MASK GENMASK(1, 0) + +#endif /* __STARFIVE_JH7110_REGS_H */ diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h new file mode 100644 index 0000000000..23ce8871b3 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#ifndef _SPL_STARFIVE_H +#define _SPL_STARFIVE_H + +int spl_soc_init(void); + +#endif /* _SPL_STARFIVE_H */

Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- include/dt-bindings/reset/starfive-jh7110.h | 183 ++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 include/dt-bindings/reset/starfive-jh7110.h

diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h new file mode 100644 index 0000000000..da87356889 --- /dev/null +++ b/include/dt-bindings/reset/starfive-jh7110.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG2APB 0 +#define JH7110_SYSRST_SYSCON 1 +#define JH7110_SYSRST_IOMUX 2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG 4 +#define JH7110_SYSRST_CORE0 5 +#define JH7110_SYSRST_CORE1 6 +#define JH7110_SYSRST_CORE2 7 +#define JH7110_SYSRST_CORE3 8 +#define JH7110_SYSRST_CORE4 9 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM 20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 +#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_DOM_ISP_TOP_N 41 +#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 +#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 +#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB 64 +#define JH7110_SYSRST_SDIO1_AHB 65 +#define JH7110_SYSRST_GMAC1_AXI 66 +#define JH7110_SYSRST_GMAC1_AHB 67 +#define JH7110_SYSRST_MAILBOX 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define JH7110_SYSRST_I2C5_APB 81 +#define JH7110_SYSRST_I2C6_APB 82 +#define JH7110_SYSRST_UART0_APB 83 +#define JH7110_SYSRST_UART0_CORE 84 +#define JH7110_SYSRST_UART1_APB 85 +#define JH7110_SYSRST_UART1_CORE 86 +#define JH7110_SYSRST_UART2_APB 87 +#define JH7110_SYSRST_UART2_CORE 88 +#define JH7110_SYSRST_UART3_APB 89 +#define JH7110_SYSRST_UART3_CORE 90 +#define JH7110_SYSRST_UART4_APB 91 +#define JH7110_SYSRST_UART4_CORE 92 +#define JH7110_SYSRST_UART5_APB 93 +#define JH7110_SYSRST_UART5_CORE 94 +#define JH7110_SYSRST_SPDIF_APB 95 + +#define JH7110_SYSRST_PWMDAC_APB 96 +#define JH7110_SYSRST_PDM_DMIC 97 +#define JH7110_SYSRST_PDM_APB 98 +#define JH7110_SYSRST_I2SRX_APB 99 +#define JH7110_SYSRST_I2SRX_BCLK 100 +#define JH7110_SYSRST_I2STX0_APB 101 +#define JH7110_SYSRST_I2STX0_BCLK 102 +#define JH7110_SYSRST_I2STX1_APB 103 +#define JH7110_SYSRST_I2STX1_BCLK 104 +#define JH7110_SYSRST_TDM_AHB 105 +#define JH7110_SYSRST_TDM_CORE 106 +#define JH7110_SYSRST_TDM_APB 107 +#define JH7110_SYSRST_PWM_APB 108 +#define JH7110_SYSRST_WDT_APB 109 +#define JH7110_SYSRST_WDT_CORE 110 +#define JH7110_SYSRST_CAN0_APB 111 +#define JH7110_SYSRST_CAN0_CORE 112 +#define JH7110_SYSRST_CAN0_TIMER 113 +#define JH7110_SYSRST_CAN1_APB 114 +#define JH7110_SYSRST_CAN1_CORE 115 +#define JH7110_SYSRST_CAN1_TIMER 116 +#define JH7110_SYSRST_TIMER_APB 117 +#define JH7110_SYSRST_TIMER0 118 +#define JH7110_SYSRST_TIMER1 119 +#define JH7110_SYSRST_TIMER2 120 +#define JH7110_SYSRST_TIMER3 121 +#define JH7110_SYSRST_INT_CTRL_APB 122 +#define JH7110_SYSRST_TEMP_APB 123 +#define JH7110_SYSRST_TEMP_CORE 124 +#define JH7110_SYSRST_JTAG_CERTIFICATION 125 + +#define JH7110_SYSRST_END 126 + +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_AON_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + +/* STGCRG resets */ +#define JH7110_STGRST_SYSCON_PRESETN 0 +#define JH7110_STGRST_HIFI4_CORE 1 +#define JH7110_STGRST_HIFI4_AXI 2 +#define JH7110_STGRST_SEC_TOP_HRESETN 3 +#define JH7110_STGRST_E24_CORE 4 +#define JH7110_STGRST_DMA1P_AXI 5 +#define JH7110_STGRST_DMA1P_AHB 6 +#define JH7110_STGRST_USB_AXI 7 +#define JH7110_STGRST_USB_APB 8 +#define JH7110_STGRST_USB_UTMI_APB 9 +#define JH7110_STGRST_USB_PWRUP 10 +#define JH7110_STGRST_PCIE0_MST0 11 +#define JH7110_STGRST_PCIE0_SLV0 12 +#define JH7110_STGRST_PCIE0_SLV 13 +#define JH7110_STGRST_PCIE0_BRG 14 +#define JH7110_STGRST_PCIE0_CORE 15 +#define JH7110_STGRST_PCIE0_APB 16 +#define JH7110_STGRST_PCIE1_MST0 17 +#define JH7110_STGRST_PCIE1_SLV0 18 +#define JH7110_STGRST_PCIE1_SLV 19 +#define JH7110_STGRST_PCIE1_BRG 20 +#define JH7110_STGRST_PCIE1_CORE 21 +#define JH7110_STGRST_PCIE1_APB 22 + +#define JH7110_STGRST_END 23 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */

Add all clock outputs for the StarFive JH7110 clock generator.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- include/dt-bindings/clock/starfive-jh7110.h | 271 ++++++++++++++++++++ 1 file changed, 271 insertions(+) create mode 100644 include/dt-bindings/clock/starfive-jh7110.h

diff --git a/include/dt-bindings/clock/starfive-jh7110.h b/include/dt-bindings/clock/starfive-jh7110.h new file mode 100644 index 0000000000..f25b6730c0 --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7110.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLOCK_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLOCK_H__ + +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT 4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS_FUNC 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV2 13 +#define JH7110_SYSCLK_PLL1_DIV2 14 +#define JH7110_SYSCLK_PLL2_DIV2 15 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK0 22 +#define JH7110_SYSCLK_GCLK1 23 +#define JH7110_SYSCLK_GCLK2 24 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE1 26 +#define JH7110_SYSCLK_CORE2 27 +#define JH7110_SYSCLK_CORE3 28 +#define JH7110_SYSCLK_CORE4 29 +#define JH7110_SYSCLK_DEBUG 30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM 37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV4 41 +#define JH7110_SYSCLK_PLL1_DIV8 42 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI 55 +#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 +#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 +#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 +#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI 65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 +#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB 81 +#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 +#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 +#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 +#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 +#define JH7110_SYSCLK_AXIMEM2_AXI 86 +#define JH7110_SYSCLK_QSPI_AHB 87 +#define JH7110_SYSCLK_QSPI_APB 88 +#define JH7110_SYSCLK_QSPI_REF_SRC 89 +#define JH7110_SYSCLK_QSPI_REF 90 +#define JH7110_SYSCLK_SDIO0_AHB 91 +#define JH7110_SYSCLK_SDIO1_AHB 92 +#define JH7110_SYSCLK_SDIO0_SDCARD 93 +#define JH7110_SYSCLK_SDIO1_SDCARD 94 +#define JH7110_SYSCLK_USB_125M 95 +#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 +#define JH7110_SYSCLK_GMAC1_AHB 97 +#define JH7110_SYSCLK_GMAC1_AXI 98 +#define JH7110_SYSCLK_GMAC_SRC 99 +#define JH7110_SYSCLK_GMAC1_GTXCLK 100 +#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 +#define JH7110_SYSCLK_GMAC1_PTP 102 +#define JH7110_SYSCLK_GMAC1_RX 103 +#define JH7110_SYSCLK_GMAC1_RX_INV 104 +#define JH7110_SYSCLK_GMAC1_TX 105 +#define JH7110_SYSCLK_GMAC1_TX_INV 106 +#define JH7110_SYSCLK_GMAC1_GTXC 107 +#define JH7110_SYSCLK_GMAC0_GTXCLK 108 +#define JH7110_SYSCLK_GMAC0_PTP 109 +#define JH7110_SYSCLK_GMAC_PHY 110 +#define JH7110_SYSCLK_GMAC0_GTXC 111 +#define JH7110_SYSCLK_IOMUX 112 +#define JH7110_SYSCLK_MAILBOX 113 +#define JH7110_SYSCLK_INT_CTRL_APB 114 +#define JH7110_SYSCLK_CAN0_APB 115 +#define JH7110_SYSCLK_CAN0_TIMER 116 +#define JH7110_SYSCLK_CAN0_CAN 117 +#define JH7110_SYSCLK_CAN1_APB 118 +#define JH7110_SYSCLK_CAN1_TIMER 119 +#define JH7110_SYSCLK_CAN1_CAN 120 +#define JH7110_SYSCLK_PWM_APB 121 +#define JH7110_SYSCLK_WDT_APB 122 +#define JH7110_SYSCLK_WDT_CORE 123 +#define JH7110_SYSCLK_TIMER_APB 124 +#define JH7110_SYSCLK_TIMER0 125 +#define JH7110_SYSCLK_TIMER1 126 +#define JH7110_SYSCLK_TIMER2 127 +#define JH7110_SYSCLK_TIMER3 128 +#define JH7110_SYSCLK_TEMP_APB 129 +#define JH7110_SYSCLK_TEMP_CORE 130 +#define JH7110_SYSCLK_SPI0_APB 131 +#define JH7110_SYSCLK_SPI1_APB 132 +#define JH7110_SYSCLK_SPI2_APB 133 +#define JH7110_SYSCLK_SPI3_APB 134 +#define JH7110_SYSCLK_SPI4_APB 135 +#define JH7110_SYSCLK_SPI5_APB 136 +#define JH7110_SYSCLK_SPI6_APB 137 +#define JH7110_SYSCLK_I2C0_APB 138 +#define JH7110_SYSCLK_I2C1_APB 139 +#define JH7110_SYSCLK_I2C2_APB 140 +#define JH7110_SYSCLK_I2C3_APB 141 +#define JH7110_SYSCLK_I2C4_APB 142 +#define JH7110_SYSCLK_I2C5_APB 143 +#define JH7110_SYSCLK_I2C6_APB 144 +#define JH7110_SYSCLK_UART0_APB 145 +#define JH7110_SYSCLK_UART0_CORE 146 +#define JH7110_SYSCLK_UART1_APB 147 +#define JH7110_SYSCLK_UART1_CORE 148 +#define JH7110_SYSCLK_UART2_APB 149 +#define JH7110_SYSCLK_UART2_CORE 150 +#define JH7110_SYSCLK_UART3_APB 151 +#define JH7110_SYSCLK_UART3_CORE 152 +#define JH7110_SYSCLK_UART4_APB 153 +#define JH7110_SYSCLK_UART4_CORE 154 +#define JH7110_SYSCLK_UART5_APB 155 +#define JH7110_SYSCLK_UART5_CORE 156 +#define JH7110_SYSCLK_PWMDAC_APB 157 +#define JH7110_SYSCLK_PWMDAC_CORE 158 +#define JH7110_SYSCLK_SPDIF_APB 159 +#define JH7110_SYSCLK_SPDIF_CORE 160 +#define JH7110_SYSCLK_I2STX0_APB 161 +#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 +#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 +#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 +#define JH7110_SYSCLK_I2STX0_BCLK 165 +#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 +#define JH7110_SYSCLK_I2STX0_LRCK 167 +#define JH7110_SYSCLK_I2STX1_APB 168 +#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 +#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 +#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 +#define JH7110_SYSCLK_I2STX1_BCLK 172 +#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 +#define JH7110_SYSCLK_I2STX1_LRCK 174 +#define JH7110_SYSCLK_I2SRX_APB 175 +#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 +#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 +#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 +#define JH7110_SYSCLK_I2SRX_BCLK 179 +#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 +#define JH7110_SYSCLK_I2SRX_LRCK 181 +#define JH7110_SYSCLK_PDM_DMIC 182 +#define JH7110_SYSCLK_PDM_APB 183 +#define JH7110_SYSCLK_TDM_AHB 184 +#define JH7110_SYSCLK_TDM_APB 185 +#define JH7110_SYSCLK_TDM_INTERNAL 186 +#define JH7110_SYSCLK_TDM_CLK_TDM 187 +#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 +#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 + +#define JH7110_SYSCLK_PLL0_OUT 190 +#define JH7110_SYSCLK_PLL1_OUT 191 +#define JH7110_SYSCLK_PLL2_OUT 192 +#define JH7110_SYSCLK_PCLK2_MUX_FUNC 193 +#define JH7110_SYSCLK_PCLK2_MUX 194 +#define JH7110_SYSCLK_APB_BUS 195 +#define JH7110_SYSCLK_AXI_CFG1 196 +#define JH7110_SYSCLK_APB12 197 +#define JH7110_SYSCLK_VOUT_ROOT 198 +#define JH7110_SYSCLK_VENC_ROOT 199 +#define JH7110_SYSCLK_VDEC_ROOT 200 +#define JH7110_SYSCLK_GMACUSB_ROOT 201 +#define JH7110_SYSCLK_AON_APB 202 +#define JH7110_SYSCLK_AON_AHB 203 +#define JH7110_SYSCLK_I2C5_CORE 204 + +#define JH7110_SYSCLK_END 205 + +#define JH7110_AONCLK_OSC_DIV4 (JH7110_SYSCLK_END + 0) +#define JH7110_AONCLK_APB_FUNC (JH7110_SYSCLK_END + 1) +#define JH7110_AONCLK_GMAC0_AHB (JH7110_SYSCLK_END + 2) +#define JH7110_AONCLK_GMAC0_AXI (JH7110_SYSCLK_END + 3) +#define JH7110_AONCLK_GMAC0_RMII_RTX (JH7110_SYSCLK_END + 4) +#define JH7110_AONCLK_GMAC0_TX (JH7110_SYSCLK_END + 5) +#define JH7110_AONCLK_GMAC0_TX_INV (JH7110_SYSCLK_END + 6) +#define JH7110_AONCLK_GMAC0_RX (JH7110_SYSCLK_END + 7) +#define JH7110_AONCLK_GMAC0_RX_INV (JH7110_SYSCLK_END + 8) +#define JH7110_AONCLK_OTPC_APB (JH7110_SYSCLK_END + 9) +#define JH7110_AONCLK_RTC_APB (JH7110_SYSCLK_END + 10) +#define JH7110_AONCLK_RTC_INTERNAL (JH7110_SYSCLK_END + 11) +#define JH7110_AONCLK_RTC_32K (JH7110_SYSCLK_END + 12) +#define JH7110_AONCLK_RTC_CAL (JH7110_SYSCLK_END + 13) + +#define JH7110_AONCLK_END (JH7110_SYSCLK_END + 14) + +#define JH7110_STGCLK_HIFI4_CORE (JH7110_AONCLK_END + 0) +#define JH7110_STGCLK_USB_APB (JH7110_AONCLK_END + 1) +#define JH7110_STGCLK_USB_UTMI_APB (JH7110_AONCLK_END + 2) +#define JH7110_STGCLK_USB_AXI (JH7110_AONCLK_END + 3) +#define JH7110_STGCLK_USB_LPM (JH7110_AONCLK_END + 4) +#define JH7110_STGCLK_USB_STB (JH7110_AONCLK_END + 5) +#define JH7110_STGCLK_USB_APP_125 (JH7110_AONCLK_END + 6) +#define JH7110_STGCLK_USB_REFCLK (JH7110_AONCLK_END + 7) +#define JH7110_STGCLK_PCIE0_AXI (JH7110_AONCLK_END + 8) +#define JH7110_STGCLK_PCIE0_APB (JH7110_AONCLK_END + 9) +#define JH7110_STGCLK_PCIE0_TL (JH7110_AONCLK_END + 10) +#define JH7110_STGCLK_PCIE1_AXI (JH7110_AONCLK_END + 11) +#define JH7110_STGCLK_PCIE1_APB (JH7110_AONCLK_END + 12) +#define JH7110_STGCLK_PCIE1_TL (JH7110_AONCLK_END + 13) +#define JH7110_STGCLK_PCIE01_MAIN (JH7110_AONCLK_END + 14) +#define JH7110_STGCLK_SEC_HCLK (JH7110_AONCLK_END + 15) +#define JH7110_STGCLK_SEC_MISCAHB (JH7110_AONCLK_END + 16) +#define JH7110_STGCLK_MTRX_GRP0_MAIN (JH7110_AONCLK_END + 17) +#define JH7110_STGCLK_MTRX_GRP0_BUS (JH7110_AONCLK_END + 18) +#define JH7110_STGCLK_MTRX_GRP0_STG (JH7110_AONCLK_END + 19) +#define JH7110_STGCLK_MTRX_GRP1_MAIN (JH7110_AONCLK_END + 20) +#define JH7110_STGCLK_MTRX_GRP1_BUS (JH7110_AONCLK_END + 21) +#define JH7110_STGCLK_MTRX_GRP1_STG (JH7110_AONCLK_END + 22) +#define JH7110_STGCLK_MTRX_GRP1_HIFI (JH7110_AONCLK_END + 23) +#define JH7110_STGCLK_E2_RTC (JH7110_AONCLK_END + 24) +#define JH7110_STGCLK_E2_CORE (JH7110_AONCLK_END + 25) +#define JH7110_STGCLK_E2_DBG (JH7110_AONCLK_END + 26) +#define JH7110_STGCLK_DMA1P_AXI (JH7110_AONCLK_END + 27) +#define JH7110_STGCLK_DMA1P_AHB (JH7110_AONCLK_END + 28) + +#define JH7110_STGCLK_STG_APB (JH7110_AONCLK_END + 29) + +#define JH7110_STGCLK_END (JH7110_AONCLK_END + 30) + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLOCK_H__ */

Add a DM clock driver for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 17 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 293 ++++++++++++++ drivers/clk/starfive/clk-jh7110.c | 559 ++++++++++++++++++++++++++ drivers/clk/starfive/clk.h | 60 +++ 7 files changed, 935 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c..4d60c84aad 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c274cda77c..66f5860356 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o

obj-y += analogbits/ obj-y += imx/ +obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 0000000000..9399ef6d51 --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on STARFIVE_JH7110 && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM support for clock driver in JH7110. + +config CLK_JH7110 + bool "StarFive JH7110 clock support" + depends on STARFIVE_JH7110 + select CLK + select CLK_CCF + help + This enables support clock driver for StarFive JH7110 SoC platform. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 0000000000..ec0d157094 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk-jh7110.o +obj-y += clk-jh7110-pll.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c new file mode 100644 index 0000000000..08e1755d3a --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm/device.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include "clk.h" + +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +#define CLK_DDR_BUS_MASK GENMASK(29, 24) +#define CLK_DDR_BUS_OFFSET 0xAC +#define CLK_DDR_BUS_OSC_DIV2 0 +#define CLK_DDR_BUS_PLL1_DIV2 1 +#define CLK_DDR_BUS_PLL1_DIV4 2 +#define CLK_DDR_BUS_PLL1_DIV8 3 + +struct clk_jh7110_pllx { + struct clk clk; + void __iomem *base; + void __iomem *sysreg; + enum starfive_pll_type type; + const struct starfive_pllx_offset *offset; + const struct starfive_pllx_rate *rate_table; + int rate_count; +}; + +#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask))) + +#define PLLX_SET(offset, mask, val) do {\ + reg = readl((ulong *)((ulong)pll->base + (offset))); \ + reg &= ~(mask); \ + reg |= (mask) & ((val) << __ffs(mask)); \ + writel(reg, (ulong *)((ulong)pll->base + (offset))); \ + } while (0) + +#define PLLX_RATE(_rate, _pd, _fd, _pd1, _da, _ds) \ + { \ + .rate = (_rate), \ + .prediv = (_pd), \ + .fbdiv = (_fd), \ + .postdiv1 = (_pd1), \ + .dacpd = (_da), \ + .dsmpd = (_ds), \ + } + +#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk) + +static const struct starfive_pllx_rate jh7110_pll0_tbl[] = { + PLLX_RATE(375000000UL, 8, 125, 1, 1, 1), + PLLX_RATE(500000000UL, 6, 125, 1, 1, 1), + PLLX_RATE(625000000UL, 24, 625, 1, 1, 1), + PLLX_RATE(750000000UL, 4, 125, 1, 1, 1), + PLLX_RATE(875000000UL, 24, 875, 1, 1, 1), + PLLX_RATE(1000000000UL, 3, 125, 1, 1, 1), + PLLX_RATE(1250000000UL, 12, 625, 1, 1, 1), + PLLX_RATE(1375000000UL, 24, 1375, 1, 1, 1), + PLLX_RATE(1500000000UL, 2, 125, 1, 1, 1), + PLLX_RATE(1625000000UL, 24, 1625, 1, 1, 1), + PLLX_RATE(1750000000UL, 12, 875, 1, 1, 1), + PLLX_RATE(1800000000UL, 3, 225, 1, 1, 1), +}; + +static const struct starfive_pllx_rate jh7110_pll1_tbl[] = { + PLLX_RATE(1066000000UL, 12, 533, 1, 1, 1), + PLLX_RATE(1200000000UL, 1, 50, 1, 1, 1), + PLLX_RATE(1400000000UL, 6, 350, 1, 1, 1), + PLLX_RATE(1600000000UL, 3, 200, 1, 1, 1), +}; + +static const struct starfive_pllx_rate jh7110_pll2_tbl[] = { + PLLX_RATE(1228800000UL, 15, 768, 1, 1, 1), + PLLX_RATE(1188000000UL, 2, 99, 1, 1, 1), +}; + +static const struct starfive_pllx_offset jh7110_pll0_offset = { + .prediv = 0x24, + .fbdiv = 0x1c, + .frac = 0x20, + .postdiv1 = 0x20, + .dacpd = 0x18, + .dsmpd = 0x18, + .prediv_mask = GENMASK(5, 0), + .fbdiv_mask = GENMASK(11, 0), + .frac_mask = GENMASK(23, 0), + .postdiv1_mask = GENMASK(29, 28), + .dacpd_mask = BIT(24), + .dsmpd_mask = BIT(25) +}; + +static const struct starfive_pllx_offset jh7110_pll1_offset = { + .prediv = 0x2c, + .fbdiv = 0x24, + .frac = 0x28, + .postdiv1 = 0x28, + .dacpd = 0x24, + .dsmpd = 0x24, + .prediv_mask = GENMASK(5, 0), + .fbdiv_mask = GENMASK(28, 17), + .frac_mask = GENMASK(23, 0), + .postdiv1_mask = GENMASK(29, 28), + .dacpd_mask = BIT(15), + .dsmpd_mask = BIT(16) +}; + +static const struct starfive_pllx_offset jh7110_pll2_offset = { + .prediv = 0x34, + .fbdiv = 0x2c, + .frac = 0x30, + .postdiv1 = 0x30, + .dacpd = 0x2c, + .dsmpd = 0x2c, + .prediv_mask = GENMASK(5, 0), + .fbdiv_mask = GENMASK(28, 17), + .frac_mask = GENMASK(23, 0), + .postdiv1_mask = GENMASK(29, 28), + .dacpd_mask = BIT(15), + .dsmpd_mask = BIT(16) +}; + +struct starfive_pllx_clk starfive_jh7110_pll0 __initdata = { + .type = PLL0, + .offset = &jh7110_pll0_offset, + .rate_table = jh7110_pll0_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll0_tbl), +}; + +struct starfive_pllx_clk starfive_jh7110_pll1 __initdata = { + .type = PLL1, + .offset = &jh7110_pll1_offset, + .rate_table = jh7110_pll1_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll1_tbl), +}; + +struct starfive_pllx_clk starfive_jh7110_pll2 __initdata = { + .type = PLL2, + .offset = &jh7110_pll2_offset, + .rate_table = jh7110_pll2_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll2_tbl), +}; + +static const struct starfive_pllx_rate * + jh7110_get_pll_settings(struct clk_jh7110_pllx *pll, unsigned long rate) +{ + for (int i = 0; i < pll->rate_count; i++) + if (rate == pll->rate_table[i].rate) + return &pll->rate_table[i]; + + return NULL; +} + +static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, + const struct starfive_pllx_rate *rate) +{ + u32 reg; + bool set = (pll->type == PLL1) ? true : false; + + if (set) { + reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); + reg &= ~CLK_DDR_BUS_MASK; + reg |= CLK_DDR_BUS_OSC_DIV2 << __ffs(CLK_DDR_BUS_MASK); + writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); + } + + PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_OFF); + PLLX_SET(pll->offset->dacpd, pll->offset->dacpd_mask, rate->dacpd); + PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, rate->dsmpd); + PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); + PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv); + PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, rate->postdiv1 >> 1); + PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); + + if (set) { + udelay(100); + reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); + reg &= ~CLK_DDR_BUS_MASK; + reg |= CLK_DDR_BUS_PLL1_DIV2 << __ffs(CLK_DDR_BUS_MASK); + writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET)); + } +} + +static ulong jh7110_pllx_recalc_rate(struct clk *clk) +{ + struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev)); + u64 refclk = clk_get_parent_rate(clk); + u32 dacpd, dsmpd; + u32 prediv, fbdiv, postdiv1; + u64 frac; + + dacpd = getbits_le32((ulong)pll->base + pll->offset->dacpd, + pll->offset->dacpd_mask); + dsmpd = getbits_le32((ulong)pll->base + pll->offset->dsmpd, + pll->offset->dsmpd_mask); + prediv = getbits_le32((ulong)pll->base + pll->offset->prediv, + pll->offset->prediv_mask); + fbdiv = getbits_le32((ulong)pll->base + pll->offset->fbdiv, + pll->offset->fbdiv_mask); + postdiv1 = 1 << getbits_le32((ulong)pll->base + pll->offset->postdiv1, + pll->offset->postdiv1_mask); + frac = (u64)getbits_le32((ulong)pll->base + pll->offset->frac, + pll->offset->frac_mask); + + /* Integer Mode or Fraction Mode */ + if (dacpd == 1 && dsmpd == 1) + frac = 0; + else if (dacpd == 0 && dsmpd == 0) + do_div(frac, 1 << 24); + else + return -EINVAL; + + refclk *= (fbdiv + frac); + do_div(refclk, prediv * postdiv1); + + return refclk; +} + +static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate) +{ + struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev)); + const struct starfive_pllx_rate *rate; + + rate = jh7110_get_pll_settings(pll, drate); + if (!rate) + return -EINVAL; + + jh7110_pll_set_rate(pll, rate); + + return jh7110_pllx_recalc_rate(clk); +} + +static const struct clk_ops clk_jh7110_ops = { + .set_rate = jh7110_pllx_set_rate, + .get_rate = jh7110_pllx_recalc_rate, +}; + +struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, + void __iomem *base, void __iomem *sysreg, + const struct starfive_pllx_clk *pll_clk) +{ + struct clk_jh7110_pllx *pll; + struct clk *clk; + int ret; + + if (!pll_clk || !base || !sysreg) + return ERR_PTR(-EINVAL); + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->sysreg = sysreg; + pll->type = pll_clk->type; + pll->offset = pll_clk->offset; + pll->rate_table = pll_clk->rate_table; + pll->rate_count = pll_clk->rate_count; + + clk = &pll->clk; + ret = clk_register(clk, UBOOT_DM_CLK_JH7110_PLLX, name, parent_name); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0) + jh7110_pllx_set_rate(clk, 1250000000); + + if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2) + jh7110_pllx_set_rate(clk, 1188000000); + + return clk; +} + +U_BOOT_DRIVER(jh7110_clk_pllx) = { + .name = UBOOT_DM_CLK_JH7110_PLLX, + .id = UCLASS_CLK, + .ops = &clk_jh7110_ops, +}; diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c new file mode 100644 index 0000000000..a904852cab --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110.c @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dt-bindings/clock/starfive-jh7110.h> +#include <log.h> +#include <linux/clk-provider.h> + +#include "clk.h" + +#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */ +#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */ +#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */ +#define STARFIVE_CLK_DIV_SHIFT 0 /* [23:0] */ + +#define OFFSET(id) ((id) * 4) +#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4) +#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4) + +typedef int (*jh1710_init_fn)(struct udevice *dev); + +struct jh7110_clk_priv { + void __iomem *reg; + jh1710_init_fn init; +}; + +static const char *cpu_root_sels[2] = { + [0] = "osc", + [1] = "pll0_out", +}; + +static const char *perh_root_sels[2] = { + [0] = "pll0_out", + [1] = "pll2_out", +}; + +static const char *bus_root_sels[2] = { + [0] = "osc", + [1] = "pll2_out", +}; + +static const char *qspi_ref_sels[2] = { + [0] = "osc", + [1] = "qspi_ref_src", +}; + +static const char *gmac1_tx_sels[2] = { + [0] = "gmac1_gtxclk", + [1] = "gmac1_rmii_rtx", +}; + +static const char *gmac0_tx_sels[2] = { + [0] = "gmac0_gtxclk", + [1] = "gmac0_rmii_rtx", +}; + +static struct clk *starfive_clk_mux(void __iomem *reg, + const char *name, + unsigned int offset, + u8 width, + const char * const *parent_names, + u8 num_parents) +{ + return clk_register_mux(NULL, name, parent_names, num_parents, 0, + reg + offset, STARFIVE_CLK_MUX_SHIFT, + width, 0); +} + +static struct clk *starfive_clk_gate(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg + offset, + STARFIVE_CLK_ENABLE_SHIFT, 0, NULL); +} + +static struct clk *starfive_clk_fix_factor(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent_name, + 0, mult, div); +} + +static struct clk *starfive_clk_divider(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset, + u8 width) +{ + return clk_register_divider(NULL, name, parent_name, 0, reg + offset, + 0, width, CLK_DIVIDER_ONE_BASED); +} + +static struct clk *starfive_clk_composite(void __iomem *reg, + const char *name, + const char * const *parent_names, + unsigned int num_parents, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + int mask_arry[4] = {0x1, 0x3, 0x7, 0xF}; + int mask; + + if (mux_width) { + if (mux_width > 4) + goto fail; + else + mask = mask_arry[mux_width - 1]; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg + offset; + mux->mask = mask; + mux->shift = STARFIVE_CLK_MUX_SHIFT; + mux->num_parents = num_parents; + mux->flags = 0; + mux->parent_names = parent_names; + } + + if (gate_width) { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + + if (!gate) + goto fail; + + gate->reg = reg + offset; + gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT; + gate->flags = 0; + } + + if (div_width) { + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg + offset; + + if (offset == OFFSET(JH7110_SYSCLK_UART3_CORE) || + offset == OFFSET(JH7110_SYSCLK_UART4_CORE) || + offset == OFFSET(JH7110_SYSCLK_UART5_CORE)) { + div->shift = 8; + div->width = 8; + } else { + div->shift = STARFIVE_CLK_DIV_SHIFT; + div->width = div_width; + } + div->flags = CLK_DIVIDER_ONE_BASED; + div->table = NULL; + } + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + &gate->clk, &clk_gate_ops, 0); + + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} + +static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg, + const char *name, + const char *parent_names, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + const char * const *parents; + + parents = &parent_names; + + return starfive_clk_composite(reg, name, parents, 1, offset, + mux_width, gate_width, div_width); +} + +static struct clk *starfive_clk_gate_divider(void __iomem *reg, + const char *name, + const char *parent, + unsigned int offset, + unsigned int width) +{ + const char * const *parent_names; + + parent_names = &parent; + + return starfive_clk_composite(reg, name, parent_names, 1, + offset, 0, 1, width); +} + +static int jh7110_syscrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + fdt_addr_t addr; + int ret; + + ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args); + if (ret) + return ret; + + addr = ofnode_get_addr(args.node); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + clk_dm(JH7110_SYSCLK_PLL0_OUT, + starfive_jh7110_pll("pll0_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll0)); + clk_dm(JH7110_SYSCLK_PLL1_OUT, + starfive_jh7110_pll("pll1_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll1)); + clk_dm(JH7110_SYSCLK_PLL2_OUT, + starfive_jh7110_pll("pll2_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll2)); + clk_dm(JH7110_SYSCLK_CPU_ROOT, + starfive_clk_mux(priv->reg, "cpu_root", + OFFSET(JH7110_SYSCLK_CPU_ROOT), 1, + cpu_root_sels, ARRAY_SIZE(cpu_root_sels))); + clk_dm(JH7110_SYSCLK_CPU_CORE, + starfive_clk_divider(priv->reg, + "cpu_core", "cpu_root", + OFFSET(JH7110_SYSCLK_CPU_CORE), 3)); + clk_dm(JH7110_SYSCLK_CPU_BUS, + starfive_clk_divider(priv->reg, + "cpu_bus", "cpu_core", + OFFSET(JH7110_SYSCLK_CPU_BUS), 2)); + clk_dm(JH7110_SYSCLK_GMACUSB_ROOT, + starfive_clk_fix_factor(priv->reg, + "gmacusb_root", "pll0_out", 1, 1)); + clk_dm(JH7110_SYSCLK_PERH_ROOT, + starfive_clk_composite(priv->reg, + "perh_root", + perh_root_sels, ARRAY_SIZE(perh_root_sels), + OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2)); + clk_dm(JH7110_SYSCLK_BUS_ROOT, + starfive_clk_mux(priv->reg, "bus_root", + OFFSET(JH7110_SYSCLK_BUS_ROOT), 1, + bus_root_sels, ARRAY_SIZE(bus_root_sels))); + clk_dm(JH7110_SYSCLK_AXI_CFG0, + starfive_clk_divider(priv->reg, + "axi_cfg0", "bus_root", + OFFSET(JH7110_SYSCLK_AXI_CFG0), 2)); + clk_dm(JH7110_SYSCLK_STG_AXIAHB, + starfive_clk_divider(priv->reg, + "stg_axiahb", "axi_cfg0", + OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2)); + clk_dm(JH7110_SYSCLK_AHB0, + starfive_clk_gate(priv->reg, + "ahb0", "stg_axiahb", + OFFSET(JH7110_SYSCLK_AHB0))); + clk_dm(JH7110_SYSCLK_AHB1, + starfive_clk_gate(priv->reg, + "ahb1", "stg_axiahb", + OFFSET(JH7110_SYSCLK_AHB1))); + clk_dm(JH7110_SYSCLK_APB_BUS_FUNC, + starfive_clk_divider(priv->reg, + "apb_bus_func", "stg_axiahb", + OFFSET(JH7110_SYSCLK_APB_BUS_FUNC), 4)); + clk_dm(JH7110_SYSCLK_PCLK2_MUX_FUNC, + starfive_clk_fix_factor(priv->reg, + "pclk2_mux_func", "apb_bus_func", 1, 1)); + clk_dm(JH7110_SYSCLK_PCLK2_MUX, + starfive_clk_fix_factor(priv->reg, + "pclk2_mux", "pclk2_mux_func", 1, 1)); + clk_dm(JH7110_SYSCLK_APB_BUS, + starfive_clk_fix_factor(priv->reg, + "apb_bus", "pclk2_mux", 1, 1)); + clk_dm(JH7110_SYSCLK_APB0, + starfive_clk_gate(priv->reg, + "apb0", "apb_bus", + OFFSET(JH7110_SYSCLK_APB0))); + clk_dm(JH7110_SYSCLK_APB12, + starfive_clk_fix_factor(priv->reg, + "apb12", "apb_bus", 1, 1)); + clk_dm(JH7110_SYSCLK_AON_APB, + starfive_clk_fix_factor(priv->reg, + "aon_apb", "apb_bus_func", 1, 1)); + clk_dm(JH7110_SYSCLK_QSPI_AHB, + starfive_clk_gate(priv->reg, + "qspi_ahb", "ahb1", + OFFSET(JH7110_SYSCLK_QSPI_AHB))); + clk_dm(JH7110_SYSCLK_QSPI_APB, + starfive_clk_gate(priv->reg, + "qspi_apb", "apb12", + OFFSET(JH7110_SYSCLK_QSPI_APB))); + clk_dm(JH7110_SYSCLK_QSPI_REF_SRC, + starfive_clk_divider(priv->reg, + "qspi_ref_src", "gmacusb_root", + OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5)); + clk_dm(JH7110_SYSCLK_QSPI_REF, + starfive_clk_composite(priv->reg, + "qspi_ref", + qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels), + OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0)); + clk_dm(JH7110_SYSCLK_SDIO0_AHB, + starfive_clk_gate(priv->reg, + "sdio0_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_SDIO0_AHB))); + clk_dm(JH7110_SYSCLK_SDIO1_AHB, + starfive_clk_gate(priv->reg, + "sdio1_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_SDIO1_AHB))); + clk_dm(JH7110_SYSCLK_SDIO0_SDCARD, + starfive_clk_fix_parent_composite(priv->reg, + "sdio0_sdcard", "axi_cfg0", + OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4)); + clk_dm(JH7110_SYSCLK_SDIO1_SDCARD, + starfive_clk_fix_parent_composite(priv->reg, + "sdio1_sdcard", "axi_cfg0", + OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4)); + clk_dm(JH7110_SYSCLK_USB_125M, + starfive_clk_divider(priv->reg, + "usb_125m", "gmacusb_root", + OFFSET(JH7110_SYSCLK_USB_125M), 4)); + clk_dm(JH7110_SYSCLK_GMAC1_AHB, + starfive_clk_gate(priv->reg, + "gmac1_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_GMAC1_AHB))); + clk_dm(JH7110_SYSCLK_GMAC1_AXI, + starfive_clk_gate(priv->reg, + "gmac1_axi", "stg_axiahb", + OFFSET(JH7110_SYSCLK_GMAC1_AXI))); + clk_dm(JH7110_SYSCLK_GMAC_SRC, + starfive_clk_divider(priv->reg, + "gmac_src", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC_SRC), 3)); + clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK, + starfive_clk_divider(priv->reg, + "gmac1_gtxclk", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4)); + clk_dm(JH7110_SYSCLK_GMAC1_GTXC, + starfive_clk_gate(priv->reg, + "gmac1_gtxc", "gmac1_gtxclk", + OFFSET(JH7110_SYSCLK_GMAC1_GTXC))); + clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX, + starfive_clk_divider(priv->reg, + "gmac1_rmii_rtx", "gmac1_rmii_refin", + OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5)); + clk_dm(JH7110_SYSCLK_GMAC1_PTP, + starfive_clk_gate_divider(priv->reg, + "gmac1_ptp", "gmac_src", + OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5)); + clk_dm(JH7110_SYSCLK_GMAC1_TX, + starfive_clk_composite(priv->reg, + "gmac1_tx", + gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels), + OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0)); + clk_dm(JH7110_SYSCLK_AON_AHB, + starfive_clk_fix_factor(priv->reg, "aon_ahb", + "stg_axiahb", 1, 1)); + clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK, + starfive_clk_gate_divider(priv->reg, + "gmac0_gtxclk", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4)); + clk_dm(JH7110_SYSCLK_GMAC0_PTP, + starfive_clk_gate_divider(priv->reg, + "gmac0_ptp", "gmac_src", + OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5)); + clk_dm(JH7110_SYSCLK_GMAC0_GTXC, + starfive_clk_gate(priv->reg, + "gmac0_gtxc", "gmac0_gtxclk", + OFFSET(JH7110_SYSCLK_GMAC0_GTXC))); + clk_dm(JH7110_SYSCLK_UART0_APB, + starfive_clk_gate(priv->reg, + "uart0_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART0_APB))); + clk_dm(JH7110_SYSCLK_UART0_CORE, + starfive_clk_gate(priv->reg, + "uart0_core", "osc", + OFFSET(JH7110_SYSCLK_UART0_CORE))); + clk_dm(JH7110_SYSCLK_UART1_APB, + starfive_clk_gate(priv->reg, + "uart1_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART1_APB))); + clk_dm(JH7110_SYSCLK_UART1_CORE, + starfive_clk_gate(priv->reg, + "uart1_core", "osc", + OFFSET(JH7110_SYSCLK_UART1_CORE))); + clk_dm(JH7110_SYSCLK_UART2_APB, + starfive_clk_gate(priv->reg, + "uart2_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART2_APB))); + clk_dm(JH7110_SYSCLK_UART2_CORE, + starfive_clk_gate(priv->reg, + "uart2_core", "osc", + OFFSET(JH7110_SYSCLK_UART2_CORE))); + clk_dm(JH7110_SYSCLK_UART3_APB, + starfive_clk_gate(priv->reg, + "uart3_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART3_APB))); + clk_dm(JH7110_SYSCLK_UART3_CORE, + starfive_clk_gate_divider(priv->reg, + "uart3_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART3_CORE), 8)); + clk_dm(JH7110_SYSCLK_UART4_APB, + starfive_clk_gate(priv->reg, + "uart4_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART4_APB))); + clk_dm(JH7110_SYSCLK_UART4_CORE, + starfive_clk_gate_divider(priv->reg, + "uart4_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART4_CORE), 8)); + clk_dm(JH7110_SYSCLK_UART5_APB, + starfive_clk_gate(priv->reg, + "uart5_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART5_APB))); + clk_dm(JH7110_SYSCLK_UART5_CORE, + starfive_clk_gate_divider(priv->reg, + "uart5_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART5_CORE), 8)); + clk_dm(JH7110_SYSCLK_I2C5_APB, + starfive_clk_gate(priv->reg, + "i2c5_apb", "apb12", + OFFSET(JH7110_SYSCLK_I2C5_APB))); + clk_dm(JH7110_SYSCLK_I2C5_CORE, + starfive_clk_fix_factor(priv->reg, + "i2c5_core", "i2c5_apb", 1, 1)); + + return 0; +} + +static int jh7110_aoncrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_AONCLK_GMAC0_AHB, + starfive_clk_gate(priv->reg, + "gmac0_ahb", "aon_ahb", + AONOFFSET(JH7110_AONCLK_GMAC0_AHB))); + clk_dm(JH7110_AONCLK_GMAC0_AXI, + starfive_clk_gate(priv->reg, + "gmac0_axi", "aon_ahb", + AONOFFSET(JH7110_AONCLK_GMAC0_AXI))); + clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX, + starfive_clk_divider(priv->reg, + "gmac0_rmii_rtx", "gmac0_rmii_refin", + AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5)); + clk_dm(JH7110_AONCLK_GMAC0_TX, + starfive_clk_composite(priv->reg, + "gmac0_tx", gmac0_tx_sels, + ARRAY_SIZE(gmac0_tx_sels), + AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0)); + clk_dm(JH7110_AONCLK_OTPC_APB, + starfive_clk_gate(priv->reg, + "otpc_apb", "aon_apb", + AONOFFSET(JH7110_AONCLK_OTPC_APB))); + + return 0; +} + +static int jh7110_stgcrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_STGCLK_STG_APB, + starfive_clk_fix_factor(priv->reg, + "stg_apb", "apb_bus", 1, 1)); + clk_dm(JH7110_STGCLK_USB_APB, + starfive_clk_gate(priv->reg, + "usb_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_USB_APB))); + clk_dm(JH7110_STGCLK_USB_UTMI_APB, + starfive_clk_gate(priv->reg, + "usb_utmi_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_USB_UTMI_APB))); + clk_dm(JH7110_STGCLK_USB_AXI, + starfive_clk_gate(priv->reg, + "usb_axi", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_USB_AXI))); + clk_dm(JH7110_STGCLK_USB_LPM, + starfive_clk_gate_divider(priv->reg, + "usb_lpm", "osc", + STGOFFSET(JH7110_STGCLK_USB_LPM), 2)); + clk_dm(JH7110_STGCLK_USB_STB, + starfive_clk_gate_divider(priv->reg, + "usb_stb", "osc", + STGOFFSET(JH7110_STGCLK_USB_STB), 3)); + clk_dm(JH7110_STGCLK_USB_APP_125, + starfive_clk_gate(priv->reg, + "usb_app_125", "usb_125m", + STGOFFSET(JH7110_STGCLK_USB_APP_125))); + clk_dm(JH7110_STGCLK_USB_REFCLK, + starfive_clk_divider(priv->reg, "usb_refclk", "osc", + STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2)); + return 0; +} + +static int jh7110_clk_probe(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + priv->init = (jh1710_init_fn)dev_get_driver_data(dev); + priv->reg = (void __iomem *)dev_read_addr_ptr(dev); + + if (priv->init) + return priv->init(dev); + + return 0; +} + +static int jh7110_clk_bind(struct udevice *dev) +{ + /* The reset driver does not have a device node, so bind it here */ + return device_bind_driver_to_node(dev, "jh7110_reset", dev->name, + dev_ofnode(dev), NULL); +} + +static const struct udevice_id jh7110_clk_of_match[] = { + { .compatible = "starfive,jh7110-syscrg", + .data = (ulong)&jh7110_syscrg_init + }, + { .compatible = "starfive,jh7110-stgcrg", + .data = (ulong)&jh7110_stgcrg_init + }, + { .compatible = "starfive,jh7110-aoncrg", + .data = (ulong)&jh7110_aoncrg_init + }, + { } +}; + +U_BOOT_DRIVER(jh7110_clk) = { + .name = "jh7110_clk", + .id = UCLASS_CLK, + .of_match = jh7110_clk_of_match, + .probe = jh7110_clk_probe, + .ops = &ccf_clk_ops, + .priv_auto = sizeof(struct jh7110_clk_priv), + .bind = jh7110_clk_bind, +}; diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h new file mode 100644 index 0000000000..eb158e6517 --- /dev/null +++ b/drivers/clk/starfive/clk.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + * + */ + +#ifndef __CLK_STARFIVE_H +#define __CLK_STARFIVE_H + +enum starfive_pll_type { + PLL0 = 0, + PLL1, + PLL2, + PLL_MAX = PLL2 +}; + +struct starfive_pllx_rate { + u64 rate; + u32 prediv; + u32 fbdiv; + u32 frac; + u32 postdiv1; + u32 dacpd; + u32 dsmpd; +}; + +struct starfive_pllx_offset { + u32 pd; + u32 prediv; + u32 fbdiv; + u32 frac; + u32 postdiv1; + u32 dacpd; + u32 dsmpd; + u32 pd_mask; + u32 prediv_mask; + u32 fbdiv_mask; + u32 frac_mask; + u32 postdiv1_mask; + u32 dacpd_mask; + u32 dsmpd_mask; +}; + +struct starfive_pllx_clk { + enum starfive_pll_type type; + const struct starfive_pllx_offset *offset; + const struct starfive_pllx_rate *rate_table; + int rate_count; + int flags; +}; + +extern struct starfive_pllx_clk starfive_jh7110_pll0; +extern struct starfive_pllx_clk starfive_jh7110_pll1; +extern struct starfive_pllx_clk starfive_jh7110_pll2; + +struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, + void __iomem *base, void __iomem *sysreg, + const struct starfive_pllx_clk *pll_clk); +#endif

From: Kuan Lim Lee kuanlim.lee@linux.starfivetech.com

Add pinctrl driver for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee kuanlim.lee@linux.starfivetech.com Signed-off-by: Emil Renner Berthing kernel@esmil.dk Signed-off-by: Jianlong Huang jianlong.huang@starfivetech.com Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/starfive/Kconfig | 16 + drivers/pinctrl/starfive/Makefile | 6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 +++++ drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++++++++++++++++ drivers/pinctrl/starfive/pinctrl-starfive.c | 428 ++++++++++++++++++ drivers/pinctrl/starfive/pinctrl-starfive.h | 55 +++ 8 files changed, 1019 insertions(+) create mode 100644 drivers/pinctrl/starfive/Kconfig create mode 100644 drivers/pinctrl/starfive/Makefile create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b6ef2acced..75b3ff47a2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -359,5 +359,6 @@ source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" +source "drivers/pinctrl/starfive/Kconfig"

endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 3b167d099f..852adee4b4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig new file mode 100644 index 0000000000..ece05b25d3 --- /dev/null +++ b/drivers/pinctrl/starfive/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_STARFIVE + bool "Pinctrl driver for StarFive SoC" + depends on PINCTRL_FULL + help + Say yes here to support pin control on the StarFive RISC-V SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + +config PINCTRL_STARFIVE_JH7110 + bool "Pinctrl and GPIO driver for StarFive JH7110 SoC" + depends on PINCTRL_STARFIVE + help + This selects the pinctrl driver for JH7110 starfive. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile new file mode 100644 index 0000000000..e4caa4cbb7 --- /dev/null +++ b/drivers/pinctrl/starfive/Makefile @@ -0,0 +1,6 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o +# SoC Drivers +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c new file mode 100644 index 0000000000..2d739906e2 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim kuanlim.lee@starfivetech.com + * Author: Jianlong Huang jianlong.huang@starfivetech.com + */ + +#include <dm/read.h> +#include <dm/device_compat.h> +#include <linux/io.h> + +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> +#include "pinctrl-starfive.h" + +#define JH7110_AON_NGPIO 4 +#define JH7110_AON_GC_BASE 64 + +/* registers */ +#define JH7110_AON_DOEN 0x0 +#define JH7110_AON_DOUT 0x4 +#define JH7110_AON_GPI 0x8 +#define JH7110_AON_GPIOIN 0x2c + +#define JH7110_AON_GPIOEN 0xc +#define JH7110_AON_GPIOIS 0x10 +#define JH7110_AON_GPIOIC 0x14 +#define JH7110_AON_GPIOIBE 0x18 +#define JH7110_AON_GPIOIEV 0x1c +#define JH7110_AON_GPIOIE 0x20 +#define JH7110_AON_GPIORIS 0x28 +#define JH7110_AON_GPIOMIS 0x28 + +#define AON_GPO_PDA_0_5_CFG 0x30 + +static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + + if (pin < priv->info->ngpios && func == 0) + starfive_set_gpiomux(dev, pin, din, dout, doen); + + return 0; +} + +static int jh7110_aon_get_padcfg_base(struct udevice *dev, + unsigned int pin) +{ + if (pin < PAD_GMAC0_MDC) + return AON_GPO_PDA_0_5_CFG; + + return -1; +} + +static void jh7110_aon_init_hw(struct udevice *dev) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + + /* mask all GPIO interrupts */ + writel(0, priv->base + JH7110_AON_GPIOIE); + /* clear edge interrupt flags */ + writel(0, priv->base + JH7110_AON_GPIOIC); + writel(0x0f, priv->base + JH7110_AON_GPIOIC); + /* enable GPIO interrupts */ + writel(1, priv->base + JH7110_AON_GPIOEN); +} + +const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = { + /* pin conf */ + .set_one_pinmux = jh7110_aon_set_one_pin_mux, + .get_padcfg_base = jh7110_aon_get_padcfg_base, + + /* gpio dout/doen/din/gpioinput register */ + .dout_reg_base = JH7110_AON_DOUT, + .dout_mask = GENMASK(3, 0), + .doen_reg_base = JH7110_AON_DOEN, + .doen_mask = GENMASK(2, 0), + .gpi_reg_base = JH7110_AON_GPI, + .gpi_mask = GENMASK(3, 0), + .gpioin_reg_base = JH7110_AON_GPIOIN, + + /* gpio */ + .gpio_bank_name = "RGPIO", + .ngpios = JH7110_AON_NGPIO, + .gpio_init_hw = jh7110_aon_init_hw, +}; + +static int jh7110_aon_pinctrl_probe(struct udevice *dev) +{ + struct starfive_pinctrl_soc_info *info = + (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev); + + return starfive_pinctrl_probe(dev, info); +} + +static const struct udevice_id jh7110_aon_pinctrl_ids[] = { + /* JH7110 aon pinctrl */ + { .compatible = "starfive,jh7110-aon-pinctrl", + .data = (ulong)&jh7110_aon_pinctrl_info, }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(jh7110_aon_pinctrl) = { + .name = "jh7110-aon-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = jh7110_aon_pinctrl_ids, + .priv_auto = sizeof(struct starfive_pinctrl_priv), + .ops = &starfive_pinctrl_ops, + .probe = jh7110_aon_pinctrl_probe, +}; diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c new file mode 100644 index 0000000000..dafba65eae --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim kuanlim.lee@starfivetech.com + * Author: Jianlong Huang jianlong.huang@starfivetech.com + */ + +#include <dm/read.h> +#include <dm/device_compat.h> +#include <linux/io.h> + +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> +#include "pinctrl-starfive.h" + +#define JH7110_SYS_NGPIO 64 +#define JH7110_SYS_GC_BASE 0 + +/* registers */ +#define JH7110_SYS_DOEN 0x000 +#define JH7110_SYS_DOUT 0x040 +#define JH7110_SYS_GPI 0x080 +#define JH7110_SYS_GPIOIN 0x118 + +#define JH7110_SYS_GPIOEN 0x0dc +#define JH7110_SYS_GPIOIS0 0x0e0 +#define JH7110_SYS_GPIOIS1 0x0e4 +#define JH7110_SYS_GPIOIC0 0x0e8 +#define JH7110_SYS_GPIOIC1 0x0ec +#define JH7110_SYS_GPIOIBE0 0x0f0 +#define JH7110_SYS_GPIOIBE1 0x0f4 +#define JH7110_SYS_GPIOIEV0 0x0f8 +#define JH7110_SYS_GPIOIEV1 0x0fc +#define JH7110_SYS_GPIOIE0 0x100 +#define JH7110_SYS_GPIOIE1 0x104 +#define JH7110_SYS_GPIORIS0 0x108 +#define JH7110_SYS_GPIORIS1 0x10c +#define JH7110_SYS_GPIOMIS0 0x110 +#define JH7110_SYS_GPIOMIS1 0x114 + +#define SYS_GPO_PDA_0_74_CFG 0x120 +#define SYS_GPO_PDA_89_94_CFG 0x284 + +static const struct starfive_pinctrl_pin jh7110_sys_pins[] = { + STARFIVE_PINCTRL(PAD_GPIO0, "GPIO0"), + STARFIVE_PINCTRL(PAD_GPIO1, "GPIO1"), + STARFIVE_PINCTRL(PAD_GPIO2, "GPIO2"), + STARFIVE_PINCTRL(PAD_GPIO3, "GPIO3"), + STARFIVE_PINCTRL(PAD_GPIO4, "GPIO4"), + STARFIVE_PINCTRL(PAD_GPIO5, "GPIO5"), + STARFIVE_PINCTRL(PAD_GPIO6, "GPIO6"), + STARFIVE_PINCTRL(PAD_GPIO7, "GPIO7"), + STARFIVE_PINCTRL(PAD_GPIO8, "GPIO8"), + STARFIVE_PINCTRL(PAD_GPIO9, "GPIO9"), + STARFIVE_PINCTRL(PAD_GPIO10, "GPIO10"), + STARFIVE_PINCTRL(PAD_GPIO11, "GPIO11"), + STARFIVE_PINCTRL(PAD_GPIO12, "GPIO12"), + STARFIVE_PINCTRL(PAD_GPIO13, "GPIO13"), + STARFIVE_PINCTRL(PAD_GPIO14, "GPIO14"), + STARFIVE_PINCTRL(PAD_GPIO15, "GPIO15"), + STARFIVE_PINCTRL(PAD_GPIO16, "GPIO16"), + STARFIVE_PINCTRL(PAD_GPIO17, "GPIO17"), + STARFIVE_PINCTRL(PAD_GPIO18, "GPIO18"), + STARFIVE_PINCTRL(PAD_GPIO19, "GPIO19"), + STARFIVE_PINCTRL(PAD_GPIO20, "GPIO20"), + STARFIVE_PINCTRL(PAD_GPIO21, "GPIO21"), + STARFIVE_PINCTRL(PAD_GPIO22, "GPIO22"), + STARFIVE_PINCTRL(PAD_GPIO23, "GPIO23"), + STARFIVE_PINCTRL(PAD_GPIO24, "GPIO24"), + STARFIVE_PINCTRL(PAD_GPIO25, "GPIO25"), + STARFIVE_PINCTRL(PAD_GPIO26, "GPIO26"), + STARFIVE_PINCTRL(PAD_GPIO27, "GPIO27"), + STARFIVE_PINCTRL(PAD_GPIO28, "GPIO28"), + STARFIVE_PINCTRL(PAD_GPIO29, "GPIO29"), + STARFIVE_PINCTRL(PAD_GPIO30, "GPIO30"), + STARFIVE_PINCTRL(PAD_GPIO31, "GPIO31"), + STARFIVE_PINCTRL(PAD_GPIO32, "GPIO32"), + STARFIVE_PINCTRL(PAD_GPIO33, "GPIO33"), + STARFIVE_PINCTRL(PAD_GPIO34, "GPIO34"), + STARFIVE_PINCTRL(PAD_GPIO35, "GPIO35"), + STARFIVE_PINCTRL(PAD_GPIO36, "GPIO36"), + STARFIVE_PINCTRL(PAD_GPIO37, "GPIO37"), + STARFIVE_PINCTRL(PAD_GPIO38, "GPIO38"), + STARFIVE_PINCTRL(PAD_GPIO39, "GPIO39"), + STARFIVE_PINCTRL(PAD_GPIO40, "GPIO40"), + STARFIVE_PINCTRL(PAD_GPIO41, "GPIO41"), + STARFIVE_PINCTRL(PAD_GPIO42, "GPIO42"), + STARFIVE_PINCTRL(PAD_GPIO43, "GPIO43"), + STARFIVE_PINCTRL(PAD_GPIO44, "GPIO44"), + STARFIVE_PINCTRL(PAD_GPIO45, "GPIO45"), + STARFIVE_PINCTRL(PAD_GPIO46, "GPIO46"), + STARFIVE_PINCTRL(PAD_GPIO47, "GPIO47"), + STARFIVE_PINCTRL(PAD_GPIO48, "GPIO48"), + STARFIVE_PINCTRL(PAD_GPIO49, "GPIO49"), + STARFIVE_PINCTRL(PAD_GPIO50, "GPIO50"), + STARFIVE_PINCTRL(PAD_GPIO51, "GPIO51"), + STARFIVE_PINCTRL(PAD_GPIO52, "GPIO52"), + STARFIVE_PINCTRL(PAD_GPIO53, "GPIO53"), + STARFIVE_PINCTRL(PAD_GPIO54, "GPIO54"), + STARFIVE_PINCTRL(PAD_GPIO55, "GPIO55"), + STARFIVE_PINCTRL(PAD_GPIO56, "GPIO56"), + STARFIVE_PINCTRL(PAD_GPIO57, "GPIO57"), + STARFIVE_PINCTRL(PAD_GPIO58, "GPIO58"), + STARFIVE_PINCTRL(PAD_GPIO59, "GPIO59"), + STARFIVE_PINCTRL(PAD_GPIO60, "GPIO60"), + STARFIVE_PINCTRL(PAD_GPIO61, "GPIO61"), + STARFIVE_PINCTRL(PAD_GPIO62, "GPIO62"), + STARFIVE_PINCTRL(PAD_GPIO63, "GPIO63"), + STARFIVE_PINCTRL(PAD_SD0_CLK, "SD0_CLK"), + STARFIVE_PINCTRL(PAD_SD0_CMD, "SD0_CMD"), + STARFIVE_PINCTRL(PAD_SD0_DATA0, "SD0_DATA0"), + STARFIVE_PINCTRL(PAD_SD0_DATA1, "SD0_DATA1"), + STARFIVE_PINCTRL(PAD_SD0_DATA2, "SD0_DATA2"), + STARFIVE_PINCTRL(PAD_SD0_DATA3, "SD0_DATA3"), + STARFIVE_PINCTRL(PAD_SD0_DATA4, "SD0_DATA4"), + STARFIVE_PINCTRL(PAD_SD0_DATA5, "SD0_DATA5"), + STARFIVE_PINCTRL(PAD_SD0_DATA6, "SD0_DATA6"), + STARFIVE_PINCTRL(PAD_SD0_DATA7, "SD0_DATA7"), + STARFIVE_PINCTRL(PAD_SD0_STRB, "SD0_STRB"), + STARFIVE_PINCTRL(PAD_GMAC1_MDC, "GMAC1_MDC"), + STARFIVE_PINCTRL(PAD_GMAC1_MDIO, "GMAC1_MDIO"), + STARFIVE_PINCTRL(PAD_GMAC1_RXD0, "GMAC1_RXD0"), + STARFIVE_PINCTRL(PAD_GMAC1_RXD1, "GMAC1_RXD1"), + STARFIVE_PINCTRL(PAD_GMAC1_RXD2, "GMAC1_RXD2"), + STARFIVE_PINCTRL(PAD_GMAC1_RXD3, "GMAC1_RXD3"), + STARFIVE_PINCTRL(PAD_GMAC1_RXDV, "GMAC1_RXDV"), + STARFIVE_PINCTRL(PAD_GMAC1_RXC, "GMAC1_RXC"), + STARFIVE_PINCTRL(PAD_GMAC1_TXD0, "GMAC1_TXD0"), + STARFIVE_PINCTRL(PAD_GMAC1_TXD1, "GMAC1_TXD1"), + STARFIVE_PINCTRL(PAD_GMAC1_TXD2, "GMAC1_TXD2"), + STARFIVE_PINCTRL(PAD_GMAC1_TXD3, "GMAC1_TXD3"), + STARFIVE_PINCTRL(PAD_GMAC1_TXEN, "GMAC1_TXEN"), + STARFIVE_PINCTRL(PAD_GMAC1_TXC, "GMAC1_TXC"), + STARFIVE_PINCTRL(PAD_QSPI_SCLK, "QSPI_SCLK"), + STARFIVE_PINCTRL(PAD_QSPI_CS0, "QSPI_CS0"), + STARFIVE_PINCTRL(PAD_QSPI_DATA0, "QSPI_DATA0"), + STARFIVE_PINCTRL(PAD_QSPI_DATA1, "QSPI_DATA1"), + STARFIVE_PINCTRL(PAD_QSPI_DATA2, "QSPI_DATA2"), + STARFIVE_PINCTRL(PAD_QSPI_DATA3, "QSPI_DATA3"), +}; + +struct jh7110_func_sel { + u16 offset; + u8 shift; + u8 max; +}; + +static const struct jh7110_func_sel + jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = { + [PAD_GMAC1_RXC] = { 0x29c, 0, 1 }, + [PAD_GPIO10] = { 0x29c, 2, 3 }, + [PAD_GPIO11] = { 0x29c, 5, 3 }, + [PAD_GPIO12] = { 0x29c, 8, 3 }, + [PAD_GPIO13] = { 0x29c, 11, 3 }, + [PAD_GPIO14] = { 0x29c, 14, 3 }, + [PAD_GPIO15] = { 0x29c, 17, 3 }, + [PAD_GPIO16] = { 0x29c, 20, 3 }, + [PAD_GPIO17] = { 0x29c, 23, 3 }, + [PAD_GPIO18] = { 0x29c, 26, 3 }, + [PAD_GPIO19] = { 0x29c, 29, 3 }, + + [PAD_GPIO20] = { 0x2a0, 0, 3 }, + [PAD_GPIO21] = { 0x2a0, 3, 3 }, + [PAD_GPIO22] = { 0x2a0, 6, 3 }, + [PAD_GPIO23] = { 0x2a0, 9, 3 }, + [PAD_GPIO24] = { 0x2a0, 12, 3 }, + [PAD_GPIO25] = { 0x2a0, 15, 3 }, + [PAD_GPIO26] = { 0x2a0, 18, 3 }, + [PAD_GPIO27] = { 0x2a0, 21, 3 }, + [PAD_GPIO28] = { 0x2a0, 24, 3 }, + [PAD_GPIO29] = { 0x2a0, 27, 3 }, + + [PAD_GPIO30] = { 0x2a4, 0, 3 }, + [PAD_GPIO31] = { 0x2a4, 3, 3 }, + [PAD_GPIO32] = { 0x2a4, 6, 3 }, + [PAD_GPIO33] = { 0x2a4, 9, 3 }, + [PAD_GPIO34] = { 0x2a4, 12, 3 }, + [PAD_GPIO35] = { 0x2a4, 15, 3 }, + [PAD_GPIO36] = { 0x2a4, 17, 3 }, + [PAD_GPIO37] = { 0x2a4, 20, 3 }, + [PAD_GPIO38] = { 0x2a4, 23, 3 }, + [PAD_GPIO39] = { 0x2a4, 26, 3 }, + [PAD_GPIO40] = { 0x2a4, 29, 3 }, + + [PAD_GPIO41] = { 0x2a8, 0, 3 }, + [PAD_GPIO42] = { 0x2a8, 3, 3 }, + [PAD_GPIO43] = { 0x2a8, 6, 3 }, + [PAD_GPIO44] = { 0x2a8, 9, 3 }, + [PAD_GPIO45] = { 0x2a8, 12, 3 }, + [PAD_GPIO46] = { 0x2a8, 15, 3 }, + [PAD_GPIO47] = { 0x2a8, 18, 3 }, + [PAD_GPIO48] = { 0x2a8, 21, 3 }, + [PAD_GPIO49] = { 0x2a8, 24, 3 }, + [PAD_GPIO50] = { 0x2a8, 27, 3 }, + [PAD_GPIO51] = { 0x2a8, 30, 3 }, + + [PAD_GPIO52] = { 0x2ac, 0, 3 }, + [PAD_GPIO53] = { 0x2ac, 2, 3 }, + [PAD_GPIO54] = { 0x2ac, 4, 3 }, + [PAD_GPIO55] = { 0x2ac, 6, 3 }, + [PAD_GPIO56] = { 0x2ac, 9, 3 }, + [PAD_GPIO57] = { 0x2ac, 12, 3 }, + [PAD_GPIO58] = { 0x2ac, 15, 3 }, + [PAD_GPIO59] = { 0x2ac, 18, 3 }, + [PAD_GPIO60] = { 0x2ac, 21, 3 }, + [PAD_GPIO61] = { 0x2ac, 24, 3 }, + [PAD_GPIO62] = { 0x2ac, 27, 3 }, + [PAD_GPIO63] = { 0x2ac, 30, 3 }, + + [PAD_GPIO6] = { 0x2b0, 0, 3 }, + [PAD_GPIO7] = { 0x2b0, 2, 3 }, + [PAD_GPIO8] = { 0x2b0, 5, 3 }, + [PAD_GPIO9] = { 0x2b0, 8, 3 }, +}; + +struct jh7110_vin_group_sel { + u16 offset; + u8 shift; + u8 group; +}; + +static const struct jh7110_vin_group_sel + jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = { + [PAD_GPIO6] = { 0x2b4, 21, 0 }, + [PAD_GPIO7] = { 0x2b4, 18, 0 }, + [PAD_GPIO8] = { 0x2b4, 15, 0 }, + [PAD_GPIO9] = { 0x2b0, 11, 0 }, + [PAD_GPIO10] = { 0x2b0, 20, 0 }, + [PAD_GPIO11] = { 0x2b0, 23, 0 }, + [PAD_GPIO12] = { 0x2b0, 26, 0 }, + [PAD_GPIO13] = { 0x2b0, 29, 0 }, + [PAD_GPIO14] = { 0x2b4, 0, 0 }, + [PAD_GPIO15] = { 0x2b4, 3, 0 }, + [PAD_GPIO16] = { 0x2b4, 6, 0 }, + [PAD_GPIO17] = { 0x2b4, 9, 0 }, + [PAD_GPIO18] = { 0x2b4, 12, 0 }, + [PAD_GPIO19] = { 0x2b0, 14, 0 }, + [PAD_GPIO20] = { 0x2b0, 17, 0 }, + + [PAD_GPIO21] = { 0x2b4, 21, 1 }, + [PAD_GPIO22] = { 0x2b4, 18, 1 }, + [PAD_GPIO23] = { 0x2b4, 15, 1 }, + [PAD_GPIO24] = { 0x2b0, 11, 1 }, + [PAD_GPIO25] = { 0x2b0, 20, 1 }, + [PAD_GPIO26] = { 0x2b0, 23, 1 }, + [PAD_GPIO27] = { 0x2b0, 26, 1 }, + [PAD_GPIO28] = { 0x2b0, 29, 1 }, + [PAD_GPIO29] = { 0x2b4, 0, 1 }, + [PAD_GPIO30] = { 0x2b4, 3, 1 }, + [PAD_GPIO31] = { 0x2b4, 6, 1 }, + [PAD_GPIO32] = { 0x2b4, 9, 1 }, + [PAD_GPIO33] = { 0x2b4, 12, 1 }, + [PAD_GPIO34] = { 0x2b0, 14, 1 }, + [PAD_GPIO35] = { 0x2b0, 17, 1 }, + + [PAD_GPIO36] = { 0x2b4, 21, 2 }, + [PAD_GPIO37] = { 0x2b4, 18, 2 }, + [PAD_GPIO38] = { 0x2b4, 15, 2 }, + [PAD_GPIO39] = { 0x2b0, 11, 2 }, + [PAD_GPIO40] = { 0x2b0, 20, 2 }, + [PAD_GPIO41] = { 0x2b0, 23, 2 }, + [PAD_GPIO42] = { 0x2b0, 26, 2 }, + [PAD_GPIO43] = { 0x2b0, 29, 2 }, + [PAD_GPIO44] = { 0x2b4, 0, 2 }, + [PAD_GPIO45] = { 0x2b4, 3, 2 }, + [PAD_GPIO46] = { 0x2b4, 6, 2 }, + [PAD_GPIO47] = { 0x2b4, 9, 2 }, + [PAD_GPIO48] = { 0x2b4, 12, 2 }, + [PAD_GPIO49] = { 0x2b0, 14, 2 }, + [PAD_GPIO50] = { 0x2b0, 17, 2 }, +}; + +static void jh7110_set_function(struct udevice *dev, + unsigned int pin, u32 func) +{ + const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin]; + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + void __iomem *reg; + u32 mask; + + if (!fs->offset) + return; + + if (func > fs->max) + return; + + reg = priv->base + fs->offset; + func = func << fs->shift; + mask = 0x3U << fs->shift; + + func |= readl(reg) & ~mask; + writel(func, reg); +} + +static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin) +{ + const struct jh7110_vin_group_sel *gs = + &jh7110_sys_vin_group_sel[pin]; + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + void __iomem *reg; + u32 mask; + u32 grp; + + if (!gs->offset) + return; + + reg = priv->base + gs->offset; + grp = gs->group << gs->shift; + mask = 0x3U << gs->shift; + + grp |= readl(reg) & ~mask; + writel(grp, reg); +} + +static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin, + unsigned int din, u32 dout, u32 doen, u32 func) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + + if (pin < priv->info->ngpios && func == 0) + starfive_set_gpiomux(dev, pin, din, dout, doen); + + jh7110_set_function(dev, pin, func); + + if (pin < priv->info->ngpios && func == 2) + jh7110_set_vin_group(dev, pin); + + return 0; +} + +static int jh7110_sys_get_padcfg_base(struct udevice *dev, + unsigned int pin) +{ + if (pin < PAD_GMAC1_MDC) + return SYS_GPO_PDA_0_74_CFG; + else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3) + return SYS_GPO_PDA_89_94_CFG; + else + return -1; +} + +static void jh7110_sys_init_hw(struct udevice *dev) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + + /* mask all GPIO interrupts */ + writel(0U, priv->base + JH7110_SYS_GPIOIE0); + writel(0U, priv->base + JH7110_SYS_GPIOIE1); + /* clear edge interrupt flags */ + writel(~0U, priv->base + JH7110_SYS_GPIOIC0); + writel(~0U, priv->base + JH7110_SYS_GPIOIC1); + /* enable GPIO interrupts */ + writel(1U, priv->base + JH7110_SYS_GPIOEN); +} + +const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = { + /* pin conf */ + .set_one_pinmux = jh7110_sys_set_one_pin_mux, + .get_padcfg_base = jh7110_sys_get_padcfg_base, + + /* gpio dout/doen/din/gpioinput register */ + .dout_reg_base = JH7110_SYS_DOUT, + .dout_mask = GENMASK(6, 0), + .doen_reg_base = JH7110_SYS_DOEN, + .doen_mask = GENMASK(5, 0), + .gpi_reg_base = JH7110_SYS_GPI, + .gpi_mask = GENMASK(6, 0), + .gpioin_reg_base = JH7110_SYS_GPIOIN, + + /* gpio */ + .gpio_bank_name = "GPIO", + .ngpios = JH7110_SYS_NGPIO, + .gpio_init_hw = jh7110_sys_init_hw, +}; + +static int jh7110_sys_pinctrl_probe(struct udevice *dev) +{ + struct starfive_pinctrl_soc_info *info = + (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev); + + return starfive_pinctrl_probe(dev, info); +} + +static const struct udevice_id jh7110_sys_pinctrl_ids[] = { + /* JH7110 sys pinctrl */ + { .compatible = "starfive,jh7110-sys-pinctrl", + .data = (ulong)&jh7110_sys_pinctrl_info, }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(jh7110_sys_pinctrl) = { + .name = "jh7110-sys-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = jh7110_sys_pinctrl_ids, + .priv_auto = sizeof(struct starfive_pinctrl_priv), + .ops = &starfive_pinctrl_ops, + .probe = jh7110_sys_pinctrl_probe, +}; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c new file mode 100644 index 0000000000..d55f5d67b5 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7100 SoC + * + * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim kuanlim.lee@starfivetech.com + * Author: Jianlong Huang jianlong.huang@starfivetech.com + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <asm-generic/gpio.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <dm/device_compat.h> + +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> +#include "pinctrl-starfive.h" + +/* pad control bits */ +#define STARFIVE_PADCFG_POS BIT(7) +#define STARFIVE_PADCFG_SMT BIT(6) +#define STARFIVE_PADCFG_SLEW BIT(5) +#define STARFIVE_PADCFG_PD BIT(4) +#define STARFIVE_PADCFG_PU BIT(3) +#define STARFIVE_PADCFG_BIAS (STARFIVE_PADCFG_PD | STARFIVE_PADCFG_PU) +#define STARFIVE_PADCFG_DS_MASK GENMASK(2, 1) +#define STARFIVE_PADCFG_DS_2MA (0U << 1) +#define STARFIVE_PADCFG_DS_4MA BIT(1) +#define STARFIVE_PADCFG_DS_8MA (2U << 1) +#define STARFIVE_PADCFG_DS_12MA (3U << 1) +#define STARFIVE_PADCFG_IE BIT(0) +#define GPIO_NUM_PER_WORD 32 + +/* + * The packed pinmux values from the device tree look like this: + * + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | pin | + */ +static unsigned int starfive_pinmux_din(u32 v) +{ + return (v & GENMASK(31, 24)) >> 24; +} + +static u32 starfive_pinmux_dout(u32 v) +{ + return (v & GENMASK(23, 16)) >> 16; +} + +static u32 starfive_pinmux_doen(u32 v) +{ + return (v & GENMASK(15, 10)) >> 10; +} + +static u32 starfive_pinmux_function(u32 v) +{ + return (v & GENMASK(9, 8)) >> 8; +} + +static unsigned int starfive_pinmux_pin(u32 v) +{ + return v & GENMASK(7, 0); +} + +void starfive_set_gpiomux(struct udevice *dev, unsigned int pin, + unsigned int din, u32 dout, u32 doen) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + const struct starfive_pinctrl_soc_info *info = priv->info; + + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout_mask = info->dout_mask << shift; + u32 done_mask = info->doen_mask << shift; + u32 ival, imask; + void __iomem *reg_dout; + void __iomem *reg_doen; + void __iomem *reg_din; + + reg_dout = priv->base + info->dout_reg_base + offset; + reg_doen = priv->base + info->doen_reg_base + offset; + dout <<= shift; + doen <<= shift; + if (din != GPI_NONE) { + unsigned int ioffset = 4 * (din / 4); + unsigned int ishift = 8 * (din % 4); + + reg_din = priv->base + info->gpi_reg_base + ioffset; + ival = (pin + 2) << ishift; + imask = info->gpi_mask << ishift; + } else { + reg_din = NULL; + } + + dout |= readl(reg_dout) & ~dout_mask; + writel(dout, reg_dout); + doen |= readl(reg_doen) & ~done_mask; + writel(doen, reg_doen); + if (reg_din) { + ival |= readl(reg_din) & ~imask; + writel(ival, reg_din); + } +} + +static int starfive_pinctrl_set_state_subnode(struct udevice *dev, + ofnode node) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_soc_info *info = priv->info; + int ret, i; + int npins; + u32 *pinmux; + + npins = ofnode_read_size(node, "pinmux") / sizeof(u32); + if (npins < 1) + return -EINVAL; + + pinmux = kcalloc(npins, sizeof(*pinmux), GFP_KERNEL); + if (!pinmux) + return -ENOMEM; + + ret = ofnode_read_u32_array(node, "pinmux", pinmux, npins); + if (ret < 0) + return ret; + + for (i = 0; i < npins; i++) { + u32 v = pinmux[i]; + + if (info->set_one_pinmux) + info->set_one_pinmux(dev, + starfive_pinmux_pin(v), + starfive_pinmux_din(v), + starfive_pinmux_dout(v), + starfive_pinmux_doen(v), + starfive_pinmux_function(v)); + } + + return 0; +} + +/* + * starfive_pinctrl_set_state: configure a pin state. + * @dev: pin controller device + * @config: pseudo device pointing to config node + */ +int starfive_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + ofnode node; + int ret; + + dev_for_each_subnode(node, config) { + ret = starfive_pinctrl_set_state_subnode(dev, node); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_param starfive_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, +}; + +static const u8 starfive_drive_strength_mA[4] = { 2, 4, 8, 12 }; + +static u32 starfive_padcfg_ds_from_mA(u32 v) +{ + int i; + + for (i = 0; i < 3; i++) { + if (v <= starfive_drive_strength_mA[i]) + break; + } + return i << 1; +} + +static void starfive_padcfg_rmw(struct udevice *dev, + unsigned int pin, u32 mask, u32 value) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_soc_info *info = priv->info; + void __iomem *reg; + int padcfg_base; + + if (!info->get_padcfg_base) + return; + + padcfg_base = info->get_padcfg_base(dev, pin); + if (padcfg_base < 0) + return; + + reg = priv->base + padcfg_base + 4 * pin; + value &= mask; + + value |= readl(reg) & ~mask; + writel(value, reg); +} + +static int starfive_pinconf_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + u16 mask = 0; + u16 value = 0; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= STARFIVE_PADCFG_BIAS; + value &= ~STARFIVE_PADCFG_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -EINVAL; + mask |= STARFIVE_PADCFG_BIAS; + value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -EINVAL; + mask |= STARFIVE_PADCFG_BIAS; + value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= STARFIVE_PADCFG_DS_MASK; + value = (value & ~STARFIVE_PADCFG_DS_MASK) | + starfive_padcfg_ds_from_mA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= STARFIVE_PADCFG_IE; + if (arg) + value |= STARFIVE_PADCFG_IE; + else + value &= ~STARFIVE_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= STARFIVE_PADCFG_SMT; + if (arg) + value |= STARFIVE_PADCFG_SMT; + else + value &= ~STARFIVE_PADCFG_SMT; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= STARFIVE_PADCFG_SLEW; + if (arg) + value |= STARFIVE_PADCFG_SLEW; + else + value &= ~STARFIVE_PADCFG_SLEW; + break; + default: + return -EINVAL; + } + + starfive_padcfg_rmw(dev, pin, mask, value); + + return 0; +} + +const struct pinctrl_ops starfive_pinctrl_ops = { + .set_state = starfive_pinctrl_set_state, + .pinconf_num_params = ARRAY_SIZE(starfive_pinconf_params), + .pinconf_params = starfive_pinconf_params, + .pinconf_set = starfive_pinconf_set, +}; + +static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off) +{ + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_soc_info *info = priv->info; + + /* enable input and schmitt trigger */ + starfive_padcfg_rmw(pdev, off, + STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT, + STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT); + + if (info->set_one_pinmux) + info->set_one_pinmux(pdev, off, + GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0); + + return 0; +} + +static int starfive_gpio_direction_output(struct udevice *dev, + unsigned int off, int val) +{ + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_soc_info *info = priv->info; + + if (info->set_one_pinmux) + info->set_one_pinmux(pdev, off, + GPI_NONE, val ? GPOUT_HIGH : GPOUT_LOW, + GPOEN_ENABLE, 0); + + /* disable input, schmitt trigger and bias */ + starfive_padcfg_rmw(pdev, off, + STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT + | STARFIVE_PADCFG_BIAS, + 0); + + return 0; +} + +static int starfive_gpio_get_value(struct udevice *dev, unsigned int off) +{ + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); + struct starfive_pinctrl_soc_info *info = priv->info; + + void __iomem *reg = priv->base + info->gpioin_reg_base + + 4 * (off / GPIO_NUM_PER_WORD); + + return !!(readl(reg) & BIT(off % GPIO_NUM_PER_WORD)); +} + +static int starfive_gpio_set_value(struct udevice *dev, + unsigned int off, int val) +{ + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); + struct starfive_pinctrl_soc_info *info = priv->info; + + unsigned int offset = 4 * (off / 4); + unsigned int shift = 8 * (off % 4); + void __iomem *reg_dout = priv->base + info->dout_reg_base + offset; + u32 dout = (val ? GPOUT_HIGH : GPOUT_LOW) << shift; + u32 mask = info->dout_mask << shift; + + dout |= readl(reg_dout) & ~mask; + writel(dout, reg_dout); + + return 0; +} + +static int starfive_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv; + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); + struct starfive_pinctrl_soc_info *info = priv->info; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = info->gpio_bank_name; + uc_priv->gpio_count = info->ngpios; + + if (!info->gpio_init_hw) + return -ENXIO; + + info->gpio_init_hw(pdev); + + return 0; +} + +static const struct dm_gpio_ops starfive_gpio_ops = { + .direction_input = starfive_gpio_direction_input, + .direction_output = starfive_gpio_direction_output, + .get_value = starfive_gpio_get_value, + .set_value = starfive_gpio_set_value, +}; + +static struct driver starfive_gpio_driver = { + .name = "starfive_gpio", + .id = UCLASS_GPIO, + .probe = starfive_gpio_probe, + .ops = &starfive_gpio_ops, +}; + +static int starfive_gpiochip_register(struct udevice *parent) +{ + struct uclass_driver *drv; + struct udevice *dev; + int ret; + ofnode node; + + drv = lists_uclass_lookup(UCLASS_GPIO); + if (!drv) + return -ENOENT; + + node = dev_ofnode(parent); + ret = device_bind_with_driver_data(parent, &starfive_gpio_driver, + "starfive_gpio", 0, node, &dev); + + if (ret) + return ret; + + return 0; +} + +int starfive_pinctrl_probe(struct udevice *dev, + const struct starfive_pinctrl_soc_info *info) +{ + struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + int ret; + + /* Bind pinctrl_info from .data to priv */ + priv->info = + (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev); + + if (!priv->info) + return -EINVAL; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* gpiochip register */ + ret = starfive_gpiochip_register(dev); + if (ret) + return ret; + + dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", + priv->info->ngpios); + + return 0; +} diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h new file mode 100644 index 0000000000..5721c3c36e --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pinctrl / GPIO driver for StarFive SoC + * + * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim kuanlim.lee@starfivetech.com + * Author: Jianlong Huang jianlong.huang@starfivetech.com + */ + +#define STARFIVE_PINCTRL(a, b) { .number = a, .name = b } + +extern const struct pinctrl_ops starfive_pinctrl_ops; + +struct starfive_pinctrl_pin { + unsigned int number; + const char *name; +}; + +struct starfive_pinctrl_soc_info { + /* pinctrl */ + int (*set_one_pinmux)(struct udevice *dev, unsigned int pin, + unsigned int din, u32 dout, u32 doen, u32 func); + int (*get_padcfg_base)(struct udevice *dev, + unsigned int pin); + + /* gpio dout/doen/din/gpioinput register */ + unsigned int dout_reg_base; + unsigned int dout_mask; + unsigned int doen_reg_base; + unsigned int doen_mask; + unsigned int gpi_reg_base; + unsigned int gpi_mask; + unsigned int gpioin_reg_base; + + /* gpio */ + const char *gpio_bank_name; + int ngpios; + void (*gpio_init_hw)(struct udevice *dev); +}; + +/* + * struct starfive_pinctrl_priv - private data for Starfive pinctrl driver + * + * @padctl_base: base address of the pinctrl device + * @info: SoC specific data & function + */ +struct starfive_pinctrl_priv { + void __iomem *base; + struct starfive_pinctrl_soc_info *info; +}; + +void starfive_set_gpiomux(struct udevice *dev, unsigned int pin, + unsigned int din, u32 dout, u32 doen); +int starfive_pinctrl_probe(struct udevice *dev, + const struct starfive_pinctrl_soc_info *info);

Add board support for StarFive VisionFive v2.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- board/starfive/visionfive2/MAINTAINERS | 7 ++ board/starfive/visionfive2/Makefile | 7 ++ board/starfive/visionfive2/spl.c | 118 ++++++++++++++++++ .../visionfive2/starfive_visionfive2.c | 38 ++++++ include/configs/starfive-visionfive2.h | 18 +++ 5 files changed, 188 insertions(+) create mode 100644 board/starfive/visionfive2/MAINTAINERS create mode 100644 board/starfive/visionfive2/Makefile create mode 100644 board/starfive/visionfive2/spl.c create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c create mode 100644 include/configs/starfive-visionfive2.h

diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS new file mode 100644 index 0000000000..c5369086d8 --- /dev/null +++ b/board/starfive/visionfive2/MAINTAINERS @@ -0,0 +1,7 @@ +STARFIVE JH7110 VISIONFIVE2 BOARD +M: startfive +S: Maintained +F: arch/riscv/include/asm/arch-jh7110/ +F: board/starfive/visionfive2/ +F: include/configs/starfive-visionfive2.h +F: configs/starfive_visionfive2_defconfig diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile new file mode 100644 index 0000000000..66c854df39 --- /dev/null +++ b/board/starfive/visionfive2/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. +# + +obj-y := starfive_visionfive2.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c new file mode 100644 index 0000000000..9e14cd56af --- /dev/null +++ b/board/starfive/visionfive2/spl.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <asm/arch/regs.h> +#include <asm/arch/spl.h> +#include <asm/io.h> +#include <log.h> +#include <spl.h> + +#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U +#define JH7110_CLK_CPU_ROOT_SHIFT 24 +#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_BUS_ROOT_OFFSET 0x14U +#define JH7110_CLK_BUS_ROOT_SHIFT 24 +#define JH7110_CLK_BUS_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_PERH_ROOT_OFFSET 0x10U +#define JH7110_CLK_PERH_ROOT_SHIFT 24 +#define JH7110_CLK_PERH_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_NOC_BUS_STG_AXI_OFFSET 0x180U +#define JH7110_CLK_NOC_BUS_STG_AXI_SHIFT 31 +#define JH7110_CLK_NOC_BUS_STG_AXI_MASK BIT(31) +#define JH7110_CLK_AON_APB_FUNC_OFFSET 0x4U +#define JH7110_CLK_AON_APB_FUNC_SHIFT 24 +#define JH7110_CLK_AON_APB_FUNC_MASK GENMASK(29, 24) +#define JH7110_CLK_QSPI_REF_OFFSET 0x168U +#define JH7110_CLK_QSPI_REF_SHIFT 24 +#define JH7110_CLK_QSPI_REF_MASK GENMASK(29, 24) + +#define ASSIGNED_CLOCK_PARENTS(type, val) \ + clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_##type##_OFFSET, \ + JH7110_CLK_##type##_MASK, \ + ((val) << JH7110_CLK_##type##_SHIFT) & JH7110_CLK_##type##_MASK) + +int spl_board_init_f(void) +{ + int ret; + + ret = spl_soc_init(); + if (ret) { + debug("JH7110 SPL init failed: %d\n", ret); + return ret; + } + + return 0; +} + +u32 spl_boot_device(void) +{ + u32 mode; + + mode = in_le32(JH7110_BOOT_MODE_SELECT_REG) + & JH7110_BOOT_MODE_SELECT_MASK; + switch (mode) { + case 0: + return BOOT_DEVICE_SPI; + + case 1: + return BOOT_DEVICE_MMC2; + + case 2: + return BOOT_DEVICE_MMC1; + + case 3: + return BOOT_DEVICE_UART; + + default: + debug("Unsupported boot device 0x%x.\n", mode); + return BOOT_DEVICE_NONE; + } +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + riscv_cpu_setup(NULL, NULL); + preloader_console_init(); + + /* select clk_pll0 by default */ + ASSIGNED_CLOCK_PARENTS(CPU_ROOT, 1); + + /* select clk_pll2 by default */ + ASSIGNED_CLOCK_PARENTS(BUS_ROOT, 1); + + /* select clk_pll2 by default */ + ASSIGNED_CLOCK_PARENTS(PERH_ROOT, 1); + + ASSIGNED_CLOCK_PARENTS(NOC_BUS_STG_AXI, 1); + + clrsetbits_le32(JH7110_AON_CRG + JH7110_CLK_AON_APB_FUNC_OFFSET, + JH7110_CLK_AON_APB_FUNC_MASK, + BIT(JH7110_CLK_AON_APB_FUNC_SHIFT)); + + /* select clk_pll0 by default */ + ASSIGNED_CLOCK_PARENTS(QSPI_REF, 1); + + ret = spl_board_init_f(); + if (ret) { + debug("spl_board_init_f init failed: %d\n", ret); + return; + } +} + +#if CONFIG_IS_ENABLED(SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c new file mode 100644 index 0000000000..57f1b6ea5d --- /dev/null +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/bitops.h> + +#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000 +#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 + +/* enable U74-mc hart1~hart4 prefetcher */ +static void enable_prefetcher(void) +{ + u8 hart; + u32 *reg; + + /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7), + * but only U7 cores support prefetcher configuration + */ + for (hart = 1; hart < 5; hart++) { + reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR + + hart * JH7110_L2_PREFETCHER_HART_OFFSET); + + mb(); /* memory barrier */ + setbits_le32(reg, 0x1); + mb(); /* memory barrier */ + } +} + +int board_init(void) +{ + enable_prefetcher(); + + return 0; +} diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h new file mode 100644 index 0000000000..a5fba1869b --- /dev/null +++ b/include/configs/starfive-visionfive2.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#ifndef _STARFIVE_VISIONFIVE2_H +#define _STARFIVE_VISIONFIVE2_H + +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 4000000 + +#define RISCV_SMODE_TIMER_FREQ 4000000 + +#define __io + +#endif /* _STARFIVE_VISIONFIVE2_H */

Add Kconfig to select the basic functions for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/cpu/jh7110/Kconfig | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 0000000000..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT

Add initial device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/dts/jh7110.dtsi | 497 +++++++++++++++++++++++++++++++++++++ 1 file changed, 497 insertions(+) create mode 100644 arch/riscv/dts/jh7110.dtsi

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi new file mode 100644 index 0000000000..49d34b85af --- /dev/null +++ b/arch/riscv/dts/jh7110.dtsi @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; + +#include <dt-bindings/clock/starfive-jh7110.h> +#include <dt-bindings/reset/starfive-jh7110.h> + +/ { + compatible = "starfive,jh7110"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + S76_0: cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imacu"; + tlb-split; + status = "disabled"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_1: cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdcbsu"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_2: cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <2>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdcbsu"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_3: cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <3>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdcbsu"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_4: cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <4>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdcbsu"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&S76_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + + core2 { + cpu = <&U74_2>; + }; + + core3 { + cpu = <&U74_3>; + }; + + core4 { + cpu = <&U74_4>; + }; + }; + }; + }; + + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + clk_rtc: clk_rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac0_rmii_refin: gmac0_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac0_rgmii_rxin: gmac0_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac1_rmii_refin: gmac1_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + gmac1_rgmii_rxin: gmac1_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + i2stx_bclk_ext: i2stx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + i2stx_lrck_ext: i2stx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + i2srx_bclk_ext: i2srx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + i2srx_lrck_ext: i2srx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + tdm_ext: tdm_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + mclk_ext: mclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + plic: plic@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <136>; + }; + + ccache: cache-controller@2010000 { + compatible = "starfive,jh7110-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + + syscrg: clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x0 0x13020000 0x0 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; + clocks = <&osc>, <&clk_rtc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names = "osc", "clk_rtc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus_func", "gmac0_gtxclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpio: gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + reg-names = "control"; + clocks = <&syscrg JH7110_SYSCLK_IOMUX>; + resets = <&syscrg JH7110_SYSRST_IOMUX>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioa: gpio@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; + reg-names = "control"; + resets = <&aoncrg JH7110_AONRST_AON_IOMUX>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + uart0: serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, + <&syscrg JH7110_SYSCLK_UART0_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART0_APB>, + <&syscrg JH7110_SYSRST_UART0_CORE>; + interrupts = <32>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, + <&syscrg JH7110_SYSCLK_UART1_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART1_APB>, + <&syscrg JH7110_SYSRST_UART1_CORE>; + interrupts = <33>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, + <&syscrg JH7110_SYSCLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART2_APB>, + <&syscrg JH7110_SYSRST_UART2_CORE>; + interrupts = <34>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, + <&syscrg JH7110_SYSCLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART3_APB>, + <&syscrg JH7110_SYSRST_UART3_CORE>; + interrupts = <45>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, + <&syscrg JH7110_SYSCLK_UART4_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART4_APB>, + <&syscrg JH7110_SYSRST_UART4_CORE>; + interrupts = <46>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, + <&syscrg JH7110_SYSCLK_UART5_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART5_APB>, + <&syscrg JH7110_SYSRST_UART5_CORE>; + interrupts = <47>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + sdio0: mmc@16010000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu", "ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + sdio1: mmc@16020000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu", "ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + qspi: spi@13010000 { + compatible = "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; + clock-names = "clk_ref"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + resets-names = "rst_apb", "rst_ahb", "rst_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +};

Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/dts/jh7110-u-boot.dtsi | 72 +++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi new file mode 100644 index 0000000000..a15e1c6a45 --- /dev/null +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <dt-bindings/reset/starfive-jh7110.h> + +/ { + cpus: cpus { + u-boot,dm-spl; + + S76_0: cpu@0 { + u-boot,dm-spl; + status = "okay"; + cpu0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + U74_1: cpu@1 { + u-boot,dm-spl; + cpu1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + U74_2: cpu@2 { + u-boot,dm-spl; + cpu2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + U74_3: cpu@3 { + u-boot,dm-spl; + cpu3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + U74_4: cpu@4 { + u-boot,dm-spl; + cpu4_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + soc { + u-boot,dm-spl; + + clint: clint@2000000 { + u-boot,dm-spl; + }; + }; +}; + +&gmac0_rmii_refin { + u-boot,dm-spl; +}; + +&aoncrg { + u-boot,dm-spl; +}; + +&syscrg { + u-boot,dm-spl; +}; + +&stgcrg { + u-boot,dm-spl; +};

This is the initial basic config for StarFive VisionFive v2 board. It includes consol, Norflash, sdio, ddr etc.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- configs/starfive_visionfive2_defconfig | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 configs/starfive_visionfive2_defconfig

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig new file mode 100644 index 0000000000..54ae6b2a43 --- /dev/null +++ b/configs/starfive_visionfive2_defconfig @@ -0,0 +1,72 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2" +CONFIG_SPL_TEXT_BASE=0x8000000 +CONFIG_SYS_PROMPT="StarFive #" +CONFIG_SPL_MMC=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TARGET_STARFIVE_VISIONFIVE2=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000 +CONFIG_FIT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" +CONFIG_DEFAULT_FDT_FILE="starfive/starfive_visionfive2.dtb" +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_BSS_START_ADDR=0x8040000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x8180000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_JH7110=y +# CONFIG_I2C is not set +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_STARFIVE=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RESET=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_TIMER_EARLY=y +CONFIG_OF_LIBFDT_OVERLAY=y