The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM A1 in the memory map.

Signed-off-by: Icenowy Zheng icenowy@aosc.io Reviewed-by: Andre Przywara andre.przywara@arm.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com --- Changes in v2: - Added Maxime's Acked-by and Andre's Reviewed-by tags.

arch/arm/include/asm/arch-sunxi/spl.h | 6 +----- arch/arm/mach-sunxi/Kconfig | 14 +++++--------- include/configs/sunxi-common.h | 19 +++++++++++-------- 3 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 4277d836e5..55f2deb18d 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -11,11 +11,7 @@ #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ #define SPL_HEADER_VERSION 2

-#ifdef CONFIG_SUNXI_HIGH_SRAM -#define SPL_ADDR 0x10000 -#else -#define SPL_ADDR 0x0 -#endif +#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS

/* The low 8-bits of the 'boot_media' field in the SPL header */ #define SUNXI_BOOTED_FROM_MMC0 0 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 678e33dd40..ccf4b35734 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -73,16 +73,15 @@ config SUN8I_RSB with various RSB based devices, such as AXP223, AXP8XX PMICs, and AC100/AC200 ICs.

-config SUNXI_HIGH_SRAM - bool - default n +config SUNXI_SRAM_ADDRESS + hex + default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 + default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, with the first SRAM region being located at address 0. Some newer SoCs map the boot ROM at address 0 instead and move the - SRAM to 64KB, just behind the mask ROM. - Chips using the latter setup are supposed to select this option to - adjust the addresses accordingly. + SRAM to a different address.

config SUNXI_A64_TIMER_ERRATUM bool @@ -257,7 +256,6 @@ config MACH_SUN9I select CPU_V7A select DRAM_SUN9I select SUN6I_PRCM - select SUNXI_HIGH_SRAM select SUNXI_GEN_SUN6I select SUN8I_RSB select SUPPORT_SPL @@ -269,7 +267,6 @@ config MACH_SUN50I select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_GEN_SUN6I - select SUNXI_HIGH_SRAM select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT @@ -281,7 +278,6 @@ config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)" select ARM64 select MACH_SUNXI_H3_H5 - select SUNXI_HIGH_SRAM select FIT select SPL_LOAD_FIT

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 21371f4919..1b5daa8928 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -82,20 +82,19 @@

#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */

-#ifdef CONFIG_SUNXI_HIGH_SRAM /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. + * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register + * is known yet. + * H6 has SRAM A1 at 0x00020000. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x10000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0x0 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#endif +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +/* FIXME: this may be larger on some SoCs */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */

#define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -187,7 +186,11 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #endif

-#ifdef CONFIG_SUNXI_HIGH_SRAM +/* + * We cannot use expressions here, because expressions won't be evaluated in + * autoconf.mk. + */ +#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ #ifdef CONFIG_ARM64

On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address) is at 0x20000, which is different with any old Allwinner SoCs.

Add SPL position and size configuration for this.

Signed-off-by: Icenowy Zheng icenowy@aosc.io Reviewed-by: Andre Przywara andre.przywara@arm.com --- Changes in v2: - Added Andre's Reviewed-by tag.

include/configs/sunxi-common.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1b5daa8928..4db770d69d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -199,6 +199,11 @@ #else #define LOW_LEVEL_SRAM_STACK 0x00018000 #endif /* !CONFIG_ARM64 */ +#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 +#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ +/* end of SRAM A2 on H6 for now */ +#define LOW_LEVEL_SRAM_STACK 0x00118000 #else #define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */

As the Allwinner H6 chip has a new memory map, its GIC MMIO address is thus different.

Change the address on H6.

Signed-off-by: Icenowy Zheng icenowy@aosc.io Reviewed-by: Andre Przywara andre.przywara@arm.com --- Changes in v2: - Added Andre's Reviewed-by tag.

include/configs/sun50i.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 5ce2cde388..e029218cf8 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -17,8 +17,13 @@

#define CONFIG_SUNXI_USB_PHYS 1

+#ifndef CONFIG_MACH_SUN50I_H6 #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 +#else +#define GICD_BASE 0x3021000 +#define GICC_BASE 0x3022000 +#endif

/* * Include common sunxi configuration where most the settings are

The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng icenowy@aosc.io --- Changes in v2: - Move the /4 divider in clk_get_pll6() to prevent possible overflow.

arch/arm/include/asm/arch-sunxi/clock.h | 2 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 320 ++++++++++++++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +++++ 4 files changed, 417 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 46c3eed377..5994130e6b 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -16,6 +16,8 @@ /* clock control module regs definition */ #if defined(CONFIG_MACH_SUN8I_A83T) #include <asm/arch/clock_sun8i_a83t.h> +#elif defined(CONFIG_MACH_SUN50I_H6) +#include <asm/arch/clock_sun50i_h6.h> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ defined(CONFIG_MACH_SUN50I) #include <asm/arch/clock_sun6i.h> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h new file mode 100644 index 0000000000..e36937059b --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -0,0 +1,320 @@ +/* + * Allwinner H6 clock register definitions + * + * (C) Copyright 2017 Icenowy Zheng icenowy@aosc.io + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN50I_H6_H +#define _SUNXI_CLOCK_SUN50I_H6_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ + u8 reserved_0x004[12]; + u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ + u8 reserved_0x014[12]; + u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ + u8 reserved_0x020[4]; + u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ + u8 reserved_0x028[4]; + u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ + u8 reserved_0x034[12]; + u32 pll3_cfg; /* 0x040 pll3 (video0) control */ + u8 reserved_0x044[4]; + u32 pll_video1_cfg; /* 0x048 pll video1 control */ + u8 reserved_0x04c[12]; + u32 pll4_cfg; /* 0x058 pll4 (ve) control */ + u8 reserved_0x05c[4]; + u32 pll10_cfg; /* 0x060 pll10 (de) control */ + u8 reserved_0x064[12]; + u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ + u8 reserved_0x074[4]; + u32 pll2_cfg; /* 0x078 pll2 (audio) control */ + u8 reserved_0x07c[148]; + u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ + u8 reserved_0x114[20]; + u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ + u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ + u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ + u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ + u8 reserved_0x138[8]; + u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ + u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ + u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ + u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ + u8 reserved_0x150[8]; + u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ + u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ + u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ + u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ + u8 reserved_0x168[8]; + u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ + u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ + u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ + u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ + u8 reserved_0x180[384]; + u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ + u8 reserved_0x304[12]; + u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ + u8 reserved_0x314[12]; + u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ + u8 reserved_0x324[4]; + u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ + u8 reserved_0x32c[4]; + u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ + u8 reserved_0x334[12]; + u32 pll3_bias; /* 0x340 pll3 (video0) bias */ + u8 reserved_0x344[4]; + u32 pll_video1_bias; /* 0x348 pll video1 bias */ + u8 reserved_0x34c[12]; + u32 pll4_bias; /* 0x358 pll4 (ve) bias */ + u8 reserved_0x35c[4]; + u32 pll10_bias; /* 0x360 pll10 (de) bias */ + u8 reserved_0x364[12]; + u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ + u8 reserved_0x374[4]; + u32 pll2_bias; /* 0x378 pll2 (audio) bias */ + u8 reserved_0x37c[132]; + u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ + u8 reserved_0x404[252]; + u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ + u8 reserved_0x504[12]; + u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ + u8 reserved_0x514[8]; + u32 ahb3_cfg; /* 0x51c AHB3 clock control */ + u32 apb1_cfg; /* 0x520 APB1 clock control */ + u32 apb2_cfg; /* 0x524 APB2 clock control */ + u8 reserved_0x528[24]; + u32 mbus_cfg; /* 0x540 MBUS clock control */ + u8 reserved_0x544[188]; + u32 de_clk_cfg; /* 0x600 DE clock control */ + u8 reserved_0x604[8]; + u32 de_gate_reset; /* 0x60c DE gate/reset control */ + u8 reserved_0x610[16]; + u32 di_clk_cfg; /* 0x620 DI clock control */ + u8 reserved_0x024[8]; + u32 di_gate_reset; /* 0x62c DI gate/reset control */ + u8 reserved_0x630[64]; + u32 gpu_clk_cfg; /* 0x670 GPU clock control */ + u8 reserved_0x674[8]; + u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ + u32 ce_clk_cfg; /* 0x680 CE clock control */ + u8 reserved_0x684[8]; + u32 ce_gate_reset; /* 0x68c CE gate/reset control */ + u32 ve_clk_cfg; /* 0x690 VE clock control */ + u8 reserved_0x694[8]; + u32 ve_gate_reset; /* 0x69c VE gate/reset control */ + u8 reserved_0x6a0[16]; + u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ + u8 reserved_0x6b4[8]; + u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ + u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ + u8 reserved_0x6c4[8]; + u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ + u8 reserved_0x6d0[60]; + u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ + u8 reserved_0x710[12]; + u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ + u8 reserved_0x720[12]; + u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ + u8 reserved_0x730[12]; + u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ + u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ + u8 reserved_0x744[72]; + u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ + u8 reserved_0x790[12]; + u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ + u8 reserved_0x7a0[12]; + u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ + u8 reserved_0x7b0[12]; + u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ + u8 reserved_0x7c0[64]; + u32 dram_clk_cfg; /* 0x800 DRAM clock control */ + u32 mbus_gate; /* 0x804 MBUS gate control */ + u8 reserved_0x808[4]; + u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ + u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ + u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ + u8 reserved_0x818[20]; + u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ + u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ + u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ + u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ + u8 reserved_0x83c[16]; + u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ + u8 reserved_0x850[188]; + u32 uart_gate_reset; /* 0x90c UART gate/reset control */ + u8 reserved_0x910[12]; + u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ + u8 reserved_0x920[28]; + u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ + u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ + u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ + u8 reserved_0x948[36]; + u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ + u8 reserved_0x970[12]; + u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ + u8 reserved_0x980[48]; + u32 ts_clk_cfg; /* 0x9b0 TS clock control */ + u8 reserved_0x9b4[8]; + u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ + u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ + u8 reserved_0x9c4[8]; + u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ + u8 reserved_0x9d0[44]; + u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ + u8 reserved_0xa00[12]; + u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ + u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ + u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ + u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ + u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ + u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ + u8 reserved_0xa24[8]; + u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ + u8 reserved_0xa30[16]; + u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ + u8 reserved_0xa44[8]; + u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ + u8 reserved_0xa50[16]; + u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ + u8 reserved_0xa64[8]; + u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ + u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ + u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ + u8 reserved_0xa78[4]; + u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ + u8 reserved_0xa80[12]; + u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ + u8 reserved_0xa90[32]; + u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ + u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ + u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ + u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ + u8 reserved_0xac0[64]; + u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ + u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ + u8 reserved_0xb08[8]; + u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ + u8 reserved_0xb14[8]; + u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ + u8 reserved_0xb20[60]; + u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ + u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ + u8 reserved_0xb64[24]; + u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ + u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ + u8 reserved_0xb84[24]; + u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ + u8 reserved_0xba0[96]; + u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ + u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ + u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ + u8 reserved_0xc0c[32]; + u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ + u8 reserved_0xc30[16]; + u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ + u8 reserved_0xc44[8]; + u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ + u8 reserved_0xc50[688]; + u32 ccu_sec_switch; /* 0xf00 CCU security switch */ + u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ +}; + +/* pll1 bit field */ +#define CCM_PLL1_CTRL_EN BIT(31) +#define CCM_PLL1_LOCK_EN BIT(29) +#define CCM_PLL1_LOCK BIT(28) +#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) +#define CCM_PLL1_CTRL_P(p) ((p) << 16) +#define CCM_PLL1_CTRL_N(n) ((n) << 8) + +/* pll5 bit field */ +#define CCM_PLL5_CTRL_EN BIT(31) +#define CCM_PLL5_LOCK_EN BIT(29) +#define CCM_PLL5_LOCK BIT(28) +#define CCM_PLL5_CTRL_N(n) ((n) << 8) +#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) +#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) + +/* pll6 bit field */ +#define CCM_PLL6_CTRL_EN BIT(31) +#define CCM_PLL6_LOCK_EN BIT(29) +#define CCM_PLL6_LOCK BIT(28) +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_DIV1_SHIFT 0 +#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) +#define CCM_PLL6_CTRL_DIV2_SHIFT 1 +#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) +#define CCM_PLL6_DEFAULT 0xa0006300 + +/* cpu_axi bit field*/ +#define CCM_CPU_AXI_MUX_MASK (0x3 << 24) +#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) +#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) +#define CCM_CPU_AXI_APB_MASK 0x300 +#define CCM_CPU_AXI_AXI_MASK 0x3 +#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 + +/* psi_ahb1_ahb2 bit field */ +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 + +/* ahb3 bit field */ +#define CCM_AHB3_DEFAULT 0x03000002 + +/* apb1 bit field */ +#define CCM_APB1_DEFAULT 0x03000102 + +/* apb2 bit field */ +#define APB2_CLK_SRC_OSC24M (0x0 << 24) +#define APB2_CLK_SRC_OSC32K (0x1 << 24) +#define APB2_CLK_SRC_PSI (0x2 << 24) +#define APB2_CLK_SRC_PLL6 (0x3 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 8) +#define APB2_CLK_RATE_N_2 (0x1 << 8) +#define APB2_CLK_RATE_N_4 (0x2 << 8) +#define APB2_CLK_RATE_N_8 (0x3 << 8) +#define APB2_CLK_RATE_N_MASK (3 << 8) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (3 << 0) + +/* MBUS clock bit field */ +#define MBUS_ENABLE BIT(31) +#define MBUS_RESET BIT(30) +#define MBUS_CLK_SRC_MASK GENMASK(25, 24) +#define MBUS_CLK_SRC_OSCM24 (0 << 24) +#define MBUS_CLK_SRC_PLL6X2 (1 << 24) +#define MBUS_CLK_SRC_PLL5 (2 << 24) +#define MBUS_CLK_SRC_PLL6X4 (3 << 24) +#define MBUS_CLK_M(m) (((m)-1) << 0) + +/* Module gate/reset shift*/ +#define RESET_SHIFT (16) + +/* DRAM clock bit field */ +#define DRAM_MOD_RESET BIT(30) +#define DRAM_CLK_UPDATE BIT(27) +#define DRAM_CLK_SRC_MASK GENMASK(25, 24) +#define DRAM_CLK_SRC_PLL5 (0 << 24) +#define DRAM_CLK_M(m) (((m)-1) << 0) + +/* MMC clock bit field */ +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_N(x) ((x) << 8) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) +#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) +/* H6 doesn't have these delays */ +#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) +#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN50I_H6_H */ diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 4c752491a1..97a4f22d8a 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -26,6 +26,7 @@ else obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o endif obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o +obj-$(CONFIG_MACH_SUN50I_H6) += clock_sun50i_h6.o

ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c new file mode 100644 index 0000000000..ba8a26eb0d --- /dev/null +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -0,0 +1,94 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + clock_set_pll1(408000000); + + writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) + ; + + clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, + CCM_CPU_AXI_DEFAULT_FACTORS); + + writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); + writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); + writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); + + /* + * The mux and factor are set, but the clock will be enabled in + * DRAM initialization code. + */ + writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_cfg); + + /* open the clock for uart */ + setbits_le32(&ccm->uart_gate_reset, + 1 << (CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->uart_gate_reset, + 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + u32 val; + + /* Do not support clocks < 288MHz as they need factor P */ + if (clk < 288000000) clk = 288000000; + + /* Switch to 24MHz clock while changing PLL1 */ + val = readl(&ccm->cpu_axi_cfg); + val &= ~CCM_CPU_AXI_MUX_MASK; + val |= CCM_CPU_AXI_MUX_OSC24M; + writel(val, &ccm->cpu_axi_cfg); + + /* clk = 24*n/p, p is ignored if clock is >288MHz */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); + while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} + + /* Switch CPU to PLL1 */ + val = readl(&ccm->cpu_axi_cfg); + val &= ~CCM_CPU_AXI_MUX_MASK; + val |= CCM_CPU_AXI_MUX_PLL_CPUX; + writel(val, &ccm->cpu_axi_cfg); +} +#endif + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + /* The register defines PLL6-4X, not plain PLL6 */ + return 24000000 / 4 * n / div1 / div2; +}

The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng icenowy@aosc.io --- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index cb02dd8bf8..6f138d04b8 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -76,7 +76,7 @@ struct sunxi_timer_reg { struct sunxi_tgp tgp[4]; u8 res5[8]; u32 cpu_cfg; -#elif defined(CONFIG_SUNXI_GEN_SUN6I) +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) u8 res3[16]; struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ #endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 58fef05bd7..40a6436ca5 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -282,7 +282,7 @@ void reset_cpu(ulong addr) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } -#elif defined(CONFIG_SUNXI_GEN_SUN6I) +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) static const struct sunxi_wdog *wdog = ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng icenowy@aosc.io Reviewed-by: Andre Przywara andre.przywara@arm.com --- Changes in v2: - Added Andre's Reviewed-by tag.

arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/board.c | 4 ++++ 2 files changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index e4fe54d8b8..6a5eafc3d3 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -198,6 +198,7 @@ enum sunxi_gpio_number { #define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUN9I_GPH_UART0 2 +#define SUN50I_H6_GPH_UART0 2

#define SUNXI_GPI_SDC3 2 #define SUN7I_GPI_TWI3 3 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 40a6436ca5..d22a84ea6b 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -107,6 +107,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);

The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with the MMC2 come with the capability to do crypto by EMCE.

Add MMC support for H6. EMCE support is not added yet.

Signed-off-by: Icenowy Zheng icenowy@aosc.io --- arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- board/sunxi/board.c | 7 +++++++ drivers/mmc/sunxi_mmc.c | 13 ++++++++++++- 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 1574b8e8fe..d98c53faaa 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -45,7 +45,7 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res2[26]; -#ifdef CONFIG_SUNXI_GEN_SUN6I +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) u32 res3[64]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 5ed1b8bae1..857d5ff010 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -443,6 +443,13 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } +#elif defined(CONFIG_MACH_SUN50I_H6) + /* SDC2: PC4-PC14 */ + for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } #elif defined(CONFIG_MACH_SUN9I) /* SDC2: PC6-PC16 */ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 7fa1ae8b16..39f15eb423 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no) priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; priv->mclkreg = &ccm->sd2_clk_cfg; break; +#ifdef SUNXI_MMC3_BASE case 3: priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; priv->mclkreg = &ccm->sd3_clk_cfg; break; +#endif default: printf("Wrong mmc number %d\n", sdc_no); return -1; @@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) #ifdef CONFIG_MACH_SUN9I pll = CCM_MMC_CTRL_PLL_PERIPH0; pll_hz = clock_get_pll4_periph0(); +#elif defined(CONFIG_MACH_SUN50I_H6) + pll = CCM_MMC_CTRL_PLL6X2; + pll_hz = clock_get_pll6() * 2; #else pll = CCM_MMC_CTRL_PLL6; pll_hz = clock_get_pll6(); @@ -494,7 +499,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)

cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT; -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6) if (sdc_no == 2) cfg->host_caps = MMC_MODE_8BIT; #endif @@ -509,6 +514,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)

/* config ahb clock */ debug("init mmc %d clock and io\n", sdc_no); +#if !defined(CONFIG_MACH_SUN50I_H6) setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));

#ifdef CONFIG_SUNXI_GEN_SUN6I @@ -519,6 +525,11 @@ struct mmc *sunxi_mmc_init(int sdc_no) /* sun9i has a mmc-common module, also set the gate and reset there */ writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, SUNXI_MMC_COMMON_BASE + 4 * sdc_no); +#endif +#else /* CONFIG_MACH_SUN50I_H6 */ + setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no); + /* unassert reset */ + setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no)); #endif ret = mmc_set_mod_clk(priv, 24000000); if (ret)

Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also introduced.

Signed-off-by: Icenowy Zheng icenowy@aosc.io --- Changes in v2: - Sync device tree to next-20180720.

arch/arm/dts/sun50i-h6.dtsi | 288 ++++++++++++++++++++ arch/arm/mach-sunxi/Kconfig | 17 +- arch/arm/mach-sunxi/cpu_info.c | 2 + common/spl/Kconfig | 2 +- include/dt-bindings/clock/sun50i-h6-ccu.h | 125 +++++++++ include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 ++ include/dt-bindings/reset/sun50i-h6-ccu.h | 73 +++++ include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 ++ 8 files changed, 546 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6.dtsi create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h

diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi new file mode 100644 index 0000000000..cfa5fffcf6 --- /dev/null +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun50i-h6-ccu.h> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/reset/sun50i-h6-ccu.h> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h6-ccu"; + reg = <0x03001000 0x1000>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-h6-pinctrl"; + reg = <0x0300b000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_ph_pins: uart0-ph { + pins = "PH0", "PH1"; + function = "uart0"; + }; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun50i-h6-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@5000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@5000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@5000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@5000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-h6-r-ccu"; + reg = <0x07010000 0x400>; + clocks = <&osc24M>, <&osc32k>, <&iosc>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_intc: interrupt-controller@7021000 { + compatible = "allwinner,sun50i-h6-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x07021000 0x400>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-h6-r-pinctrl"; + reg = <0x07022000 0x400>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c { + pins = "PL0", "PL1"; + function = "s_i2c"; + }; + }; + + r_i2c: i2c@7081400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_I2C>; + resets = <&r_ccu RST_R_APB2_I2C>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 32a46797e2..558363b52d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -82,6 +82,7 @@ config SUN8I_RSB config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 + default 0x20000 if MACH_SUN50I_H6 default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, @@ -287,6 +288,14 @@ config MACH_SUN50I_H5 select FIT select SPL_LOAD_FIT

+config MACH_SUN50I_H6 + bool "sun50i (Allwinner H6)" + select ARM64 + select SUPPORT_SPL + select FIT + select SPL_LOAD_FIT + select DRAM_SUN50I_H6 + endchoice

# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" @@ -380,6 +389,7 @@ config DRAM_CLK default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ MACH_SUN8I_V3S default 672 if MACH_SUN50I + default 744 if MACH_SUN50I_H6 ---help--- Set the dram clock speed, valid range 240 - 480 (prior to sun9i), must be a multiple of 24. For the sun9i (A80), the tested values @@ -399,7 +409,7 @@ config DRAM_ZQ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I default 14779 if MACH_SUN8I_V3S - default 3881979 if MACH_SUN8I_R40 + default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I ---help--- @@ -411,6 +421,7 @@ config DRAM_ODT_EN default y if MACH_SUN8I_A23 default y if MACH_SUN8I_R40 default y if MACH_SUN50I + default y if MACH_SUN50I_H6 ---help--- Select this to enable dram odt (on die termination).

@@ -501,6 +512,7 @@ config SYS_CLK_FREQ default 816000000 if MACH_SUN50I || MACH_SUN50I_H5 default 1008000000 if MACH_SUN8I default 1008000000 if MACH_SUN9I + default 888000000 if MACH_SUN50I_H6

config SYS_CONFIG_NAME default "sun4i" if MACH_SUN4I @@ -510,6 +522,7 @@ config SYS_CONFIG_NAME default "sun8i" if MACH_SUN8I default "sun9i" if MACH_SUN9I default "sun50i" if MACH_SUN50I + default "sun50i" if MACH_SUN50I_H6

config SYS_BOARD default "sunxi" @@ -715,6 +728,7 @@ config VIDEO_SUNXI depends on !MACH_SUN8I_V3S depends on !MACH_SUN9I depends on !MACH_SUN50I + depends on !MACH_SUN50I_H6 select VIDEO imply VIDEO_DT_SIMPLEFB default y @@ -947,6 +961,7 @@ config SPL_STACK_R_ADDR default 0x4fe00000 if MACH_SUN8I default 0x2fe00000 if MACH_SUN9I default 0x4fe00000 if MACH_SUN50I + default 0x4fe00000 if MACH_SUN50I_H6

config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index aadf575ef2..ae4745bfec 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -96,6 +96,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A64 (SUN50I)\n"); #elif defined CONFIG_MACH_SUN50I_H5 puts("CPU: Allwinner H5 (SUN50I)\n"); +#elif defined CONFIG_MACH_SUN50I_H6 + puts("CPU: Allwinner H6 (SUN50I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 99c9053ab8..954f055123 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -256,7 +256,7 @@ config SPL_SHA256_SUPPORT config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT - default y if MACH_SUN50I || MACH_SUN50I_H5 + default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h new file mode 100644 index 0000000000..a1545cd60e --- /dev/null +++ b/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_H_ + +#define CLK_PLL_PERIPH0 3 + +#define CLK_CPUX 21 + +#define CLK_APB1 26 + +#define CLK_DE 29 +#define CLK_BUS_DE 30 +#define CLK_DEINTERLACE 31 +#define CLK_BUS_DEINTERLACE 32 +#define CLK_GPU 33 +#define CLK_BUS_GPU 34 +#define CLK_CE 35 +#define CLK_BUS_CE 36 +#define CLK_VE 37 +#define CLK_BUS_VE 38 +#define CLK_EMCE 39 +#define CLK_BUS_EMCE 40 +#define CLK_VP9 41 +#define CLK_BUS_VP9 42 +#define CLK_BUS_DMA 43 +#define CLK_BUS_MSGBOX 44 +#define CLK_BUS_SPINLOCK 45 +#define CLK_BUS_HSTIMER 46 +#define CLK_AVS 47 +#define CLK_BUS_DBG 48 +#define CLK_BUS_PSI 49 +#define CLK_BUS_PWM 50 +#define CLK_BUS_IOMMU 51 + +#define CLK_MBUS_DMA 53 +#define CLK_MBUS_VE 54 +#define CLK_MBUS_CE 55 +#define CLK_MBUS_TS 56 +#define CLK_MBUS_NAND 57 +#define CLK_MBUS_CSI 58 +#define CLK_MBUS_DEINTERLACE 59 + +#define CLK_NAND0 61 +#define CLK_NAND1 62 +#define CLK_BUS_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_BUS_MMC0 67 +#define CLK_BUS_MMC1 68 +#define CLK_BUS_MMC2 69 +#define CLK_BUS_UART0 70 +#define CLK_BUS_UART1 71 +#define CLK_BUS_UART2 72 +#define CLK_BUS_UART3 73 +#define CLK_BUS_I2C0 74 +#define CLK_BUS_I2C1 75 +#define CLK_BUS_I2C2 76 +#define CLK_BUS_I2C3 77 +#define CLK_BUS_SCR0 78 +#define CLK_BUS_SCR1 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_BUS_SPI0 82 +#define CLK_BUS_SPI1 83 +#define CLK_BUS_EMAC 84 +#define CLK_TS 85 +#define CLK_BUS_TS 86 +#define CLK_IR_TX 87 +#define CLK_BUS_IR_TX 88 +#define CLK_BUS_THS 89 +#define CLK_I2S3 90 +#define CLK_I2S0 91 +#define CLK_I2S1 92 +#define CLK_I2S2 93 +#define CLK_BUS_I2S0 94 +#define CLK_BUS_I2S1 95 +#define CLK_BUS_I2S2 96 +#define CLK_BUS_I2S3 97 +#define CLK_SPDIF 98 +#define CLK_BUS_SPDIF 99 +#define CLK_DMIC 100 +#define CLK_BUS_DMIC 101 +#define CLK_AUDIO_HUB 102 +#define CLK_BUS_AUDIO_HUB 103 +#define CLK_USB_OHCI0 104 +#define CLK_USB_PHY0 105 +#define CLK_USB_PHY1 106 +#define CLK_USB_OHCI3 107 +#define CLK_USB_PHY3 108 +#define CLK_USB_HSIC_12M 109 +#define CLK_USB_HSIC 110 +#define CLK_BUS_OHCI0 111 +#define CLK_BUS_OHCI3 112 +#define CLK_BUS_EHCI0 113 +#define CLK_BUS_XHCI 114 +#define CLK_BUS_EHCI3 115 +#define CLK_BUS_OTG 116 +#define CLK_PCIE_REF_100M 117 +#define CLK_PCIE_REF 118 +#define CLK_PCIE_REF_OUT 119 +#define CLK_PCIE_MAXI 120 +#define CLK_PCIE_AUX 121 +#define CLK_BUS_PCIE 122 +#define CLK_HDMI 123 +#define CLK_HDMI_SLOW 124 +#define CLK_HDMI_CEC 125 +#define CLK_BUS_HDMI 126 +#define CLK_BUS_TCON_TOP 127 +#define CLK_TCON_LCD0 128 +#define CLK_BUS_TCON_LCD0 129 +#define CLK_TCON_TV0 130 +#define CLK_BUS_TCON_TV0 131 +#define CLK_CSI_CCI 132 +#define CLK_CSI_TOP 133 +#define CLK_CSI_MCLK 134 +#define CLK_BUS_CSI 135 +#define CLK_HDCP 136 +#define CLK_BUS_HDCP 137 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h new file mode 100644 index 0000000000..76136132a1 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Icenowy Zheng icenowy@aosc.xyz + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB2_UART 7 +#define CLK_R_APB2_I2C 8 +#define CLK_R_APB1_IR 9 +#define CLK_R_APB1_W1 10 + +#define CLK_IR 11 +#define CLK_W1 12 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h new file mode 100644 index 0000000000..81106f4550 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ +#define _DT_BINDINGS_RESET_SUN50I_H6_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_EMCE 6 +#define RST_BUS_VP9 7 +#define RST_BUS_DMA 8 +#define RST_BUS_MSGBOX 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PSI 13 +#define RST_BUS_PWM 14 +#define RST_BUS_IOMMU 15 +#define RST_BUS_DRAM 16 +#define RST_BUS_NAND 17 +#define RST_BUS_MMC0 18 +#define RST_BUS_MMC1 19 +#define RST_BUS_MMC2 20 +#define RST_BUS_UART0 21 +#define RST_BUS_UART1 22 +#define RST_BUS_UART2 23 +#define RST_BUS_UART3 24 +#define RST_BUS_I2C0 25 +#define RST_BUS_I2C1 26 +#define RST_BUS_I2C2 27 +#define RST_BUS_I2C3 28 +#define RST_BUS_SCR0 29 +#define RST_BUS_SCR1 30 +#define RST_BUS_SPI0 31 +#define RST_BUS_SPI1 32 +#define RST_BUS_EMAC 33 +#define RST_BUS_TS 34 +#define RST_BUS_IR_TX 35 +#define RST_BUS_THS 36 +#define RST_BUS_I2S0 37 +#define RST_BUS_I2S1 38 +#define RST_BUS_I2S2 39 +#define RST_BUS_I2S3 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_DMIC 42 +#define RST_BUS_AUDIO_HUB 43 +#define RST_USB_PHY0 44 +#define RST_USB_PHY1 45 +#define RST_USB_PHY3 46 +#define RST_USB_HSIC 47 +#define RST_BUS_OHCI0 48 +#define RST_BUS_OHCI3 49 +#define RST_BUS_EHCI0 50 +#define RST_BUS_XHCI 51 +#define RST_BUS_EHCI3 52 +#define RST_BUS_OTG 53 +#define RST_BUS_PCIE 54 +#define RST_PCIE_POWERUP 55 +#define RST_BUS_HDMI 56 +#define RST_BUS_HDMI_SUB 57 +#define RST_BUS_TCON_TOP 58 +#define RST_BUS_TCON_LCD0 59 +#define RST_BUS_TCON_TV0 60 +#define RST_BUS_CSI 61 +#define RST_BUS_HDCP 62 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h new file mode 100644 index 0000000000..01c84dba49 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2016 Icenowy Zheng icenowy@aosc.xyz + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_TWD 1 +#define RST_R_APB1_PWM 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C 4 +#define RST_R_APB1_IR 5 +#define RST_R_APB1_W1 6 + +#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */

Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features 1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port and a mPCIE slot.

Add support for it.

The device tree is from Linux next-20180720.

Signed-off-by: Icenowy Zheng icenowy@aosc.io --- Changes in v2: - Sync device tree to next-20180720.

arch/arm/dts/Makefile | 2 + arch/arm/dts/sun50i-h6-pine-h64.dts | 185 ++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/pine_h64_defconfig | 15 +++ 4 files changed, 207 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-pine-h64.dts create mode 100644 configs/pine_h64_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9607239b03..2cfd39c4e3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -385,6 +385,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-pc2.dtb \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb +dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-pine-h64.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts new file mode 100644 index 0000000000..ceffc40810 --- /dev/null +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (c) 2017 Icenowy Zheng icenowy@aosc.io + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Pine H64"; + compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "pine-h64:green:heartbeat"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; + + link { + label = "pine-h64:white:link"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ + }; + + status { + label = "pine-h64:blue:status"; + gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + }; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&reg_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&reg_cldo1>; + vqmmc-supply = <&reg_bldo2>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + }; + + reg_aldo3: aldo3 { + /* This regulator is connected with CLDO1 */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-1"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + /* This regulator is connected with ALDO3 */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-2"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index db51f48ab6..8468227c2a 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -370,6 +370,11 @@ M: Andre Przywara andre.przywara@arm.com S: Maintained F: configs/pine64_plus_defconfig

+PINE H64 BOARD +M: Icenowy Zheng icenowy@aosc.io +S: Maintained +F: configs/pine_h64_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz quentin.schulz@free-electrons.com S: Maintained diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig new file mode 100644 index 0000000000..e9596c0284 --- /dev/null +++ b/configs/pine_h64_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set