Use driver data->variant information to select device specific pin mux and phy clock settings.

Suggested by Jagan Teki

Signed-off-by: Lothar Felten lothar.felten@gmail.com --- Changelog: new in v3 v3 -> v4 use driver data to distinguish between variants

drivers/net/sun8i_emac.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 23c4d68f77..ee3b2aa7f4 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -65,11 +65,9 @@

#define AHB_GATE_OFFSET_EPHY 0

-#if defined(CONFIG_MACH_SUNXI_H3_H5) -#define SUN8I_GPD8_GMAC 2 -#else -#define SUN8I_GPD8_GMAC 4 -#endif +/* IO mux settings */ +#define SUN8I_IOMUX_H3 2 +#define SUN8I_IOMUX 4

/* H3/A64 EMAC Register's offset */ #define EMAC_CTL0 0x00 @@ -453,6 +451,7 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)

static int parse_phy_pins(struct udevice *dev) { + struct emac_eth_dev *priv = dev_get_priv(dev); int offset; const char *pin_name; int drive, pull = SUN4I_PINCTRL_NO_PULL, i; @@ -494,7 +493,11 @@ static int parse_phy_pins(struct udevice *dev) if (pin < 0) continue;

- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); + if (priv->variant == H3_EMAC) + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3); + else + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX); + if (drive != ~0) sunxi_gpio_set_drv(pin, drive); if (pull != ~0) @@ -618,16 +621,18 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

-#ifdef CONFIG_MACH_SUNXI_H3_H5 - /* Only H3/H5 have clock controls for internal EPHY */ - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); - - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); + if (priv->variant == H3_EMAC) { + /* Only H3/H5 have clock controls for internal EPHY */ + if (priv->use_internal_phy) { + /* Set clock gating for ephy */ + setbits_le32(&ccm->bus_gate4, + BIT(AHB_GATE_OFFSET_EPHY)); + + /* Deassert EPHY */ + setbits_le32(&ccm->ahb_reset2_cfg, + BIT(AHB_RESET_OFFSET_EPHY)); + } } -#endif

/* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));

Add support for the GMAC found in the Allwinner R40/V40 SoC.

The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC).

Signed-off-by: Lothar Felten lothar.felten@gmail.com --- Changelog: new in v3 v3 -> v4 use driver data to distinguish between variants

drivers/net/sun8i_emac.c | 79 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 26 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index ee3b2aa7f4..3ba3a1ff8b 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -67,6 +67,7 @@

/* IO mux settings */ #define SUN8I_IOMUX_H3 2 +#define SUN8I_IOMUX_R40 5 #define SUN8I_IOMUX 4

/* H3/A64 EMAC Register's offset */ @@ -97,6 +98,7 @@ enum emac_variant { A83T_EMAC = 1, H3_EMAC, A64_EMAC, + R40_GMAC, };

struct emac_dma_desc { @@ -278,6 +280,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)

reg = readl(priv->sysctl_reg + 0x30);

+ if (priv->variant == R40_GMAC) + return 0; + if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, &reg); if (ret) @@ -495,6 +500,8 @@ static int parse_phy_pins(struct udevice *dev)

if (priv->variant == H3_EMAC) sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3); + else if (priv->variant == R40_GMAC) + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40); else sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);

@@ -634,11 +641,26 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } }

- /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); + if (priv->variant == R40_GMAC) { + /* Set clock gating for emac */ + setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); + + /* De-assert EMAC */ + setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); + + /* Select RGMII for R40 */ + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); + } else { + /* Set clock gating for emac */ + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + + /* De-assert EMAC */ + setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); + } }

#if defined(CONFIG_DM_GPIO) @@ -805,22 +827,32 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }

- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); - if (offset < 0) { - debug("%s: cannot find syscon node\n", __func__); - return -EINVAL; - } - reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); - if (!reg) { - debug("%s: cannot find reg property in syscon node\n", - __func__); + priv->variant = dev_get_driver_data(dev); + + if (!priv->variant) { + printf("%s: Missing variant\n", __func__); return -EINVAL; } - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, - offset, reg); - if (priv->sysctl_reg == FDT_ADDR_T_NONE) { - debug("%s: Cannot find syscon base address\n", __func__); - return -EINVAL; + + if (priv->variant != R40_GMAC) { + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", + __func__); + return -EINVAL; + } }

pdata->phy_interface = -1; @@ -845,13 +877,6 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }

- priv->variant = dev_get_driver_data(dev); - - if (!priv->variant) { - printf("%s: Missing variant\n", __func__); - return -EINVAL; - } - if (priv->variant == H3_EMAC) { int parent = fdt_parent_offset(gd->fdt_blob, offset);

@@ -892,6 +917,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (uintptr_t)A64_EMAC }, {.compatible = "allwinner,sun8i-a83t-emac", .data = (uintptr_t)A83T_EMAC }, + {.compatible = "allwinner,sun8i-r40-gmac", + .data = (uintptr_t)R40_GMAC }, { } };

Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins.

Signed-off-by: Lothar Felten lothar.felten@gmail.com --- Changelog: new in v2 v2 -> v3 omit syscon node for R40 v3 -> v4 remove phy-mode from gmac node

arch/arm/dts/sun8i-r40.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 0aa76a2f10..3a0b3ab543 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -52,6 +52,7 @@ interrupt-parent = <&gic>;

aliases { + ethernet0 = &gmac; };

chosen { @@ -161,6 +162,15 @@ #interrupt-cells = <3>; #gpio-cells = <3>;

+ gmac_pins_rgmii: gmac_rgmii { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + function = "gmac"; + }; + i2c0_pins: i2c0_pins { pins = "PB0", "PB1"; function = "i2c0"; @@ -202,6 +212,26 @@ #size-cells = <0>; };

+ gmac: ethernet@01c50000 { + compatible = "allwinner,sun8i-r40-gmac"; + reg = <0x01c50000 0x2000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&osc24M>, <&osc24M>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>,