This patch makes use of common code, i.e. removes duplicate board specific code. Fix wrong GPIO direction.

Signed-off-by: André Schwarz andre.schwarz@matrix-vision.de ---

Kim, please note that this patch depends on WD applying the "add common code" patch.

Cheers, André

board/matrix_vision/mvblm7/mvblm7.c | 54 +++++++++++++++------------------- board/matrix_vision/mvblm7/mvblm7.h | 3 +- board/matrix_vision/mvblm7/pci.c | 32 ++------------------ 3 files changed, 29 insertions(+), 60 deletions(-)

diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index 6984af9..53d873a 100644 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -42,8 +42,15 @@ int fixed_sdram(void) u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; + char *s = getenv("ddr_size");

msize = CONFIG_SYS_DDR_SIZE; + if (s) { + u32 env_ddr_size = simple_strtoul(s, NULL, 10); + if (env_ddr_size == 512) + msize = 512; + } + for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { @@ -63,14 +70,19 @@ int fixed_sdram(void) im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;

- udelay(300); + asm("sync;isync"); + udelay(600);

im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

- return CONFIG_SYS_DDR_SIZE; + asm("sync;isync"); + udelay(500); + + return msize; }

phys_size_t initdram(int board_type) @@ -88,40 +100,22 @@ phys_size_t initdram(int board_type) return msize * 1024 * 1024; }

-int checkboard(void) +int misc_init_r(void) { - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} + char *s = getenv("reset_env");

-u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - ptr = getenv("dhcp_vendor-class-identifier"); - if (ptr) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - ptr = getenv("dhcp_client_id"); - if (ptr) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; + if (s) { + mv_reset_environment(); }

- return e; + return 0; }

-u8 *dhcp_vendorex_proc(u8 *popt) +int checkboard(void) { - return NULL; + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; }

#ifdef CONFIG_HARD_SPI diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h index 03e9f41..de9fec7 100644 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ b/board/matrix_vision/mvblm7/mvblm7.h @@ -8,14 +8,13 @@ #define FPGA_DIN 0x20000000 #define FPGA_STATUS 0x10000000 #define FPGA_CONF_DONE 0x08000000 -#define MMC_CS 0x04000000

#define WD_WDI 0x00400000 #define WD_TS 0x00200000 #define MAN_RST 0x00100000

#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI| MMC_CS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) #define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)

#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index 9f31719..3ed0b80 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -35,21 +35,6 @@

DECLARE_GLOBAL_DATA_PTR;

-int mvblm7_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -84,32 +69,23 @@ void pci_init_board(void) volatile law83xx_t *pci_law; struct pci_region *reg[] = { pci_regions };

- load_fpga = 1; immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) &immr->clk; pci_ctrl = immr->pci_ctrl; pci_law = immr->sysconf.pcilaw; gpio = (volatile gpio83xx_t *)&immr->gpio[0];

- s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - gpio->dat = MV_GPIO_DAT; gpio->odr = MV_GPIO_ODE; - if (load_fpga) - gpio->dir = MV_GPIO_OUT; - else - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + gpio->dir = MV_GPIO_OUT;

printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, immr->sysconf.sicrl);

mvblm7_init_fpga(); - if (load_fpga) - mvblm7_load_fpga(); + mv_load_fpga(); + + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);

/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ clk->occr = 0xc0000000;

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