[U-Boot] [PATCH v1 0/3] Enable HPS execution stage notification
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: (1) First Stage Boot Loader (FSBL) which is U-Boot SPL. (2) Second Stage Boot Loader (SSBL) which is U-Boot. (3) Operating System which is Linux.
Ang, Chee Hong (3): ARM: socfpga: stratix10: Add HPS execution stage notification function ARM: socfpga: stratix10: To notify SDM when SPL pass control to U-Boot ARM: socfpga: stratix10: To notify SDM when U-Boot pass control to Linux
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ arch/arm/mach-socfpga/misc_s10.c | 5 +++++ arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 4 files changed, 24 insertions(+)
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System which is Linux.
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Ang, Chee Hong chee.hong.ang@intel.com --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ 2 files changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index ae728a5..e815bdf 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -87,6 +87,12 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 + +/* Defines for HPS_STAGE_NOTIFY */ +#define HPS_EXECUTION_STATE_FSBL 0 +#define HPS_EXECUTION_STATE_SSBL 1 +#define HPS_EXECUTION_STATE_OS 2
/* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -146,6 +152,7 @@ int mbox_qspi_open(void); #endif
int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4498ab5..250df84 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -390,6 +390,12 @@ int __secure mbox_get_fpga_config_status_psci(u32 cmd) return mbox_get_fpga_config_status_common(cmd); }
+int mbox_hps_stage_notify(u32 execution_stage) +{ + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +} + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf) {
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Prior SPL pass control to U-Boot, SPL will send a mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW transition.
This is for debug purpose as user can query SDM on HPS error details when HPS enters a warm reset due to error such as watchdog.
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ang, Chee Hong chee.hong.ang@intel.com --- arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index e063229..0721415 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -191,3 +191,9 @@ void board_init_f(ulong dummy) mbox_qspi_open(); #endif } + +/* board specific function prior loading SSBL / U-Boot */ +void spl_board_prepare_for_boot(void) +{ + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); +}
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Prior U-Boot pass control to Linux, U-Boot will send a mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW transition.
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ang, Chee Hong chee.hong.ang@intel.com --- arch/arm/mach-socfpga/misc_s10.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 0e4133f..5ae6ed2 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -166,3 +166,8 @@ void do_bridge_reset(int enable)
socfpga_bridges_reset(enable); } + +void arch_preboot_os(void) +{ + mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS); +}
On 5/7/19 7:07 AM, chee.hong.ang@intel.com wrote:
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: (1) First Stage Boot Loader (FSBL) which is U-Boot SPL. (2) Second Stage Boot Loader (SSBL) which is U-Boot. (3) Operating System which is Linux.
Ang, Chee Hong (3): ARM: socfpga: stratix10: Add HPS execution stage notification function ARM: socfpga: stratix10: To notify SDM when SPL pass control to U-Boot ARM: socfpga: stratix10: To notify SDM when U-Boot pass control to Linux
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ arch/arm/mach-socfpga/misc_s10.c | 5 +++++ arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 4 files changed, 24 insertions(+)
Can we expect any of this mbox stuff to be ever migrated over to DM and moved into drivers/ instead of constantly adding stuff to mach-socfpga ?
On Tue, 2019-05-07 at 15:03 +0200, Marek Vasut wrote:
On 5/7/19 7:07 AM, chee.hong.ang@intel.com wrote:
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: (1) First Stage Boot Loader (FSBL) which is U-Boot SPL. (2) Second Stage Boot Loader (SSBL) which is U-Boot. (3) Operating System which is Linux.
Ang, Chee Hong (3): ARM: socfpga: stratix10: Add HPS execution stage notification function ARM: socfpga: stratix10: To notify SDM when SPL pass control to U-Boot ARM: socfpga: stratix10: To notify SDM when U-Boot pass control to Linux
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ arch/arm/mach-socfpga/misc_s10.c | 5 +++++ arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 4 files changed, 24 insertions(+)
Can we expect any of this mbox stuff to be ever migrated over to DM and moved into drivers/ instead of constantly adding stuff to mach- socfpga ?
These mailbox stuffs are basically a set of functions shared by SPL, u- boot and Linux (PSCI) which is specific to our platform. Even if we convert this mailbox stuffs to DM and move to drivers/, we still need to duplicate those functions for PSCI which can be called by Linux. We are starting to spend time converting our existing clock manager and etc for S10 platform to DM and will move them to drivers/. But we still need to keep those PSCI stuffs which are specific to our platform in mach-sofcpga.
On 5/7/19 4:08 PM, Ang, Chee Hong wrote:
On Tue, 2019-05-07 at 15:03 +0200, Marek Vasut wrote:
On 5/7/19 7:07 AM, chee.hong.ang@intel.com wrote:
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: (1) First Stage Boot Loader (FSBL) which is U-Boot SPL. (2) Second Stage Boot Loader (SSBL) which is U-Boot. (3) Operating System which is Linux.
Ang, Chee Hong (3): ARM: socfpga: stratix10: Add HPS execution stage notification function ARM: socfpga: stratix10: To notify SDM when SPL pass control to U-Boot ARM: socfpga: stratix10: To notify SDM when U-Boot pass control to Linux
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ arch/arm/mach-socfpga/misc_s10.c | 5 +++++ arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 4 files changed, 24 insertions(+)
Can we expect any of this mbox stuff to be ever migrated over to DM and moved into drivers/ instead of constantly adding stuff to mach- socfpga ?
These mailbox stuffs are basically a set of functions shared by SPL, u- boot and Linux (PSCI) which is specific to our platform. Even if we convert this mailbox stuffs to DM and move to drivers/, we still need to duplicate those functions for PSCI which can be called by Linux. We are starting to spend time converting our existing clock manager and etc for S10 platform to DM and will move them to drivers/. But we still need to keep those PSCI stuffs which are specific to our platform in mach-sofcpga.
There was some discussion about the PSCI here: https://www.mail-archive.com/u-boot@lists.denx.de/msg319458.html
On Tue, 2019-05-07 at 16:39 +0200, Marek Vasut wrote:
On 5/7/19 4:08 PM, Ang, Chee Hong wrote:
On Tue, 2019-05-07 at 15:03 +0200, Marek Vasut wrote:
On 5/7/19 7:07 AM, chee.hong.ang@intel.com wrote:
From: "Ang, Chee Hong" chee.hong.ang@intel.com
Notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: (1) First Stage Boot Loader (FSBL) which is U-Boot SPL. (2) Second Stage Boot Loader (SSBL) which is U-Boot. (3) Operating System which is Linux.
Ang, Chee Hong (3): ARM: socfpga: stratix10: Add HPS execution stage notification function ARM: socfpga: stratix10: To notify SDM when SPL pass control to U-Boot ARM: socfpga: stratix10: To notify SDM when U-Boot pass control to Linux
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ arch/arm/mach-socfpga/misc_s10.c | 5 +++++ arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 4 files changed, 24 insertions(+)
Can we expect any of this mbox stuff to be ever migrated over to DM and moved into drivers/ instead of constantly adding stuff to mach- socfpga ?
These mailbox stuffs are basically a set of functions shared by SPL, u- boot and Linux (PSCI) which is specific to our platform. Even if we convert this mailbox stuffs to DM and move to drivers/, we still need to duplicate those functions for PSCI which can be called by Linux. We are starting to spend time converting our existing clock manager and etc for S10 platform to DM and will move them to drivers/. But we still need to keep those PSCI stuffs which are specific to our platform in mach-sofcpga.
There was some discussion about the PSCI here: https://www.mail-archive.com/u-boot@lists.denx.de/msg319458.html
Yes. I am aware of it. Current implementation of PSCI in u-boot is "just work" but not elegant.
Currently, the PSCI sections only exist right before u-boot booting Linux, because those PSCI functions will be used by Linux only. Our current boot flow involve only u-boot (no ATF): 1) SPL (EL3, secure) 2) U-boot (El3. secure) 3) Install PSCI sections (EL3, secure) 4) Linux (EL1, non-secure)
U-boot don't need PSCI call to access secure resources because it's already running in EL3 (secure). Linux will be calling those PSCI functions(EL3) from EL1 to access secure resources.
For those users who typically don't use u-boot's PSCI, their boot flow is as follow:
1) ATF (EL3, secure) 2) Install PSCI sections (also known as secure monitor) (EL3, secure) 3) U-boot (EL2, non-secure) 4) Linux (EL1, non-secure)
With this boot flow, all PSCI stuffs are in ATF. So u-boot and Linux don't have access to secure resources so both of them have to access it via PSCI/SMC calls. The downside is this boot flow involves 2 pieces of software component which are ATF and u-boot.
Back to our u-boot use case, so far our PSCI services don't have dependency on common full driver such as (SPI, I2C and etc). That's the reason we just have sets of functions which can be directly called by u-boot(EL3) and also called by Linux(EL1) through PSCI/SMC.
Those PSCI discussions are some good discussions. You have made your points and I know where you stand in those discussions. Currently, PSCI is just part of u-boot (2nd stage boot loader) and it is detached from u-boot right before booting Linux because u-boot is not expected to stay resident in memory after booting Linux.
Whether PSCI should be part of SPL or TPL to support full drivers in DM and how/when it should be installed need some serious thought and effort to do it right.
participants (3)
-
Ang, Chee Hong -
chee.hong.ang＠intel.com
-
Marek Vasut