[PATCH 1/3] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one then CPLD triggers reset of CPU in few ms.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, calls board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7b168fa091b1..26ea8a525228 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -91,6 +91,16 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); }
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */
If watchdog timer was already set to non-disabled value then it means that watchdog timer was already activated, has already expired and caused CPU reset. If this happened then due to CPLD firmware bug, writing to wd_cfg register has no effect and therefore it is not possible to reactivate watchdog timer again. Also if CPU was reset via watchdog then some peripherals like i2c do not work. Watchdog and i2c start working again after CPU reset via non-watchdog method.
Implement this workaround (reset CPU when it was reset by watchdog) to make watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is connected to CPLD, not to SoC itself.
Signed-off-by: Pali Rohár pali@kernel.org --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 26ea8a525228..24b5ec435e4e 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -86,6 +86,7 @@ struct cpld_data { void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); out_8(&cpld_data->status_led, CPLD_STATUS_LED); @@ -102,6 +103,23 @@ void board_cpld_init(void) * is to try to clear CPLD's system reset register as early as possible. */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) + do_reset(NULL, 0, 0, NULL); }
void board_gpio_init(void)
Do board reset via CPLD's system reset register.
Signed-off-by: Pali Rohár pali@kernel.org --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 24b5ec435e4e..53ff121d3b3d 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,6 +83,12 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00
+void board_reset(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->system_rst, 1); +} + void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
PING?
On Sunday 01 May 2022 14:23:12 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one then CPLD triggers reset of CPU in few ms.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, calls board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7b168fa091b1..26ea8a525228 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -91,6 +91,16 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible.*/}
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
Hello! This change is waiting here since May 01.
On Tuesday 05 July 2022 18:39:19 Pali Rohár wrote:
PING?
On Sunday 01 May 2022 14:23:12 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one then CPLD triggers reset of CPU in few ms.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, calls board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7b168fa091b1..26ea8a525228 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -91,6 +91,16 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible.*/}
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org --- Changes in v2: * Resend patch * Update comment about watchdog --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * CPLD does not trigger reset of CPU for 100ms after the last reset. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible + * and it has to be done in 100ms since the last start of reset. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); }
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */
If watchdog timer was already set to non-disabled value then it means that watchdog timer was already activated, has already expired and caused CPU reset. If this happened then due to CPLD firmware bug, writing to wd_cfg register has no effect and therefore it is not possible to reactivate watchdog timer again. Watchdog starts working again after CPU reset via non-watchdog method.
Implement this workaround (reset CPU when it was reset by watchdog) to make watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is connected to CPLD, not to SoC itself.
Note that reset does not occur immediately after calling do_reset(), but after few ms later as real reset is done by CPLD. So it is normal that function do_reset() returns. Therefore hangs after calling do_reset() to prevent CPU execution of the rest U-Boot code.
Signed-off-by: Pali Rohár pali@kernel.org --- Changes in v2: * Call eieio() before do_reset() to ensure that all IO operations completes * Hang after calling do_reset() as reset does not occur immediately. --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 84e1d65cdb1f..16224752adb1 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -92,6 +92,7 @@ void board_reset(void) void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); out_8(&cpld_data->status_led, CPLD_STATUS_LED); @@ -111,6 +112,26 @@ void board_cpld_init(void) * and it has to be done in 100ms since the last start of reset. */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) { + eieio(); + do_reset(NULL, 0, 0, NULL); + while (1); /* do_reset() does not occur immediately */ + } }
void board_gpio_init(void)
CPLD's system reset register is buggy and requires workaround in U-Boot. So use this kind of board reset only when there is no other reset option.
Introduce a new board_reset_last() callback which is last-stage board-specific reset and implement CPLD's system reset in this new board_reset_last() callback instead of board_reset() callback.
Fixes: 20fb58fc5a1c ("board: freescale: p1_p2_rdb_pc: Implement board_reset()") Signed-off-by: Pali Rohár pali@kernel.org --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 226a26ba320a..c63c17286811 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -44,6 +44,7 @@ __board_reset(void) /* Do nothing */ } void board_reset(void) __attribute__((weak, alias("__board_reset"))); +void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
int checkcpu (void) { @@ -328,6 +329,9 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* Next try asserting HRESET_REQ */ out_be32(&gur->rstcr, 0x2); udelay(100); + + /* Attempt last-stage board-specific reset */ + board_reset_last(); #endif
return 1; diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 16224752adb1..4bcb05bed9b8 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,7 +83,7 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00
-void board_reset(void) +void board_reset_last(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); out_8(&cpld_data->system_rst, 1);
P1/P2 RDB boards have external max6370 watchdog connected to CPLD and this watchdog is not deactivated on board reset. So if it is active during board reset, it can trigger another reset when CPU is booting U-Boot. To prevent possible infinite reset loop caused by external watchdog, turn it off before reset.
Do it via a new board_reset_prepare() callback which is called from do_reset() function before any reset sequence.
Signed-off-by: Pali Rohár pali@kernel.org --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 12 ++++++++++++ 2 files changed, 16 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index c63c17286811..015bd3661c59 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -43,6 +43,7 @@ __board_reset(void) { /* Do nothing */ } +void board_reset_prepare(void) __attribute__((weak, alias("__board_reset"))); void board_reset(void) __attribute__((weak, alias("__board_reset"))); void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
@@ -323,6 +324,9 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #else volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ /* Call board-specific preparation for reset */ + board_reset_prepare(); + /* Attempt board-specific reset */ board_reset();
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4bcb05bed9b8..42409a864854 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,6 +83,18 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00
+void board_reset_prepare(void) +{ + /* + * During reset preparation, turn off external watchdog. + * This ensures that external watchdog does not trigger + * another reset or possible infinite reset loop. + */ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); + in_8(&cpld_data->wd_cfg); /* Read back to sync write */ +} + void board_reset_last(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
PING?
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/}
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
PING???? I have not received any response for these patches. Why you are ignoring me?
You have already merged commit "board: freescale: p1_p2_rdb_pc: Implement board_reset()" from v1 of this patch series https://source.denx.de/u-boot/u-boot/-/commit/20fb58fc5a1c83ee0085b2e9f7ecda... without applying reset workaround commit from v1 (also available in v2) which effectively broke reset support in U-Boot.
Why you are continuing breaking P1/P2 boards?
Patches for this are already waiting on the list.
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/}
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
PING????
On Sunday 21 August 2022 12:30:04 Pali Rohár wrote:
PING???? I have not received any response for these patches. Why you are ignoring me?
You have already merged commit "board: freescale: p1_p2_rdb_pc: Implement board_reset()" from v1 of this patch series https://source.denx.de/u-boot/u-boot/-/commit/20fb58fc5a1c83ee0085b2e9f7ecda... without applying reset workaround commit from v1 (also available in v2) which effectively broke reset support in U-Boot.
Why you are continuing breaking P1/P2 boards?
Patches for this are already waiting on the list.
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/}
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
Hi Pali,
On 8/31/2022 8:04 PM, Pali Rohár wrote:
PING????
Please cc me for freescale ppc boards. The patches not show in my patchwork[freenix].
I will put your patches into CI now.
Thanks, Peng.
On Sunday 21 August 2022 12:30:04 Pali Rohár wrote:
PING???? I have not received any response for these patches. Why you are ignoring me?
You have already merged commit "board: freescale: p1_p2_rdb_pc: Implement board_reset()" from v1 of this patch series https://source.denx.de/u-boot/u-boot/-/commit/20fb58fc5a1c83ee0085b2e9f7ecda... without applying reset workaround commit from v1 (also available in v2) which effectively broke reset support in U-Boot.
Why you are continuing breaking P1/P2 boards? >> Patches for this are already waiting on the list.
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
On 8/31/2022 8:04 PM, Pali Rohár wrote:
PING????
In tag: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/tags/fsl-qoriq-2...
Waiting CI results.
Regards, Peng.
On Sunday 21 August 2022 12:30:04 Pali Rohár wrote:
PING???? I have not received any response for these patches. Why you are ignoring me?
You have already merged commit "board: freescale: p1_p2_rdb_pc: Implement board_reset()" from v1 of this patch series https://source.denx.de/u-boot/u-boot/-/commit/20fb58fc5a1c83ee0085b2e9f7ecda... without applying reset workaround commit from v1 (also available in v2) which effectively broke reset support in U-Boot.
Why you are continuing breaking P1/P2 boards?
Patches for this are already waiting on the list.
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1
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