[U-Boot] [PATCH] powerpc/85xx: Add support for 4th PCI controller on corenet_ds
We configure the controller but dont have virtual address space thus any devices on the 4th controller are not accessible in u-boot.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/corenet_ds/pci.c | 28 +++++++++++++++++++++++++++- include/configs/corenet_ds.h | 8 ++++++++ 2 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 2994e36..e1bca19 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif
+#ifdef CONFIG_PCIE4 +static struct pci_controller pcie4_hose; +#endif + void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info[4]; u32 devdisr; int first_free_busno = 0; int num = 0; @@ -119,6 +123,28 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ #endif + +#ifdef CONFIG_PCIE4 + pcie_configured = is_serdes_configured(PCIE4); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { + set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_4); + set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_4); + SET_STD_PCIE_INFO(pci_info[num], 4); + pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); + printf(" PCIE4 connected to as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie4_hose, first_free_busno); + } else { + printf (" PCIE4: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ +#endif }
void pci_of_setup(void *blob, bd_t *bd) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 6486869..9184eeb 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -399,6 +399,14 @@ #endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
From: Kim Phillips kim.phillips@freescale.com
pumping line-rate traffic though a p4080 rev.2, which is configured to encrypt packets prior to forwarding through an IPsec tunnel, gets this error:
of_platform ffe302000.jq: DECO: desc idx 22: LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the "shared from" DECO's Descriptor required that the SEQ LIODNs be the same and they aren't.
Since high traffic rates cause DECOs to begin to start sharing shared descriptors amongst themselves, and DECOs inherit job queue LIODNs when accessing shared descriptors, and a recently discovered rev.2 h/w erratum requires all sharing job queues in a partition have same liodn assignment, reassign the first job queue's liodn assignment to the rest.
Signed-off-by: Kim Phillips kim.phillips@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index a6cfaa5..df25048 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,16 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif
struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 146, 154), - SET_SEC_JR_LIODN_ENTRY(1, 147, 155), - SET_SEC_JR_LIODN_ENTRY(2, 178, 186), - SET_SEC_JR_LIODN_ENTRY(3, 179, 187), + /* + * We assume currently that all JR are in the same partition + * and as such they need to represent the same LIODN due to + * a 4080 rev.2 h/w requirement that DECOs sharing from themselves + * or from another DECO have the two Non-SEQ LIODN values equal + */ + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */ + SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */ + SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */ + SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */ SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176),
From: Emil Medve Emilian.Medve@freescale.com
* Make the U-Boot update command sequence conditional. Helps prevent accidental erasing if an upload or previous step fails * Make it easier to update other FLASH banks * Enable DDR controller cache line interleaving and bank cs0/cs1 by default
Signed-off-by: Emil Medve Emilian.Medve@Freescale.com Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- include/configs/corenet_ds.h | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d223a4d..6486869 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -607,14 +607,17 @@ #define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "ubootaddr=" MK_STR(TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \
Manual was updated to add a new register for disabling CDQ speculation.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/include/asm/immap_85xx.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3dd2b7f..30c64eb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1589,7 +1589,9 @@ typedef struct cpc_corenet { u32 cpcerreaddr; /* error extended address */ u32 cpcerraddr; /* error address */ u32 cpcerrctl; /* error control */ - u32 res9[105]; /* pad out to 4k */ + u32 res9[41]; /* pad out to 4k */ + u32 cpchdbcr0; /* hardware debug control register 0 */ + u32 res10[63]; /* pad out to 4k */ } cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */ @@ -1616,6 +1618,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */
On Sep 30, 2010, at 9:11 AM, Kumar Gala wrote:
Manual was updated to add a new register for disabling CDQ speculation.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/include/asm/immap_85xx.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
applied to 85xx
- k
On Sep 30, 2010, at 9:11 AM, Kumar Gala wrote:
From: Emil Medve Emilian.Medve@freescale.com
- Make the U-Boot update command sequence conditional. Helps prevent
accidental erasing if an upload or previous step fails
- Make it easier to update other FLASH banks
- Enable DDR controller cache line interleaving and bank cs0/cs1 by default
Signed-off-by: Emil Medve Emilian.Medve@Freescale.com Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
include/configs/corenet_ds.h | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-)
applied to 85xx
- k
On Sep 30, 2010, at 9:11 AM, Kumar Gala wrote:
From: Kim Phillips kim.phillips@freescale.com
pumping line-rate traffic though a p4080 rev.2, which is configured to encrypt packets prior to forwarding through an IPsec tunnel, gets this error:
of_platform ffe302000.jq: DECO: desc idx 22: LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the "shared from" DECO's Descriptor required that the SEQ LIODNs be the same and they aren't.
Since high traffic rates cause DECOs to begin to start sharing shared descriptors amongst themselves, and DECOs inherit job queue LIODNs when accessing shared descriptors, and a recently discovered rev.2 h/w erratum requires all sharing job queues in a partition have same liodn assignment, reassign the first job queue's liodn assignment to the rest.
Signed-off-by: Kim Phillips kim.phillips@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/p4080_ids.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-)
applied to 85xx
- k
On Sep 30, 2010, at 9:11 AM, Kumar Gala wrote:
We configure the controller but dont have virtual address space thus any devices on the 4th controller are not accessible in u-boot.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/corenet_ds/pci.c | 28 +++++++++++++++++++++++++++- include/configs/corenet_ds.h | 8 ++++++++ 2 files changed, 35 insertions(+), 1 deletions(-)
applied to 85xx
- k
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Kumar Gala