[U-Boot] [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT
From: Stuart Yoder stuart.yoder@nxp.com
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID.
This patch implements infrastructure to enable LUT initialization: -define registers offsets -add an index to 'struct ls_pcie' to track next available slot in LUT -add function to allocate the next available entry index -add function to program a LUT entry
Signed-off-by: Stuart Yoder stuart.yoder@nxp.com --- -v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +++ drivers/pci/pcie_layerscape.c | 30 ++++++++++++++++++++ 2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..d04e336 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -86,6 +86,10 @@ #define PCIE_LUT_BASE 0x80000 #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_ENABLE (1 << 31) +#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index bb29222..5cc6855 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -93,6 +93,7 @@ struct ls_pcie { void __iomem *dbi; void __iomem *va_cfg0; void __iomem *va_cfg1; + int next_lut_index; struct pci_controller hose; };
@@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) } }
+#ifdef CONFIG_FSL_LSCH3 +/* + * Return next available LUT index. + */ +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) +{ + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) + return pcie->next_lut_index++; + else + return -1; /* LUT is full */ +} + +/* + * Program a single LUT entry + */ +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, + u32 streamid) +{ + void __iomem *lut; + + lut = pcie->dbi + PCIE_LUT_BASE; + + /* leave mask as all zeroes, want to match all bits */ + writel((devid << 16), lut + PCIE_LUT_UDR(index)); + writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); +} +#endif + int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) { struct ls_pcie *pcie; @@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) pcie->va_cfg1 = map_physmem(info->cfg1_phys, info->cfg1_size, MAP_NOCACHE); + pcie->next_lut_index = 0;
/* outbound memory */ pci_set_region(&hose->regions[0],
On 03/09/2016 08:24 AM, Stuart Yoder wrote:
From: Stuart Yoder stuart.yoder@nxp.com
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID.
This patch implements infrastructure to enable LUT initialization: -define registers offsets -add an index to 'struct ls_pcie' to track next available slot in LUT -add function to allocate the next available entry index -add function to program a LUT entry
Signed-off-by: Stuart Yoder stuart.yoder@nxp.com
-v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +++ drivers/pci/pcie_layerscape.c | 30 ++++++++++++++++++++ 2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..d04e336 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -86,6 +86,10 @@ #define PCIE_LUT_BASE 0x80000 #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_ENABLE (1 << 31) +#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index bb29222..5cc6855 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -93,6 +93,7 @@ struct ls_pcie { void __iomem *dbi; void __iomem *va_cfg0; void __iomem *va_cfg1;
- int next_lut_index; struct pci_controller hose;
};
@@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) } }
+#ifdef CONFIG_FSL_LSCH3 +/*
- Return next available LUT index.
- */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie) +{
- if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
return pcie->next_lut_index++;- else
return -1; /* LUT is full */+}
+/*
- Program a single LUT entry
- */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
u32 streamid)+{
- void __iomem *lut;
- lut = pcie->dbi + PCIE_LUT_BASE;
- /* leave mask as all zeroes, want to match all bits */
- writel((devid << 16), lut + PCIE_LUT_UDR(index));
- writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+} +#endif
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) { struct ls_pcie *pcie; @@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) pcie->va_cfg1 = map_physmem(info->cfg1_phys, info->cfg1_size, MAP_NOCACHE);
pcie->next_lut_index = 0;
/* outbound memory */ pci_set_region(&hose->regions[0],
Stuart,
This patch breaks git bisect. Please rearrange your changes. warning: ‘ls_pcie_next_lut_index’ defined but not used [-Wunused-function] static int ls_pcie_next_lut_index(struct ls_pcie *pcie) ^ warning: ‘ls_pcie_lut_set_mapping’ defined but not used [-Wunused-function] static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, ^
York
-----Original Message----- From: york sun Sent: Wednesday, March 09, 2016 12:01 PM To: Stuart Yoder stuart.yoder@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Yang-Leo Li leoyang.li@nxp.com Subject: Re: [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT
On 03/09/2016 08:24 AM, Stuart Yoder wrote:
From: Stuart Yoder stuart.yoder@nxp.com
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID.
This patch implements infrastructure to enable LUT initialization: -define registers offsets -add an index to 'struct ls_pcie' to track next available slot in LUT -add function to allocate the next available entry index -add function to program a LUT entry
Signed-off-by: Stuart Yoder stuart.yoder@nxp.com
-v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +++ drivers/pci/pcie_layerscape.c | 30 ++++++++++++++++++++ 2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..d04e336 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -86,6 +86,10 @@ #define PCIE_LUT_BASE 0x80000 #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_ENABLE (1 << 31) +#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index bb29222..5cc6855 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -93,6 +93,7 @@ struct ls_pcie { void __iomem *dbi; void __iomem *va_cfg0; void __iomem *va_cfg1;
- int next_lut_index; struct pci_controller hose;
};
@@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct
ls_pcie_info *info)
} }
+#ifdef CONFIG_FSL_LSCH3 +/*
- Return next available LUT index.
- */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie) +{
- if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
return pcie->next_lut_index++;- else
return -1; /* LUT is full */+}
+/*
- Program a single LUT entry
- */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
u32 streamid)+{
- void __iomem *lut;
- lut = pcie->dbi + PCIE_LUT_BASE;
- /* leave mask as all zeroes, want to match all bits */
- writel((devid << 16), lut + PCIE_LUT_UDR(index));
- writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+} +#endif
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) { struct ls_pcie *pcie; @@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct
ls_pcie_info *info)
pcie->va_cfg1 = map_physmem(info->cfg1_phys, info->cfg1_size, MAP_NOCACHE);
pcie->next_lut_index = 0;
/* outbound memory */ pci_set_region(&hose->regions[0],
Stuart,
This patch breaks git bisect. Please rearrange your changes. warning: 'ls_pcie_next_lut_index' defined but not used [-Wunused-function] static int ls_pcie_next_lut_index(struct ls_pcie *pcie) ^ warning: 'ls_pcie_lut_set_mapping' defined but not used [-Wunused-function] static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, ^
Ugh...will fix.
Stuart
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york sun