Add clocks support for the video subsystem.

Signed-off-by: Michael Trimarchi michael@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 457acb8a40..baac79dd29 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -23,6 +23,7 @@ static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };

static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -30,6 +31,10 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };

+static const char *imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext4", }; + static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };

@@ -139,6 +144,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MN_VIDEO_PLL1_REF_SEL, + imx_clk_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));

clk_dm(IMX8MN_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", @@ -155,6 +163,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll)); + clk_dm(IMX8MN_VIDEO_PLL1, + imx_clk_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll));

/* PLL bypass out */ clk_dm(IMX8MN_DRAM_PLL_BYPASS, @@ -183,6 +194,12 @@ static int imx8mn_clk_probe(struct udevice *dev) ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));

+ clk_dm(IMX8MN_VIDEO_PLL1_BYPASS, + imx_clk_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT)); + /* PLL out gate */ clk_dm(IMX8MN_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", @@ -199,6 +216,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); + clk_dm(IMX8MN_VIDEO_PLL1_OUT, + imx_clk_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13));

/* SYS PLL fixed output */ clk_dm(IMX8MN_SYS_PLL1_40M, @@ -275,6 +295,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80)); + + clk_dm(IMX8MN_CLK_DISP_PIXEL, + imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500)); clk_dm(IMX8MN_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00)); clk_dm(IMX8MN_CLK_I2C2,