On Tuesday, April 15, 2003 2:00 AM, Wolfgang Denk [SMTP:wd@denx.de] wrote:

In message 01C302F0.40E40DC0.robdlg@att.net you wrote:

...

...in Table 11-11 of the _MPC8245 Integrated Processor User's Manual_, there is the statement "The timers operate at 1/8 the speed of the SDRAM_CLK signal."

Should the divisor in get_tbclk( ) be 8L for the MPC8245?

You can easily try it out: how long does "sleep 10" sleep on your system?

Yes--thanks. I tested "sleep 10" on both our '8245 reference board (an Artis Microsystems SBC-A3000) and our own custom '8241 board. In both cases, the sleep interval was correct.

Thus, the divisor in get_tbclk( ) appears to be fine. I will disregard Table 11-11, as it does not seem to apply here.