[U-Boot] [PATCH 0/6] dm: pci: add Freescale PowerPC PCIe driver
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add PCIe DM driver for Freescale PowerPC PCIe controllers.
Hou Zhiqiang (6): powerpc: mpc85xx: Update the condition to compile PCI routines powerpc: T208xQDS: Compile the legacy PCIe routines conditionally t2080: dts: Added PCIe DT nodes dm: pci: add Freescale PowerPC PCIe driver powerpc: T208xQDS: Disable legacy PCIe driver configs: T2080QDS: Enable PCIe driver
arch/powerpc/cpu/mpc85xx/pci.c | 2 +- arch/powerpc/dts/t2080.dtsi | 48 +++ board/freescale/t208xqds/pci.c | 2 + configs/T2080QDS_defconfig | 5 + drivers/pci/Kconfig | 7 + drivers/pci/Makefile | 1 + drivers/pci/pcie_fsl.c | 612 +++++++++++++++++++++++++++++++++ drivers/pci/pcie_fsl.h | 60 ++++ drivers/pci/pcie_fsl_fixup.c | 40 +++ include/configs/T208xQDS.h | 18 - 10 files changed, 776 insertions(+), 19 deletions(-) create mode 100644 drivers/pci/pcie_fsl.c create mode 100644 drivers/pci/pcie_fsl.h create mode 100644 drivers/pci/pcie_fsl_fixup.c
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- arch/powerpc/cpu/mpc85xx/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c index 90ccc3427c..1d0213a513 100644 --- a/arch/powerpc/cpu/mpc85xx/pci.c +++ b/arch/powerpc/cpu/mpc85xx/pci.c @@ -12,7 +12,7 @@ #include <asm/cpm_85xx.h> #include <pci.h>
-#if !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
#ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
arch/powerpc/cpu/mpc85xx/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- board/freescale/t208xqds/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c index c761aea0ac..ef26f14c46 100644 --- a/board/freescale/t208xqds/pci.c +++ b/board/freescale/t208xqds/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
board/freescale/t208xqds/pci.c | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T2080 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- arch/powerpc/dts/t2080.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index db65ea5725..89b2c618ae 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -59,4 +59,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; };
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T2080 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
arch/powerpc/dts/t2080.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add PCIe DM driver for Freescale PowerPC PCIe controllers.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- drivers/pci/Kconfig | 7 + drivers/pci/Makefile | 1 + drivers/pci/pcie_fsl.c | 612 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie_fsl.h | 60 ++++ drivers/pci/pcie_fsl_fixup.c | 40 +++ 5 files changed, 720 insertions(+) create mode 100644 drivers/pci/pcie_fsl.c create mode 100644 drivers/pci/pcie_fsl.h create mode 100644 drivers/pci/pcie_fsl_fixup.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 1521885bde..36674db6c1 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,6 +60,13 @@ config PCIE_DW_MVEBU Armada-8K SoCs. The PCIe controller on Armada-8K is based on DesignWare hardware.
+config PCIE_FSL + bool "FSL PowerPC PCIe support" + depends on DM_PCI + help + Say Y here if you want to enable PCIe controller support on + FSL PowerPC series SoCs. + config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 4923641895..d984848266 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o +obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c new file mode 100644 index 0000000000..95973fd8d9 --- /dev/null +++ b/drivers/pci/pcie_fsl.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com + */ + +#include <common.h> +#include <malloc.h> +#include <dm.h> +#include <pci.h> +#include <clk.h> +#include <mapmem.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include "pcie_fsl.h" + +LIST_HEAD(fsl_pcie_list); + +static inline int fsl_pcie_link_up(struct fsl_pcie *pcie); + +static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf) +{ + struct udevice *bus = pcie->bus; + + if (!pcie->enabled) + return -ENXIO; + + if (PCI_BUS(bdf) < bus->seq) + return -EINVAL; + + if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode)) + return -EINVAL; + + if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0)) + return -EINVAL; + + if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0)) + return -EINVAL; + + return 0; +} + +static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + if (fsl_pcie_addr_valid(pcie, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + *valuep = in_8((u8 *)®s->cfg_data + (offset & 3)); + break; + case PCI_SIZE_16: + *valuep = in_le16((u16 *)((u8 *)®s->cfg_data + + (offset & 2))); + break; + case PCI_SIZE_32: + *valuep = in_le32(®s->cfg_data); + break; + } + + return 0; +} + +static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + u8 val_8; + u16 val_16; + u32 val_32; + + if (fsl_pcie_addr_valid(pcie, bdf)) + return 0; + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + val_8 = value; + out_8((u8 *)®s->cfg_data + (offset & 3), val_8); + break; + case PCI_SIZE_16: + val_16 = value; + out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16); + break; + case PCI_SIZE_32: + val_32 = value; + out_le32(®s->cfg_data, val_32); + break; + } + + return 0; +} + +static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset, + ulong *valuep, enum pci_size_t size) +{ + int ret; + struct udevice *bus = pcie->bus; + + ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, valuep, size); + + return ret; +} + +static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset, + ulong value, enum pci_size_t size) +{ + struct udevice *bus = pcie->bus; + + return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, value, size); +} + +static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset, + u8 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset, + u16 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset, + u32 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset, + u8 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8); +} + +static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset, + u16 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16); +} + +static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset, + u32 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32); +} + +static inline int fsl_pcie_link_up(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u16 ltssm; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + ltssm = (in_be32(®s->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + return ltssm == LTSSM_L0_REV3; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + + return ltssm == LTSSM_L0; +} + +static bool fsl_pcie_is_agent(struct fsl_pcie *pcie) +{ + u8 header_type; + + fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type); + + return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; +} + +static int fsl_pcie_setup_law(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (mem) + set_next_law(mem->phys_start, + law_size_bits(mem->size), + pcie->law_trgt_if); + + if (io) + set_next_law(io->phys_start, + law_size_bits(io->size), + pcie->law_trgt_if); + + return 0; +} + +static void fsl_pcie_config_ready(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY); + return; + } + + fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1); +} + +static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx, + int type, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pot_t *po = ®s->pot[idx]; + u32 war, sz; + + if (idx < 0) + return -EINVAL; + + out_be32(&po->powbar, phys >> 12); + out_be32(&po->potar, bus_addr >> 12); +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&po->potear, bus_addr >> 44); +#else + out_be32(&po->potear, 0); +#endif + + sz = (__ilog2_u64((u64)size) - 1); + war = POWAR_EN | sz; + + if (type == PCI_REGION_IO) + war |= POWAR_IO_READ | POWAR_IO_WRITE; + else + war |= POWAR_MEM_READ | POWAR_MEM_WRITE; + + out_be32(&po->powar, war); + + return 0; +} + +static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, + bool pf, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pit_t *pi = ®s->pit[idx]; + u32 sz = (__ilog2_u64(size) - 1); +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + u32 flag = 0; +#else + u32 flag = PIWAR_LOCAL; +#endif + + if (idx < 0) + return -EINVAL; + + out_be32(&pi->pitar, phys >> 12); + out_be32(&pi->piwbar, bus_addr >> 12); + +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&pi->piwbear, bus_addr >> 44); +#else + out_be32(&pi->piwbear, 0); +#endif + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; + if (pf) + flag |= PIWAR_PF; + out_be32(&pi->piwar, flag | sz); + + return 0; +} + +static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + int idx = 1; /* skip 0 */ + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (io) + /* ATU : OUTBOUND : IO */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_IO, + io->phys_start, + io->bus_start, + io->size); + + if (mem) + /* ATU : OUTBOUND : MEM */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_MEM, + mem->phys_start, + mem->bus_start, + mem->size); + return 0; +} + +static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) +{ + phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + u64 sz = min((u64)gd->ram_size, (1ull << 32)); + pci_size_t pci_sz; + int idx; + + if (pcie->block_rev >= PEX_IP_BLK_REV_2_2) + idx = 2; + else + idx = 3; + + pci_sz = 1ull << __ilog2_u64(sz); + + dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)bus_start, (u64)phys_start, (u64)sz); + + /* if we aren't an exact power of two match, pci_sz is smaller + * round it up to the next power of two. We report the actual + * size to pci region tracking. + */ + if (pci_sz != sz) + sz = 2ull << __ilog2_u64(sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_BUS, sz); +#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) + /* + * On 64-bit capable systems, set up a mapping for all of DRAM + * in high pci address space. + */ + pci_sz = 1ull << __ilog2_u64(gd->ram_size); + /* round up to the next largest power of two */ + if (gd->ram_size > pci_sz) + pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); + + dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)CONFIG_SYS_PCI64_MEMORY_BUS, + (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); +#endif + + return 0; +} + +static int fsl_pcie_init_atmu(struct fsl_pcie *pcie) +{ + fsl_pcie_setup_outbound_wins(pcie); + fsl_pcie_setup_inbound_wins(pcie); + + return 0; +} + +static int fsl_pcie_init_port(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val_32; + u16 val_16; + + fsl_pcie_init_atmu(pcie); + +#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); +#endif + +#ifdef CONFIG_FSL_PCIE_RESET + u16 ltssm; + int i; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(100); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + if (!fsl_pcie_link_up(pcie)) { + serdes_corenet_t *srds_regs; + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + val_32 = in_be32(&srds_regs->srdspccr0); + + if ((val_32 >> 28) == 3) { + int i; + + out_be32(&srds_regs->srdspccr0, 2 << 28); + setbits_be32(®s->pdb_stat, 0x08000000); + in_be32(®s->pdb_stat); + udelay(100); + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#endif + + /* + * Enable All Error Interrupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ + out_be32(®s->peer, ~0x20140); + + /* set URR, FER, NFER (but not CER) */ + fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32); + val_32 |= 0xf000e; + fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32); + + /* Clear all error indications */ + out_be32(®s->pme_msg_det, 0xffffffff); + out_be32(®s->pme_msg_int_en, 0xffffffff); + out_be32(®s->pedr, 0xffffffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff); + + return 0; +} + +static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + val &= 0xff; + val |= PCI_CLASS_BRIDGE_PCI << 16; + fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + return 0; +} + +static int fsl_pcie_init_rc(struct fsl_pcie *pcie) +{ + return fsl_pcie_fixup_classcode(pcie); +} + +static int fsl_pcie_init_ep(struct fsl_pcie *pcie) +{ + fsl_pcie_config_ready(pcie); + + return 0; +} + +static int fsl_pcie_probe(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + ccsr_fsl_pci_t *regs = pcie->regs; + u16 val_16; + + pcie->bus = dev; + pcie->block_rev = in_be32(®s->block_rev1); + + list_add(&pcie->list, &fsl_pcie_list); + pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx); + if (!pcie->enabled) { + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + return 0; + } + + fsl_pcie_setup_law(pcie); + + pcie->mode = fsl_pcie_is_agent(pcie); + + fsl_pcie_init_port(pcie); + + printf("PCIe%d: %s ", pcie->idx, dev->name); + + if (pcie->mode) { + printf("Endpoint"); + fsl_pcie_init_ep(pcie); + } else { + printf("Root Complex"); + fsl_pcie_init_rc(pcie); + } + + if (!fsl_pcie_link_up(pcie)) { + printf(": %s\n", pcie->mode ? "undetermined link" : "no link"); + return 0; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16); + printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf)); + + return 0; +} + +static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + int ret; + + pcie->regs = dev_remap_addr(dev); + if (!pcie->regs) { + pr_err(""reg" resource not found\n"); + return -EINVAL; + } + + ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if); + if (ret < 0) { + pr_err(""law_trgt_if" not found\n"); + return ret; + } + + pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + + return 0; +} + +static const struct dm_pci_ops fsl_pcie_ops = { + .read_config = fsl_pcie_read_config, + .write_config = fsl_pcie_write_config, +}; + +static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t2080" }, + { } +}; + +U_BOOT_DRIVER(fsl_pcie) = { + .name = "fsl_pcie", + .id = UCLASS_PCI, + .of_match = fsl_pcie_ids, + .ops = &fsl_pcie_ops, + .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata, + .probe = fsl_pcie_probe, + .priv_auto_alloc_size = sizeof(struct fsl_pcie), +}; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h new file mode 100644 index 0000000000..ed089bfb71 --- /dev/null +++ b/drivers/pci/pcie_fsl.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com + */ + +#ifndef _PCIE_FSL_H_ +#define _PCIE_FSL_H_ +#include <pci.h> +#include <dm.h> +#include <asm/fsl_pci.h> + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#define FSL_PCIE_CAP_ID 0x70 +#else +#define FSL_PCIE_CAP_ID 0x4c +#endif +/* PCIe Device Control Register */ +#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08) +/* PCIe Device Status Register */ +#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a) +/* PCIe Link Control Register */ +#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10) +/* PCIe Link Status Register */ +#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) + +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#endif + +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) +#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#endif + +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define LTSSM_L0_REV3 0x11 +#define LTSSM_L0 0x16 + +struct fsl_pcie { + int idx; + struct udevice *bus; + void __iomem *regs; + u32 law_trgt_if; + u32 block_rev; + bool mode; + bool enabled; + struct list_head list; +}; + +extern struct list_head fsl_pcie_list; + +#endif /* _PCIE_FSL_H_ */ diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c new file mode 100644 index 0000000000..c3cd1dc09a --- /dev/null +++ b/drivers/pci/pcie_fsl_fixup.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com + */ + +#include <common.h> +#ifdef CONFIG_OF_BOARD_SETUP +#include <linux/libfdt.h> +#include <fdt_support.h> +#include "pcie_fsl.h" + +static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie) +{ + struct pci_controller *hose = dev_get_uclass_priv(pcie->bus); + int off; + + off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, + dev_read_addr(pcie->bus)); + if (off < 0) + return; + + if (!hose || !pcie->enabled) + fdt_del_node(blob, off); + else + fdt_pci_dma_ranges(blob, off, hose); +} + +/* Fixup Kernel DT for PCIe */ +void pci_of_setup(void *blob, bd_t *bd) +{ + struct fsl_pcie *pcie; + + list_for_each_entry(pcie, &fsl_pcie_list, list) + ft_fsl_pcie_setup(blob, pcie); +} +#endif
Hi,
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add PCIe DM driver for Freescale PowerPC PCIe controllers.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
drivers/pci/Kconfig | 7 + drivers/pci/Makefile | 1 + drivers/pci/pcie_fsl.c | 612 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie_fsl.h | 60 ++++ drivers/pci/pcie_fsl_fixup.c | 40 +++ 5 files changed, 720 insertions(+) create mode 100644 drivers/pci/pcie_fsl.c create mode 100644 drivers/pci/pcie_fsl.h create mode 100644 drivers/pci/pcie_fsl_fixup.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 1521885bde..36674db6c1 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,6 +60,13 @@ config PCIE_DW_MVEBU Armada-8K SoCs. The PCIe controller on Armada-8K is based on DesignWare hardware.
+config PCIE_FSL
bool "FSL PowerPC PCIe support"depends on DM_PCIhelpSay Y here if you want to enable PCIe controller support onFSL PowerPC series SoCs.
Please add a bit more detail here. Which SoCs are supported? Which hardware features are supported, and which not supported?
config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 4923641895..d984848266 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o +obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c new file mode 100644 index 0000000000..95973fd8d9 --- /dev/null +++ b/drivers/pci/pcie_fsl.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 NXP
- Copyright 2007-2012 Freescale Semiconductor, Inc.
- PCIe DM U-Boot driver for Freescale PowerPC SoCs
- Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com
- */
+#include <common.h> +#include <malloc.h> +#include <dm.h> +#include <pci.h> +#include <clk.h> +#include <mapmem.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include "pcie_fsl.h"
Please sort these properly:
common clk dm malloc mapmem pci asm/fsl asm/io pcie_fsl
+LIST_HEAD(fsl_pcie_list);
+static inline int fsl_pcie_link_up(struct fsl_pcie *pcie);
Why is this inline? Do you need the forward declaration?
+static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf) +{
struct udevice *bus = pcie->bus;if (!pcie->enabled)return -ENXIO;if (PCI_BUS(bdf) < bus->seq)return -EINVAL;if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))return -EINVAL;if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))return -EINVAL;if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))return -EINVAL;return 0;+}
+static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct fsl_pcie *pcie = dev_get_priv(bus);ccsr_fsl_pci_t *regs = pcie->regs;u32 val;if (fsl_pcie_addr_valid(pcie, bdf)) {*valuep = pci_get_ff(size);return 0;}bdf = bdf - PCI_BDF(bus->seq, 0, 0);val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;out_be32(®s->cfg_addr, val);sync();switch (size) {case PCI_SIZE_8:*valuep = in_8((u8 *)®s->cfg_data + (offset & 3));break;case PCI_SIZE_16:*valuep = in_le16((u16 *)((u8 *)®s->cfg_data +(offset & 2)));break;case PCI_SIZE_32:*valuep = in_le32(®s->cfg_data);break;}return 0;+}
+static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,enum pci_size_t size)+{
struct fsl_pcie *pcie = dev_get_priv(bus);ccsr_fsl_pci_t *regs = pcie->regs;u32 val;u8 val_8;u16 val_16;u32 val_32;if (fsl_pcie_addr_valid(pcie, bdf))return 0;bdf = bdf - PCI_BDF(bus->seq, 0, 0);val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;out_be32(®s->cfg_addr, val);sync();switch (size) {case PCI_SIZE_8:val_8 = value;out_8((u8 *)®s->cfg_data + (offset & 3), val_8);break;case PCI_SIZE_16:val_16 = value;out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);break;case PCI_SIZE_32:val_32 = value;out_le32(®s->cfg_data, val_32);break;}return 0;+}
+static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
ulong *valuep, enum pci_size_t size)+{
int ret;struct udevice *bus = pcie->bus;ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),offset, valuep, size);return ret;+}
+static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
ulong value, enum pci_size_t size)+{
struct udevice *bus = pcie->bus;return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),offset, value, size);+}
+static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
u8 *valuep)+{
ulong val;int ret;ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);*valuep = val;return ret;+}
+static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
u16 *valuep)+{
ulong val;int ret;ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);*valuep = val;return ret;+}
+static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
u32 *valuep)+{
ulong val;int ret;ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);*valuep = val;return ret;+}
+static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
u8 value)+{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);+}
+static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
u16 value)+{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);+}
+static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
u32 value)+{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);+}
+static inline int fsl_pcie_link_up(struct fsl_pcie *pcie) +{
ccsr_fsl_pci_t *regs = pcie->regs;u16 ltssm;if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {ltssm = (in_be32(®s->pex_csr0)& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;return ltssm == LTSSM_L0_REV3;}fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);return ltssm == LTSSM_L0;+}
+static bool fsl_pcie_is_agent(struct fsl_pcie *pcie) +{
u8 header_type;fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;+}
+static int fsl_pcie_setup_law(struct fsl_pcie *pcie) +{
struct pci_region *io, *mem, *pref;pci_get_regions(pcie->bus, &io, &mem, &pref);if (mem)set_next_law(mem->phys_start,law_size_bits(mem->size),pcie->law_trgt_if);if (io)set_next_law(io->phys_start,law_size_bits(io->size),pcie->law_trgt_if);return 0;+}
+static void fsl_pcie_config_ready(struct fsl_pcie *pcie) +{
ccsr_fsl_pci_t *regs = pcie->regs;if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);return;}fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);+}
+static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
int type, u64 phys, u64 bus_addr,pci_size_t size)+{
ccsr_fsl_pci_t *regs = pcie->regs;pot_t *po = ®s->pot[idx];u32 war, sz;if (idx < 0)return -EINVAL;out_be32(&po->powbar, phys >> 12);out_be32(&po->potar, bus_addr >> 12);+#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&po->potear, bus_addr >> 44);+#else
out_be32(&po->potear, 0);+#endif
sz = (__ilog2_u64((u64)size) - 1);war = POWAR_EN | sz;if (type == PCI_REGION_IO)war |= POWAR_IO_READ | POWAR_IO_WRITE;elsewar |= POWAR_MEM_READ | POWAR_MEM_WRITE;out_be32(&po->powar, war);return 0;+}
+static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
bool pf, u64 phys, u64 bus_addr,pci_size_t size)+{
ccsr_fsl_pci_t *regs = pcie->regs;pit_t *pi = ®s->pit[idx];u32 sz = (__ilog2_u64(size) - 1);+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
This should be handled by the compatible string, not an #ifdef
Please fix this globally.
[...]
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h new file mode 100644 index 0000000000..ed089bfb71 --- /dev/null +++ b/drivers/pci/pcie_fsl.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- Copyright 2007-2012 Freescale Semiconductor, Inc.
- PCIe DM U-Boot driver for Freescale PowerPC SoCs
- Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com
- */
+#ifndef _PCIE_FSL_H_ +#define _PCIE_FSL_H_ +#include <pci.h> +#include <dm.h> +#include <asm/fsl_pci.h>
Please remove these includes. The C file has them alreadyy.
+#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#define FSL_PCIE_CAP_ID 0x70 +#else +#define FSL_PCIE_CAP_ID 0x4c +#endif +/* PCIe Device Control Register */ +#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08) +/* PCIe Device Status Register */ +#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a) +/* PCIe Link Control Register */ +#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10) +/* PCIe Link Status Register */ +#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#endif
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#endif
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) +#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#endif
+#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define LTSSM_L0_REV3 0x11 +#define LTSSM_L0 0x16
+struct fsl_pcie {
Need struct/member docs.
int idx;struct udevice *bus;void __iomem *regs;u32 law_trgt_if;u32 block_rev;bool mode;bool enabled;struct list_head list;+};
+extern struct list_head fsl_pcie_list;
+#endif /* _PCIE_FSL_H_ */ diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c new file mode 100644 index 0000000000..c3cd1dc09a --- /dev/null +++ b/drivers/pci/pcie_fsl_fixup.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 NXP
- Copyright 2007-2012 Freescale Semiconductor, Inc.
- PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs
- Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com
- */
+#include <common.h> +#ifdef CONFIG_OF_BOARD_SETUP
Shouldn't need this.
+#include <linux/libfdt.h> +#include <fdt_support.h> +#include "pcie_fsl.h"
+static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie) +{
struct pci_controller *hose = dev_get_uclass_priv(pcie->bus);int off;off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT,dev_read_addr(pcie->bus));if (off < 0)return;
Should return an error?
if (!hose || !pcie->enabled)fdt_del_node(blob, off);elsefdt_pci_dma_ranges(blob, off, hose);+}
+/* Fixup Kernel DT for PCIe */ +void pci_of_setup(void *blob, bd_t *bd) +{
struct fsl_pcie *pcie;list_for_each_entry(pcie, &fsl_pcie_list, list)ft_fsl_pcie_setup(blob, pcie);+}
+#endif
2.17.1
Regards, Simon
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and remove unused PCIe macros.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- include/configs/T208xQDS.h | 18 ------------------ 1 file changed, 18 deletions(-)
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 9ca384cc0c..c414081ca5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -508,49 +508,31 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and remove unused PCIe macros.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
include/configs/T208xQDS.h | 18 ------------------ 1 file changed, 18 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- configs/T2080QDS_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 79cf4424b4..b7fdd3ffb4 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -28,6 +29,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9 CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_IS_IN_FLASH=y +CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -43,6 +45,9 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y
On Fri, 3 May 2019 at 20:03, Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Needs a commit message.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
configs/T2080QDS_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
participants (2)
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Simon Glass -
Z.q. Hou