[PATCH 1/2] arm64: dts: rockchip: add (but disabled) SFC node for Radxa ROCK 5A
This commit adds SFC node for Radxa ROCK 5A.
since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot be enabled both nodes at the same time. so status = "okay" is omitted here.
you may be able to enable sfc (and disable sdhci) by fdt overlay.
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
Signed-off-by: FUKAUMI Naoki naoki@radxa.com Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: 00224650dd45e166ea6eb1593f5f064583963ccf ]
(cherry picked from commit fde218de3133705f3f56dc8eb26baa878f0e0dc9) --- dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 3b9a349362d..2e2f7f0e769 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -377,6 +377,19 @@ status = "okay"; };
+&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>;
on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins (i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts specifically for SPI NOR flash is required.
Signed-off-by: FUKAUMI Naoki naoki@radxa.com --- arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 24 ++++++ arch/arm/dts/rk3588s-rock-5a-spi.dts | 4 + board/radxa/rock5a-rk3588s/MAINTAINERS | 5 +- configs/rock5a-spi-rk3588s_defconfig | 83 ++++++++++++++++++++ 4 files changed, 113 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts create mode 100644 configs/rock5a-spi-rk3588s_defconfig
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi new file mode 100644 index 00000000000..5cd131d3cb1 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include "rk3588s-u-boot.dtsi" + +&fspim0_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + status = "disabled"; +}; + +&sfc { + status = "okay"; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts b/arch/arm/dts/rk3588s-rock-5a-spi.dts new file mode 100644 index 00000000000..780e90d041b --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3588s-rock-5a.dts" diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index a569efa74e3..06ebc9829f4 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -4,6 +4,5 @@ R: Jonas Karlman jonas@kwiboo.se S: Maintained F: board/radxa/rock5a-rk3588s F: include/configs/rock5a-rk3588s.h -F: configs/rock5a-rk3588s_defconfig -F: arch/arm/dts/rk3588s-rock-5a.dts -F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +F: configs/rock5a* +F: arch/arm/dts/rk3588s-rock-5a* diff --git a/configs/rock5a-spi-rk3588s_defconfig b/configs/rock5a-spi-rk3588s_defconfig new file mode 100644 index 00000000000..297278c7a06 --- /dev/null +++ b/configs/rock5a-spi-rk3588s_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROCK5A_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y
participants (1)
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FUKAUMI Naoki