Hi Simon,

Hi Akshay,

On 21 May 2014 23:33, Akshay Saraswat akshay.s@samsung.com wrote:

...

This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, hence, we need to disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin.

Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com

Acked-by: Simon Glass sjg@chromium.org

Does this mean that the read_leveling_enable structure member is not used?

Yes, we don't use read_leveling_enable structure member anymore but I think it's good to keep it because if we update this file in future for next version of SoCs, we may need it.

Regards, Simon

Regards, Akshay Saraswat