[PATCH 0/3] qcom: add pinctrl driver for SM8550 and SM8650
Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.
This driver only handles the gpio and qup debug uart pinmux, and makes sure the pinconf applies on SDC2 pins.
Finally enable both drivers in the Qualcomm defconfig
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- Neil Armstrong (3): pinctrl: qcom: Add SM8550 pinctrl driver pinctrl: qcom: Add SM8650 pinctrl driver qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
configs/qcom_defconfig | 2 + drivers/pinctrl/qcom/Kconfig | 14 +++++++ drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ 5 files changed, 168 insertions(+) --- base-commit: cec1c47bdaf84a643f318d480b1218bfff1041ff change-id: 20240404-topic-sm8x50-pinctrl-101fac729d23
Best regards,
Add pinctrl driver for the TLMM block found in the SM8550 SoC.
This driver only handles the gpio and qup1_se7 pinmux, and makes sure the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2fe63981478..f760bbcdd52 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845 Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8550 + bool "Qualcomm SM8550 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, + as well as the associated GPIO driver. + endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6d9aca6d7b7..970902e28c8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c new file mode 100644 index 00000000000..d9a8a652111 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8550 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup1_se7", 1}, + {"gpio", 0}, +}; + +static const char *sm8550_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8550_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 210 && selector <= 213) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8550_data = { + .pin_data = { + .pin_count = 214, + .special_pins_start = 210, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8550_get_function_name, + .get_function_mux = sm8550_get_function_mux, + .get_pin_name = sm8550_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8550) = { + .name = "pinctrl_sm8550", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; +
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong neil.armstrong@linaro.org wrote:
Add pinctrl driver for the TLMM block found in the SM8550 SoC.
This driver only handles the gpio and qup1_se7 pinmux, and makes sure the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org
drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+)
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2fe63981478..f760bbcdd52 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845 Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8550
bool "Qualcomm SM8550 GCC"select PINCTRL_QCOMhelpSay Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,as well as the associated GPIO driver.endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6d9aca6d7b7..970902e28c8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c new file mode 100644 index 00000000000..d9a8a652111 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Qualcomm sm8550 pinctrl
- (C) Copyright 2024 Linaro Ltd.
- */
+#include <common.h> +#include <dm.h>
+#include "pinctrl-qcom.h"
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = {
{"qup1_se7", 1},{"gpio", 0},+};
+static const char *sm8550_get_function_name(struct udevice *dev,
unsigned int selector)+{
return msm_pinctrl_functions[selector].name;+}
+static const char *sm8550_get_pin_name(struct udevice *dev,
unsigned int selector)+{
static const char *special_pins_names[] = {"ufs_reset","sdc2_clk","sdc2_cmd","sdc2_data",};if (selector >= 210 && selector <= 213)snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);elsesnprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);return pin_name;+}
+static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
unsigned int selector)+{
return msm_pinctrl_functions[selector].val;+}
+static struct msm_pinctrl_data sm8550_data = {
.pin_data = {.pin_count = 214,.special_pins_start = 210,},.functions_count = ARRAY_SIZE(msm_pinctrl_functions),.get_function_name = sm8550_get_function_name,.get_function_mux = sm8550_get_function_mux,.get_pin_name = sm8550_get_pin_name,+};
+static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data },{ /* Sentinel */ }+};
+U_BOOT_DRIVER(pinctrl_sm8550) = {
.name = "pinctrl_sm8550",.id = UCLASS_NOP,.of_match = msm_pinctrl_ids,.ops = &msm_pinctrl_ops,.bind = msm_pinctrl_bind,+};
-- 2.34.1
Add pinctrl driver for the TLMM block found in the SM8650 SoC.
This driver only handles the gpio and qup2_se7 pinmux, and makes sure the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f760bbcdd52..e0196a83e60 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550 Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8650 + bool "Qualcomm SM8650 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + as well as the associated GPIO driver. + endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 970902e28c8..d83e89ef4f0 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c new file mode 100644 index 00000000000..932132fa4a6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8650 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup2_se7", 1}, + {"gpio", 0}, +}; + +static const char *sm8650_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8650_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 210 && selector <= 213) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8650_data = { + .pin_data = { + .pin_count = 214, + .special_pins_start = 210, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8650_get_function_name, + .get_function_mux = sm8650_get_function_mux, + .get_pin_name = sm8650_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8650) = { + .name = "pinctrl_sm8650", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; +
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong neil.armstrong@linaro.org wrote:
Add pinctrl driver for the TLMM block found in the SM8650 SoC.
This driver only handles the gpio and qup2_se7 pinmux, and makes sure the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org
drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+)
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f760bbcdd52..e0196a83e60 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550 Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8650
bool "Qualcomm SM8650 GCC"select PINCTRL_QCOMhelpSay Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,as well as the associated GPIO driver.endmenu
endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 970902e28c8..d83e89ef4f0 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c new file mode 100644 index 00000000000..932132fa4a6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Qualcomm sm8650 pinctrl
- (C) Copyright 2024 Linaro Ltd.
- */
+#include <common.h> +#include <dm.h>
+#include "pinctrl-qcom.h"
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = {
{"qup2_se7", 1},{"gpio", 0},+};
+static const char *sm8650_get_function_name(struct udevice *dev,
unsigned int selector)+{
return msm_pinctrl_functions[selector].name;+}
+static const char *sm8650_get_pin_name(struct udevice *dev,
unsigned int selector)+{
static const char *special_pins_names[] = {"ufs_reset","sdc2_clk","sdc2_cmd","sdc2_data",};if (selector >= 210 && selector <= 213)snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);elsesnprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);return pin_name;+}
+static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
unsigned int selector)+{
return msm_pinctrl_functions[selector].val;+}
+static struct msm_pinctrl_data sm8650_data = {
.pin_data = {.pin_count = 214,.special_pins_start = 210,},.functions_count = ARRAY_SIZE(msm_pinctrl_functions),.get_function_name = sm8650_get_function_name,.get_function_mux = sm8650_get_function_mux,.get_pin_name = sm8650_get_pin_name,+};
+static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data },{ /* Sentinel */ }+};
+U_BOOT_DRIVER(pinctrl_sm8650) = {
.name = "pinctrl_sm8650",.id = UCLASS_NOP,.of_match = msm_pinctrl_ids,.ops = &msm_pinctrl_ops,.bind = msm_pinctrl_bind,+};
-- 2.34.1
Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 222db6448ab..a92b6ef7911 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -43,6 +43,8 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_PINCTRL_QCOM_SM8550=y +CONFIG_PINCTRL_QCOM_SM8650=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_SCSI=y
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong neil.armstrong@linaro.org wrote:
Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org
configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+)
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 222db6448ab..a92b6ef7911 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -43,6 +43,8 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_PINCTRL_QCOM_SM8550=y +CONFIG_PINCTRL_QCOM_SM8650=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_SCSI=y
-- 2.34.1
On 05/04/2024 10:15, Neil Armstrong wrote:
Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.
This driver only handles the gpio and qup debug uart pinmux, and makes sure the pinconf applies on SDC2 pins.
Finally enable both drivers in the Qualcomm defconfig
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org
Reviewed-by: Caleb Connolly caleb.connolly@linaro.org
Neil Armstrong (3): pinctrl: qcom: Add SM8550 pinctrl driver pinctrl: qcom: Add SM8650 pinctrl driver qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
configs/qcom_defconfig | 2 + drivers/pinctrl/qcom/Kconfig | 14 +++++++ drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ 5 files changed, 168 insertions(+)
base-commit: cec1c47bdaf84a643f318d480b1218bfff1041ff change-id: 20240404-topic-sm8x50-pinctrl-101fac729d23
Best regards,
On Fri, 05 Apr 2024 10:15:09 +0200, Neil Armstrong wrote:
Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.
This driver only handles the gpio and qup debug uart pinmux, and makes sure the pinconf applies on SDC2 pins.
Finally enable both drivers in the Qualcomm defconfig
[...]
Applied, thanks!
[1/3] pinctrl: qcom: Add SM8550 pinctrl driver commit: 225c991b41a2255054dfcafb7667979c6a88bffd [2/3] pinctrl: qcom: Add SM8650 pinctrl driver commit: b0725abe0ae5c41c03dfc9af921120fe501f07f5 [3/3] qcom_defconfig: enable SM8550 & SM8650 pinctrl driver commit: c32ab322d04eed52d5ad30b19d45fe041c19a250
Best regards,
participants (3)
-
Caleb Connolly -
Neil Armstrong -
Sumit Garg