[U-Boot] [PATCH v2] mmc: fsl_esdhc: Add support for DDR mode
Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only.
Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com --- drivers/mmc/fsl_esdhc.c | 8 ++++++-- include/configs/mx6_common.h | 2 ++ include/fsl_esdhc.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28..f5d2ccb 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) esdhc_write32(®s->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(®s->mixctrl, - (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(®s->xfertyp, xfertyp); @@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break;
- pre_div >>= 1; + pre_div >>= mmc->ddr_mode ? 2 : 1; div -= 1;
clk = (pre_div << 8) | (div << 4); @@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) }
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; +#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; +#endif
if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648..313fa1e 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001
On 01/20/2015 07:16 AM, Volodymyr Riazantsev wrote:
Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only.
Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com
Applied to u-boot-fsl-qoriq master branch, awaiting upstream.
York
On 25.02.2015 22:37, York Sun wrote:
On 01/20/2015 07:16 AM, Volodymyr Riazantsev wrote:
Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only.
Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com
Applied to u-boot-fsl-qoriq master branch, awaiting upstream.
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK
Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.
Thanks, Stefan
Volodymyr,
On 03/06/2015 05:43 AM, Stefan Roese wrote:
On 25.02.2015 22:37, York Sun wrote:
On 01/20/2015 07:16 AM, Volodymyr Riazantsev wrote:
Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only.
Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com
Applied to u-boot-fsl-qoriq master branch, awaiting upstream.
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK
Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.
Please look into this issue and post a patch to fix if applicable. Thanks.
York
Hi Stefan,
On Fri, Mar 6, 2015 at 10:43 AM, Stefan Roese sr@denx.de wrote:
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK
Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.
Does this fix from Peng help? http://lists.denx.de/pipermail/u-boot/2015-March/207632.html
Regards,
Fabio Estevam
Hi Fabio,
On 10.03.2015 14:29, Fabio Estevam wrote:
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write: dev # 0, block # 2, count 711 ... 711 blocks written: OK
Any ideas what might cause this breakage? If this issue can't be solved soon I suggest to revert this patch for this release.
Does this fix from Peng help? http://lists.denx.de/pipermail/u-boot/2015-March/207632.html
No, it does unfortunately not.
Thanks, Stefan
Volodymyr,
On Tue, Jan 20, 2015 at 1:16 PM, Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com wrote:
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Shouldn't this be defined per board config file instead?
Stefan,
Does your board work if CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE is removed from mx6_common.h?
Regards,
Fabio Estevam
Fabio, Yes, it was too optimistic to enable it for all i.MX6 base devices, I'll submit patch for disable it by default. Vendors can enable it separately for custom boards.
Stefan, Please let me know if you have any results with debug patches.
BR, Volodymyr. http://www.globallogic.com/email_disclaimer.txt
On Wed, Mar 11, 2015 at 7:42 PM, Fabio Estevam festevam@gmail.com wrote:
Volodymyr,
On Tue, Jan 20, 2015 at 1:16 PM, Volodymyr Riazantsev volodymyr.riazantsev@globallogic.com wrote:
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Shouldn't this be defined per board config file instead?
Stefan,
Does your board work if CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE is removed from mx6_common.h?
Regards,
Fabio Estevam
Hi Volodymyr,
On 12.03.2015 00:48, Volodymyr Riazantsev wrote:
Yes, it was too optimistic to enable it for all i.MX6 base devices, I'll submit patch for disable it by default. Vendors can enable it separately for custom boards.
Stefan, Please let me know if you have any results with debug patches.
I tought that I already send the debug output a few days ago. But here again.
Thanks, Stefan
participants (4)
-
Fabio Estevam -
Stefan Roese -
Volodymyr Riazantsev -
York Sun