[U-Boot] [PATCH 1/3] video: Kconfig: Add VIDEO_IPV3 entry
From: Jagan Teki jagan@amarulasolutions.com
Added kconfig entry for CONFIG_VIDEO_IPV3 driver.
Cc: Anatolij Gustschin agust@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Matteo Lisi matteo.lisi@engicam.com Cc: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/video/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8361a71..4cf95e1 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -337,6 +337,13 @@ config VIDEO_LCD_SPI_MISO option takes a string in the format understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on MX6 + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + config VIDEO_MVEBU bool "Armada XP LCD controller" default n
From: Jagan Teki jagan@amarulasolutions.com
Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin agust@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Matteo Lisi matteo.lisi@engicam.com Cc: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- board/engicam/icorem6/icorem6.c | 113 +++++++++++++++++++++++++++++++++++ configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + include/configs/imx6qdl_icore.h | 16 +++++ 4 files changed, 131 insertions(+)
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 587775e..171ec45 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -18,6 +18,7 @@ #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -90,6 +91,113 @@ static void setup_gpmi_nand(void) } #endif
+#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const rgb_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), +}; + +static void enable_rgb(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(rgb_pads); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "Amp-WD", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30000, + .left_margin = 30, + .right_margin = 30, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 64, + .vsync_len = 20, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + int board_early_init_f(void) { SETUP_IOMUX_PADS(uart4_pads); @@ -105,6 +213,11 @@ int board_init(void) #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif + return 0; }
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index fbcbdc8..8d90c58 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -31,6 +31,7 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO_IPUV3=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 4b544fc..911ab80 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -27,6 +27,7 @@ CONFIG_NAND_MXS=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO_IPUV3=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index f8a1263..889211f 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -149,6 +149,22 @@ # define CONFIG_PHY_SMSC #endif
+/* Framebuffer */ +#ifdef CONFIG_VIDEO_IPUV3 +# define CONFIG_VIDEO +# define CONFIG_IPUV3_CLK 260000000 +# define CONFIG_IMX_VIDEO_SKIP +# define CONFIG_CFB_CONSOLE +# define CONFIG_VGA_AS_SINGLE_DEVICE + +# define CONFIG_SPLASH_SCREEN +# define CONFIG_SYS_CONSOLE_IS_IN_ENV +# define CONFIG_BMP_16BPP +# define CONFIG_VIDEO_BMP_RLE8 +# define CONFIG_VIDEO_LOGO +# define CONFIG_VIDEO_BMP_LOGO +#endif + /* SPL */ #ifdef CONFIG_SPL # ifdef CONFIG_NAND_MXS
From: Jagan Teki jagan@amarulasolutions.com
Add custom splashscreen, engicam.bmp support for Engicam i.CoreM6 qdl board.
Cc: Anatolij Gustschin agust@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Matteo Lisi matteo.lisi@engicam.com Cc: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/configs/imx6qdl_icore.h | 2 ++ tools/logos/engicam.bmp | Bin 0 -> 60214 bytes 2 files changed, 2 insertions(+) create mode 100755 tools/logos/engicam.bmp
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 889211f..4637b00 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -37,6 +37,7 @@ /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ + "splashpos=m,m\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ @@ -158,6 +159,7 @@ # define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_SPLASH_SCREEN +# define CONFIG_SPLASH_SCREEN_ALIGN # define CONFIG_SYS_CONSOLE_IS_IN_ENV # define CONFIG_BMP_16BPP # define CONFIG_VIDEO_BMP_RLE8 diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp new file mode 100755 index 0000000000000000000000000000000000000000..f6c60fb810d29830941e18d6725ef95785d95967 GIT binary patch literal 60214 zcmeHQy{;oUb}kzN)XMw_3jG8d3(oxxdV~$;0V-UDRydJ>F&s^}4^XkQQP^@I>=H2G zwt(#(j1mX!k7V)ie21)3Rd-+A*}hfX=aMWQp5KpTiPF{mmw)}khbCNqST)T*qxMh# z*ff7c`47#z*zw=7D1Ww1ga1w2#sWW4ZMv>&y8r5$zy0TbG|hGg+Jn%sJ%KvVwP|(@ zXbVDRw+FSL6Q~1Sn`YmDwxAsdjeQF`fjZE&*Skfz1MNXA=mhFO*QP<WIc-5Z&>qx+ zPM{8Sg^>+t3)+G9pcZrjb)ak0;D2-7f_9)is0E!s9q8KZ8kpH^LH^$!)Phc+4s?yK zZMP_QpgpJsoj@Jv8r|M)QSLx{PzySNI?y$SWWPnZ1MNXA=mhFO*BGvLi*g6rgIdrD z)Pb%sl&3Aq9cT|~K_^fLy2dbfTa-J{9@K(Ppbm5mDcD`ND0iSes0E!s9q8J$@V{-g zAn*Ae<o}&O9q8J$+Xl1+?Ld1_3p#;1&^4xQw?(-F?LjT*1nNN7n9}_g<qot5wV)HI z16^afp`>khpgpJsoj@Jv8liC7qTGS@pcZrjb)aj6Nw-D01MNXA=mhFO*8rjRx<$DI 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participants (1)
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Jagan Teki