[PATCH v2 13/21] dts: mtmips: add alternative pinmux node for uart2
This patch adds a new pinmux for UART2, which shares the pins with SPIS.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- Changes since v1: newly added --- arch/mips/dts/mt7628a.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 744594c45a..f265cb6ad9 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -93,6 +93,11 @@ function = "uart2"; };
+ uart2_pwm_pins: uart2_pwm_pins { + groups = "spis"; + function = "pwm_uart2"; + }; + i2c_pins: i2c_pins { groups = "i2c"; function = "i2c";
Added Mauro to Cc
On 17.01.20 08:46, Weijie Gao wrote:
This patch adds a new pinmux for UART2, which shares the pins with SPIS.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com
Changes since v1: newly added
arch/mips/dts/mt7628a.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 744594c45a..f265cb6ad9 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -93,6 +93,11 @@ function = "uart2"; };
uart2_pwm_pins: uart2_pwm_pins {groups = "spis";function = "pwm_uart2";};
Thanks. AFAIK, this will not be used by any of the currently supported boards. Is this correct?
Mauro is currently trying to port mainline U-Boot to the VoCore2 board which also uses UART2. I did not look to close, but might this pin mux option here be necessary for this VoCore2 board?
Thanks, Stefan
On Fri, 2020-01-17 at 15:50 +0100, Stefan Roese wrote:
Added Mauro to Cc
On 17.01.20 08:46, Weijie Gao wrote:
This patch adds a new pinmux for UART2, which shares the pins with SPIS.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com
Changes since v1: newly added
arch/mips/dts/mt7628a.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 744594c45a..f265cb6ad9 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -93,6 +93,11 @@ function = "uart2"; };
uart2_pwm_pins: uart2_pwm_pins {groups = "spis";function = "pwm_uart2";};Thanks. AFAIK, this will not be used by any of the currently supported boards. Is this correct?
Yes.
Mauro is currently trying to port mainline U-Boot to the VoCore2 board which also uses UART2. I did not look to close, but might this pin mux option here be necessary for this VoCore2 board?
Yes. I added this because of your discussions about the pinmux. I've tested this pinmux and it worked well. I believe it's necessary for the VoCore2.
Thanks, Stefan
Hi Weijie, Hi Mauro,
On 19.01.20 03:26, Weijie Gao wrote:
On Fri, 2020-01-17 at 15:50 +0100, Stefan Roese wrote:
Added Mauro to Cc
On 17.01.20 08:46, Weijie Gao wrote:
This patch adds a new pinmux for UART2, which shares the pins with SPIS.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com
Changes since v1: newly added
arch/mips/dts/mt7628a.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 744594c45a..f265cb6ad9 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -93,6 +93,11 @@ function = "uart2"; };
uart2_pwm_pins: uart2_pwm_pins {groups = "spis";function = "pwm_uart2";};Thanks. AFAIK, this will not be used by any of the currently supported boards. Is this correct?
Yes.
Mauro is currently trying to port mainline U-Boot to the VoCore2 board which also uses UART2. I did not look to close, but might this pin mux option here be necessary for this VoCore2 board?
Yes. I added this because of your discussions about the pinmux. I've tested this pinmux and it worked well. I believe it's necessary for the VoCore2.
Thanks Weijie for your assistance here.
I can confirm that your latest patchset works like a charm on the LinkIt 7688 board.
Mauro, please find attached a new binary to flash at offset 0x0 in SPI NOR based on Weijie's latest patchset with this alternate UART pin mux setting enabled. I've also attached the defconfig for this. Please give it a try and let us know, if this works now for you.
Thanks, Stefan
SUCCESS!!!
=> usb start; load usb 0:1 85000000 u-boot-mtmips.bin starting USB... Bus ehci@101c0000: pinctrl_select_state_full('ehci@101c0000', 'default'): USB EHCI 1.00 scanning bus ehci@101c0000 for devices... 3 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found 213156 bytes read in 11 ms (18.5 MiB/s) => sf probe; sf update ${fileaddr} 0 ${filesize} pinctrl_select_state_full('spi@b00', 'default'): SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB device 0 offset 0x0, size 0x340a4 213156 bytes written, 0 bytes skipped in 5.465s, speed 39918 B/s => sf read 86000000 0 ${filesize}; cmp 86000000 ${fileaddr} ${filesize} device 0 offset 0x0, size 0x340a4 SF: 213156 bytes @ 0x0 Read: OK word at 0x860340a4 (0x2e220918) != word at 0x850340a4 (0x1ab4834a) Total of 53289 word(s) were the same => reset resetting ... pinctrl_select_state_full('syscon-reboot', 'default'): pinctrl_select_state_full('system-controller@0', 'default'):
U-Boot SPL 2020.01-00643-g1262a953f1 (Jan 20 2020 - 09:33:36 +0100) Trying to boot from NOR
U-Boot 2020.01-00643-g1262a953f1 (Jan 20 2020 - 09:33:36 +0100)
CPU: MediaTek MT7628A ver:1 eco:2 Boot: DDR2, SPI-NOR 3-Byte Addr, CPU clock from XTAL Clock: CPU: 580MHz, Bus: 193MHz, XTAL: 40MHz Model: LinkIt-Smart-7688 DRAM: 128 MiB Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment
Net: Warning: eth@10110000 (eth0) using random MAC address - 72:2c:95:10:90:e9 eth0: eth@10110000 =>
*** THANKS!! ***
now I need to be able to duplicate this and, if needed, to modify. I tried using last Weijie patch-set, but I got the same error You reported, I "fixed" it removing `obj-y += time.o` from `arch/mips/cpu/Makefile`, but I was afraid to test results ;)
What is the right sequence to get Your results?
Note: I will need to have also working MMC/SD; in stock U-Boot I had to backport some drivers for that; is it supposed to work out-of-the-box (given right config, of course) in this version?
Many, MANY thanks to You both.
Regards Mauro
On 1/20/20 9:38 AM, Stefan Roese wrote:
Hi Weijie, Hi Mauro,
On 19.01.20 03:26, Weijie Gao wrote:
On Fri, 2020-01-17 at 15:50 +0100, Stefan Roese wrote:
Added Mauro to Cc
On 17.01.20 08:46, Weijie Gao wrote:
This patch adds a new pinmux for UART2, which shares the pins with SPIS.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com
Changes since v1: newly added
arch/mips/dts/mt7628a.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 744594c45a..f265cb6ad9 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -93,6 +93,11 @@ function = "uart2"; }; + uart2_pwm_pins: uart2_pwm_pins { + groups = "spis"; + function = "pwm_uart2"; + };
Thanks. AFAIK, this will not be used by any of the currently supported boards. Is this correct?
Yes.
Mauro is currently trying to port mainline U-Boot to the VoCore2 board which also uses UART2. I did not look to close, but might this pin mux option here be necessary for this VoCore2 board?
Yes. I added this because of your discussions about the pinmux. I've tested this pinmux and it worked well. I believe it's necessary for the VoCore2.
Thanks Weijie for your assistance here.
I can confirm that your latest patchset works like a charm on the LinkIt 7688 board.
Mauro, please find attached a new binary to flash at offset 0x0 in SPI NOR based on Weijie's latest patchset with this alternate UART pin mux setting enabled. I've also attached the defconfig for this. Please give it a try and let us know, if this works now for you.
Thanks, Stefan
Hi Mauro,
On 20.01.20 10:14, Mauro Condarelli wrote:
SUCCESS!!!
Uffff. ;)
=> usb start; load usb 0:1 85000000 u-boot-mtmips.bin starting USB... Bus ehci@101c0000: pinctrl_select_state_full('ehci@101c0000', 'default'): USB EHCI 1.00 scanning bus ehci@101c0000 for devices... 3 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found 213156 bytes read in 11 ms (18.5 MiB/s) => sf probe; sf update ${fileaddr} 0 ${filesize} pinctrl_select_state_full('spi@b00', 'default'): SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB device 0 offset 0x0, size 0x340a4 213156 bytes written, 0 bytes skipped in 5.465s, speed 39918 B/s => sf read 86000000 0 ${filesize}; cmp 86000000 ${fileaddr} ${filesize} device 0 offset 0x0, size 0x340a4 SF: 213156 bytes @ 0x0 Read: OK word at 0x860340a4 (0x2e220918) != word at 0x850340a4 (0x1ab4834a) Total of 53289 word(s) were the same => reset resetting ... pinctrl_select_state_full('syscon-reboot', 'default'): pinctrl_select_state_full('system-controller@0', 'default'):
U-Boot SPL 2020.01-00643-g1262a953f1 (Jan 20 2020 - 09:33:36 +0100) Trying to boot from NOR
U-Boot 2020.01-00643-g1262a953f1 (Jan 20 2020 - 09:33:36 +0100)
CPU: MediaTek MT7628A ver:1 eco:2 Boot: DDR2, SPI-NOR 3-Byte Addr, CPU clock from XTAL Clock: CPU: 580MHz, Bus: 193MHz, XTAL: 40MHz Model: LinkIt-Smart-7688 DRAM: 128 MiB Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment
Net: Warning: eth@10110000 (eth0) using random MAC address - 72:2c:95:10:90:e9 eth0: eth@10110000 =>
*** THANKS!! ***
now I need to be able to duplicate this and, if needed, to modify. I tried using last Weijie patch-set, but I got the same error You reported, I "fixed" it removing `obj-y += time.o` from `arch/mips/cpu/Makefile`, but I was afraid to test results ;)
What is the right sequence to get Your results?
Note: I will need to have also working MMC/SD; in stock U-Boot I had to backport some drivers for that; is it supposed to work out-of-the-box (given right config, of course) in this version?
I've already attached the defconfig file you should use as a base for your VoCore2 port in my last mail. Please find it attached again. Other than that you need to apply all 21 patches of Weijie's latest patchset and this one:
https://patchwork.ozlabs.org/patch/1215073/
Then start changing the configuration to your needs - port to the VoCore2 with its changes (MMC, SD etc). Most of this can be done by using the RAM version now (again). There is no additional RAM booting target now any more. You can use the normal U-Boot image for this now. Please note the changes TEXT_BASE here. Its now 0x80200000.
HTH.
Thanks, Stefan
participants (3)
-
Mauro Condarelli -
Stefan Roese -
Weijie Gao