[U-Boot] [PATCH 0/3] rk3399: enable dwmmc controller for sdcard
rk3399 using dwmmc controller for sdcard, let's enable it. this patch set has been test on rk3399 evb.
Kever Yang (3): clock: rk3399: add support for dwmmc 400K dts: rk3399: enable dwmmc for sdcard config: rk3399: enable dwmmc controller
arch/arm/dts/rk3399-evb.dts | 4 ++++ arch/arm/dts/rk3399.dtsi | 2 +- configs/evb-rk3399_defconfig | 1 + drivers/clk/clk_rk3399.c | 29 +++++++++++++++++++++-------- include/configs/rk3399_common.h | 1 + 5 files changed, 28 insertions(+), 9 deletions(-)
MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
drivers/clk/clk_rk3399.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/clk_rk3399.c b/drivers/clk/clk_rk3399.c index 5d9bce0..802b8a1 100644 --- a/drivers/clk/clk_rk3399.c +++ b/drivers/clk/clk_rk3399.c @@ -142,6 +142,7 @@ enum { CLK_EMMC_PLL_SHIFT = 8, CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, CLK_EMMC_PLL_SEL_GPLL = 0x1, + CLK_EMMC_PLL_SEL_24M = 0x5, CLK_EMMC_DIV_CON_SHIFT = 0, CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
@@ -640,9 +641,13 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) default: return -EINVAL; } - div = (con>>CLK_EMMC_DIV_CON_SHIFT) & CLK_EMMC_DIV_CON_MASK; + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
- return DIV_TO_RATE(GPLL_HZ, div); + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT + == CLK_EMMC_PLL_SEL_24M) + return DIV_TO_RATE(24*1024*1024, div); + else + return DIV_TO_RATE(GPLL_HZ, div); }
static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, @@ -653,14 +658,22 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
switch (clk_id) { case SCLK_SDMMC: - /* Select clk_sdmmc source from GPLL too */ + /* Select clk_sdmmc source from GPLL by default */ src_clk_div = GPLL_HZ / set_rate; - assert(src_clk_div - 1 < 127);
- rk_clrsetreg(&cru->clksel_con[16], - CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, - CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | - (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = 24*1024*1024 / set_rate; + rk_clrsetreg(&cru->clksel_con[16], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[16], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } break; case SCLK_EMMC: /* Select aclk_emmc source from GPLL */
On 1 August 2016 at 20:47, Kever Yang kever.yang@rock-chips.com wrote:
MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
drivers/clk/clk_rk3399.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/dts/rk3399-evb.dts | 4 ++++ arch/arm/dts/rk3399.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index bbcfcd0..e92a492 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -61,6 +61,10 @@ status = "okay"; };
+&sdmmc { + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index fb5af54..9547627 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -172,7 +172,7 @@ reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>;
Hi Kever,
On 1 August 2016 at 21:00, Kever Yang kever.yang@rock-chips.com wrote:
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Please add a commit message.
arch/arm/dts/rk3399-evb.dts | 4 ++++ arch/arm/dts/rk3399.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index bbcfcd0..e92a492 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -61,6 +61,10 @@ status = "okay"; };
+&sdmmc {
status = "okay";+};
&sdhci { bus-width = <8>; mmc-hs400-1_8v; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index fb5af54..9547627 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -172,7 +172,7 @@ reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>;-- 1.9.1
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
configs/evb-rk3399_defconfig | 1 + include/configs/rk3399_common.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3f9b47e..18f6ae6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -22,6 +22,7 @@ CONFIG_FIT=y CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_SDHCI=y +CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_SYS_NS16550=y diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ca05e5c..12327d5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -30,6 +30,7 @@ /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC #define CONFIG_SDHCI #define CONFIG_BOUNCE_BUFFER #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
On 1 August 2016 at 21:00, Kever Yang kever.yang@rock-chips.com wrote:
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Commit message please.
configs/evb-rk3399_defconfig | 1 + include/configs/rk3399_common.h | 1 + 2 files changed, 2 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3f9b47e..18f6ae6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -22,6 +22,7 @@ CONFIG_FIT=y CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_SDHCI=y +CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_SYS_NS16550=y diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ca05e5c..12327d5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -30,6 +30,7 @@ /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC #define CONFIG_SDHCI #define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
1.9.1
participants (2)
-
Kever Yang -
Simon Glass