From: Sin Hui Kho sin.hui.kho@intel.com

Change NAND flash MTD partition in device tree after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components.

Signed-off-by: Sin Hui Kho sin.hui.kho@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_agilex_socdk_nand.dts | 55 ++++++ arch/arm/dts/socfpga_stratix10_socdk_nand.dts | 167 ++++++++++++++++++ 2 files changed, 222 insertions(+) create mode 100755 arch/arm/dts/socfpga_agilex_socdk_nand.dts create mode 100755 arch/arm/dts/socfpga_stratix10_socdk_nand.dts

diff --git a/arch/arm/dts/socfpga_agilex_socdk_nand.dts b/arch/arm/dts/socfpga_agilex_socdk_nand.dts new file mode 100755 index 0000000000..3237e34c99 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk_nand.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + */ +#include "socfpga_agilex_socdk.dts" +#include "socfpga_agilex_socdk-u-boot.dtsi" +&gmac0 { + status = "disabled"; +}; +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + max-frame-size = <3800>; + mdio2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy2: ethernet-phy@2 { + reg = <4>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; +&mmc { + status = "disabled"; +}; +&nand { + flash@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand.dts b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts new file mode 100755 index 0000000000..9a23c36b92 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + */ +#include "socfpga_stratix10.dtsi" +/ { + model = "SoCFPGA Stratix 10 SoCDK"; + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + eccmgr { + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; + }; +}; +&gpio1 { + status = "okay"; +}; +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + max-frame-size = <9000>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; +&nand { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + nand-bus-width = <16>; + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; +&uart0 { + status = "okay"; +}; +&usb0 { + status = "okay"; + disable-over-current; +}; +&watchdog0 { + status = "okay"; +}; +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <890>; /* hcnt */ + i2c-sdl-falling-time-ns = <890>; /* lcnt */ + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x034B0000>; + }; + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x034B0000 0x0EB50000>; + }; + }; + }; +}; \ No newline at end of file