[U-Boot-Users] [PATCH v2] 85xx: Reworked initial processor init
Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs
The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that.
There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu_init.c | 56 +++++++++++++++++++-- cpu/mpc85xx/start.S | 131 +++++++++++++++++++++++------------------------- 2 files changed, 115 insertions(+), 72 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9a65142..4e2bfe7 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -31,6 +31,7 @@ #include <asm/processor.h> #include <ioports.h> #include <asm/io.h> +#include <asm/mmu.h> #include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR; @@ -123,6 +124,54 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif
+/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void) +{ + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 0, BOOKE_PAGESZ_4K, 0); + + /* set up CCSR if we want it moved */ +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + { + u32 temp; + + set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 1, BOOKE_PAGESZ_4K, 0); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR); + } +#endif + + init_laws(); + invalidate_tlb(0); +#ifdef CONFIG_FSL_INIT_TLBS + init_tlbs(); +#else + { + extern u32 tlb1_entry; + u32 *tmp = &tlb1_entry; + int i; + int num = tmp[2]; + + /* skip to actual table */ + tmp += 3; + + for (i = 0; i < num; i++, tmp += 4) { + mtspr(MAS0, tmp[0]); + mtspr(MAS1, tmp[1]); + mtspr(MAS2, tmp[2]); + mtspr(MAS3, tmp[3]); + asm volatile("isync;msync;tlbwe;isync"); + } + } +#endif +} + /* * Breathe some life into the CPU... * @@ -135,16 +184,15 @@ void cpu_init_f (void) volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void);
+ disable_tlb(14); + disable_tlb(15); + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t));
-#ifdef CONFIG_FSL_LAW - init_laws(); -#endif - #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2044722..e8e5eb2 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -143,68 +143,8 @@ _start_e500: li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */
- - /* - * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. - * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB - * region before we can access any CCSR registers such as L2 - * registers, Local Access Registers,etc. We will also re-allocate - * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. - * - * Please refer to board-specif directory for TLB1 entry configuration. - * (e.g. board/<yourboard>/init.S) - * - */ - bl tlb1_entry - mr r5,r0 - lwzu r4,0(r5) /* how many TLB1 entries we actually use */ - mtctr r4 - -0: lwzu r6,4(r5) - lwzu r7,4(r5) - lwzu r8,4(r5) - lwzu r9,4(r5) - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - isync - bdnz 0b - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* Special sequence needed to update CCSRBAR itself */ - lis r4,CFG_CCSRBAR_DEFAULT@h - ori r4,r4,CFG_CCSRBAR_DEFAULT@l - - lis r5,CFG_CCSRBAR@h - ori r5,r5,CFG_CCSRBAR@l - srwi r6,r5,12 - stw r6,0(r4) - isync - - lis r5,0xffff - ori r5,r5,0xf000 - lwz r5,0(r5) - isync - - lis r3,CFG_CCSRBAR@h - lwz r5,CFG_CCSRBAR@l(r3) - isync -#endif - - - /* set up local access windows, defined at board/<boardname>/init.S */ - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - /* Clear and set up some registers. */ - li r0,0 - mtmsr r0 - li r0,0x0000 + li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ mttbl r0 /* prevent fit & wdt exceptions */ @@ -214,18 +154,13 @@ _start_e500: mtspr ESR,r0 /* clear exception syndrome register */ mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ - lis r1,0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1200 /* set ME/DE bit */ - mtmsr r1 /* change MSR */ - isync
/* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ #if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */ -#else - ori r0,r0,HID0_TBEN@l /* enable Timebase */ + ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ #endif + ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ @@ -246,6 +181,58 @@ _start_e500: mtspr DBCR0,r0 #endif
+ /* create a temp mapping in AS=1 to the boot window */ + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* create a temp mapping in AS=1 to the stack */ + lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l + + lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h + ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l + + lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h + ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l + lis r7,switch_as@h + ori r7,r7,switch_as@l + + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi + +switch_as: /* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache. @@ -305,6 +292,14 @@ _start_cont: stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT + bl cpu_init_early_f + + /* switch back to AS = 0 */ + lis r3,(MSR_CE|MSR_ME|MSR_DE)@h + ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l + mtmsr r3 + isync + bl cpu_init_f bl board_init_f isync
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8544ds/Makefile | 4 +- board/freescale/mpc8544ds/init.S | 174 ---------------------------------- board/freescale/mpc8544ds/tlb.c | 99 +++++++++++++++++++ board/freescale/mpc8544ds/u-boot.lds | 2 - include/configs/MPC8544DS.h | 1 + 5 files changed, 101 insertions(+), 179 deletions(-) delete mode 100644 board/freescale/mpc8544ds/init.S create mode 100644 board/freescale/mpc8544ds/tlb.c
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 665251d..53368b2 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,9 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o - -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S deleted file mode 100644 index 3918176..0000000 --- a/board/freescale/mpc8544ds/init.S +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 -1: - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe100_0000 255M PCI IO range - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#ifdef CFG_LBC_CACHE_BASE - /* - * TLB 5: 64M Cacheable, non-guarded - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -2: - entry_end diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c new file mode 100644 index 0000000..34cfb38 --- /dev/null +++ b/board/freescale/mpc8544ds/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + /* + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1G, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe100_0000 255M PCI IO range + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + +#ifdef CFG_LBC_CACHE_BASE + /* + * TLB 5: 64M Cacheable, non-guarded + */ + SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), +#endif + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF + */ + SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index 66bd4b6..17db8c0 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8544ds/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8544ds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a894209..1269c8a 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -43,6 +43,7 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/atum8548/Makefile | 4 +- board/atum8548/init.S | 175 -------------------------------------------- board/atum8548/tlb.c | 90 ++++++++++++++++++++++ board/atum8548/u-boot.lds | 2 - include/configs/ATUM8548.h | 1 + 5 files changed, 92 insertions(+), 180 deletions(-) delete mode 100644 board/atum8548/init.S create mode 100644 board/atum8548/tlb.c
diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile index bf0830c..ac4e583 100644 --- a/board/atum8548/Makefile +++ b/board/atum8548/Makefile @@ -29,9 +29,7 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o - -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/atum8548/init.S b/board/atum8548/init.S deleted file mode 100644 index 7e161c1..0000000 --- a/board/atum8548/init.S +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2007 - * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com - * Copyright 2004, 2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* TLB 1 Initializations */ - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3, 4: 512M Non-cacheable, guarded - * 0xc0000000 1G PCI2 - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c new file mode 100644 index 0000000..bb6ce76 --- /dev/null +++ b/board/atum8548/tlb.c @@ -0,0 +1,90 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 Initializations */ + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* + * TLB 3, 4: 512M Non-cacheable, guarded + * 0xc0000000 1G PCI2 + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/atum8548/u-boot.lds b/board/atum8548/u-boot.lds index 0d1c217..3f04cae 100644 --- a/board/atum8548/u-boot.lds +++ b/board/atum8548/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/atum8548/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/atum8548/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c14376e..c2dde41 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -64,6 +64,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8540ads/Makefile | 3 +- board/freescale/mpc8540ads/init.S | 212 -------------------------------- board/freescale/mpc8540ads/tlb.c | 130 ++++++++++++++++++++ board/freescale/mpc8540ads/u-boot.lds | 2 - board/freescale/mpc8560ads/Makefile | 3 +- board/freescale/mpc8560ads/init.S | 213 --------------------------------- board/freescale/mpc8560ads/tlb.c | 130 ++++++++++++++++++++ board/freescale/mpc8560ads/u-boot.lds | 2 - include/configs/MPC8540ADS.h | 1 + include/configs/MPC8560ADS.h | 1 + 10 files changed, 264 insertions(+), 433 deletions(-) delete mode 100644 board/freescale/mpc8540ads/init.S create mode 100644 board/freescale/mpc8540ads/tlb.c delete mode 100644 board/freescale/mpc8560ads/init.S create mode 100644 board/freescale/mpc8560ads/tlb.c
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 0c8f470..be24388 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S deleted file mode 100644 index 4c8dd0e..0000000 --- a/board/freescale/mpc8540ads/init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c new file mode 100644 index 0000000..3eaff01 --- /dev/null +++ b/board/freescale/mpc8540ads/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds index bc0db55..86f8f13 100644 --- a/board/freescale/mpc8540ads/u-boot.lds +++ b/board/freescale/mpc8540ads/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8540ads/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8540ads/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 0c8f470..be24388 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S deleted file mode 100644 index 8ade9ca..0000000 --- a/board/freescale/mpc8560ads/init.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c new file mode 100644 index 0000000..3eaff01 --- /dev/null +++ b/board/freescale/mpc8560ads/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds index 96af2b1..e2474e5 100644 --- a/board/freescale/mpc8560ads/u-boot.lds +++ b/board/freescale/mpc8560ads/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8560ads/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8560ads/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5ea7b25..74076fb 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -56,6 +56,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 08884b3..84c517f 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -53,6 +53,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8541cds/Makefile | 4 +- board/freescale/mpc8541cds/init.S | 192 --------------------------------- board/freescale/mpc8541cds/tlb.c | 112 +++++++++++++++++++ board/freescale/mpc8541cds/u-boot.lds | 2 - board/freescale/mpc8548cds/Makefile | 4 +- board/freescale/mpc8548cds/init.S | 184 ------------------------------- board/freescale/mpc8548cds/tlb.c | 104 ++++++++++++++++++ board/freescale/mpc8548cds/u-boot.lds | 2 - board/freescale/mpc8555cds/Makefile | 4 +- board/freescale/mpc8555cds/init.S | 192 --------------------------------- board/freescale/mpc8555cds/tlb.c | 112 +++++++++++++++++++ board/freescale/mpc8555cds/u-boot.lds | 2 - include/configs/MPC8541CDS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + 15 files changed, 334 insertions(+), 583 deletions(-) delete mode 100644 board/freescale/mpc8541cds/init.S create mode 100644 board/freescale/mpc8541cds/tlb.c delete mode 100644 board/freescale/mpc8548cds/init.S create mode 100644 board/freescale/mpc8548cds/tlb.c delete mode 100644 board/freescale/mpc8555cds/init.S create mode 100644 board/freescale/mpc8555cds/tlb.c
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -29,14 +29,12 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o
-SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S deleted file mode 100644 index 6e93fb0..0000000 --- a/board/freescale/mpc8541cds/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c new file mode 100644 index 0000000..92f759b --- /dev/null +++ b/board/freescale/mpc8541cds/tlb.c @@ -0,0 +1,112 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds index 1e490d0..1cbadf2 100644 --- a/board/freescale/mpc8541cds/u-boot.lds +++ b/board/freescale/mpc8541cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8541cds/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8541cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -29,14 +29,12 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o
-SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S deleted file mode 100644 index 51e1cc4..0000000 --- a/board/freescale/mpc8548cds/init.S +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2004, 2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#ifdef CFG_RIO_MEM_PHYS - /* - * TLB 2: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 64M Non-cacheable, guarded - * 0xf8000000 64M CADMUS registers, relocated L2SRAM - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c new file mode 100644 index 0000000..b21f71b --- /dev/null +++ b/board/freescale/mpc8548cds/tlb.c @@ -0,0 +1,104 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1G, 1), + +#ifdef CFG_RIO_MEM_PHYS + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), +#endif + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 64M Non-cacheable, guarded + * 0xf8000000 64M CADMUS registers, relocated L2SRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds index acf25e3..d701096 100644 --- a/board/freescale/mpc8548cds/u-boot.lds +++ b/board/freescale/mpc8548cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8548cds/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8548cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -29,14 +29,12 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o
-SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S deleted file mode 100644 index 6e93fb0..0000000 --- a/board/freescale/mpc8555cds/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c new file mode 100644 index 0000000..92f759b --- /dev/null +++ b/board/freescale/mpc8555cds/tlb.c @@ -0,0 +1,112 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds index e9fa51e..1cbadf2 100644 --- a/board/freescale/mpc8555cds/u-boot.lds +++ b/board/freescale/mpc8555cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8555cds/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8555cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7334088..92195ed 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -48,6 +48,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a3db9f4..77bcc29 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -56,6 +56,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 93877ae..e7b9694 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -48,6 +48,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID,
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8568mds/Makefile | 4 +- board/freescale/mpc8568mds/init.S | 178 --------------------------------- board/freescale/mpc8568mds/tlb.c | 100 ++++++++++++++++++ board/freescale/mpc8568mds/u-boot.lds | 2 - include/configs/MPC8568MDS.h | 1 + 5 files changed, 102 insertions(+), 183 deletions(-) delete mode 100644 board/freescale/mpc8568mds/init.S create mode 100644 board/freescale/mpc8568mds/tlb.c
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index ef78942..d9f20f9 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -29,9 +29,7 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o bcsr.o law.o - -SOBJS := init.o +COBJS := $(BOARD).o bcsr.o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S deleted file mode 100644 index c777eb1..0000000 --- a/board/freescale/mpc8568mds/init.S +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* TLB 1 Initializations */ - /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 2: 1G Non-cacheable, guarded - * 0x80000000 512M PCI1 MEM - * 0xa0000000 512M PCIe MEM - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 3: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 4: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) - .long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c new file mode 100644 index 0000000..225fc94 --- /dev/null +++ b/board/freescale/mpc8568mds/tlb.c @@ -0,0 +1,100 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 Initializations */ + /* + * TLBe 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH (upper half) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLBe 1: 16M Non-cacheable, guarded + * 0xfe000000 16M FLASH (lower half) + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* + * TLBe 2: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* + * TLBe 3: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_64M, 1), + + /* + * TLBe 4: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_64M, 1), + + /* + * TLBe 5: 256K Non-cacheable, guarded + * 0xf8000000 32K BCSR + * 0xf8008000 32K PIB (CS4) + * 0xf8010000 32K PIB (CS5) + */ + SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds index 7917409..6b30f15 100644 --- a/board/freescale/mpc8568mds/u-boot.lds +++ b/board/freescale/mpc8568mds/u-boot.lds @@ -37,7 +37,6 @@ SECTIONS .bootpg 0xFFFFF000: { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8568mds/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -67,7 +66,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8568mds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a12d193..04f442f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -50,6 +50,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID,
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/mpc8540eval/Makefile | 3 +- board/mpc8540eval/init.S | 137 ----------------------------------------- board/mpc8540eval/tlb.c | 78 +++++++++++++++++++++++ board/mpc8540eval/u-boot.lds | 2 - include/configs/MPC8540EVAL.h | 1 + 5 files changed, 80 insertions(+), 141 deletions(-) delete mode 100644 board/mpc8540eval/init.S create mode 100644 board/mpc8540eval/tlb.c
diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index c892247..28d6cb9 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o law.o -SOBJS := init.o +COBJS := $(BOARD).o flash.o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S deleted file mode 100644 index 93654a5..0000000 --- a/board/mpc8540eval/init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao X.Xiao@motorola.com -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - .long 0x0a /* the following data table uses a few of 16 TLB entries */ - - .long FSL_BOOKE_MAS0(1,1,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - #if defined(CFG_FLASH_PORT_WIDTH_16) - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - #if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - .long FSL_BOOKE_MAS0(1,6,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - #if defined(CONFIG_RAM_AS_FLASH) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G)) - #else - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0) - #endif - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,7,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - #ifdef CONFIG_L2_INIT_RAM - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) - #else - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) - #endif - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,8,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,9,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - entry_end diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c new file mode 100644 index 0000000..f041236 --- /dev/null +++ b/board/mpc8540eval/tlb.c @@ -0,0 +1,78 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + #if defined(CFG_FLASH_PORT_WIDTH_16) + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_4M, 1), + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_4M, 1), + #else + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + #endif + + #if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), + #endif + + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + #if defined(CONFIG_RAM_AS_FLASH) + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + #else + MAS3_SX|MAS3_SW|MAS3_SR, 0, + #endif + 0, 6, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16K, 1), + + SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_16K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds index 4b342c7..9bbba30 100644 --- a/board/mpc8540eval/u-boot.lds +++ b/board/mpc8540eval/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/mpc8540eval/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) @@ -143,7 +142,6 @@ SECTIONS .bootpg : { cpu/mpc85xx/start.o (.bootpg) - board/mpc8540eval/init.o (.bootpg) } = 0xffff
. = (. & 0xFFF80000) + 0x0007FFFC; diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index bf64f27..416cee4 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -44,6 +44,7 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/pm854/Makefile | 3 +- board/pm854/init.S | 198 ----------------------------------------------- board/pm854/tlb.c | 117 ++++++++++++++++++++++++++++ board/pm854/u-boot.lds | 2 - board/pm856/Makefile | 3 +- board/pm856/init.S | 198 ----------------------------------------------- board/pm856/tlb.c | 117 ++++++++++++++++++++++++++++ board/pm856/u-boot.lds | 2 - include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + 10 files changed, 238 insertions(+), 404 deletions(-) delete mode 100644 board/pm854/init.S create mode 100644 board/pm854/tlb.c delete mode 100644 board/pm856/init.S create mode 100644 board/pm856/tlb.c
diff --git a/board/pm854/Makefile b/board/pm854/Makefile index 0c8f470..be24388 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm854/init.S b/board/pm854/init.S deleted file mode 100644 index 770daa0..0000000 --- a/board/pm854/init.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c new file mode 100644 index 0000000..5d87537 --- /dev/null +++ b/board/pm854/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds index 9feaf55..86f8f13 100644 --- a/board/pm854/u-boot.lds +++ b/board/pm854/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/pm854/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/pm854/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/pm856/Makefile b/board/pm856/Makefile index 0c8f470..be24388 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm856/init.S b/board/pm856/init.S deleted file mode 100644 index 770daa0..0000000 --- a/board/pm856/init.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c new file mode 100644 index 0000000..5d87537 --- /dev/null +++ b/board/pm856/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds index c68f05a..6cfddea 100644 --- a/board/pm856/u-boot.lds +++ b/board/pm856/u-boot.lds @@ -36,7 +36,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/pm856/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -66,7 +65,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/pm856/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 819bee7..d881057 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 8902f42..48bbef6 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/sbc8548/Makefile | 3 +- board/sbc8548/init.S | 193 --------------------------------------------- board/sbc8548/tlb.c | 108 +++++++++++++++++++++++++ board/sbc8548/u-boot.lds | 2 - board/sbc8560/Makefile | 3 +- board/sbc8560/init.S | 120 ---------------------------- board/sbc8560/tlb.c | 65 +++++++++++++++ board/sbc8560/u-boot.lds | 2 - include/configs/SBC8540.h | 1 + include/configs/sbc8548.h | 1 + include/configs/sbc8560.h | 1 + 11 files changed, 178 insertions(+), 321 deletions(-) delete mode 100644 board/sbc8548/init.S create mode 100644 board/sbc8548/tlb.c delete mode 100644 board/sbc8560/init.S create mode 100644 board/sbc8560/tlb.c
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index c346fdf..4b2a9f6 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S deleted file mode 100644 index 162c326..0000000 --- a/board/sbc8548/init.S +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> - * Copyright 2007 Embedded Specialties, Inc. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - .section .bootpg, "ax" - .globl tlb1_entry - -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xe4010000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Cacheable, non-guarded - * 0x0 256M DDR SDRAM - */ - #if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 16M Cacheable, non-guarded - * 0xf8000000 1M 7-segment LED display - * 0xf8100000 1M User switches - * 0xf8300000 1M Board revision - * 0xf8b00000 1M EEPROM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c new file mode 100644 index 0000000..8d6625e --- /dev/null +++ b/board/sbc8548/tlb.c @@ -0,0 +1,108 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff800000 16M TLB for 8MB FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Cacheable, non-guarded + * 0x0 256M DDR SDRAM + */ + #if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 3, BOOKE_PAGESZ_256M, 1), + #endif + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 5: 64M Cacheable, non-guarded + * 0xf0000000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 16M Cacheable, non-guarded + * 0xf8000000 1M 7-segment LED display + * 0xf8100000 1M User switches + * 0xf8300000 1M Board revision + * 0xf8b00000 1M EEPROM + */ + SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds index 8e301d4..d701096 100644 --- a/board/sbc8548/u-boot.lds +++ b/board/sbc8548/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/sbc8548/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/sbc8548/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index c346fdf..4b2a9f6 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S deleted file mode 100644 index 3baa506..0000000 --- a/board/sbc8560/init.S +++ /dev/null @@ -1,120 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao X.Xiao@motorola.com -* -* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. -* Added support for Wind River SBC8560 board -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry - -tlb1_entry: - entry_start - - .long 0x08 /* the following data table uses a few of 16 TLB entries */ - -/* TLB for CCSRBAR (IMMR) */ - - .long FSL_BOOKE_MAS0(1,1,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -/* TLB for Local Bus stuff, just map the whole 512M */ -/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#else - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - .long FSL_BOOKE_MAS0(1,6,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) -#ifdef CONFIG_L2_INIT_RAM - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) -#else - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) -#endif - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,7,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#else - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - entry_end diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c new file mode 100644 index 0000000..155ff64 --- /dev/null +++ b/board/sbc8560/tlb.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { +/* TLB for CCSRBAR (IMMR) */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +/* TLB for Local Bus stuff, just map the whole 512M */ +/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ + + SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + + SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_16K, 1), + + SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index 449fed8..f3dbf26 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -38,7 +38,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/sbc8560/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -68,7 +67,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/sbc8560/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2bbfe9a..322b5fa 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -57,6 +57,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0a7a904..9c80a79 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -57,6 +57,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index f9ede5f..7761f51 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -51,6 +51,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/stxgp3/Makefile | 3 +- board/stxgp3/init.S | 219 ---------------------------------------------- board/stxgp3/tlb.c | 130 +++++++++++++++++++++++++++ board/stxgp3/u-boot.lds | 2 - board/stxssa/Makefile | 3 +- board/stxssa/init.S | 191 ---------------------------------------- board/stxssa/tlb.c | 106 ++++++++++++++++++++++ board/stxssa/u-boot.lds | 2 - include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + 10 files changed, 240 insertions(+), 418 deletions(-) delete mode 100644 board/stxgp3/init.S create mode 100644 board/stxgp3/tlb.c delete mode 100644 board/stxssa/init.S create mode 100644 board/stxssa/tlb.c
diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index c892247..28d6cb9 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o law.o -SOBJS := init.o +COBJS := $(BOARD).o flash.o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S deleted file mode 100644 index 8e1f16e..0000000 --- a/board/stxgp3/init.S +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2004 Embedded Edge, LLC - * Dan Malek dan@embeddededge.com - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560. We only support 32-bit flash - * and DDR with SPD EEPROM configuration. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) - .long FSL_BOOKE_MAS2(CFG_LBC_LCLDEVS_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_LCLDEVS_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c new file mode 100644 index 0000000..529f230 --- /dev/null +++ b/board/stxgp3/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xfc000000 16K Configuration Latch register + */ + SET_TLB_ENTRY(1, CFG_LBC_LCLDEVS_BASE, CFG_LBC_LCLDEVS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 3f9bc55..4a9a103 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -40,7 +40,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/stxgp3/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -70,7 +69,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/stxgp3/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile index c43dd4e..f1f5d0b 100644 --- a/board/stxssa/Makefile +++ b/board/stxssa/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/stxssa/init.S b/board/stxssa/init.S deleted file mode 100644 index d747946..0000000 --- a/board/stxssa/init.S +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2005 Embedded Alley Solutions, Inc. - * Dan Malek dan@embeddedalley.com - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA. We only support 32-bit flash - * and DDR with SPD EEPROM configuration. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 12 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - entry_end diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c new file mode 100644 index 0000000..46b1440 --- /dev/null +++ b/board/stxssa/tlb.c @@ -0,0 +1,106 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 6M4 FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xf0000000 Local bus expansion option. + * 0xfb000000 Configuration Latch register (one word) + * 0xfc000000 Up to 64M flash + */ + SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index a0ba125..99a8a8b 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -40,7 +40,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/stxssa/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -70,7 +69,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/stxssa/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 047e1cf..d6d4c46 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index e09dd71..21fb6f6 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx */
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/tqm85xx/Makefile | 3 +- board/tqm85xx/init.S | 178 --------------------------------------------- board/tqm85xx/tlb.c | 114 +++++++++++++++++++++++++++++ board/tqm85xx/u-boot.lds | 2 - include/configs/TQM85xx.h | 1 + 5 files changed, 116 insertions(+), 182 deletions(-) delete mode 100644 board/tqm85xx/init.S create mode 100644 board/tqm85xx/tlb.c
diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile index 66f2830..52f5ef9 100644 --- a/board/tqm85xx/Makefile +++ b/board/tqm85xx/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o sdram.o law.o -SOBJS := init.o +COBJS := $(BOARD).o sdram.o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S deleted file mode 100644 index f8b9fa2..0000000 --- a/board/tqm85xx/init.S +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc85xx.h> - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x4000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c new file mode 100644 index 0000000..a178cfe --- /dev/null +++ b/board/tqm85xx/tlb.c @@ -0,0 +1,114 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds index a8ca3c8..6c1f904 100644 --- a/board/tqm85xx/u-boot.lds +++ b/board/tqm85xx/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/tqm85xx/init.o (.bootpg) } = 0xffff
/* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/tqm85xx/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index dd0654b..e2e9964 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -51,6 +51,7 @@ #endif
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx
Now that all boards have been converted, remove old config code and the config option for the new style.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu_init.c | 20 -------------------- cpu/mpc85xx/tlb.c | 2 -- include/configs/ATUM8548.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/PM854.h | 1 - include/configs/PM856.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/stxgp3.h | 1 - include/configs/stxssa.h | 1 - 19 files changed, 0 insertions(+), 39 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 4e2bfe7..c0ff1d5 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -149,27 +149,7 @@ void cpu_init_early_f(void)
init_laws(); invalidate_tlb(0); -#ifdef CONFIG_FSL_INIT_TLBS init_tlbs(); -#else - { - extern u32 tlb1_entry; - u32 *tmp = &tlb1_entry; - int i; - int num = tmp[2]; - - /* skip to actual table */ - tmp += 3; - - for (i = 0; i < num; i++, tmp += 4) { - mtspr(MAS0, tmp[0]); - mtspr(MAS1, tmp[1]); - mtspr(MAS2, tmp[2]); - mtspr(MAS3, tmp[3]); - asm volatile("isync;msync;tlbwe;isync"); - } - } -#endif }
/* diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index b319ad4..b2c799a 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -79,7 +79,6 @@ void invalidate_tlb(u8 tlb)
void init_tlbs(void) { -#ifdef CONFIG_FSL_INIT_TLBS int i;
for (i = 0; i < num_tlb_entries; i++) { @@ -88,7 +87,6 @@ void init_tlbs(void) tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, tlb_table[i].iprot); } -#endif
return ; } diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c2dde41..c14376e 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -64,7 +64,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 74076fb..5ea7b25 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -56,7 +56,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 416cee4..bf64f27 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -44,7 +44,6 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 92195ed..7334088 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -48,7 +48,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 1269c8a..a894209 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -43,7 +43,6 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 77bcc29..a3db9f4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -56,7 +56,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e7b9694..93877ae 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -48,7 +48,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 84c517f..08884b3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -53,7 +53,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 04f442f..a12d193 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -50,7 +50,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/PM854.h b/include/configs/PM854.h index d881057..819bee7 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -52,7 +52,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 48bbef6..8902f42 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -52,7 +52,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 322b5fa..2bbfe9a 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -57,7 +57,6 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index e2e9964..dd0654b 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -51,7 +51,6 @@ #endif
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* * sysclk for MPC85xx diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 9c80a79..0a7a904 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -57,7 +57,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 7761f51..f9ede5f 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -51,7 +51,6 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index d6d4c46..047e1cf 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -52,7 +52,6 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 21fb6f6..e09dd71 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -52,7 +52,6 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx */
participants (1)
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Kumar Gala