[PATCH 00/13] x86: Various fixes for chromebooks
This adds some fixes for x86-based Chromebook builds which have picked up a few problems recently.
With this, chromebook_link, chromebook_samus and chromebook_coral work correctly. For chromebook_link64 a problem remains where it fails to jump into 64-bit U-Boot.
Simon Glass (13): Revert "buildman: Correct CROSS_COMPILE output for sandbox" buildman: Fix CROSS_COMPILE output for sandbox x86: samus: Drop EFI_LOADER x86: ivybridge: Ensure LPC is available for GPIO base x86: Support debug UART in 64-bit mode x86: Tidy up availability of string functions x86: mrc: Correct SPL debug message x86: spl: Show debugging for BSS sf: Guard against zero erasesize sf: Rename spi-nor-tiny functions dm: Emit the arch_cpu_init_dm() even only before relocation x86: Allow listing MTRRs in SPL x86: Add on to existing MTRRs in SPL
arch/arm/mach-imx/imx8/cpu.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/imx9/soc.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 2 +- arch/arm/mach-omap2/hwinit-common.c | 2 +- arch/mips/mach-pic32/cpu.c | 2 +- arch/nios2/cpu/cpu.c | 2 +- arch/riscv/cpu/cpu.c | 2 +- arch/x86/cpu/baytrail/cpu.c | 2 +- arch/x86/cpu/broadwell/cpu.c | 2 +- arch/x86/cpu/ivybridge/bd82x6x.c | 17 ++++---- arch/x86/cpu/ivybridge/cpu.c | 2 +- arch/x86/cpu/mtrr.c | 61 +++++++++++++++++++++++++++++ arch/x86/cpu/quark/quark.c | 2 +- arch/x86/cpu/x86_64/cpu.c | 7 ++++ arch/x86/include/asm/mtrr.h | 20 ++++++++++ arch/x86/include/asm/string.h | 6 ++- arch/x86/lib/Makefile | 4 +- arch/x86/lib/fsp2/fsp_init.c | 2 +- arch/x86/lib/mrccache.c | 2 +- arch/x86/lib/spl.c | 21 +++++++--- cmd/x86/mtrr.c | 60 ++-------------------------- configs/chromebook_link64_defconfig | 2 + configs/chromebook_samus_defconfig | 1 + doc/develop/event.rst | 6 +-- drivers/core/root.c | 4 +- drivers/cpu/microblaze_cpu.c | 2 +- drivers/mtd/spi/sf_probe.c | 3 +- drivers/mtd/spi/spi-nor-tiny.c | 16 ++++---- include/event.h | 2 +- tools/buildman/toolchain.py | 4 +- 32 files changed, 162 insertions(+), 104 deletions(-)
This reverts commit bd0a548ad4a155fec29473d4cc8e135832926973.
Signed-off-by: Simon Glass sjg@chromium.org ---
tools/buildman/toolchain.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 8f9130bdcdf6..688f2e268726 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -156,8 +156,9 @@ class Toolchain: Returns: Value of that environment variable or arguments """ + wrapper = self.GetWrapper() if which == VAR_CROSS_COMPILE: - return self.GetWrapper() + self.cross + return wrapper + os.path.join(self.path, self.cross) elif which == VAR_PATH: return self.path elif which == VAR_ARCH:
The previous attempt at fixing this broke the normal usage of the -A flag.
At present, 'buildman -A sandbox' adds the path containing the toolchain. We can assume that this is in the path and we don't want to set CROSS_COMPILE=/bin/
Change this to align with what MakeEnvironment() does, but only for sandbox boards.
Signed-off-by: Simon Glass sjg@chromium.org ---
tools/buildman/toolchain.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 688f2e268726..241e8e69307f 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -156,9 +156,10 @@ class Toolchain: Returns: Value of that environment variable or arguments """ - wrapper = self.GetWrapper() if which == VAR_CROSS_COMPILE: - return wrapper + os.path.join(self.path, self.cross) + wrapper = self.GetWrapper() + base = '' if self.arch == 'sandbox' else self.path + return wrapper + os.path.join(base, self.cross) elif which == VAR_PATH: return self.path elif which == VAR_ARCH:
This adds a lot of code so that it cannot be build with the binary blobs. It is not used on this board. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org ---
configs/chromebook_samus_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index b933a2352e3f..0d20891d2bcc 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -84,3 +84,4 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_TPM=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set
The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem.
In chromebook_link64 this propblem shows up as an inability to read the GPIO straps for the memory type.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/bd82x6x.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 89312a863499..417290f559e9 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; #define RCBA_AUDIO_CONFIG_HDA BIT(31) #define RCBA_AUDIO_CONFIG_MASK 0xfe
-#ifndef CONFIG_HAVE_FSP static int pch_revision_id = -1; static int pch_type = -1;
@@ -162,15 +161,19 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
static int bd82x6x_probe(struct udevice *dev) { - if (!(gd->flags & GD_FLG_RELOC)) - return 0; + /* make sure the LPC is inited since it provides the gpio base */ + uclass_first_device(UCLASS_LPC, &dev); + + if (!IS_ENABLED(CONFIG_HAVE_FSP)) { + if (!(gd->flags & GD_FLG_RELOC)) + return 0;
- /* Cause the SATA device to do its init */ - uclass_first_device(UCLASS_AHCI, &dev); + /* Cause the SATA device to do its init */ + uclass_first_device(UCLASS_AHCI, &dev); + }
return 0; } -#endif /* CONFIG_HAVE_FSP */
static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) { @@ -269,8 +272,6 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .name = "bd82x6x", .id = UCLASS_PCH, .of_match = bd82x6x_ids, -#ifndef CONFIG_HAVE_FSP .probe = bd82x6x_probe, -#endif .ops = &bd82x6x_pch_ops, };
The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/x86_64/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 6a387612916c..d1c3873dd6a7 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -50,3 +50,10 @@ int x86_cpu_init_f(void) { return 0; } + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* this was already done in SPL */ +} +#endif
For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/include/asm/string.h | 6 +++++- arch/x86/lib/Makefile | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index c15b264a5c08..5c49b0f009b7 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -14,7 +14,11 @@ extern char *strrchr(const char *s, int c); #undef __HAVE_ARCH_STRCHR extern char *strchr(const char *s, int c);
-#ifdef CONFIG_X86_64 +/* + * Our assembly routines do not work on in 64-bit mode and we don't do a lot of + * copying in SPL, so code size is more important there. + */ +#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT)
#undef __HAVE_ARCH_MEMCPY extern void *memcpy(void *, const void *, __kernel_size_t); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index a6f22441474b..b0612ae6dd5f 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,7 +10,9 @@ obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -obj-y += string.o +endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_X86_32BIT_INIT) += string.o endif ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o
SPL printf() does not normally support %#x so just use %x instead. Hex is expected in U-Boot anyway.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/lib/mrccache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 38632e513fce..2f6f6880003e 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -303,7 +303,7 @@ static int mrccache_save_type(enum mrc_type_t type) mrc = &gd->arch.mrc[type]; if (!mrc->len) return 0; - log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n", + log_debug("Saving %x bytes of MRC output data type %d to SPI flash\n", mrc->len, type); ret = mrccache_get_region(type, &sf, &entry); if (ret)
Show the area of memory cleared for BSS, when debugging is enabled.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/lib/spl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index bdf57ef7b5bd..eb0af219ae29 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -117,7 +117,9 @@ static int x86_spl_init(void) }
#ifndef CONFIG_SYS_COREBOOT - memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); + debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start, + (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start); + memset(&__bss_start, '\0', (ulong)&__bss_end - (ulong)&__bss_start); # ifndef CONFIG_TPL
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero error. Check for this and returns a proper error instead.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/mtd/spi/sf_probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index e192f97efdc4..de6516f1065b 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -189,7 +189,8 @@ static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) struct mtd_info *mtd = &flash->mtd; struct erase_info instr;
- if (offset % mtd->erasesize || len % mtd->erasesize) { + if (!mtd->erasesize || + (offset % mtd->erasesize || len % mtd->erasesize)) { debug("SF: Erase offset/length not multiple of erase size\n"); return -EINVAL; }
The 'tiny' SPI nor functions have the same name as their big brothers, which can be confusing. Use different names so it is clear which version is in the image.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/mtd/spi/spi-nor-tiny.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 68152ce3b4b9..7aa24e129f96 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -361,7 +361,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) * Erase an address range on the nor chip. The address range may extend * one or more erase sectors. Return an error is there is a problem erasing. */ -static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) +static int spi_nor_erase_tiny(struct mtd_info *mtd, struct erase_info *instr) { return -ENOTSUPP; } @@ -390,8 +390,8 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) return ERR_PTR(-EMEDIUMTYPE); }
-static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) +static int spi_nor_read_tiny(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; @@ -426,8 +426,8 @@ read_err: * FLASH_PAGESIZE chunks. The address range may be any size provided * it is within the physical boundaries. */ -static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) +static int spi_nor_write_tiny(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) { return -ENOTSUPP; } @@ -741,9 +741,9 @@ int spi_nor_scan(struct spi_nor *nor) mtd->writesize = 1; mtd->flags = MTD_CAP_NORFLASH; mtd->size = info->sector_size * info->n_sectors; - mtd->_erase = spi_nor_erase; - mtd->_read = spi_nor_read; - mtd->_write = spi_nor_write; + mtd->_erase = spi_nor_erase_tiny; + mtd->_read = spi_nor_read_tiny; + mtd->_write = spi_nor_write_tiny;
nor->size = mtd->size;
The original function was only called once, before relocation. The new one is called again after relocation. This was not the intend of the original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442f ("event: Convert arch_cpu_init_dm() to")
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-imx/imx8/cpu.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/imx9/soc.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 2 +- arch/arm/mach-omap2/hwinit-common.c | 2 +- arch/mips/mach-pic32/cpu.c | 2 +- arch/nios2/cpu/cpu.c | 2 +- arch/riscv/cpu/cpu.c | 2 +- arch/x86/cpu/baytrail/cpu.c | 2 +- arch/x86/cpu/broadwell/cpu.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 2 +- arch/x86/cpu/quark/quark.c | 2 +- arch/x86/lib/fsp2/fsp_init.c | 2 +- doc/develop/event.rst | 6 +++--- drivers/core/root.c | 4 ++-- drivers/cpu/microblaze_cpu.c | 2 +- include/event.h | 2 +- 18 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index be1f4edded10..99772f68c32b 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -89,7 +89,7 @@ static int imx8_init_mu(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu); +EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index df865e997d38..903620ad6a83 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -549,7 +549,7 @@ static int imx8m_check_clock(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); +EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
static void imx8m_setup_snvs(void) { diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 5d95fb89a61c..70142cbb0f4b 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -685,7 +685,7 @@ static int imx8ulp_check_mu(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu); +EVENT_SPY(EVT_DM_POST_INIT_F, imx8ulp_check_mu);
#if defined(CONFIG_SPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index a16e22ea6bbf..252663a9eec2 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -262,7 +262,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu); +EVENT_SPY(EVT_DM_POST_INIT_F, imx9_probe_mu);
int timer_init(void) { diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index a52d04d85c8a..ecc0a592e993 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -535,4 +535,4 @@ static int am33xx_dm_post_init(void *ctx, struct event *event) #endif return 0; } -EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init); +EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init); diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index c4a8eabc3ebe..771533394bcd 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -246,7 +246,7 @@ static int omap2_system_init(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init); +EVENT_SPY(EVT_DM_POST_INIT_F, omap2_system_init);
/* * Routine: wait_for_command_complete diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index de449e3c6a20..ec3c2505313c 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -102,7 +102,7 @@ static int pic32_flash_prefetch(void *ctx, struct event *event) prefetch_init(); return 0; } -EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch); +EVENT_SPY(EVT_DM_POST_INIT_F, pic32_flash_prefetch);
/* Un-gate DDR2 modules (gated by default) */ static void ddr2_pmd_ungate(void) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 85544503a5ee..da167f4b29e9 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -80,7 +80,7 @@ static int nios_cpu_setup(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup); +EVENT_SPY(EVT_DM_POST_INIT_F, nios_cpu_setup);
static int altera_nios2_get_desc(const struct udevice *dev, char *buf, int size) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index e1ed4ec01d04..ecfb1fb08c4b 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -145,7 +145,7 @@ int riscv_cpu_setup(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup); +EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
int arch_early_init_r(void) { diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 4fb6a485542f..4a7b4f617f8a 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -64,7 +64,7 @@ static int baytrail_uart_init(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init); +EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init);
static void set_max_freq(void) { diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 7877961451a6..f30aebfe4c62 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -40,7 +40,7 @@ static int broadwell_init_cpu(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu); +EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
void set_max_freq(void) { diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index cffc5d5b1d86..c988d7ff477f 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -86,7 +86,7 @@ static int ivybridge_cpu_init(void *ctx, struct event *ev)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init); +EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
#define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 0a1fbb34d40d..1be8e38cdf41 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -263,7 +263,7 @@ static int quark_init_pcie(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie); +EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie);
int checkcpu(void) { diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index b15926e8247b..afec7d08d67f 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -42,7 +42,7 @@ int fsp_setup_pinctrl(void *ctx, struct event *event)
return ret; } -EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl); +EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
#if !defined(CONFIG_TPL_BUILD) binman_sym_declare(ulong, intel_fsp_m, image_pos); diff --git a/doc/develop/event.rst b/doc/develop/event.rst index 4ff593483715..4c34fffc63bc 100644 --- a/doc/develop/event.rst +++ b/doc/develop/event.rst @@ -11,7 +11,7 @@ block device is probed. Rather than using weak functions and direct calls across subsystemss, it is often easier to use an event.
-An event consists of a type (e.g. EVT_DM_POST_INIT) and some optional data, +An event consists of a type (e.g. EVT_DM_POST_INIT_F) and some optional data, in `union event_data`. An event spy can be creasted to watch for events of a particular type. When the event is created, it is sent to each spy in turn.
@@ -26,9 +26,9 @@ To declare a spy, use something like this:: /* do something */ return 0; } - EVENT_SPY(EVT_DM_POST_INIT, snow_setup_cpus); + EVENT_SPY(EVT_DM_POST_INIT_F, snow_setup_cpus);
-Your function is called when EVT_DM_POST_INIT is emitted, i.e. after driver +Your function is called when EVT_DM_POST_INIT_F is emitted, i.e. after driver model is inited (in SPL, or in U-Boot proper before and after relocation).
diff --git a/drivers/core/root.c b/drivers/core/root.c index c4fb48548bb3..6775fb0b6575 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -436,8 +436,8 @@ int dm_init_and_scan(bool pre_reloc_only) return ret; } } - if (CONFIG_IS_ENABLED(DM_EVENT)) { - ret = event_notify_null(EVT_DM_POST_INIT); + if (CONFIG_IS_ENABLED(DM_EVENT) && !(gd->flags & GD_FLG_RELOC)) { + ret = event_notify_null(EVT_DM_POST_INIT_F); if (ret) return log_msg_ret("ev", ret); } diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c index b9d07928223f..c97a89fbd5c8 100644 --- a/drivers/cpu/microblaze_cpu.c +++ b/drivers/cpu/microblaze_cpu.c @@ -29,7 +29,7 @@ static int microblaze_cpu_probe_all(void *ctx, struct event *event)
return 0; } -EVENT_SPY(EVT_DM_POST_INIT, microblaze_cpu_probe_all); +EVENT_SPY(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci) { diff --git a/include/event.h b/include/event.h index e4580b683502..fe41080fa63b 100644 --- a/include/event.h +++ b/include/event.h @@ -22,7 +22,7 @@ enum event_t { EVT_TEST,
/* Events related to driver model */ - EVT_DM_POST_INIT, + EVT_DM_POST_INIT_F, EVT_DM_PRE_PROBE, EVT_DM_POST_PROBE, EVT_DM_PRE_REMOVE,
Move MTRR-listing code into a common file so it can be used from SPL. Update the 'mtrr' command to call it.
Use this in SPL just before adjusting the MTRRs, so we can see the state set up by the board. Only show it when debug is enabled.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/mtrr.c | 61 +++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 20 ++++++++++++ arch/x86/lib/spl.c | 7 +++++ cmd/x86/mtrr.c | 60 +++--------------------------------- 4 files changed, 92 insertions(+), 56 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index e69dfb552b16..1d3beee33555 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -30,6 +30,16 @@
DECLARE_GLOBAL_DATA_PTR;
+const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state, bool do_caches) { @@ -320,3 +330,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
return mtrr_start_op(cpu_select, &oper); } + +static void read_mtrrs_(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_read_all(info); +} + +int mtrr_list(int reg_count, int cpu_select) +{ + struct mtrr_info info; + int ret; + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + memset(&info, '\0', sizeof(info)); + ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info); + if (ret) + return log_msg_ret("run", ret); + for (i = 0; i < reg_count; i++) { + const char *type = "Invalid"; + uint64_t base, mask, size; + bool valid; + + base = info.mtrr[i].base; + mask = info.mtrr[i].mask; + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, + mask & ~MTRR_PHYS_MASK_VALID, size); + } + + return 0; +} + +int mtrr_get_type_by_name(const char *typename) +{ + int i; + + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + return i; + } + + return -EINVAL; +}; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index ca2edc7878f7..2e995f540616 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); */ int mtrr_get_var_count(void);
+/** + * mtrr_list() - List the MTRRs + * + * Shows a list of all the MTRRs including their values + * + * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for + * this + * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU + * Returns: 0 if OK, -ve if the CPU was not found + */ +int mtrr_list(int reg_count, int cpu_select); + +/** + * mtrr_get_type_by_name() - Get the type of an MTRR given its type name + * + * @typename: Name to check + * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid + */ +int mtrr_get_type_by_name(const char *typename); + #endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index eb0af219ae29..0f2319ccc212 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -19,6 +19,7 @@ #include <asm/cpu_common.h> #include <asm/fsp2/fsp_api.h> #include <asm/global_data.h> +#include <asm/mp.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -139,6 +140,12 @@ static int x86_spl_init(void) arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr;
+ if (_LOG_DEBUG) { + ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); + if (ret) + printf("mtrr_list failed\n"); + } + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ ret = mtrr_add_request(MTRR_TYPE_WRBACK, (1ULL << 32) - CONFIG_XIP_ROM_SIZE, diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index b213a942fde4..c1880c7806e6 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -10,71 +10,19 @@ #include <asm/mp.h> #include <asm/mtrr.h>
-static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { - "Uncacheable", - "Combine", - "2", - "3", - "Through", - "Protect", - "Back", -}; - -static void read_mtrrs(void *arg) -{ - struct mtrr_info *info = arg; - - mtrr_read_all(info); -} - -static int do_mtrr_list(int reg_count, int cpu_select) -{ - struct mtrr_info info; - int ret; - int i; - - printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", - "Mask ||", "Size ||"); - memset(&info, '\0', sizeof(info)); - ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info); - if (ret) - return log_msg_ret("run", ret); - for (i = 0; i < reg_count; i++) { - const char *type = "Invalid"; - uint64_t base, mask, size; - bool valid; - - base = info.mtrr[i].base; - mask = info.mtrr[i].mask; - size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); - size |= (1 << 12) - 1; - size += 1; - valid = mask & MTRR_PHYS_MASK_VALID; - type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; - printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, - valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, - mask & ~MTRR_PHYS_MASK_VALID, size); - } - - return 0; -} - static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) { const char *typename = argv[0]; uint32_t start, size; uint64_t base, mask; - int i, type = -1; + int type = -1; bool valid; int ret;
if (argc < 3) return CMD_RET_USAGE; - for (i = 0; i < MTRR_TYPE_COUNT; i++) { - if (*typename == *mtrr_type_name[i]) - type = i; - } - if (type == -1) { + type = mtrr_get_type_by_name(typename); + if (type < 0) { printf("Invalid type name %s\n", typename); return CMD_RET_USAGE; } @@ -146,7 +94,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, if (!first) printf("\n"); printf("CPU %d:\n", i); - ret = do_mtrr_list(reg_count, i); + ret = mtrr_list(reg_count, i); if (ret) { printf("Failed to read CPU %d (err=%d)\n", i, ret);
We don't actually set up all of these registers in SPL, so using mtrr_commit() with erase some. Use mtrr_set_next_var() instead.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/lib/spl.c | 10 +++++----- configs/chromebook_link64_defconfig | 2 ++ 2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 0f2319ccc212..88d7e1424174 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -147,14 +147,14 @@ static int x86_spl_init(void) }
/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ - ret = mtrr_add_request(MTRR_TYPE_WRBACK, + mtrr_set_next_var(MTRR_TYPE_WRBACK, (1ULL << 32) - CONFIG_XIP_ROM_SIZE, CONFIG_XIP_ROM_SIZE); - if (ret) { - debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret); - return ret; + if (_LOG_DEBUG) { + ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); + if (ret) + printf("mtrr_list failed\n"); } - mtrr_commit(true); # else ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); if (ret) diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 8c75d654290b..192cbbecbe0e 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -69,6 +69,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y # CONFIG_ACPIGEN is not set CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y @@ -88,6 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_VIDEO_IVYBRIDGE_IGD=y CONFIG_CONSOLE_SCROLL_LINES=5 +# CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y # CONFIG_GZIP is not set
participants (1)
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Simon Glass