This is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/power/mfd/Makefile | 1 - drivers/power/mfd/fg_max77693.c | 137 -------------------------------- 2 files changed, 138 deletions(-) delete mode 100644 drivers/power/mfd/fg_max77693.c

diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile index a8eb7f81e72..5dfbdbd1b0f 100644 --- a/drivers/power/mfd/Makefile +++ b/drivers/power/mfd/Makefile @@ -5,4 +5,3 @@

obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o -obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o diff --git a/drivers/power/mfd/fg_max77693.c b/drivers/power/mfd/fg_max77693.c deleted file mode 100644 index 983a6d4a2bd..00000000000 --- a/drivers/power/mfd/fg_max77693.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek p.wilczek@samsung.com - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_fg.h> -#include <i2c.h> -#include <power/power_chrg.h> -#include <power/battery.h> -#include <power/fg_battery_cell_params.h> -#include <errno.h> - -static int max77693_get_vcell(u32 *vcell) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *vcell = (u32)(value >> 3); - *vcell = *vcell * 625; - - return 0; -} - -static int max77693_get_soc(u32 *soc) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *soc = (u32)(value >> 8); - - return 0; -} - -static int power_update_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - int ret; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = max77693_get_soc(&pb->bat->state_of_chrg); - if (ret) - return ret; - - max77693_get_vcell(&pb->bat->voltage_uV); - - return 0; -} - -static int power_check_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = pmic_reg_read(p, MAX77693_STATUS, &val); - if (ret) - return ret; - debug("fg status: 0x%x\n", val); - - ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version); - if (ret) - return ret; - - ret = power_update_battery(p, bat); - if (ret) - return ret; - debug("fg ver: 0x%x\n", pb->bat->version); - printf("BAT: state_of_charge(SOC):%d%%\n", - pb->bat->state_of_chrg); - - printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", - pb->bat->voltage_uV / 1000000, - pb->bat->voltage_uV % 1000000, - pb->bat->capacity); - - if (pb->bat->voltage_uV > 3850000) - pb->bat->state = EXT_SOURCE; - else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) - pb->bat->state = CHARGE; - else - pb->bat->state = NORMAL; - - return 0; -} - -static struct power_fg power_fg_ops = { - .fg_battery_check = power_check_battery, - .fg_battery_update = power_update_battery, -}; - -int power_fg_init(unsigned char bus) -{ - static const char name[] = "MAX77693_FG"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Fuel Gauge init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = FG_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR; - p->hw.i2c.tx_num = 2; - p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; - p->bus = bus; - - p->fg = &power_fg_ops; - - return 0; -}

Drop this driver and the associated CONFIG option, as it is not used.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/power/mfd/Makefile | 1 - drivers/power/mfd/pmic_max77693.c | 96 ------------------------------- 2 files changed, 97 deletions(-) delete mode 100644 drivers/power/mfd/pmic_max77693.c

diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile index 5dfbdbd1b0f..b5ec8f00bb0 100644 --- a/drivers/power/mfd/Makefile +++ b/drivers/power/mfd/Makefile @@ -3,5 +3,4 @@ # Copyright (C) 2013 Samsung Electronics # Piotr Wilczek p.wilczek@samsung.com

-obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c deleted file mode 100644 index e32a9722a40..00000000000 --- a/drivers/power/mfd/pmic_max77693.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek p.wilczek@samsung.com - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_pmic.h> -#include <i2c.h> -#include <errno.h> - -static int max77693_charger_state(struct pmic *p, int state, int current) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - /* unlock write capability */ - val = MAX77693_CHG_UNLOCK; - pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); - - if (state == PMIC_CHARGER_DISABLE) { - puts("Disable the charger.\n"); - pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); - val &= ~0x01; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - return -ENOTSUPP; - } - - if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) { - printf("%s: Wrong charge current: %d [mA]\n", - __func__, current); - return -EINVAL; - } - - /* set charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= ~MAX77693_CHG_CC; - val |= current * 10 / 333; /* 0.1A/3 steps */ - pmic_reg_write(p, MAX77693_CHG_CNFG_02, val); - - /* enable charging */ - val = MAX77693_CHG_MODE_ON; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - - /* check charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= 0x3f; - printf("Enable the charger @ %d [mA]\n", val * 333 / 10); - - return 0; -} - -static int max77693_charger_bat_present(struct pmic *p) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - pmic_reg_read(p, MAX77693_CHG_INT_OK, &val); - - return !(val & MAX77693_CHG_DETBAT); -} - -static struct power_chrg power_chrg_pmic_ops = { - .chrg_bat_present = max77693_charger_bat_present, - .chrg_state = max77693_charger_state, -}; - -int pmic_init_max77693(unsigned char bus) -{ - static const char name[] = "MAX77693_PMIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board PMIC init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_pmic_ops; - - return 0; -}

This is not defined anywhere. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Makefile b/Makefile index 9c38cc29e9d..debe691c39e 100644 --- a/Makefile +++ b/Makefile @@ -1528,8 +1528,7 @@ MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_TEXT_BASE) u-boot.ubl: u-boot-with-spl.bin FORCE $(call if_changed,mkimage)

-MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ - $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ +MKIMAGEFLAGS_u-boot-spl.ais = -s -n "/dev/null" \ -T aisimage -e $(CONFIG_SPL_TEXT_BASE) spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage)

This is not used anywhere. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/sandbox/config.mk | 2 -- 1 file changed, 2 deletions(-)

diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 1284ef390b5..2d184c5f652 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -44,8 +44,6 @@ cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ -Wl,--no-whole-archive \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)

-CONFIG_ARCH_DEVICE_TREE := sandbox - ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds EFI_TARGET := --target=efi-app-x86_64

This is not defined anywhere. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Stefan Roese sr@denx.de ---

(no changes since v1)

arch/arm/mach-mvebu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 28d3e5e1052..a9f506cf2fb 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -38,7 +38,7 @@ extra-y += kwbimage.cfg ifneq ($(CONFIG_ARMADA_XP),) KWB_REPLACE += CPU KWB_CFG_CPU = SHEEVA -else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),) +else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X),) KWB_REPLACE += CPU KWB_CFG_CPU = A9 endif

This option does not exist and should refer to CONFIG_ROCKCHIP_BOOT_MODE_REG instead. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/arm/mach-rockchip/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 32138fa723f..e3d4a8b42e4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)

# Always include boot_mode.o, as we bypass it (i.e. turn it off) -# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, +# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o

This is not used anywhere. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

cmd/Makefile | 1 - cmd/mfsl.c | 387 --------------------------------------------------- 2 files changed, 388 deletions(-) delete mode 100644 cmd/mfsl.c

diff --git a/cmd/Makefile b/cmd/Makefile index 0b6a96c1d91..4adc7530a0a 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -108,7 +108,6 @@ obj-$(CONFIG_ID_EEPROM) += mac.o obj-$(CONFIG_CMD_MD5SUM) += md5sum.o obj-$(CONFIG_CMD_MEMORY) += mem.o obj-$(CONFIG_CMD_IO) += io.o -obj-$(CONFIG_CMD_MFSL) += mfsl.o obj-$(CONFIG_CMD_MII) += mii.o obj-$(CONFIG_CMD_MISC) += misc.o obj-$(CONFIG_CMD_MDIO) += mdio.o diff --git a/cmd/mfsl.c b/cmd/mfsl.c deleted file mode 100644 index 0c78720ec46..00000000000 --- a/cmd/mfsl.c +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK monstr@monstr.eu - */ - -/* - * Microblaze FSL support - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <asm/asm.h> - -int do_frd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int fslnum; - unsigned int num; - unsigned int blocking; - - if (argc < 2) - return CMD_RET_USAGE; - - fslnum = (unsigned int)hextoul(argv[1], NULL); - blocking = (unsigned int)hextoul(argv[2], NULL); - if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { - puts ("Bad number of FSL\n"); - return CMD_RET_USAGE; - } - - switch (fslnum) { -#if (XILINX_FSL_NUMBER > 0) - case 0: - switch (blocking) { - case 0: NGET (num, 0); - break; - case 1: NCGET (num, 0); - break; - case 2: GET (num, 0); - break; - case 3: CGET (num, 0); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 1) - case 1: - switch (blocking) { - case 0: NGET (num, 1); - break; - case 1: NCGET (num, 1); - break; - case 2: GET (num, 1); - break; - case 3: CGET (num, 1); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 2) - case 2: - switch (blocking) { - case 0: NGET (num, 2); - break; - case 1: NCGET (num, 2); - break; - case 2: GET (num, 2); - break; - case 3: CGET (num, 2); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 3) - case 3: - switch (blocking) { - case 0: NGET (num, 3); - break; - case 1: NCGET (num, 3); - break; - case 2: GET (num, 3); - break; - case 3: CGET (num, 3); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 4) - case 4: - switch (blocking) { - case 0: NGET (num, 4); - break; - case 1: NCGET (num, 4); - break; - case 2: GET (num, 4); - break; - case 3: CGET (num, 4); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 5) - case 5: - switch (blocking) { - case 0: NGET (num, 5); - break; - case 1: NCGET (num, 5); - break; - case 2: GET (num, 5); - break; - case 3: CGET (num, 5); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 6) - case 6: - switch (blocking) { - case 0: NGET (num, 6); - break; - case 1: NCGET (num, 6); - break; - case 2: GET (num, 6); - break; - case 3: CGET (num, 6); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 7) - case 7: - switch (blocking) { - case 0: NGET (num, 7); - break; - case 1: NCGET (num, 7); - break; - case 2: GET (num, 7); - break; - case 3: CGET (num, 7); - break; - default: - return 2; - } - break; -#endif - default: - return 1; - } - - printf ("%01x: 0x%08x - %s %s read\n", fslnum, num, - blocking < 2 ? "non blocking" : "blocking", - ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); - return 0; -} - -int do_fwr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int fslnum; - unsigned int num; - unsigned int blocking; - - if (argc < 3) - return CMD_RET_USAGE; - - fslnum = (unsigned int)hextoul(argv[1], NULL); - num = (unsigned int)hextoul(argv[2], NULL); - blocking = (unsigned int)hextoul(argv[3], NULL); - if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) - return CMD_RET_USAGE; - - switch (fslnum) { -#if (XILINX_FSL_NUMBER > 0) - case 0: - switch (blocking) { - case 0: NPUT (num, 0); - break; - case 1: NCPUT (num, 0); - break; - case 2: PUT (num, 0); - break; - case 3: CPUT (num, 0); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 1) - case 1: - switch (blocking) { - case 0: NPUT (num, 1); - break; - case 1: NCPUT (num, 1); - break; - case 2: PUT (num, 1); - break; - case 3: CPUT (num, 1); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 2) - case 2: - switch (blocking) { - case 0: NPUT (num, 2); - break; - case 1: NCPUT (num, 2); - break; - case 2: PUT (num, 2); - break; - case 3: CPUT (num, 2); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 3) - case 3: - switch (blocking) { - case 0: NPUT (num, 3); - break; - case 1: NCPUT (num, 3); - break; - case 2: PUT (num, 3); - break; - case 3: CPUT (num, 3); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 4) - case 4: - switch (blocking) { - case 0: NPUT (num, 4); - break; - case 1: NCPUT (num, 4); - break; - case 2: PUT (num, 4); - break; - case 3: CPUT (num, 4); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 5) - case 5: - switch (blocking) { - case 0: NPUT (num, 5); - break; - case 1: NCPUT (num, 5); - break; - case 2: PUT (num, 5); - break; - case 3: CPUT (num, 5); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 6) - case 6: - switch (blocking) { - case 0: NPUT (num, 6); - break; - case 1: NCPUT (num, 6); - break; - case 2: PUT (num, 6); - break; - case 3: CPUT (num, 6); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 7) - case 7: - switch (blocking) { - case 0: NPUT (num, 7); - break; - case 1: NCPUT (num, 7); - break; - case 2: PUT (num, 7); - break; - case 3: CPUT (num, 7); - break; - default: - return 2; - } - break; -#endif - default: - return 1; - } - - printf ("%01x: 0x%08x - %s %s write\n", fslnum, num, - blocking < 2 ? "non blocking" : "blocking", - ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); - return 0; - -} - -int do_rspr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int reg = 0; - unsigned int val = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - reg = (unsigned int)hextoul(argv[1], NULL); - val = (unsigned int)hextoul(argv[2], NULL); - switch (reg) { - case 0x1: - if (argc > 2) { - MTS (val, rmsr); - NOP; - MFS (val, rmsr); - } else { - MFS (val, rmsr); - } - puts ("MSR"); - break; - case 0x3: - MFS (val, rear); - puts ("EAR"); - break; - case 0x5: - MFS (val, resr); - puts ("ESR"); - break; - default: - puts ("Unsupported register\n"); - return 1; - } - printf (": 0x%08x\n", val); - return 0; -} - -/***************************************************/ - -U_BOOT_CMD (frd, 3, 1, do_frd, - "read data from FSL", - "- [fslnum [0|1|2|3]]\n" - " 0 - non blocking data read\n" - " 1 - non blocking control read\n" - " 2 - blocking data read\n" - " 3 - blocking control read"); - -U_BOOT_CMD (fwr, 4, 1, do_fwr, - "write data to FSL", - "- [fslnum [0|1|2|3]]\n" - " 0 - non blocking data write\n" - " 1 - non blocking control write\n" - " 2 - blocking data write\n" - " 3 - blocking control write"); - -U_BOOT_CMD (rspr, 3, 1, do_rspr, - "read/write special purpose register", - "- reg_num [write value] read/write special purpose register\n" - " 1 - MSR - Machine status register\n" - " 3 - EAR - Exception address register\n" - " 5 - ESR - Exception status register");

This is not used. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

cmd/Makefile | 1 - cmd/dataflash_mmc_mux.c | 48 ----------------------------------------- 2 files changed, 49 deletions(-) delete mode 100644 cmd/dataflash_mmc_mux.c

diff --git a/cmd/Makefile b/cmd/Makefile index 4adc7530a0a..b6888a52f49 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_CMD_CONFIG) += config.o obj-$(CONFIG_CMD_CONITRACE) += conitrace.o obj-$(CONFIG_CMD_CONSOLE) += console.o obj-$(CONFIG_CMD_CPU) += cpu.o -obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o obj-$(CONFIG_CMD_DATE) += date.o obj-$(CONFIG_CMD_DEMO) += demo.o obj-$(CONFIG_CMD_DM) += dm.o diff --git a/cmd/dataflash_mmc_mux.c b/cmd/dataflash_mmc_mux.c deleted file mode 100644 index 73876e9464a..00000000000 --- a/cmd/dataflash_mmc_mux.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <command.h> - -static int mmc_nspi (const char *); - -int do_dataflash_mmc_mux(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - switch (argc) { - case 2: /* on / off */ - switch (mmc_nspi (argv[1])) { - case 0: AT91F_SelectSPI (); - break; - case 1: AT91F_SelectMMC (); - break; - } - case 1: /* get status */ - printf ("Mux is configured to be %s\n", - AT91F_GetMuxStatus () ? "MMC" : "SPI"); - return 0; - default: - return CMD_RET_USAGE; - } - return 0; -} - -static int mmc_nspi (const char *s) -{ - if (strcmp (s, "mmc") == 0) { - return 1; - } else if (strcmp (s, "spi") == 0) { - return 0; - } - return -1; -} - -U_BOOT_CMD( - dataflash_mmc_mux, 2, 1, do_dataflash_mmc_mux, - "enable or disable MMC or SPI\n", - "[mmc, spi]\n" - " - enable or disable MMC or SPI" -);

This appears in a comment but is not a real option. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile index debe691c39e..400261606e3 100644 --- a/Makefile +++ b/Makefile @@ -1082,7 +1082,7 @@ expect = $(foreach cfg,$(1),y)

# Show a deprecation message # Args: -# 1: List of CONFIG_DM_... to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK") +# 1: List of options to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK") # 2: Name of component (e.g . "Ethernet drivers") # 3: Release deadline (e.g. "v202.07") # 4: Condition to require before checking (e.g. "$(CONFIG_NET)")

This is not defined anywhere. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/video/exynos/Makefile | 1 - 1 file changed, 1 deletion(-)

diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile index 0f58954e49c..45067f562cb 100644 --- a/drivers/video/exynos/Makefile +++ b/drivers/video/exynos/Makefile @@ -7,4 +7,3 @@ obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o -obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o

There is no Kconfig option for this code, but it seems to be useful. Add one.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/fpga/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 2034d0ebd9c..61490d6d8de 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA

This provides common functionality for Gen5 and Arria10 devices.

+config FPGA_STRATIX_II + bool "Enable Stratix II FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix II FPGA-specific driver. + config FPGA_STRATIX_V bool "Enable Stratix V FPGA drivers" depends on FPGA_ALTERA

Drop this unused code.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

board/freescale/common/Makefile | 1 - board/freescale/common/pixis.c | 470 -------------------------------- board/freescale/common/pixis.h | 54 ---- 3 files changed, 525 deletions(-) delete mode 100644 board/freescale/common/pixis.c delete mode 100644 board/freescale/common/pixis.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index cc1371867d8..fc51d6d3e18 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,7 +29,6 @@ endif obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o -obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c deleted file mode 100644 index 7096b107e54..00000000000 --- a/board/freescale/common/pixis.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006,2010 Freescale Semiconductor - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> - -#define pixis_base (u8 *)PIXIS_BASE - -/* - * Simple board reset. - */ -void pixis_reset(void) -{ - out_8(pixis_base + PIXIS_RST, 0); - - while (1); -} - -/* - * Per table 27, page 58 of MPC8641HPCN spec. - */ -static int set_px_sysclk(unsigned long sysclk) -{ - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - - switch (sysclk) { - case 33: - sysclk_s = 0x04; - sysclk_r = 0x04; - sysclk_v = 0x07; - sysclk_aux = 0x00; - break; - case 40: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x20; - sysclk_aux = 0x01; - break; - case 50: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x2A; - sysclk_aux = 0x02; - break; - case 66: - sysclk_s = 0x01; - sysclk_r = 0x04; - sysclk_v = 0x04; - sysclk_aux = 0x03; - break; - case 83: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x04; - break; - case 100: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x5C; - sysclk_aux = 0x05; - break; - case 134: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x3B; - sysclk_aux = 0x06; - break; - case 166: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x07; - break; - default: - printf("Unsupported SYSCLK frequency.\n"); - return 0; - } - - vclkh = (sysclk_s << 5) | sysclk_r; - vclkl = sysclk_v; - - out_8(pixis_base + PIXIS_VCLKH, vclkh); - out_8(pixis_base + PIXIS_VCLKL, vclkl); - - out_8(pixis_base + PIXIS_AUX, sysclk_aux); - - return 1; -} - -/* Set the CFG_SYSPLL bits - * - * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if - * read_from_px_regs() is called. - */ -static int set_px_mpxpll(unsigned long mpxpll) -{ - switch (mpxpll) { - case 2: - case 4: - case 6: - case 8: - case 10: - case 12: - case 14: - case 16: - clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); - return 1; - } - - printf("Unsupported MPXPLL ratio.\n"); - return 0; -} - -static int set_px_corepll(unsigned long corepll) -{ - u8 val; - - switch (corepll) { - case 20: - val = 0x08; - break; - case 25: - val = 0x0C; - break; - case 30: - val = 0x10; - break; - case 35: - val = 0x1C; - break; - case 40: - val = 0x14; - break; - case 45: - val = 0x0E; - break; - default: - printf("Unsupported COREPLL ratio.\n"); - return 0; - } - - clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); - return 1; -} - -#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE -#define CFG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C -#endif - -/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or various other PIXIS registers to determine the values for COREPLL, - * MPXPLL, and SYSCLK. - * - * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 - * register that tells the pixis to use the various PIXIS register. - */ -static void read_from_px_regs(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN0, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1 - * register that tells the pixis to use the PX_VBOOT[LBMAP] register. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE -#define CFG_SYS_PIXIS_VBOOT_ENABLE 0x04 -#endif - -/* Configure the source of the boot location - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or the PX_VBOOT[LBMAP] register to determine where we should boot. - * - * If we want to boot from the alternate boot bank, we need to tell the PIXIS - * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. - */ -static void read_from_px_regs_altbank(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN1, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that - * tells the PIXIS what the alternate flash bank is. - * - * Note that it's not really a mask. It contains the actual LBMAP bits that - * must be set to select the alternate bank. This code assumes that the - * primary bank has these bits set to 0, and the alternate bank has these - * bits set to 1. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_MASK -#define CFG_SYS_PIXIS_VBOOT_MASK (0x40) -#endif - -/* Tell the PIXIS to boot from the default flash bank - * - * Program the default flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void clear_altbank(void) -{ - clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Tell the PIXIS to boot from the alternate flash bank - * - * Program the alternate flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void set_altbank(void) -{ - setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Reset the board with watchdog disabled. - * - * This respects the altbank setting. - */ -static void set_px_go(void) -{ - /* Disable the VELA sequencer and watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - /* Reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x1); - - while (1); -} - -/* Reset the board with watchdog enabled. - * - * This respects the altbank setting. - */ -static void set_px_go_with_watchdog(void) -{ - /* Disable the VELA sequencer */ - clrbits_8(pixis_base + PIXIS_VCTL, 1); - - /* Enable the watchdog and reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x9); - - while (1); -} - -/* Disable the watchdog - * - */ -static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* Disable the VELA sequencer and the watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - return 0; -} - -U_BOOT_CMD( - diswd, 1, 0, pixis_disable_watchdog_cmd, - "Disable watchdog timer", - "" -); - -/* - * This function takes the non-integral cpu:mpx pll ratio - * and converts it to an integer that can be used to assign - * FPGA register values. - * input: strptr i.e. argv[2] - */ -static unsigned long strfractoint(char *strptr) -{ - int i, j; - int mulconst; - int no_dec = 0; - unsigned long intval = 0, decval = 0; - char intarr[3], decarr[3]; - - /* Assign the integer part to intarr[] - * If there is no decimal point i.e. - * if the ratio is an integral value - * simply create the intarr. - */ - i = 0; - while (strptr[i] != '.') { - if (strptr[i] == 0) { - no_dec = 1; - break; - } - intarr[i] = strptr[i]; - i++; - } - - intarr[i] = '\0'; - - if (no_dec) { - /* Currently needed only for single digit corepll ratios */ - mulconst = 10; - decval = 0; - } else { - j = 0; - i++; /* Skipping the decimal point */ - while ((strptr[i] >= '0') && (strptr[i] <= '9')) { - decarr[j] = strptr[i]; - i++; - j++; - } - - decarr[j] = '\0'; - - mulconst = 1; - for (i = 0; i < j; i++) - mulconst *= 10; - decval = dectoul(decarr, NULL); - } - - intval = dectoul(intarr, NULL); - intval = intval * mulconst; - - return intval + decval; -} - -static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned int i; - char *p_cf = NULL; - char *p_cf_sysclk = NULL; - char *p_cf_corepll = NULL; - char *p_cf_mpxpll = NULL; - char *p_altbank = NULL; - char *p_wd = NULL; - int unknown_param = 0; - - /* - * No args is a simple reset request. - */ - if (argc <= 1) { - pixis_reset(); - /* not reached */ - } - - for (i = 1; i < argc; i++) { - if (strcmp(argv[i], "cf") == 0) { - p_cf = argv[i]; - if (i + 3 >= argc) { - break; - } - p_cf_sysclk = argv[i+1]; - p_cf_corepll = argv[i+2]; - p_cf_mpxpll = argv[i+3]; - i += 3; - continue; - } - - if (strcmp(argv[i], "altbank") == 0) { - p_altbank = argv[i]; - continue; - } - - if (strcmp(argv[i], "wd") == 0) { - p_wd = argv[i]; - continue; - } - - unknown_param = 1; - } - - /* - * Check that cf has all required parms - */ - if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll)) - || unknown_param) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - - /* - * PIXIS seems to be sensitive to the ordering of - * the registers that are touched. - */ - read_from_px_regs(0); - - if (p_altbank) - read_from_px_regs_altbank(0); - - clear_altbank(); - - /* - * Clock configuration specified. - */ - if (p_cf) { - unsigned long sysclk; - unsigned long corepll; - unsigned long mpxpll; - - sysclk = dectoul(p_cf_sysclk, NULL); - corepll = strfractoint(p_cf_corepll); - mpxpll = dectoul(p_cf_mpxpll, NULL); - - if (!(set_px_sysclk(sysclk) - && set_px_corepll(corepll) - && set_px_mpxpll(mpxpll))) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - read_from_px_regs(1); - } - - /* - * Altbank specified - * - * NOTE CHANGE IN BEHAVIOR: previous code would default - * to enabling watchdog if altbank is specified. - * Now the watchdog must be enabled explicitly using 'wd'. - */ - if (p_altbank) { - set_altbank(); - read_from_px_regs_altbank(1); - } - - /* - * Reset with watchdog specified. - */ - if (p_wd) - set_px_go_with_watchdog(); - else - set_px_go(); - - /* - * Shouldn't be reached. - */ - return 0; -} - - -U_BOOT_CMD( - pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "Reset the board using the FPGA sequencer", - " pixis_reset\n" - " pixis_reset [altbank]\n" - " pixis_reset altbank wd\n" - " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" - " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>" -); diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h deleted file mode 100644 index f19e85cb1c9..00000000000 --- a/board/freescale/common/pixis.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - */ -#ifndef __PIXIS_H_ -#define __PIXIS_H_ 1 - -/* PIXIS register set. */ -#if defined(CONFIG_TARGET_MPC8536DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 rst2; - u8 aux1; - u8 spd; - u8 aux2; - u8 csr2; - u8 watch; - u8 led; - u8 pwr; - u8 res[3]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[3]; - u8 sclk[3]; - u8 dclk[3]; - u8 i2cdacr; - u8 vcoreacc[4]; - u8 vcorecnt[3]; - u8 vcoremax[2]; - u8 vplatacc[4]; - u8 vplatcnt[3]; - u8 vplatmax[2]; - u8 vtempacc[4]; - u8 vtempcnt[3]; - u8 vtempmax[2]; - u8 res2[4]; -} __attribute__ ((packed)) pixis_t; -#else -#error Need to define pixis_t for this board -#endif - -/* Pointer to the PIXIS register set */ -#define pixis ((pixis_t *)PIXIS_BASE) - -#endif /* __PIXIS_H_ */

Drop this unused driver.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/arm/mach-rmobile/Makefile | 1 - arch/arm/mach-rmobile/timer.c | 87 ---------------------------------- 2 files changed, 88 deletions(-) delete mode 100644 arch/arm/mach-rmobile/timer.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 195bbeb5c88..3f77760e50d 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -7,7 +7,6 @@ obj-y = cpu_info.o obj-y += emac.o

obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o -obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c deleted file mode 100644 index 293c23b5e25..00000000000 --- a/arch/arm/mach-rmobile/timer.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <div64.h> -#include <init.h> -#include <time.h> -#include <asm/io.h> -#include <asm/arch-armv7/globaltimer.h> -#include <asm/arch/rmobile.h> -#include <linux/delay.h> - -static struct globaltimer *global_timer = \ - (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR; - -#define CLK2MHZ(clk) (clk / 1000 / 1000) -static u64 get_cpu_global_timer(void) -{ - u32 low, high; - u64 timer; - - u32 old = readl(&global_timer->cnt_h); - while (1) { - low = readl(&global_timer->cnt_l); - high = readl(&global_timer->cnt_h); - if (old == high) - break; - else - old = high; - } - - timer = high; - return (u64)((timer << 32) | low); -} - -static u64 get_time_us(void) -{ - u64 timer = get_cpu_global_timer(); - - timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); - return timer; -} - -static ulong get_time_ms(void) -{ - u64 us = get_time_us(); - - do_div(us, 1000); - return us; -} - -int timer_init(void) -{ - writel(0x01, &global_timer->ctl); - return 0; -} - -void __udelay(unsigned long usec) -{ - u64 start, current; - u64 wait; - - start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); - do { - current = get_cpu_global_timer(); - } while ((current - start) < wait); -} - -ulong get_timer(ulong base) -{ - return get_time_ms() - base; -} - -unsigned long long get_ticks(void) -{ - return get_cpu_global_timer(); -} - -ulong get_tbclk(void) -{ - return (ulong)(CFG_SYS_CPU_CLK >> 2); -}

This option does not exist, so the Makefile rule does nothing. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/arm/cpu/arm920t/Makefile | 2 -- 1 file changed, 2 deletions(-)

diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index b70822c67ab..5ac3740621c 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -7,8 +7,6 @@ extra-y = start.o

obj-y += cpu.o

-obj-$(CONFIG_IMX) += imx/ - # some files can only build in ARM mode

ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD

This is not used since this commit:

3cf02f5ffa4 imx6: remove not longer supported aristainetos boards

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/video/Makefile | 1 - drivers/video/lg4573.c | 331 ----------------------------------------- 2 files changed, 332 deletions(-) delete mode 100644 drivers/video/lg4573.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 40a871d638e..12b68cdd068 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o -obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c deleted file mode 100644 index dd87fc461b9..00000000000 --- a/drivers/video/lg4573.c +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * LCD: LG4573, TFT 4.3", 480x800, RGB24 - * LCD initialization via SPI - * - */ -#include <common.h> -#include <backlight.h> -#include <command.h> -#include <display.h> -#include <dm.h> -#include <log.h> -#include <dm/read.h> -#include <dm/uclass-internal.h> -#include <errno.h> -#include <spi.h> -#include <asm/gpio.h> -#include <linux/delay.h> - -#define PWR_ON_DELAY_MSECS 120 - -static int lb043wv_spi_write_u16(struct spi_slave *slave, u16 val) -{ - unsigned short buf16 = htons(val); - int ret = 0; - - ret = spi_xfer(slave, 16, &buf16, NULL, - SPI_XFER_BEGIN | SPI_XFER_END); - if (ret) - debug("%s: Failed to send: %d\n", __func__, ret); - - return ret; -} - -static void lb043wv_spi_write_u16_array(struct spi_slave *slave, u16 *buff, - int size) -{ - int i; - - for (i = 0; i < size; i++) - lb043wv_spi_write_u16(slave, buff[i]); -} - -static void lb043wv_display_mode_settings(struct spi_slave *slave) -{ - static u16 display_mode_settings[] = { - 0x703A, - 0x7270, - 0x70B1, - 0x7208, - 0x723B, - 0x720F, - 0x70B2, - 0x7200, - 0x72C8, - 0x70B3, - 0x7200, - 0x70B4, - 0x7200, - 0x70B5, - 0x7242, - 0x7210, - 0x7210, - 0x7200, - 0x7220, - 0x70B6, - 0x720B, - 0x720F, - 0x723C, - 0x7213, - 0x7213, - 0x72E8, - 0x70B7, - 0x7246, - 0x7206, - 0x720C, - 0x7200, - 0x7200, - }; - - debug("transfer display mode settings\n"); - lb043wv_spi_write_u16_array(slave, display_mode_settings, - ARRAY_SIZE(display_mode_settings)); -} - -static void lb043wv_power_settings(struct spi_slave *slave) -{ - static u16 power_settings[] = { - 0x70C0, - 0x7201, - 0x7211, - 0x70C3, - 0x7207, - 0x7203, - 0x7204, - 0x7204, - 0x7204, - 0x70C4, - 0x7212, - 0x7224, - 0x7218, - 0x7218, - 0x7202, - 0x7249, - 0x70C5, - 0x726F, - 0x70C6, - 0x7241, - 0x7263, - }; - - debug("transfer power settings\n"); - lb043wv_spi_write_u16_array(slave, power_settings, - ARRAY_SIZE(power_settings)); -} - -static void lb043wv_gamma_settings(struct spi_slave *slave) -{ - static u16 gamma_settings[] = { - 0x70D0, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D1, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D2, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D3, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D4, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D5, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - }; - - debug("transfer gamma settings\n"); - lb043wv_spi_write_u16_array(slave, gamma_settings, - ARRAY_SIZE(gamma_settings)); -} - -static void lb043wv_display_on(struct spi_slave *slave) -{ - static u16 sleep_out = 0x7011; - static u16 display_on = 0x7029; - - lb043wv_spi_write_u16(slave, sleep_out); - mdelay(PWR_ON_DELAY_MSECS); - lb043wv_spi_write_u16(slave, display_on); -} - -static int lg4573_spi_startup(struct spi_slave *slave) -{ - int ret; - - ret = spi_claim_bus(slave); - if (ret) - return ret; - - lb043wv_display_mode_settings(slave); - lb043wv_power_settings(slave); - lb043wv_gamma_settings(slave); - lb043wv_display_on(slave); - - spi_release_bus(slave); - return 0; -} - -static int do_lgset(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct spi_slave *slave; - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(lg4573_lcd), &dev); - if (ret) { - printf("%s: Could not get lg4573 device\n", __func__); - return ret; - } - slave = dev_get_parent_priv(dev); - if (!slave) { - printf("%s: No slave data\n", __func__); - return -ENODEV; - } - lg4573_spi_startup(slave); - - return 0; -} - -U_BOOT_CMD( - lgset, 2, 1, do_lgset, - "set lgdisplay", - "" -); - -static int lg4573_bind(struct udevice *dev) -{ - return 0; -} - -static int lg4573_probe(struct udevice *dev) -{ - return 0; -} - -static const struct udevice_id lg4573_ids[] = { - { .compatible = "lg,lg4573" }, - { } -}; - -struct lg4573_lcd_priv { - struct display_timing timing; - struct udevice *backlight; - struct gpio_desc enable; - int panel_bpp; - u32 power_on_delay; -}; - -static int lg4573_lcd_read_timing(struct udevice *dev, - struct display_timing *timing) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - - memcpy(timing, &priv->timing, sizeof(struct display_timing)); - - return 0; -} - -static int lg4573_lcd_enable(struct udevice *dev, int bpp, - const struct display_timing *edid) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret = 0; - - dm_gpio_set_value(&priv->enable, 1); - ret = backlight_enable(priv->backlight); - - mdelay(priv->power_on_delay); - lg4573_spi_startup(slave); - - return ret; -}; - -static const struct dm_display_ops lg4573_lcd_ops = { - .read_timing = lg4573_lcd_read_timing, - .enable = lg4573_lcd_enable, -}; - -static int lg4573_of_to_plat(struct udevice *dev) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret; - - ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, - "backlight", &priv->backlight); - if (ret) { - debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); - } - ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, - GPIOD_IS_OUT); - if (ret) { - debug("%s: Warning: cannot get enable GPIO: ret=%d\n", - __func__, ret); - if (ret != -ENOENT) - return log_ret(ret); - } - - priv->power_on_delay = dev_read_u32_default(dev, "power-on-delay", 10); - - return 0; -} - -U_BOOT_DRIVER(lg4573_lcd) = { - .name = "lg4573", - .id = UCLASS_DISPLAY, - .ops = &lg4573_lcd_ops, - .of_to_plat = lg4573_of_to_plat, - .of_match = lg4573_ids, - .bind = lg4573_bind, - .probe = lg4573_probe, - .priv_auto = sizeof(struct lg4573_lcd_priv), -};

CONFIG options must not use lower-case letter. Convert this to upper case.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/m68k/Kconfig | 4 ++-- arch/m68k/Makefile | 2 +- arch/m68k/cpu/mcf532x/cpu.c | 2 +- arch/m68k/cpu/mcf532x/cpu_init.c | 4 ++-- arch/m68k/cpu/mcf532x/speed.c | 12 ++++++------ arch/m68k/cpu/mcf532x/start.S | 2 +- arch/m68k/include/asm/cache.h | 2 +- arch/m68k/include/asm/immap.h | 2 +- arch/m68k/include/asm/immap_5301x.h | 2 +- board/freescale/m53017evb/README | 6 +++--- 10 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 76233ef563f..af5540f14a4 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -32,7 +32,7 @@ config MCF530x select DM_SERIAL bool

-config MCF5301x +config MCF5301X select OF_CONTROL select DM select DM_SERIAL @@ -95,7 +95,7 @@ config M5307

config M53015 bool - select MCF5301x + select MCF5301X

config M5329 bool diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 4a7960bbeb4..21e5337d309 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -14,7 +14,7 @@ cpuflags-$(CONFIG_M5272) := -mcpu=5272 cpuflags-$(CONFIG_M5275) := -mcpu=5275 cpuflags-$(CONFIG_M5282) := -mcpu=5282 cpuflags-$(CONFIG_M5307) := -mcpu=5307 -cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC +cpuflags-$(CONFIG_MCF5301X) := -mcpu=53015 -fPIC cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC

diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 548cbca36aa..96a9a422f3a 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -46,7 +46,7 @@ int print_cpuinfo(void) msk = (in_be16(&ccm->cir) >> 6); ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { -#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X case 0x78: id = 53010; break; diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 844d2cd7600..c12cb310e62 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -21,7 +21,7 @@ #include <asm/fec.h> #endif

-#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X void cpu_init_f(void) { scm1_t *scm1 = (scm1_t *) MMAP_SCM1; @@ -207,7 +207,7 @@ int fecpin_setclear(fec_info_t *info, int setclear) return 0; } #endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_MCF5301x */ +#endif /* CONFIG_MCF5301X */

#ifdef CONFIG_MCF532x void cpu_init_f(void) diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index 32ffac08135..24b2f937aeb 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MAX_FSYS 80000 /* KHz */ #define MIN_FSYS 58333 /* KHz */

-#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X #define FREF 20000 /* KHz */ #define MAX_MFD 63 /* Multiplier */ #define MIN_MFD 0 /* Multiplier */ @@ -58,14 +58,14 @@ int get_sys_clock(void) /* Test to see if device is in LIMP mode */ if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); -#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X return (FREF / (3 * (1 << divider))); #endif #ifdef CONFIG_MCF532x return (FREF / (2 << divider)); #endif } else { -#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; @@ -151,7 +151,7 @@ int clock_pll(int fsys, int flags)

if (fsys == 0) { /* Return current PLL output */ -#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; mfd = (in_be32(&pll->pcr) & 0x3F) + 1;

@@ -178,7 +178,7 @@ int clock_pll(int fsys, int flags) * point libraries. */ temp = (100 * fsys) / fref; -#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X mfd = (BUSDIV * temp) / 100;

/* Determine the output frequency for selected values */ @@ -209,7 +209,7 @@ int clock_pll(int fsys, int flags) /* Enter LIMP mode */ clock_limp(DEFAULT_LPD);

-#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X out_be32(&pll->pdr, PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | PLL_PDR_OUTDIV2(BUSDIV - 1) | diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 72a2f99b7dd..442a91f73ac 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -112,7 +112,7 @@ _start: movec %d0, %ACR0 movec %d0, %ACR1

-#ifdef CONFIG_MCF5301x +#ifdef CONFIG_MCF5301X move.l #(0xFC0a0010), %a0 move.w (%a0), %d0 and.l %d0, 0xEFFF diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 8ed2b4dbab4..78ff04fe29b 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -15,7 +15,7 @@ #endif

#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ - defined(CONFIG_MCF5301x) + defined(CONFIG_MCF5301X) #define CFG_CF_V3 #endif

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 8207c8d5b73..ec270fcf579 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -210,7 +210,7 @@ #endif #endif /* CONFIG_M5307 */

-#if defined(CONFIG_MCF5301x) +#if defined(CONFIG_MCF5301X) #include <asm/immap_5301x.h> #include <asm/m5301x.h>

diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index e1f7858b100..6bfd5c7a840 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * MCF5301x Internal Memory Map + * MCF5301X Internal Memory Map * * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 34f05f3fdc7..9c14f836cbf 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -58,12 +58,12 @@ Changed files: - arch/m68k/lib/time.c Timer functions (Dma timer and PIT) - arch/m68k/lib/traps.c Exception init code

-1 MCF5301x specific Options/Settings +1 MCF5301X specific Options/Settings ==================================== 1.1 pre-loader is no longer suppoer in thie coldfire family

1.2 Configuration settings for M53017EVB Development Board -CONFIG_MCF5301x -- define for all MCF5301x CPUs +CONFIG_MCF5301X -- define for all MCF5301X CPUs CONFIG_M53015 -- define for MCF53015 CPUs CONFIG_M53017EVB -- define for M53017EVB board

@@ -100,7 +100,7 @@ CFG_SYS_MBAR -- define MBAR offset

CONFIG_MONITOR_IS_IN_RAM -- Not support

-CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301X internal SRAM

CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register

CONFIG options must not use lower-case letter. Convert this to upper case.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/m68k/Kconfig | 4 ++-- arch/m68k/Makefile | 4 ++-- arch/m68k/cpu/mcf5445x/cpu_init.c | 12 ++++++------ arch/m68k/cpu/mcf5445x/dspi.c | 4 ++-- arch/m68k/cpu/mcf5445x/speed.c | 4 ++-- arch/m68k/cpu/mcf5445x/start.S | 8 ++++---- arch/m68k/include/asm/cache.h | 4 ++-- arch/m68k/include/asm/global_data.h | 2 +- arch/m68k/include/asm/immap_5441x.h | 2 +- drivers/mmc/fsl_esdhc_imx.c | 12 ++++++------ 10 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 6781ba28c7a..4e2a9075b10 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -50,7 +50,7 @@ config MCF537x select DM_SERIAL bool

-config MCF5441x +config MCF5441X select OF_CONTROL select DM select DM_SERIAL @@ -108,7 +108,7 @@ config M5373

config M54418 bool - select MCF5441x + select MCF5441X

# peripherals config CF_DSPI diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index cf4562c55f1..b44726242d2 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -16,12 +16,12 @@ cpuflags-$(CONFIG_M5282) := -mcpu=5282 cpuflags-$(CONFIG_M5307) := -mcpu=5307 cpuflags-$(CONFIG_MCF5301X) := -mcpu=53015 -fPIC cpuflags-$(CONFIG_MCF532X) := -mcpu=5329 -fPIC -cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC +cpuflags-$(CONFIG_MCF5441X) := -mcpu=54418 -fPIC

PLATFORM_CPPFLAGS += $(cpuflags-y)

-ldflags-$(CONFIG_MCF5441x) := --got=single +ldflags-$(CONFIG_MCF5441X) := --got=single

ifneq (,$(findstring -linux-,$(shell $(CC) --version))) ifneq (,$(findstring GOT,$(shell $(LD) --help))) diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 1ce244872f1..a70ecfbae73 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -73,7 +73,7 @@ void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *)MMAP_GPIO;

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X pm_t *pm = (pm_t *)MMAP_PM;

out_8(&gpio->par_dspi0, @@ -98,7 +98,7 @@ void cpu_init_f(void) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X scm_t *scm = (scm_t *) MMAP_SCM; pm_t *pm = (pm_t *) MMAP_PM;

@@ -203,7 +203,7 @@ void cpu_init_f(void) out_8(&gpio->par_sdhch, 0xff); out_8(&gpio->par_sdhcl, 0xff); #endif -#endif /* CONFIG_MCF5441x */ +#endif /* CONFIG_MCF5441X */

/* FlexBus Chipselect */ init_fbcs(); @@ -240,13 +240,13 @@ int cpu_init_r(void) void uart_port_conf(int port) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X pm_t *pm = (pm_t *) MMAP_PM; #endif

/* Setup Ports: */ switch (port) { -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X case 0: /* UART0 */ out_8(&pm->pmcr0, 24); @@ -340,7 +340,7 @@ int fecpin_setclear(fec_info_t *info, int setclear) if (fec_get_base_addr(0, &fec0_base)) return -1;

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X if (setclear) { out_8(&gpio->par_fec, 0x03); out_8(&gpio->srcr_fec, 0x0F); diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c index 456af171a4e..628be0c8bbb 100644 --- a/arch/m68k/cpu/mcf5445x/dspi.c +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -15,7 +15,7 @@ void dspi_chip_select(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X switch (cs) { case 0: clrbits_8(&gpio->par_dspi0, @@ -37,7 +37,7 @@ void dspi_chip_unselect(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X if (cs == 1) clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index eb73da68c6b..59a6625a4fd 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -63,7 +63,7 @@ void clock_exit_limp(void) ; }

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X void setup_5441x_clocks(void) { ccm_t *ccm = (ccm_t *)MMAP_CCM; @@ -125,7 +125,7 @@ void setup_5441x_clocks(void) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X setup_5441x_clocks(); #endif

diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index a083c3d45d2..baf39127b29 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -167,7 +167,7 @@ asm_dram_init: #endif #endif /* CONFIG_CF_SBF */

-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X /* TC: enable all peripherals, in the future only enable certain peripherals */ move.l #0xFC04002D, %a1 @@ -175,7 +175,7 @@ asm_dram_init: #if defined(CONFIG_CF_SBF) move.b #23, (%a1) /* dspi */ #endif -#endif /* CONFIG_MCF5441x */ +#endif /* CONFIG_MCF5441X */

/* mandatory board level ddr-sdram init, * for both 5441x and 5445x @@ -193,7 +193,7 @@ asm_dram_init: */ /* Enable pins for DSPI mode - chip-selects are enabled later */ asm_dspi_init: -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X move.l #0xEC09404E, %a1 move.l #0xEC09404F, %a2 move.b #0xFF, (%a1) @@ -205,7 +205,7 @@ asm_dspi_init: move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */

move.l #0xFC05C00C, %a0 -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X move.l #0x3E000016, (%a0) #endif

diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 4acd677c676..52d12a68144 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -19,7 +19,7 @@ #define CFG_CF_V3 #endif

-#if defined(CONFIG_MCF5441x) +#if defined(CONFIG_MCF5441X) #define CFG_CF_V4E /* Four Extra ACRn */ #endif

@@ -94,7 +94,7 @@ #define CF_CACR_IDSP (1 << 7) #define CF_CACR_EUSP (1 << 5)

-#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) +#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441X) #define CF_CACR_IVO (1 << 20) #define CF_CACR_SPA (1 << 14) #else diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 273e843c4ae..d63fb8130c4 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -20,7 +20,7 @@ struct arch_global_data { unsigned long vco_clk; unsigned long flb_clk; #endif -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X unsigned long sdhc_clk; #endif }; diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h index 708d0db755a..1beb14ad53b 100644 --- a/arch/m68k/include/asm/immap_5441x.h +++ b/arch/m68k/include/asm/immap_5441x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * MCF5441x Internal Memory Map + * MCF5441X Internal Memory Map * * Copyright 2010-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 66caf683f74..da888885474 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -383,7 +383,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, return 0; }

-#if IS_ENABLED(CONFIG_MCF5441x) +#if IS_ENABLED(CONFIG_MCF5441X) /* * Swaps 32-bit words to little-endian byte order. */ @@ -553,7 +553,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, dma_unmap_single(priv->dma_addr, data->blocks * data->blocksize, mmc_get_dma_dir(data)); - if (IS_ENABLED(CONFIG_MCF5441x) && + if (IS_ENABLED(CONFIG_MCF5441X) && (data->flags & MMC_DATA_READ)) sd_swap_dma_buff(data); } @@ -1026,7 +1026,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

/* Put the PROCTL reg back to the default */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); else esdhc_write32(&regs->proctl, PROCTL_INIT); @@ -1168,7 +1168,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, return ret;

/* ColdFire, using SDHC_DATA[3] for card detection */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);

if (IS_ENABLED(CONFIG_FSL_USDHC)) { @@ -1194,11 +1194,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, caps = esdhc_read32(&regs->hostcapblt);

/* - * MCF5441x RM declares in more points that sdhc clock speed must + * MCF5441X RM declares in more points that sdhc clock speed must * never exceed 25 Mhz. From this, the HS bit needs to be disabled * from host capabilities. */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) caps &= ~HOSTCAPBLT_HSS;

if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))

This option does not exist, so the #ifdefs do nothing. Drop this code.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/arm/lib/debug.S | 21 --------------------- 1 file changed, 21 deletions(-)

diff --git a/arch/arm/lib/debug.S b/arch/arm/lib/debug.S index 5983f2c04ce..af4beb4d9d2 100644 --- a/arch/arm/lib/debug.S +++ b/arch/arm/lib/debug.S @@ -21,22 +21,10 @@ #include CONFIG_DEBUG_LL_INCLUDE #endif

-#ifdef CONFIG_MMU - .macro addruart_current, rx, tmp1, tmp2 - addruart \tmp1, \tmp2, \rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 - moveq \rx, \tmp1 - movne \rx, \tmp2 - .endm - -#else /* !CONFIG_MMU */ .macro addruart_current, rx, tmp1, tmp2 addruart \rx, \tmp1, \tmp2 .endm

-#endif /* CONFIG_MMU */ - /* * Useful debugging routines */ @@ -97,15 +85,6 @@ ENTRY(printch) b 1b ENDPROC(printch)

-#ifdef CONFIG_MMU -ENTRY(debug_ll_addr) - addruart r2, r3, ip - str r2, [r0] - str r3, [r1] - mov pc, lr -ENDPROC(debug_ll_addr) -#endif - #else

ENTRY(printascii)

CONFIG options must not use lower-case letter. Convert this to upper case.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de ---

(no changes since v1)

api/api_platform-powerpc.c | 2 +- arch/Kconfig | 2 +- arch/powerpc/Kconfig | 8 ++++---- arch/powerpc/cpu/Makefile | 2 +- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++-- arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/start.S | 2 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 2 +- arch/powerpc/include/asm/fsl_dma.h | 4 ++-- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 14 +++++++------- arch/powerpc/include/asm/ppc.h | 6 +++--- arch/powerpc/include/asm/processor.h | 4 ++-- arch/powerpc/lib/bdinfo.c | 2 +- board/freescale/mpc837xerdb/README | 2 +- board/keymile/Kconfig | 4 ++-- board/keymile/km83xx/Kconfig | 2 +- configs/MPC837XERDB_defconfig | 2 +- configs/gazerbeam_defconfig | 2 +- configs/kmcoge5ne_defconfig | 2 +- configs/kmeter1_defconfig | 2 +- configs/kmopti2_defconfig | 2 +- configs/kmsupx5_defconfig | 2 +- configs/kmtepr2_defconfig | 2 +- configs/tuge1_defconfig | 2 +- configs/tuxx1_defconfig | 2 +- drivers/clk/Kconfig | 4 ++-- drivers/clk/mpc83xx_clk.c | 4 ++-- drivers/clk/mpc83xx_clk.h | 20 ++++++++++---------- drivers/cpu/Kconfig | 6 +++--- drivers/cpu/mpc83xx_cpu.c | 14 +++++++------- drivers/cpu/mpc83xx_cpu.h | 8 ++++---- drivers/ddr/fsl/Kconfig | 4 ++-- drivers/ddr/fsl/main.c | 2 +- drivers/dma/fsl_dma.c | 16 ++++++++-------- drivers/gpio/mpc83xx_gpio.c | 2 +- drivers/misc/Kconfig | 4 ++-- drivers/misc/mpc83xx_serdes.c | 4 ++-- drivers/mtd/nand/raw/fsl_elbc_spl.c | 2 +- drivers/ram/Kconfig | 2 +- drivers/ram/mpc83xx_sdram.c | 2 +- drivers/spi/mpc8xxx_spi.c | 2 +- drivers/sysreset/Kconfig | 4 ++-- drivers/timer/Kconfig | 4 ++-- drivers/timer/mpc83xx_timer.c | 2 +- env/Kconfig | 2 +- include/asm-generic/u-boot.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/linux/immap_qe.h | 2 +- include/serial.h | 2 +- post/Makefile | 2 +- 52 files changed, 103 insertions(+), 103 deletions(-)

diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 847a4a3015b..8503ba274d6 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -31,7 +31,7 @@ int platform_sys_info(struct sys_info *si)

#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base -#elif defined(CONFIG_MPC83xx) +#elif defined(CONFIG_MPC83XX) #define bi_bar bi_immrbar #endif

diff --git a/arch/Kconfig b/arch/Kconfig index d30676ae817..79044531fab 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -370,7 +370,7 @@ config SYS_IMMR depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A default 0xFF000000 if MPC8xx default 0xF0000000 if ARCH_MPC8313 - default 0xE0000000 if MPC83xx && !ARCH_MPC8313 + default 0xE0000000 if MPC83XX && !ARCH_MPC8313 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e0801c25941..eb39a03e997 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -8,8 +8,8 @@ choice prompt "CPU select" optional

-config MPC83xx - bool "MPC83xx" +config MPC83XX + bool "MPC83XX" select CREATE_ARCH_SYMLINK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -36,7 +36,7 @@ endchoice

config FSL_LBC def_bool y - depends on (MPC85xx || MPC83xx) && !FSL_IFC + depends on (MPC85xx || MPC83XX) && !FSL_IFC

config HIGH_BATS bool "Enable high BAT registers" @@ -46,7 +46,7 @@ config HIGH_BATS

config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" - depends on MPC83xx || MPC85xx + depends on MPC83XX || MPC85xx

config SYS_SRIO bool "Serial RapidIO support" diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile index e7f64059277..c56f0d78b2d 100644 --- a/arch/powerpc/cpu/Makefile +++ b/arch/powerpc/cpu/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_MPC83xx) += mpc8xxx/ +obj-$(CONFIG_MPC83XX) += mpc8xxx/ obj-$(CONFIG_MPC85xx) += mpc8xxx/ obj-$(CONFIG_MPC86xx) += mpc8xxx/ diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b695c7e4d81..1969117a25b 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -1,5 +1,5 @@ menu "mpc83xx CPU" - depends on MPC83xx + depends on MPC83XX

config DEFAULT_IMMR hex @@ -90,7 +90,7 @@ endchoice config MPC83XX_QUICC_ENGINE bool

-# TODO: Imply MPC83xx PCI driver +# TODO: Imply MPC83XX PCI driver config MPC83XX_PCI_SUPPORT bool

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index a6c063556e8..5e58023bfa8 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -4,7 +4,7 @@ */

/* - * CPU specific code for the MPC83xx family. + * CPU specific code for the MPC83XX family. * * Derived from the MPC8260 and MPC85xx. */ diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index e3878e431fb..032871313d1 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -7,7 +7,7 @@ */

/* - * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards + * U-Boot - Startup Code for MPC83XX PowerPC based Embedded Boards */

#include <asm-offsets.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 29489b46e6c..7519b214969 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -8,7 +8,7 @@ #include <init.h> #include <asm/fsl_lbc.h>

-#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX #include "../mpc83xx/elbc/elbc.h" #endif

diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 1459db74bee..fbf61ecae20 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -10,7 +10,7 @@

#include <asm/types.h>

-#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX typedef struct fsl_dma { uint mr; /* DMA mode register */ #define FSL_DMA_MR_CS 0x00000001 /* Channel start */ @@ -111,7 +111,7 @@ typedef struct fsl_dma { uint dsr; /* DMA destination stride register */ char res4[56]; } fsl_dma_t; -#endif /* !CONFIG_MPC83xx */ +#endif /* !CONFIG_MPC83XX */

#ifdef CONFIG_FSL_DMA void dma_init(void); diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index a03f091c305..8d681a1cba6 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -324,7 +324,7 @@ void lbc_sdram_init(void); */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 -#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \ +#if defined(CONFIG_MPC83XX) || defined(CONFIG_ARCH_MPC8540) || \ defined(CONFIG_ARCH_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 6ed21c781fe..2636cbbda88 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -21,7 +21,7 @@ struct arch_global_data { unsigned long brg_clk; #endif /* TODO: sjg@chromium.org: Should these be unslgned long? */ -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) #ifdef CONFIG_CLK_MPC83XX u32 core_clk; #else @@ -57,7 +57,7 @@ struct arch_global_data { u32 lbc_clk; void *cpu; #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) u32 i2c1_clk; u32 i2c2_clk; @@ -75,7 +75,7 @@ struct arch_global_data { u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; #endif unsigned long reset_status; /* reset status register at boot */ -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) unsigned long arbiter_event_attributes; unsigned long arbiter_event_address; #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 24bd438c143..3ba73113f0b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -2,7 +2,7 @@ /* * Copyright 2004-2011 Freescale Semiconductor, Inc. * - * MPC83xx Internal Memory Map + * MPC83XX Internal Memory Map * * Contributors: * Dave Liu daveliu@freescale.com @@ -864,12 +864,12 @@ struct ccsr_gpio { #define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000) #define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) -#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000) -#define CFG_SYS_MPC83xx_DMA_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET) -#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) -#define CFG_SYS_MPC83xx_ESDHC_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET) +#define CFG_SYS_MPC83XX_DMA_OFFSET (0x8000) +#define CFG_SYS_MPC83XX_DMA_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC83XX_DMA_OFFSET) +#define CFG_SYS_MPC83XX_ESDHC_OFFSET (0x2e000) +#define CFG_SYS_MPC83XX_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC83XX_ESDHC_OFFSET)

#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)

diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 2923350bd7b..3b13f7ff166 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -19,7 +19,7 @@ #include <mpc85xx.h> #include <asm/immap_85xx.h> #endif -#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX #include <mpc83xx.h> #include <asm/immap_83xx.h> #endif @@ -52,7 +52,7 @@ static inline uint get_svr(void)

#if defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || \ - defined(CONFIG_MPC83xx) + defined(CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); unsigned short in16(unsigned int); @@ -68,7 +68,7 @@ void ppcDcbi(unsigned long value); void ppcSync(void); void ppcDcbz(unsigned long value); #endif -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) void ppcDWload(unsigned int *addr, unsigned int *ret); void ppcDWstore(unsigned int *addr, unsigned int *value); void disable_addr_trans(void); diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f7e1a807746..d80b7d75563 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1004,7 +1004,7 @@ #if defined(CONFIG_MPC85xx) #define IS_E_PROCESSOR(svr) (svr & 0x80000) #else -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) #endif #endif @@ -1163,7 +1163,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core); #define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) } #else -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} #endif #endif diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index 55dcad5df8e..81cbcf988ff 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -20,7 +20,7 @@ int arch_setup_bdinfo(void) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif

-#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) bd->bi_immrbar = CONFIG_SYS_IMMR; #endif

diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README index 12df2f2e756..79accdbe7a9 100644 --- a/board/freescale/mpc837xerdb/README +++ b/board/freescale/mpc837xerdb/README @@ -52,7 +52,7 @@ Freescale MPC837xE-RDB Board

include/configs/MPC837XERDB.h

- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC83XX MPC83XX family for both MPC8349 and MPC8360 CONFIG_MPC837x MPC837x specific CONFIG_MPC837XERDB MPC837xE-RDB board specific

diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index bf899d005c4..a24d17cf8bf 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -34,7 +34,7 @@ config KM_PHRAM

config KM_RESERVED_PRAM hex "Reserved RAM" - default 0x0 if MPC83xx + default 0x0 if MPC83XX default 0x1000 if MPC85xx || ARCH_LS1021A depends on !ARCH_SOCFPGA help @@ -78,7 +78,7 @@ config SYS_CLIPS_BASE

config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" - default y if MPC83xx + default y if MPC83XX default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A help Use the Ethernet initialization implemented in common code that diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index f87a2e64163..149a2395777 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -1,5 +1,5 @@ menu "KM 83xx Options" - depends on MPC83xx + depends on MPC83XX

config KM_ENABLE_FULL_DM_DTS_SUPPORT bool "enable full DM/DTS support for KM 83xx boards" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7287ca6b247..87c89205d12 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -7,7 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" CONFIG_SYS_CLK_FREQ=66666667 CONFIG_ENV_ADDR=0xFE080000 # CONFIG_SYS_PCI_64BIT is not set -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_MPC837XERDB=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 9d09d9c37f2..2969a633bf8 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" CONFIG_IDENT_STRING=" gazerbeam 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_ENV_ADDR=0xFE080000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_GAZERBEAM=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index c8897003c10..16b3a87849a 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMCOGE5NE=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 573dc4c5c4e..a622f61e41f 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -8,7 +8,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMETER1=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 895ac4649a2..d25161386dd 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMOPTI2=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index e99c55e47a1..b9f334621ca 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMSUPX5=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index fd206f3d0e6..3068da218f8 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMTEPR2=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3301a7f936b..df317f1e91d 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_TUGE1=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 02b369beacf..22f34cee766 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 -CONFIG_MPC83xx=y +CONFIG_MPC83XX=y CONFIG_HIGH_BATS=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_TUXX1=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c0..07049f6dd46 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -138,10 +138,10 @@ config CLK_K210_SET_RATE feature adds around 1K to U-Boot's final size.

config CLK_MPC83XX - bool "Enable MPC83xx clock driver" + bool "Enable MPC83XX clock driver" depends on CLK help - Support for the clock driver of the MPC83xx series of SoCs. + Support for the clock driver of the MPC83XX series of SoCs.

config CLK_OCTEON bool "Clock controller driver for Marvell MIPS Octeon" diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 0255ccaf8a4..736fcf09291 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;

/** - * struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock + * struct mpc83xx_clk_priv - Private data structure for the MPC83XX clock * driver * @speed: Array containing the speed values of all system clocks (initialized * once, then only read back) @@ -286,7 +286,7 @@ static ulong mpc83xx_clk_get_rate(struct clk *clk)

static int mpc83xx_clk_enable(struct clk *clk) { - /* MPC83xx clocks are always enabled */ + /* MPC83XX clocks are always enabled */ return 0; }

diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h index c06a51ecd43..08b2695572f 100644 --- a/drivers/clk/mpc83xx_clk.h +++ b/drivers/clk/mpc83xx_clk.h @@ -172,12 +172,12 @@ static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type) * retrieve_mode() - Get the clock mode description for a specific clock * @clk: The identifier of the clock for which the clock description should * be retrieved - * @soc_type: The type of MPC83xx SoC for which the clock description should be + * @soc_type: The type of MPC83XX SoC for which the clock description should be * retrieved * @mode: Pointer to a clk_mode structure to be filled with data for the * clock * - * Since some clock rate are stored in different places on different MPC83xx + * Since some clock rate are stored in different places on different MPC83XX * SoCs, the SoC type has to be supplied along with the clock's identifier. * * Return: 0 if OK, -ve on error @@ -269,7 +269,7 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)

/** * get_spmr() - Read the SPMR (System PLL Mode Register) - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * * Return: The SPMR value as a 32-bit number. */ @@ -282,7 +282,7 @@ static inline u32 get_spmr(immap_t *im)

/** * get_sccr() - Read the SCCR (System Clock Control Register) - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * * Return: The SCCR value as a 32-bit number. */ @@ -295,7 +295,7 @@ static inline u32 get_sccr(immap_t *im)

/** * get_lcrr() - Read the LCRR (Clock Ratio Register) - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * * Return: The LCRR value as a 32-bit number. */ @@ -308,7 +308,7 @@ static inline u32 get_lcrr(immap_t *im)

/** * get_pci_sync_in() - Read the PCI synchronization clock speed - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * * Return: The PCI synchronization clock speed value as a 32-bit number. */ @@ -322,7 +322,7 @@ static inline u32 get_pci_sync_in(immap_t *im)

/** * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * * Return: The CSB clock speed value as a 32-bit number. */ @@ -336,7 +336,7 @@ static inline u32 get_csb_clk(immap_t *im)

/** * spmr_field() - Read a specific SPMR field - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * @mask: A bitmask that describes the bitfield to be read * * Return: The value of the bit field as a 32-bit number. @@ -351,7 +351,7 @@ static inline uint spmr_field(immap_t *im, u32 mask)

/** * sccr_field() - Read a specific SCCR field - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * @mask: A bitmask that describes the bitfield to be read * * Return: The value of the bit field as a 32-bit number. @@ -366,7 +366,7 @@ static inline uint sccr_field(immap_t *im, u32 mask)

/** * lcrr_field() - Read a specific LCRR field - * @im: Pointer to the MPC83xx main register map in question + * @im: Pointer to the MPC83XX main register map in question * @mask: A bitmask that describes the bitfield to be read * * Return: The value of the bit field as a 32-bit number. diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 3bf04105e5e..618776638cd 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -8,11 +8,11 @@ config CPU finding out information about available CPUs and making changes.

config CPU_MPC83XX - bool "Enable MPC83xx CPU driver" - depends on CPU && MPC83xx + bool "Enable MPC83XX CPU driver" + depends on CPU && MPC83XX select CLK_MPC83XX help - Support CPU cores for SoCs of the MPC83xx series. + Support CPU cores for SoCs of the MPC83XX series.

config CPU_RISCV bool "Enable RISC-V CPU driver" diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c index e451c11116a..371fb694570 100644 --- a/drivers/cpu/mpc83xx_cpu.c +++ b/drivers/cpu/mpc83xx_cpu.c @@ -16,10 +16,10 @@ #include "mpc83xx_cpu.h"

/** - * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs - * @e300_type: The e300 core type of the MPC83xx CPU - * @family: The MPC83xx family the CPU belongs to - * @type: The MPC83xx type of the CPU + * struct mpc83xx_cpu_priv - Private data for MPC83XX CPUs + * @e300_type: The e300 core type of the MPC83XX CPU + * @family: The MPC83XX family the CPU belongs to + * @type: The MPC83XX type of the CPU * @is_e_processor: Flag indicating whether the CPU is a E processor or not * @is_a_variant: Flag indicating whtther the CPU is a A variant or not * @revid: The revision ID of the CPU @@ -57,7 +57,7 @@ static inline u32 get_spridr(void) }

/** - * determine_type() - Determine CPU family of MPC83xx device + * determine_type() - Determine CPU family of MPC83XX device * @dev: CPU device from which to read CPU family from */ static inline void determine_family(const struct udevice *dev) @@ -92,7 +92,7 @@ static inline void determine_family(const struct udevice *dev) }

/** - * determine_type() - Determine CPU type of MPC83xx device + * determine_type() - Determine CPU type of MPC83XX device * @dev: CPU device from which to read CPU type from */ static inline void determine_type(const struct udevice *dev) @@ -166,7 +166,7 @@ static inline void determine_type(const struct udevice *dev) }

/** - * determine_e300_type() - Determine e300 core type of MPC83xx device + * determine_e300_type() - Determine e300 core type of MPC83XX device * @dev: CPU device from which to read e300 core type from */ static inline void determine_e300_type(const struct udevice *dev) diff --git a/drivers/cpu/mpc83xx_cpu.h b/drivers/cpu/mpc83xx_cpu.h index 2aaa4e18844..2704a0c3178 100644 --- a/drivers/cpu/mpc83xx_cpu.h +++ b/drivers/cpu/mpc83xx_cpu.h @@ -33,14 +33,14 @@ static const char * const e300_names[] = { };

/** - * enum mpc83xx_cpu_family - Identifiers for MPC83xx CPU families + * enum mpc83xx_cpu_family - Identifiers for MPC83XX CPU families * @FAMILY_830X: Identifier for the MPC830x CPU family * @FAMILY_831X: Identifier for the MPC831x CPU family * @FAMILY_832X: Identifier for the MPC832x CPU family * @FAMILY_834X: Identifier for the MPC834x CPU family * @FAMILY_836X: Identifier for the MPC836x CPU family * @FAMILY_837X: Identifier for the MPC837x CPU family - * @FAMILY_UNKNOWN: Identifier for an unknown MPC83xx CPU family + * @FAMILY_UNKNOWN: Identifier for an unknown MPC83XX CPU family */ enum mpc83xx_cpu_family { FAMILY_830X, @@ -53,7 +53,7 @@ enum mpc83xx_cpu_family { };

/** - * enum mpc83xx_cpu_type - Identifiers for MPC83xx CPU types + * enum mpc83xx_cpu_type - Identifiers for MPC83XX CPU types * @TYPE_8308: Identifier for the MPC8308 CPU type * @TYPE_8309: Identifier for the MPC8309 CPU type * @TYPE_8311: Identifier for the MPC8311 CPU type @@ -76,7 +76,7 @@ enum mpc83xx_cpu_family { * @TYPE_8377: Identifier for the MPC8377 CPU type * @TYPE_8378: Identifier for the MPC8378 CPU type * @TYPE_8379: Identifier for the MPC8379 CPU type - * @TYPE_UNKNOWN: Identifier for an unknown MPC83xx CPU type + * @TYPE_UNKNOWN: Identifier for an unknown MPC83XX CPU type */ enum mpc83xx_cpu_type { TYPE_8308, diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 7f8f3570dd8..5c928689a30 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -173,7 +173,7 @@ config DDR_ECC

config DDR_ECC_CMD bool "Access the ECC features of the memory controller" - depends on DDR_ECC && MPC83xx + depends on DDR_ECC && MPC83XX default y

config ECC_INIT_VIA_DDRCONTROLLER @@ -199,7 +199,7 @@ config SYS_FSL_DDR_INTLV_256B endif

menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" - depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx + depends on MCF52x2 || MPC8xx || MPC83XX || MPC85xx

config SYS_BR0_PRELIM_BOOL bool "Define Bank 0" diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index cd332718b64..81d081fabb0 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -29,7 +29,7 @@ * 0x80_8000_0000 ~ 0xff_ffff_ffff */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY -#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 700df2236bd..4f264c83f0c 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -16,15 +16,15 @@ /* Controller can only transfer 2^26 - 1 bytes at a time */ #define FSL_DMA_MAX_SIZE (0x3ffffff)

-#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN) #else #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT) #endif

-#if defined(CONFIG_MPC83xx) -dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR); +#if defined(CONFIG_MPC83XX) +dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83XX_DMA_ADDR); #elif defined(CONFIG_MPC85xx) ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR); #elif defined(CONFIG_MPC86xx) @@ -44,7 +44,7 @@ static void dma_sync(void)

static void out_dma32(volatile unsigned *addr, int val) { -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) out_le32(addr, val); #else out_be32(addr, val); @@ -53,7 +53,7 @@ static void out_dma32(volatile unsigned *addr, int val)

static uint in_dma32(volatile unsigned *addr) { -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) return in_le32(addr); #else return in_be32(addr); @@ -79,7 +79,7 @@ static uint dma_check(void) { return status; }

-#if !defined(CONFIG_MPC83xx) +#if !defined(CONFIG_MPC83XX) void dma_init(void) { volatile fsl_dma_t *dma = &dma_base->dma[0];

@@ -99,7 +99,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {

out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); -#if !defined(CONFIG_MPC83xx) +#if !defined(CONFIG_MPC83XX) out_dma32(&dma->satr, in_dma32(&dma->satr) | (u32)((u64)src >> 32)); out_dma32(&dma->datr, @@ -131,7 +131,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { /* * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ -#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ +#if ((!defined CONFIG_MPC83XX && defined(CONFIG_DDR_ECC) && \ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) void dma_meminit(uint size) { diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c index bf693c8d457..0e3286c915a 100644 --- a/drivers/gpio/mpc83xx_gpio.c +++ b/drivers/gpio/mpc83xx_gpio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Freescale MPC83xx GPIO handling. + * Freescale MPC83XX GPIO handling. */

#include <common.h> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b07261d3db5..5657c39cfb6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -581,10 +581,10 @@ config GDSYS_IOEP Support gdsys FPGA's IO endpoint driver.

config MPC83XX_SERDES - bool "Enable MPC83xx serdes driver" + bool "Enable MPC83XX serdes driver" depends on MISC help - Support for serdes found on MPC83xx SoCs. + Support for serdes found on MPC83XX SoCs.

config FS_LOADER bool "Enable loader driver for file system" diff --git a/drivers/misc/mpc83xx_serdes.c b/drivers/misc/mpc83xx_serdes.c index 93c87e998c4..c117e2aa363 100644 --- a/drivers/misc/mpc83xx_serdes.c +++ b/drivers/misc/mpc83xx_serdes.c @@ -3,7 +3,7 @@ * (C) Copyright 2018 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc * - * base on the MPC83xx serdes initialization, which is + * base on the MPC83XX serdes initialization, which is * * Copyright 2007,2011 Freescale Semiconductor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. @@ -19,7 +19,7 @@ #include "mpc83xx_serdes.h"

/** - * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes + * struct mpc83xx_serdes_priv - Private structure for MPC83XX serdes * @regs: The device's register map * @rfcks: Variable to keep the serdes reference clock selection set during * initialization in (is or'd to every value written to SRDSCR4) diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 26aaab08e89..beda275fcf4 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -16,7 +16,7 @@ #include <asm/fsl_lbc.h> #include <nand.h>

-#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" #endif

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index e085119963b..016603da52e 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -38,7 +38,7 @@ config MPC83XX_SDRAM bool "Enable MPC83XX SDRAM support" depends on RAM help - Enable support for the internal DDR Memory Controller of the MPC83xx + Enable support for the internal DDR Memory Controller of the MPC83XX family of SoCs. Both static configurations, as well as configuring the RAM through the use of SPD (Serial Presence Detect) is supported via device tree settings. diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 11676d4fae7..9d13ffe3284 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -122,7 +122,7 @@ phys_size_t get_effective_memsize(void) }

/** - * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers + * struct mpc83xx_sdram_priv - Private data for MPC83XX RAM controllers * @total_size: The total size of all RAM modules associated with this RAM * controller in bytes */ diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 6869d60d97b..15144b1f1a3 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -84,7 +84,7 @@ static int mpc8xxx_spi_probe(struct udevice *dev) spi8xxx_t *spi = priv->spi;

/* - * SPI pins on the MPC83xx are not muxed, so all we do is initialize + * SPI pins on the MPC83XX are not muxed, so all we do is initialize * some registers */ out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS); diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd5978..87f9e404cff 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -189,9 +189,9 @@ config SYSRESET_TPL_X86 Reboot support for generic x86 processor reset in TPL.

config SYSRESET_MPC83XX - bool "Enable support MPC83xx SoC family reboot driver" + bool "Enable support MPC83XX SoC family reboot driver" help - Reboot support for NXP MPC83xx SoCs. + Reboot support for NXP MPC83XX SoCs.

endif

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6d6665005cf..7e75902a335 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -153,11 +153,11 @@ config GXP_TIMER present on HPE GXP SoCs.

config MPC83XX_TIMER - bool "MPC83xx timer support" + bool "MPC83XX timer support" depends on TIMER help Select this to enable support for the timer found on - devices based on the MPC83xx family of SoCs. + devices based on the MPC83XX family of SoCs.

config RENESAS_OSTM_TIMER bool "Renesas RZ/A1 R7S72100 OSTM Timer" diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 7814cb6a5d6..979cac325e1 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

/** - * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver + * struct mpc83xx_timer_priv - Private data structure for MPC83XX timer driver * @decrementer_count: Value to which the decrementer register should be re-set * to when a timer interrupt occurs, thus determines the * interrupt frequency (value for 1e6/HZ microseconds) diff --git a/env/Kconfig b/env/Kconfig index 688f34841fa..e377d88eb2a 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -116,7 +116,7 @@ config ENV_IS_IN_FLASH default y if ARCH_INTEGRATOR_CP default y if M548x || M547x || M5282 default y if MCF532X || MCF52x2 - default y if MPC86xx || MPC83xx + default y if MPC86xx || MPC83XX default y if ARCH_MPC8548 default y if SH && !CPU_SH4 help diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 70303acd558..64dfb66c7cb 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -43,7 +43,7 @@ struct bd_info { #if defined(CONFIG_M68K) unsigned long bi_mbar_base; /* base of internal registers */ #endif -#if defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83XX) unsigned long bi_immrbar; #endif unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 70b1c399241..c7b95687b61 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -175,7 +175,7 @@ #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83XX_ESDHC_ADDR #endif

/* diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 45307f51c10..a46f001b44e 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -11,7 +11,7 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__

-#ifdef CONFIG_MPC83xx +#ifdef CONFIG_MPC83XX #if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 diff --git a/include/serial.h b/include/serial.h index 42bdf3759c0..ceab714f541 100644 --- a/include/serial.h +++ b/include/serial.h @@ -27,7 +27,7 @@ extern struct serial_device serial_smh_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void);

-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ defined(CONFIG_MICROBLAZE) diff --git a/post/Makefile b/post/Makefile index afd49403c28..e95eb954b43 100644 --- a/post/Makefile +++ b/post/Makefile @@ -8,4 +8,4 @@ obj-y += tests.o

obj-y += drivers/ obj-$(CONFIG_PPC) += lib_powerpc/ -obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/ +obj-$(CONFIG_MPC83XX) += cpu/mpc83xx/

CONFIG options must not use lower-case letter. Convert this to upper case.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Kconfig | 2 +- arch/Kconfig.nxp | 6 +- arch/powerpc/Kconfig | 8 +- arch/powerpc/Makefile | 2 +- arch/powerpc/cpu/Makefile | 2 +- arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 16 +- arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/cpu.c | 10 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 34 +- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 14 +- arch/powerpc/cpu/mpc85xx/fdt.c | 6 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 4 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 +- arch/powerpc/cpu/mpc85xx/interrupts.c | 8 +- arch/powerpc/cpu/mpc85xx/mp.c | 32 +- arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 8 +- arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 10 +- arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 8 +- arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 6 +- arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 14 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 6 +- arch/powerpc/cpu/mpc85xx/start.S | 28 +- arch/powerpc/cpu/mpc8xxx/Makefile | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 12 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 4 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 +- arch/powerpc/cpu/mpc8xxx/law.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 12 +- arch/powerpc/include/asm/config.h | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 8 +- arch/powerpc/include/asm/fsl_lbc.h | 4 +- arch/powerpc/include/asm/fsl_liodn.h | 26 +- arch/powerpc/include/asm/fsl_pci.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 +- arch/powerpc/include/asm/immap_85xx.h | 728 +++++++++--------- arch/powerpc/include/asm/mpc85xx_gpio.h | 4 +- arch/powerpc/include/asm/ppc.h | 8 +- arch/powerpc/include/asm/processor.h | 8 +- arch/powerpc/lib/bootm.c | 2 +- arch/powerpc/lib/ppccache.S | 4 +- board/freescale/common/fsl_chain_of_trust.c | 12 +- board/freescale/common/fsl_validate.c | 8 +- board/freescale/common/mpc85xx_sleep.c | 6 +- board/freescale/common/via.h | 4 +- board/freescale/common/vid.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/p1010rdb/p1010rdb.c | 28 +- board/freescale/p1010rdb/spl.c | 6 +- board/freescale/p1010rdb/spl_minimal.c | 4 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 20 +- board/freescale/p1_p2_rdb_pc/spl.c | 8 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 4 +- board/freescale/p2041rdb/p2041rdb.c | 4 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t102xrdb/spl.c | 6 +- board/freescale/t102xrdb/t102xrdb.c | 16 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 6 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xqds/t208xqds.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/eth.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/keymile/Kconfig | 4 +- board/keymile/kmcent2/kmcent2.c | 6 +- board/socrates/socrates.c | 6 +- board/xes/common/Makefile | 2 +- board/xes/common/fsl_8xxx_clk.c | 8 +- board/xes/common/fsl_8xxx_misc.c | 4 +- boot/Kconfig | 4 +- common/Kconfig | 2 +- common/board_r.c | 2 +- common/memsize.c | 2 +- configs/MPC8548CDS_36BIT_defconfig | 2 +- configs/MPC8548CDS_defconfig | 2 +- configs/MPC8548CDS_legacy_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PA_NAND_defconfig | 2 +- configs/P1010RDB-PA_NOR_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_NAND_defconfig | 2 +- configs/P1010RDB-PB_NOR_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_defconfig | 2 +- configs/P1020RDB-PC_NAND_defconfig | 2 +- configs/P1020RDB-PC_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_defconfig | 2 +- configs/P1020RDB-PD_NAND_defconfig | 2 +- configs/P1020RDB-PD_SDCARD_defconfig | 2 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 2 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig | 2 +- configs/T1042D4RDB_SDCARD_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 2 +- configs/T1042D4RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T2080RDB_revD_NAND_defconfig | 2 +- configs/T2080RDB_revD_SDCARD_defconfig | 2 +- configs/T2080RDB_revD_SPIFLASH_defconfig | 2 +- configs/T2080RDB_revD_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 2 +- configs/T4240RDB_defconfig | 2 +- configs/kmcent2_defconfig | 2 +- configs/qemu-ppce500_defconfig | 2 +- configs/socrates_defconfig | 2 +- drivers/ata/fsl_sata.c | 2 +- drivers/ddr/fsl/Kconfig | 4 +- drivers/ddr/fsl/ctrl_regs.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 4 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/dma/fsl_dma.c | 6 +- drivers/i2c/Kconfig | 2 +- drivers/net/fm/b4860.c | 8 +- drivers/net/fm/p1023.c | 18 +- drivers/net/fm/p4080.c | 8 +- drivers/net/fm/p5020.c | 8 +- drivers/net/fm/p5040.c | 8 +- drivers/net/fm/t1024.c | 6 +- drivers/net/fm/t1040.c | 2 +- drivers/net/fm/t2080.c | 6 +- drivers/net/fm/t4240.c | 8 +- drivers/pci/Kconfig | 4 +- drivers/qe/qe.c | 14 +- drivers/spi/fsl_espi.c | 2 +- drivers/usb/host/Kconfig | 2 +- drivers/watchdog/Kconfig | 4 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/socrates.h | 2 +- include/e500.h | 2 +- include/fsl_ddr_sdram.h | 2 +- include/fsl_fman.h | 2 +- include/ioports.h | 2 +- include/mpc85xx.h | 6 +- include/pci.h | 2 +- include/post.h | 4 +- include/serial.h | 2 +- include/watchdog.h | 2 +- 189 files changed, 802 insertions(+), 802 deletions(-)

diff --git a/Kconfig b/Kconfig index a75cce7e28f..530577fbe97 100644 --- a/Kconfig +++ b/Kconfig @@ -461,7 +461,7 @@ config BUILD_TARGET default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ ARCH_SUNXI || RISCV || ARCH_ZYNQMP) default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL - default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL + default "u-boot-with-spl.bin" if MPC85XX && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.imx" if ARCH_MX6 && SPL help diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 6e1c44b7ea8..90347c964f1 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -24,7 +24,7 @@ config CHAIN_OF_TRUST select SHA_HW_ACCEL select SHA_PROG_HW_ACCEL select ENV_IS_NOWHERE - select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT + select SYS_CPC_REINIT_F if MPC85XX && !SYS_RAMBOOT select CMD_EXT4 if ARM select CMD_EXT4_WRITE if ARM imply CMD_BLOB @@ -246,9 +246,9 @@ endif

config SYS_FSL_NUM_CC_PLLS int "Number of clock control PLLs" - depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A + depends on MPC85XX || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2 - default 6 if FSL_LSCH3 || MPC85xx + default 6 if FSL_LSCH3 || MPC85XX

config SYS_FSL_ESDHC_BE bool diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index eb39a03e997..71d5ea50f54 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -15,8 +15,8 @@ config MPC83XX select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2

-config MPC85xx - bool "MPC85xx" +config MPC85XX + bool "MPC85XX" select CREATE_ARCH_SYMLINK select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -36,7 +36,7 @@ endchoice

config FSL_LBC def_bool y - depends on (MPC85xx || MPC83XX) && !FSL_IFC + depends on (MPC85XX || MPC83XX) && !FSL_IFC

config HIGH_BATS bool "Enable high BAT registers" @@ -46,7 +46,7 @@ config HIGH_BATS

config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" - depends on MPC83XX || MPC85xx + depends on MPC83XX || MPC85XX

config SYS_SRIO bool "Serial RapidIO support" diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 5050f387a6e..e7baacf4b01 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+

head-y := arch/powerpc/cpu/$(CPU)/start.o -head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o +head-$(CONFIG_MPC85XX) += arch/powerpc/cpu/mpc85xx/resetvec.o

libs-y += arch/powerpc/cpu/$(CPU)/ libs-y += arch/powerpc/cpu/ diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile index c56f0d78b2d..914f95ca674 100644 --- a/arch/powerpc/cpu/Makefile +++ b/arch/powerpc/cpu/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+

obj-$(CONFIG_MPC83XX) += mpc8xxx/ -obj-$(CONFIG_MPC85xx) += mpc8xxx/ +obj-$(CONFIG_MPC85XX) += mpc8xxx/ obj-$(CONFIG_MPC86xx) += mpc8xxx/ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 5e58023bfa8..27e3437fd8e 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -6,7 +6,7 @@ /* * CPU specific code for the MPC83XX family. * - * Derived from the MPC8260 and MPC85xx. + * Derived from the MPC8260 and MPC85XX. */

#include <common.h> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index e813bf094d1..a31d5f94fd8 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1,5 +1,5 @@ menu "mpc85xx CPU" - depends on MPC85xx + depends on MPC85XX

config PPC_SPINTABLE_COMPATIBLE depends on MP @@ -19,7 +19,7 @@ config SYS_CPU

config CMD_ERRATA bool "Enable the 'errata' command" - depends on MPC85xx + depends on MPC85XX default y help This enables the 'errata' command which displays a list of errata @@ -27,7 +27,7 @@ config CMD_ERRATA

config FSL_PREPBL_ESDHC_BOOT_SECTOR bool "Generate QorIQ pre-PBL eSDHC boot sector" - depends on MPC85xx + depends on MPC85XX depends on SDCARD help With this option final image would have prepended QorIQ pre-PBL eSDHC @@ -943,7 +943,7 @@ config ARCH_T4240

config MPC85XX_HAVE_RESET_VECTOR bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" - depends on MPC85xx + depends on MPC85XX

config BTB bool "toggle branch predition" @@ -986,7 +986,7 @@ config HETROGENOUS_CLUSTERS bool

config MAX_CPUS - int "Maximum number of CPUs permitted for MPC85xx" + int "Maximum number of CPUs permitted for MPC85XX" default 12 if ARCH_T4240 default 8 if ARCH_P4080 default 4 if ARCH_B4860 || \ @@ -1506,14 +1506,14 @@ config SYS_FSL_USB_DUAL_PHY_ENABLE

config SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up" - depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR + depends on MPC85XX && !MPC85XX_HAVE_RESET_VECTOR help If this variable is specified, the section .resetvec is not kept and the section .bootpg is placed in the previous 4k of the .text section.

config SPL_SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up, in SPL" - depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR + depends on MPC85XX && SPL && !MPC85XX_HAVE_RESET_VECTOR help If this variable is specified, the section .resetvec is not kept and the section .bootpg is placed in the previous 4k of the .text section, @@ -1521,7 +1521,7 @@ config SPL_SYS_MPC85XX_NO_RESETVEC

config TPL_SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up, in TPL" - depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR + depends on MPC85XX && TPL && !MPC85XX_HAVE_RESET_VECTOR help If this variable is specified, the section .resetvec is not kept and the section .bootpg is placed in the previous 4k of the .text section, diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 79213348274..de6afaa2a6a 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -76,10 +76,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index e53dd43f31f..f7b462f6e6f 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -40,10 +40,10 @@ int is_serdes_configured(enum srds_prtcl device)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; const struct serdes_config *ptr; int lane;

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index e8a3e82765f..9f9742f3aad 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -59,7 +59,7 @@ int checkcpu (void) #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = - (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif

/* @@ -76,8 +76,8 @@ int checkcpu (void) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) - u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) - >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + u32 ddr_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_DDR_RATIO) + >> MPC85XX_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */ @@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) val |= 0x70000000; mtspr(DBCR0,val); #else - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* Call board-specific preparation for reset */ board_reset_prepare(); @@ -436,7 +436,7 @@ int dram_init(void)

#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); unsigned int x = 10; unsigned int i;

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 96183ac2c84..5e3e5a7b526 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -313,7 +313,7 @@ static void corenet_tb_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 void fsl_erratum_a007212_workaround(void) { - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 ddr_pll_ratio; u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); @@ -379,13 +379,13 @@ ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); #ifdef CFG_SYS_DCSRBAR_PHYS - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_ARCH_MPC8548 - ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR); uint svr = get_svr();

/* @@ -455,7 +455,7 @@ int enable_cluster_l2(void) { int i = 0; u32 cluster, svr = get_svr(); - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache;

/* only the L2 of first cluster should be enabled as expected on T4080, @@ -516,7 +516,7 @@ int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_L2_CACHE - ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85XX_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2; #endif @@ -534,20 +534,20 @@ int l2cache_init(void) cache_ctl = l2cache->l2ctl;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) - if (cache_ctl & MPC85xx_L2CTL_L2E) { + if (cache_ctl & MPC85XX_L2CTL_L2E) { /* Clear L2 SRAM memory-mapped base address */ out_be32(&l2cache->l2srbar0, 0x0); out_be32(&l2cache->l2srbar1, 0x0);

/* set MBECCDIS=0, SBECCDIS=0 */ clrbits_be32(&l2cache->l2errdis, - (MPC85xx_L2ERRDIS_MBECC | - MPC85xx_L2ERRDIS_SBECC)); + (MPC85XX_L2ERRDIS_MBECC | + MPC85XX_L2ERRDIS_SBECC));

/* set L2E=0, L2SRAM=0 */ clrbits_be32(&l2cache->l2ctl, - (MPC85xx_L2CTL_L2E | - MPC85xx_L2CTL_L2SRAM_ENTIRE)); + (MPC85XX_L2CTL_L2E | + MPC85XX_L2CTL_L2SRAM_ENTIRE)); } #endif

@@ -588,11 +588,11 @@ int l2cache_init(void) break; }

- if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { + if (l2cache->l2ctl & MPC85XX_L2CTL_L2E) { puts("already enabled"); #if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) u32 l2srbar = l2cache->l2srbar0; - if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE + if (l2cache->l2ctl & MPC85XX_L2CTL_L2SRAM_ENTIRE && l2srbar >= CFG_SYS_FLASH_BASE) { l2srbar = CFG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; @@ -821,7 +821,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy1 = - (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85XX_USB1_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy1); @@ -833,7 +833,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy2 = - (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR; + (void *)CFG_SYS_MPC85XX_USB2_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy2); @@ -859,7 +859,7 @@ int cpu_init_r(void)

#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) struct ccsr_usb_phy __iomem *usb_phy = - (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85XX_USB1_PHY_ADDR; setbits_be32(&usb_phy->pllprg[1], CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | @@ -928,11 +928,11 @@ int cpu_init_r(void) fsl_sata_reg_t *reg;

/* first SATA controller */ - reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR; + reg = (void *)CFG_SYS_MPC85XX_SATA1_ADDR; clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);

/* second SATA controller */ - reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR; + reg = (void *)CFG_SYS_MPC85XX_SATA2_ADDR; clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index a67f37e3af9..de9dc2e77ea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif #ifdef CONFIG_A003399_NOR_WORKAROUND - ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR; u32 *dst, *src; void (*setup_ifc_sram)(void); int i; @@ -121,7 +121,7 @@ void cpu_init_early_f(void *fdt) * Hence specifically selecting CS3. */ #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_LCLK_IFC_CS3); #endif

#ifdef CONFIG_FSL_LAW @@ -147,10 +147,10 @@ void cpu_init_early_f(void *fdt) out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);

out_be32(&l2cache->l2errdis, - (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + (MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC));

out_be32(&l2cache->l2ctl, - (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + (MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE));

/* * Copy the code in setup_ifc to L2SRAM. Do a word copy @@ -170,8 +170,8 @@ void cpu_init_early_f(void *fdt)

/* CLEANUP */ clrbits_be32(&l2cache->l2ctl, - (MPC85xx_L2CTL_L2E | - MPC85xx_L2CTL_L2SRAM_ENTIRE)); + (MPC85XX_L2CTL_L2E | + MPC85XX_L2CTL_L2SRAM_ENTIRE)); out_be32(&l2cache->l2srbar0, 0x0); #endif

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index e26436bf570..6bc5afe1126 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -220,7 +220,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr());

@@ -507,7 +507,7 @@ static void ft_fixup_qe_snum(void *blob) #if defined(CONFIG_ARCH_P4080) static void fdt_fixup_usb(void *fdt) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]); int off;

@@ -530,7 +530,7 @@ void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ int nodeoff; - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) #if defined(CONFIG_ARCH_T2080) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 9b6577e547e..0862a1c51fe 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)

int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 cfg = in_be32(&gur->rcwsr[4]); int i;

@@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 cfg; int lane;

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7c2de02c4c5..95f2515390f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane)

int serdes_lane_enabled(int lane) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;

int bank = lanes[lane].bank; @@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)

int is_serdes_configured(enum srds_prtcl device) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device) u32 prtcl; const ccsr_gur_t *gur;

- gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85XX_GUTS_ADDR;

/* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device) if (unlikely(device == NONE)) return;

- gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85XX_GUTS_ADDR;

/* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; #ifdef CONFIG_ARCH_P5040 diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index bcbdfac0279..0fe83e80024 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -6,7 +6,7 @@ * (C) Copyright 2002 (440 port) * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com * - * (C) Copyright 2003 Motorola Inc. (MPC85xx port) + * (C) Copyright 2003 Motorola Inc. (MPC85XX port) * Xianghua Xiao (X.Xiao@motorola.com) */

@@ -36,10 +36,10 @@ void interrupt_init_cpu(unsigned *decrementer_count) ulong post_word = post_word_load(); #endif

- out_be32(&pic->gcr, MPC85xx_PICGCR_RST); - while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) + out_be32(&pic->gcr, MPC85XX_PICGCR_RST); + while (in_be32(&pic->gcr) & MPC85XX_PICGCR_RST) ; - out_be32(&pic->gcr, MPC85xx_PICGCR_M); + out_be32(&pic->gcr, MPC85XX_PICGCR_M); in_be32(&pic->gcr);

*decrementer_count = get_tbclk() / CONFIG_SYS_HZ; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 7c47e415f05..3f159cc9d69 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -87,7 +87,7 @@ int cpu_status(u32 nr) #ifdef CONFIG_FSL_CORENET int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

setbits_be32(&gur->coredisrl, 1 << nr);

@@ -95,7 +95,7 @@ int cpu_disable(u32 nr) }

int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 coredisrl = in_be32(&gur->coredisrl);

return (coredisrl & (1 << nr)); @@ -103,14 +103,14 @@ int is_core_disabled(int nr) { #else int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

switch (nr) { case 0: - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); + setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_CPU0); break; case 1: - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); + setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_CPU1); break; default: printf("Invalid cpu number for disable %d\n", nr); @@ -121,14 +121,14 @@ int cpu_disable(u32 nr) }

int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr);

switch (nr) { case 0: - return (devdisr & MPC85xx_DEVDISR_CPU0); + return (devdisr & MPC85XX_DEVDISR_CPU0); case 1: - return (devdisr & MPC85xx_DEVDISR_CPU1); + return (devdisr & MPC85XX_DEVDISR_CPU1); default: printf("Invalid cpu number for disable %d\n", nr); } @@ -264,7 +264,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 mask = cpu_mask(); struct law_entry e;

- gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR); pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); @@ -336,8 +336,8 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)&__spin_table; volatile u32 bpcr; - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; @@ -348,9 +348,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) /* disable time base at the platform */ devdisr = in_be32(&gur->devdisr); if (whoami) - devdisr |= MPC85xx_DEVDISR_TB0; + devdisr |= MPC85XX_DEVDISR_TB0; else - devdisr |= MPC85xx_DEVDISR_TB1; + devdisr |= MPC85XX_DEVDISR_TB1; out_be32(&gur->devdisr, devdisr);

/* release the hounds */ @@ -382,9 +382,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)

/* enable time base at the platform */ if (whoami) - devdisr |= MPC85xx_DEVDISR_TB1; + devdisr |= MPC85XX_DEVDISR_TB1; else - devdisr |= MPC85xx_DEVDISR_TB0; + devdisr |= MPC85XX_DEVDISR_TB0; out_be32(&gur->devdisr, devdisr);

/* readback to sync write */ @@ -393,7 +393,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0);

- devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); + devdisr &= ~(MPC85XX_DEVDISR_TB0 | MPC85XX_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr);

#ifdef CONFIG_MPC8xxx_DISABLE_BPTR diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cbcb57fe3a5..2c45872f075 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)

void fsl_serdes_init(void) { - void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR; + void *guts = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); + void *sd = (void *)CFG_SYS_MPC85XX_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); u32 srds1_io_sel, srds2_io_sel; u32 tmp; @@ -100,8 +100,8 @@ void fsl_serdes_init(void) serdes2_prtcl_map & (1 << NONE)) return;

- srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + srds1_io_sel = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT;

/* parse the SRDS2_IO_SEL of PORDEVSR */ srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL) diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index a48f3c15128..21128ccdbeb 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -52,10 +52,10 @@ int is_serdes_configured(enum srds_prtcl device)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE) && @@ -86,10 +86,10 @@ void fsl_serdes_init(void) serdes2_prtcl_map |= (1 << lane_prtcl); }

- if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) + if (pordevsr & MPC85XX_PORDEVSR_SGMII1_DIS) serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);

- if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) + if (pordevsr & MPC85XX_PORDEVSR_SGMII3_DIS) serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);

/* Set the first bit to indicate serdes has been initialized */ diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 479ee085d3a..950ca9f957e 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -32,10 +32,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds1_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 56e5ef6468c..51a57a52523 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -51,10 +51,10 @@ int is_serdes_configured(enum srds_prtcl device)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE) && diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 47f13e3c1cd..6dce81afa05 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -50,12 +50,12 @@ int is_serdes_configured(enum srds_prtcl prtcl)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); + serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85XX_SERDES1_ADDR;

u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane; u32 mask, val;

diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index 7a8f653727e..191573f79d6 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -35,10 +35,10 @@ int is_serdes_configured(enum srds_prtcl device)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 8c5d82ae8ad..dfaa4850e6d 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -40,10 +40,10 @@ int is_serdes_configured(enum srds_prtcl prtcl)

void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + u32 srds_cfg = (pordevsr & MPC85XX_PORDEVSR_IO_SEL) >> + MPC85XX_PORDEVSR_IO_SEL_SHIFT; int lane;

if (serdes1_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 3cf41ca76d5..3fb80441d99 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io);

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9af40310b46..eb1ff3dbc10 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;

void get_sys_info(sys_info_t *sys_info) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; @@ -537,8 +537,8 @@ void get_sys_info(sys_info_t *sys_info)

#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) { - u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) - >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + u32 ddr_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_DDR_RATIO) + >> MPC85XX_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk(); } @@ -548,8 +548,8 @@ void get_sys_info(sys_info_t *sys_info) #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) sys_info->freq_qe = sys_info->freq_systembus; #else - qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) - >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + qe_ratio = ((gur->porpllsr) & MPC85XX_PORPLLSR_QE_RATIO) + >> MPC85XX_PORPLLSR_QE_RATIO_SHIFT; sys_info->freq_qe = qe_ratio * get_board_sys_clk(); #endif #endif @@ -575,7 +575,7 @@ int get_clocks(void) { sys_info_t sys_info; #ifdef CONFIG_ARCH_MPC8544 - volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85XX_GUTS_ADDR; #endif get_sys_info (&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; @@ -604,7 +604,7 @@ int get_clocks(void) * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ - if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) + if (gur->pordevsr2 & MPC85XX_PORDEVSR2_SEC_CFG) gd->arch.i2c1_clk = sys_info.freq_systembus / 3; else gd->arch.i2c1_clk = sys_info.freq_systembus / 2; diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index ce2b9c21667..8bf0350bdb6 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -15,17 +15,17 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { #ifdef CFG_SYS_INIT_L2_ADDR - ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85XX_L2_ADDR;

out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);

/* set MBECCDIS=1, SBECCDIS=1 */ out_be32(&l2cache->l2errdis, - (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + (MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC));

/* set L2E=1 & L2SRAM=001 */ out_be32(&l2cache->l2ctl, - (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + (MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE)); #endif

return 0; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 562b6993b9d..21ad14aef35 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -80,17 +80,17 @@

/* Definitions from C header file asm/immap_85xx.h */

-#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CFG_SYS_MPC85XX_L2_OFFSET 0x20000

-#define MPC85xx_L2CTL 0x000 -#define MPC85xx_L2CTL_L2E 0x80000000 -#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 +#define MPC85XX_L2CTL 0x000 +#define MPC85XX_L2CTL_L2E 0x80000000 +#define MPC85XX_L2CTL_L2SRAM_ENTIRE 0x00010000

-#define MPC85xx_L2SRBAR0 0x100 +#define MPC85XX_L2SRBAR0 0x100

-#define MPC85xx_L2ERRDIS 0xe44 -#define MPC85xx_L2ERRDIS_MBECC 0x00000008 -#define MPC85xx_L2ERRDIS_SBECC 0x00000004 +#define MPC85XX_L2ERRDIS 0xe44 +#define MPC85XX_L2ERRDIS_MBECC 0x00000008 +#define MPC85XX_L2ERRDIS_SBECC 0x00000004

/* Definitions from C header file fsl_esdhc.h */

@@ -127,14 +127,14 @@ bootsect: .org 0x80 /* Start of configuration */ .Lconf_pair_start:

- .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ .long CFG_SYS_INIT_L2_ADDR

- .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ - .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2ERRDIS /* Address: L2 cache error disable */ + .long MPC85XX_L2ERRDIS_MBECC | MPC85XX_L2ERRDIS_SBECC

- .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ - .long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85XX_L2_OFFSET + MPC85XX_L2CTL /* Address: L2 configuration 0 */ + .long MPC85XX_L2CTL_L2E | MPC85XX_L2CTL_L2SRAM_ENTIRE

.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */ .long ESDHCCTL_SNOOP @@ -1325,7 +1325,7 @@ ProgramCheck: EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException, MSR_KERNEL, COPY_EE)

- /* No FPU on MPC85xx. This exception is not supposed to happen. + /* No FPU on MPC85XX. This exception is not supposed to happen. */ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) STD_EXCEPTION(0x0900, SystemCall, UnknownException) diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index e3a536d4f8c..abcde571ac2 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -17,7 +17,7 @@ ifdef MINIMAL obj-$(CONFIG_FSL_LAW) += law.o

else -obj-$(CONFIG_MPC85xx) += cpu.o +obj-$(CONFIG_MPC85XX) += cpu.o obj-$(CONFIG_MPC86xx) += cpu.o

obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 73d28f2a4e2..d4a91622d34 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;

static struct cpu_type cpu_type_list[] = { -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) CPU_TYPE_ENTRY(8533, 8533, 1), CPU_TYPE_ENTRY(8535, 8535, 1), CPU_TYPE_ENTRY(8536, 8536, 1), @@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 static inline u32 init_type(u32 cluster, int init_id) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]);

@@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)

u32 compute_ppc_cpumask(void) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); int i = 0, count = 0; u32 cluster, type, mask = 0;

@@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void) #ifdef CONFIG_HETROGENOUS_CLUSTERS u32 compute_dsp_cpumask(void) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); int i = CONFIG_DSP_CLUSTER_START, count = 0; u32 cluster, type, dsp_mask = 0;

@@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)

int fsl_qoriq_dsp_core_to_cluster(unsigned int core) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); int count = 0, i = CONFIG_DSP_CLUSTER_START; u32 cluster;

@@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)

int fsl_qoriq_core_to_cluster(unsigned int core) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); int i = 0, count = 0; u32 cluster;

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 30042902487..6055f986b8b 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -17,7 +17,7 @@ #include <phy.h> #include <hwconfig.h>

-#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) +#if defined(CONFIG_MP) && (defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) { int off, ret = -FDT_ERR_NOTFOUND; @@ -69,7 +69,7 @@ void ft_fixup_num_cores(void *blob) { debug ("deleted %d extra core entry entries from device tree\n", del_cores); } -#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ +#endif /* defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) */

int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 7519b214969..7fae2befc35 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -12,7 +12,7 @@ #include "../mpc83xx/elbc/elbc.h" #endif

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX /* Boards should provide their own version of this if they use lbc sdram */ static void __lbc_sdram_init(void) { @@ -44,7 +44,7 @@ void init_early_memctl_regs(void) clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf); #endif

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX /* if cs1 is already set via debugger, leave cs0/cs1 alone */ if (get_lbc_br(1) & BR_V) init_br1 = 0; diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 35409dc8824..b0183edb064 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -301,7 +301,7 @@ void init_laws(void)

#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* check RCW to get which port is used for boot */ - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; u32 bootloc = in_be32(&gur->rcwsr[6]); /* * in SRIO or PCIE boot we need to set specail LAWs for diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c0b4a1217d3..89ee4ea1ac2 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -33,12 +33,12 @@ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 #endif #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU - #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR -#elif defined(CONFIG_MPC85xx) - #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO - #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO - #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG - #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85XX_GUTS_ADDR +#elif defined(CONFIG_MPC85XX) + #define _DEVDISR_SRIO1 MPC85XX_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85XX_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85XX_DEVDISR_RMSG + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85XX_GUTS_ADDR #elif defined(CONFIG_MPC86xx) #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index f0702cab143..3d411eb8661 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -6,7 +6,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX #include <asm/config_mpc85xx.h> #endif

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d990ecff96f..ae95d089cdd 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -3,10 +3,10 @@ * Copyright 2011-2012 Freescale Semiconductor, Inc. */

-#ifndef _ASM_MPC85xx_CONFIG_H_ -#define _ASM_MPC85xx_CONFIG_H_ +#ifndef _ASM_MPC85XX_CONFIG_H_ +#define _ASM_MPC85XX_CONFIG_H_

-/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ +/* SoC specific defines for Freescale MPC85XX (PQ3) and QorIQ processors */

#include <fsl_ddrc_version.h>

@@ -174,4 +174,4 @@

#endif

-#endif /* _ASM_MPC85xx_CONFIG_H_ */ +#endif /* _ASM_MPC85XX_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 8d681a1cba6..3808b2b4bf4 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -9,7 +9,7 @@ #include <config.h> #include <common.h>

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX void lbc_sdram_init(void); #endif

@@ -48,7 +48,7 @@ void lbc_sdram_init(void); #endif #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC85XX) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ #endif #define BR_MS_UPMA 0x00000080 /* UPMA */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 0af3d8902ac..93c1dc4ccfe 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ }

#define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85XX_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ }

#define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);

#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ SET_LIODN_ENTRY_1(compat, liodn, \ - offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \ + offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85XX_GUTS_OFFSET, \ compatoff)

#define SET_USB_LIODN(usbNum, compat, liodn) \ SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\ - CFG_SYS_MPC85xx_USB##usbNum##_OFFSET) + CFG_SYS_MPC85XX_USB##usbNum##_OFFSET)

#define SET_SATA_LIODN(sataNum, liodn) \ SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ - CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET) + CFG_SYS_MPC85XX_SATA##sataNum##_OFFSET)

#define SET_PCI_LIODN(compat, pciNum, liodn) \ SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ - CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET)

#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \ SET_LIODN_ENTRY_1(compat, liodn,\ - offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\ - CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET,\ + CFG_SYS_MPC85XX_PCIE##pciNum##_OFFSET)

/* reg nodes for DMA start @ 0x300 */ #define SET_DMA_LIODN(dmaNum, compat, liodn) \ SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ - CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) + CFG_SYS_MPC85XX_DMA##dmaNum##_OFFSET + 0x300)

#define SET_SDHC_LIODN(sdhcNum, liodn) \ SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ - CFG_SYS_MPC85xx_ESDHC_OFFSET) + CFG_SYS_MPC85XX_ESDHC_OFFSET)

#define SET_QE_LIODN(liodn) \ SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ - CFG_SYS_MPC85xx_QE_OFFSET) + CFG_SYS_MPC85XX_QE_OFFSET)

#define SET_TDM_LIODN(liodn) \ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\ - CFG_SYS_MPC85xx_TDM_OFFSET) + CFG_SYS_MPC85XX_TDM_OFFSET)

#define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, \ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 809ab1d4187..c2f12d76521 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -241,7 +241,7 @@ int fsl_pcie_init_board(int busno); FT_FSL_PCIE3_SETUP; \ FT_FSL_PCIE4_SETUP; #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC85XX) #define FSL_PCI_COMPAT "fsl,mpc8540-pci" #ifdef CONFIG_SYS_FSL_PCIE_COMPAT #define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 2636cbbda88..404980c1f47 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -53,11 +53,11 @@ struct arch_global_data { # endif /* CONFIG_ARCH_MPC8360 */ #endif #endif -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) u32 lbc_clk; void *cpu; -#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ -#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \ +#endif /* CONFIG_MPC85XX || CONFIG_MPC86xx */ +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \ defined(CONFIG_MPC86xx) u32 i2c1_clk; u32 i2c2_clk; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7293720fb3c..616aac5c666 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * MPC85xx Internal Memory Map + * MPC85XX Internal Memory Map * * Copyright 2007-2012 Freescale Semiconductor, Inc. * @@ -316,10 +316,10 @@ typedef struct ccsr_l2cache { u8 res15[420]; } ccsr_l2cache_t;

-#define MPC85xx_L2CTL_L2E 0x80000000 -#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 -#define MPC85xx_L2ERRDIS_MBECC 0x00000008 -#define MPC85xx_L2ERRDIS_SBECC 0x00000004 +#define MPC85XX_L2CTL_L2E 0x80000000 +#define MPC85XX_L2CTL_L2SRAM_ENTIRE 0x00010000 +#define MPC85XX_L2ERRDIS_MBECC 0x00000008 +#define MPC85XX_L2ERRDIS_SBECC 0x00000004

/* DMA Registers */ typedef struct ccsr_dma { @@ -638,8 +638,8 @@ typedef struct ccsr_pic { u32 frr; /* Feature Reporting */ u8 res10[28]; u32 gcr; /* Global Configuration */ -#define MPC85xx_PICGCR_RST 0x80000000 -#define MPC85xx_PICGCR_M 0x20000000 +#define MPC85XX_PICGCR_RST 0x80000000 +#define MPC85XX_PICGCR_M 0x20000000 u8 res11[92]; u32 vir; /* Vendor Identification */ u8 res12[12]; @@ -1787,29 +1787,29 @@ typedef struct ccsr_rcpm { typedef struct ccsr_gur { u32 porpllsr; /* POR PLL ratio status */ #ifdef CONFIG_ARCH_MPC8536 -#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 -#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#define MPC85XX_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT 25 #elif defined(CONFIG_ARCH_C29X) -#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 -#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ - & MPC85xx_PORDEVSR2_DDR_SPD_0) \ - >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) +#define MPC85XX_PORPLLSR_DDR_RATIO 0x00003f00 +#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ + & MPC85XX_PORDEVSR2_DDR_SPD_0) \ + >> MPC85XX_PORDEVSR2_DDR_SPD_0_SHIFT)) #else #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) -#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#define MPC85XX_PORPLLSR_DDR_RATIO 0x00003f00 #else -#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85XX_PORPLLSR_DDR_RATIO 0x00003e00 #endif -#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#define MPC85XX_PORPLLSR_DDR_RATIO_SHIFT 9 #endif -#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 -#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 -#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e -#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 +#define MPC85XX_PORPLLSR_QE_RATIO 0x3e000000 +#define MPC85XX_PORPLLSR_QE_RATIO_SHIFT 25 +#define MPC85XX_PORPLLSR_PLAT_RATIO 0x0000003e +#define MPC85XX_PORPLLSR_PLAT_RATIO_SHIFT 1 u32 porbmsr; /* POR boot mode status */ -#define MPC85xx_PORBMSR_HA 0x00070000 -#define MPC85xx_PORBMSR_HA_SHIFT 16 -#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24 +#define MPC85XX_PORBMSR_HA 0x00070000 +#define MPC85XX_PORBMSR_HA_SHIFT 16 +#define MPC85XX_PORBMSR_ROMLOC_SHIFT 24 #define PORBMSR_ROMLOC_SPI 0x6 #define PORBMSR_ROMLOC_SDHC 0x7 #define PORBMSR_ROMLOC_NAND_2K 0x9 @@ -1817,58 +1817,58 @@ typedef struct ccsr_gur { u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ #if defined(CONFIG_ARCH_P1023) -#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 -#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 -#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 +#define MPC85XX_PORDEVSR_SGMII1_DIS 0x10000000 +#define MPC85XX_PORDEVSR_SGMII2_DIS 0x08000000 +#define MPC85XX_PORDEVSR_TSEC1_PRTC 0x02000000 #else -#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 -#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 +#define MPC85XX_PORDEVSR_SGMII1_DIS 0x20000000 +#define MPC85XX_PORDEVSR_SGMII2_DIS 0x10000000 #endif -#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 -#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 -#define MPC85xx_PORDEVSR_PCI1 0x00800000 +#define MPC85XX_PORDEVSR_SGMII3_DIS 0x08000000 +#define MPC85XX_PORDEVSR_SGMII4_DIS 0x04000000 +#define MPC85XX_PORDEVSR_SRDS2_IO_SEL 0x38000000 +#define MPC85XX_PORDEVSR_PCI1 0x00800000 #if defined(CONFIG_ARCH_P1023) -#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#define MPC85XX_PORDEVSR_IO_SEL 0x00600000 +#define MPC85XX_PORDEVSR_IO_SEL_SHIFT 21 #else #if defined(CONFIG_ARCH_P1010) -#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#define MPC85XX_PORDEVSR_IO_SEL 0x00600000 +#define MPC85XX_PORDEVSR_IO_SEL_SHIFT 21 #elif defined(CONFIG_ARCH_BSC9132) -#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 +#define MPC85XX_PORDEVSR_IO_SEL 0x00FE0000 +#define MPC85XX_PORDEVSR_IO_SEL_SHIFT 17 #elif defined(CONFIG_ARCH_C29X) -#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#define MPC85XX_PORDEVSR_IO_SEL 0x00e00000 +#define MPC85XX_PORDEVSR_IO_SEL_SHIFT 21 #else -#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#define MPC85XX_PORDEVSR_IO_SEL 0x00780000 +#define MPC85XX_PORDEVSR_IO_SEL_SHIFT 19 #endif /* if defined(CONFIG_ARCH_P1010) */ #endif -#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 -#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 -#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 -#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 -#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 -#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 -#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 +#define MPC85XX_PORDEVSR_PCI2_ARB 0x00040000 +#define MPC85XX_PORDEVSR_PCI1_ARB 0x00020000 +#define MPC85XX_PORDEVSR_PCI1_PCI32 0x00010000 +#define MPC85XX_PORDEVSR_PCI1_SPD 0x00008000 +#define MPC85XX_PORDEVSR_PCI2_SPD 0x00004000 +#define MPC85XX_PORDEVSR_DRAM_RTYPE 0x00000060 +#define MPC85XX_PORDEVSR_RIO_CTLS 0x00000008 +#define MPC85XX_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ #if defined(CONFIG_ARCH_C29X) -#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 -#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 +#define MPC85XX_PORDEVSR2_DDR_SPD_0 0x00000008 +#define MPC85XX_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif -#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 +#define MPC85XX_PORDEVSR2_SBC_MASK 0x10000000 /* The 8544 RM says this is bit 26, but it's really bit 24 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 +#define MPC85XX_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; u32 gpporcr; /* General-purpose POR configuration */ u8 res2[12]; #if defined(CONFIG_ARCH_MPC8536) u32 gencfgr; /* General Configuration Register */ -#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 +#define MPC85XX_GENCFGR_SDHC_WP_INV 0x20000000 #else u32 gpiocr; /* GPIO control */ #endif @@ -1879,248 +1879,248 @@ typedef struct ccsr_gur { u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ #if defined(CONFIG_ARCH_P1010) -#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 -#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 -#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 -#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 -#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 -#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 -#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 -#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 -#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 -#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 -#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 -#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 -#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 -#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 -#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 -#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 -#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 -#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 -#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 -#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 -#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 -#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 -#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 -#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 -#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 -#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 -#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 -#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 -#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 -#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 -#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 -#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 -#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 -#define MPC85xx_PMUXCR_LCLK_RES 0x00000040 -#define MPC85xx_PMUXCR_LCLK_USB 0x00000080 -#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 -#define MPC85xx_PMUXCR_SPI_RES 0x00000030 -#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 -#define MPC85xx_PMUXCR_CAN1_UART 0x00000004 -#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 -#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C -#define MPC85xx_PMUXCR_CAN2_UART 0x00000001 -#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 -#define MPC85xx_PMUXCR_CAN2_RES 0x00000003 +#define MPC85XX_PMUXCR_TSEC1_0_1588 0x40000000 +#define MPC85XX_PMUXCR_TSEC1_0_RES 0xC0000000 +#define MPC85XX_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 +#define MPC85XX_PMUXCR_TSEC1_1_GPIO_12 0x20000000 +#define MPC85XX_PMUXCR_TSEC1_1_RES 0x30000000 +#define MPC85XX_PMUXCR_TSEC1_2_DMA 0x04000000 +#define MPC85XX_PMUXCR_TSEC1_2_GPIO 0x08000000 +#define MPC85XX_PMUXCR_TSEC1_2_RES 0x0C000000 +#define MPC85XX_PMUXCR_TSEC1_3_RES 0x01000000 +#define MPC85XX_PMUXCR_TSEC1_3_GPIO_15 0x02000000 +#define MPC85XX_PMUXCR_IFC_ADDR16_SDHC 0x00400000 +#define MPC85XX_PMUXCR_IFC_ADDR16_USB 0x00800000 +#define MPC85XX_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 +#define MPC85XX_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 +#define MPC85XX_PMUXCR_IFC_ADDR17_18_USB 0x00200000 +#define MPC85XX_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 +#define MPC85XX_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 +#define MPC85XX_PMUXCR_IFC_ADDR19_USB 0x00080000 +#define MPC85XX_PMUXCR_IFC_ADDR19_DMA 0x000C0000 +#define MPC85XX_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 +#define MPC85XX_PMUXCR_IFC_ADDR20_21_USB 0x00020000 +#define MPC85XX_PMUXCR_IFC_ADDR20_21_RES 0x00030000 +#define MPC85XX_PMUXCR_IFC_ADDR22_SDHC 0x00004000 +#define MPC85XX_PMUXCR_IFC_ADDR22_USB 0x00008000 +#define MPC85XX_PMUXCR_IFC_ADDR22_RES 0x0000C000 +#define MPC85XX_PMUXCR_IFC_ADDR23_SDHC 0x00001000 +#define MPC85XX_PMUXCR_IFC_ADDR23_USB 0x00002000 +#define MPC85XX_PMUXCR_IFC_ADDR23_RES 0x00003000 +#define MPC85XX_PMUXCR_IFC_ADDR24_SDHC 0x00000400 +#define MPC85XX_PMUXCR_IFC_ADDR24_USB 0x00000800 +#define MPC85XX_PMUXCR_IFC_ADDR24_RES 0x00000C00 +#define MPC85XX_PMUXCR_IFC_PAR_PERR_RES 0x00000300 +#define MPC85XX_PMUXCR_IFC_PAR_PERR_USB 0x00000200 +#define MPC85XX_PMUXCR_LCLK_RES 0x00000040 +#define MPC85XX_PMUXCR_LCLK_USB 0x00000080 +#define MPC85XX_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85XX_PMUXCR_SPI_RES 0x00000030 +#define MPC85XX_PMUXCR_SPI_GPIO 0x00000020 +#define MPC85XX_PMUXCR_CAN1_UART 0x00000004 +#define MPC85XX_PMUXCR_CAN1_TDM 0x00000008 +#define MPC85XX_PMUXCR_CAN1_RES 0x0000000C +#define MPC85XX_PMUXCR_CAN2_UART 0x00000001 +#define MPC85XX_PMUXCR_CAN2_TDM 0x00000002 +#define MPC85XX_PMUXCR_CAN2_RES 0x00000003 #endif #if defined(CONFIG_ARCH_P1023) -#define MPC85xx_PMUXCR_TSEC1_1 0x10000000 +#define MPC85XX_PMUXCR_TSEC1_1 0x10000000 #else -#define MPC85xx_PMUXCR_SD_DATA 0x80000000 -#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 -#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 -#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 -#define MPC85xx_PMUXCR_TDM_ENA 0x00800000 -#define MPC85xx_PMUXCR_QE0 0x00008000 -#define MPC85xx_PMUXCR_QE1 0x00004000 -#define MPC85xx_PMUXCR_QE2 0x00002000 -#define MPC85xx_PMUXCR_QE3 0x00001000 -#define MPC85xx_PMUXCR_QE4 0x00000800 -#define MPC85xx_PMUXCR_QE5 0x00000400 -#define MPC85xx_PMUXCR_QE6 0x00000200 -#define MPC85xx_PMUXCR_QE7 0x00000100 -#define MPC85xx_PMUXCR_QE8 0x00000080 -#define MPC85xx_PMUXCR_QE9 0x00000040 -#define MPC85xx_PMUXCR_QE10 0x00000020 -#define MPC85xx_PMUXCR_QE11 0x00000010 -#define MPC85xx_PMUXCR_QE12 0x00000008 +#define MPC85XX_PMUXCR_SD_DATA 0x80000000 +#define MPC85XX_PMUXCR_SDHC_CD 0x40000000 +#define MPC85XX_PMUXCR_SDHC_WP 0x20000000 +#define MPC85XX_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 +#define MPC85XX_PMUXCR_TDM_ENA 0x00800000 +#define MPC85XX_PMUXCR_QE0 0x00008000 +#define MPC85XX_PMUXCR_QE1 0x00004000 +#define MPC85XX_PMUXCR_QE2 0x00002000 +#define MPC85XX_PMUXCR_QE3 0x00001000 +#define MPC85XX_PMUXCR_QE4 0x00000800 +#define MPC85XX_PMUXCR_QE5 0x00000400 +#define MPC85XX_PMUXCR_QE6 0x00000200 +#define MPC85XX_PMUXCR_QE7 0x00000100 +#define MPC85XX_PMUXCR_QE8 0x00000080 +#define MPC85XX_PMUXCR_QE9 0x00000040 +#define MPC85XX_PMUXCR_QE10 0x00000020 +#define MPC85XX_PMUXCR_QE11 0x00000010 +#define MPC85XX_PMUXCR_QE12 0x00000008 #endif #if defined(CONFIG_ARCH_BSC9131) -#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 -#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 -#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 -#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 -#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 -#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 -#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 -#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 -#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 -#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 -#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 -#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 -#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 -#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 -#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 -#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 -#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 -#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 -#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 -#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 -#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 -#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 -#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 -#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 -#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 -#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 -#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 -#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 -#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 -#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 -#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 -#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 -#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 -#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 -#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 -#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 -#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 -#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 -#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C -#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 -#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 -#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 +#define MPC85XX_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 +#define MPC85XX_PMUXCR_TSEC2_USB 0xC0000000 +#define MPC85XX_PMUXCR_TSEC2_1588_PPS 0x10000000 +#define MPC85XX_PMUXCR_TSEC2_1588_RSVD 0x30000000 +#define MPC85XX_PMUXCR_IFC_AD_GPIO 0x04000000 +#define MPC85XX_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 +#define MPC85XX_PMUXCR_IFC_AD15_GPIO 0x01000000 +#define MPC85XX_PMUXCR_IFC_AD15_TIMER2 0x02000000 +#define MPC85XX_PMUXCR_IFC_AD16_GPO8 0x00400000 +#define MPC85XX_PMUXCR_IFC_AD16_MSRCID0 0x00800000 +#define MPC85XX_PMUXCR_IFC_AD17_GPO 0x00100000 +#define MPC85XX_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 +#define MPC85XX_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 +#define MPC85XX_PMUXCR_IFC_CS2_GPO65 0x00040000 +#define MPC85XX_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 +#define MPC85XX_PMUXCR_SDHC_USIM 0x00010000 +#define MPC85XX_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 +#define MPC85XX_PMUXCR_SDHC_GPIO77 0x00030000 +#define MPC85XX_PMUXCR_SDHC_RESV 0x00004000 +#define MPC85XX_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 +#define MPC85XX_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 +#define MPC85XX_PMUXCR_USB_CLK_UART_SIN 0x00001000 +#define MPC85XX_PMUXCR_USB_CLK_GPIO69 0x00002000 +#define MPC85XX_PMUXCR_USB_CLK_TIMER3 0x00003000 +#define MPC85XX_PMUXCR_USB_UART_GPIO0 0x00000400 +#define MPC85XX_PMUXCR_USB_RSVD 0x00000C00 +#define MPC85XX_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 +#define MPC85XX_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 +#define MPC85XX_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 +#define MPC85XX_PMUXCR_USB_D1_2_RSVD 0x00000300 +#define MPC85XX_PMUXCR_USB_DIR_GPIO2 0x00000040 +#define MPC85XX_PMUXCR_USB_DIR_TIMER1 0x00000080 +#define MPC85XX_PMUXCR_USB_DIR_MCP_B 0x000000C0 +#define MPC85XX_PMUXCR_SPI1_UART3 0x00000010 +#define MPC85XX_PMUXCR_SPI1_SIM 0x00000020 +#define MPC85XX_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 +#define MPC85XX_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 +#define MPC85XX_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 +#define MPC85XX_PMUXCR_SPI1_CS2_GPO75 0x0000000C +#define MPC85XX_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 +#define MPC85XX_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 +#define MPC85XX_PMUXCR_SPI1_CS3_GPO76 0x00000003 #endif #ifdef CONFIG_ARCH_BSC9132 -#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 -#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 +#define MPC85XX_PMUXCR0_SIM_SEL_MASK 0x0003b000 +#define MPC85XX_PMUXCR0_SIM_SEL 0x00014000 #endif #if defined(CONFIG_ARCH_C29X) -#define MPC85xx_PMUXCR_SPI_MASK 0x00000300 -#define MPC85xx_PMUXCR_SPI 0x00000000 -#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 +#define MPC85XX_PMUXCR_SPI_MASK 0x00000300 +#define MPC85XX_PMUXCR_SPI 0x00000000 +#define MPC85XX_PMUXCR_SPI_GPIO 0x00000100 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_ARCH_P1010) -#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 -#define MPC85xx_PMUXCR2_UART_TDM 0x80000000 -#define MPC85xx_PMUXCR2_UART_RES 0xC0000000 -#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 -#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 -#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 -#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 -#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 -#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 -#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 -#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 -#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 -#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 -#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 -#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 -#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 -#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 -#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 -#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 -#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 -#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 -#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 -#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 +#define MPC85XX_PMUXCR2_UART_GPIO 0x40000000 +#define MPC85XX_PMUXCR2_UART_TDM 0x80000000 +#define MPC85XX_PMUXCR2_UART_RES 0xC0000000 +#define MPC85XX_PMUXCR2_IRQ2_TRIG_IN 0x10000000 +#define MPC85XX_PMUXCR2_IRQ2_RES 0x30000000 +#define MPC85XX_PMUXCR2_IRQ3_SRESET 0x04000000 +#define MPC85XX_PMUXCR2_IRQ3_RES 0x0C000000 +#define MPC85XX_PMUXCR2_GPIO01_DRVVBUS 0x01000000 +#define MPC85XX_PMUXCR2_GPIO01_RES 0x03000000 +#define MPC85XX_PMUXCR2_GPIO23_CKSTP 0x00400000 +#define MPC85XX_PMUXCR2_GPIO23_RES 0x00800000 +#define MPC85XX_PMUXCR2_GPIO23_USB 0x00C00000 +#define MPC85XX_PMUXCR2_GPIO4_MCP 0x00100000 +#define MPC85XX_PMUXCR2_GPIO4_RES 0x00200000 +#define MPC85XX_PMUXCR2_GPIO4_CLK_OUT 0x00300000 +#define MPC85XX_PMUXCR2_GPIO5_UDE 0x00040000 +#define MPC85XX_PMUXCR2_GPIO5_RES 0x00080000 +#define MPC85XX_PMUXCR2_READY_ASLEEP 0x00020000 +#define MPC85XX_PMUXCR2_DDR_ECC_MUX 0x00010000 +#define MPC85XX_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 +#define MPC85XX_PMUXCR2_POST_EXPOSE 0x00004000 +#define MPC85XX_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 +#define MPC85XX_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) -#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 -#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 -#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 -#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 -#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 -#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 -#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 -#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 -#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 -#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 -#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 -#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 -#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 -#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 -#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 -#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 -#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 -#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 -#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 -#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 -#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 -#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 -#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 -#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 -#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 -#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 -#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 -#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 -#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 -#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 -#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 -#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 -#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 -#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 -#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 -#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 -#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 -#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 -#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 -#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 -#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 -#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 +#define MPC85XX_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 +#define MPC85XX_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85XX_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 +#define MPC85XX_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 +#define MPC85XX_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 +#define MPC85XX_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 +#define MPC85XX_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 +#define MPC85XX_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 +#define MPC85XX_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 +#define MPC85XX_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 +#define MPC85XX_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 +#define MPC85XX_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 +#define MPC85XX_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 +#define MPC85XX_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 +#define MPC85XX_PMUXCR2_ANT1_TIMER5 0x00100000 +#define MPC85XX_PMUXCR2_ANT1_TSEC_1588 0x00200000 +#define MPC85XX_PMUXCR2_ANT1_GPIO95_19 0x00300000 +#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 +#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 +#define MPC85XX_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 +#define MPC85XX_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 +#define MPC85XX_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 +#define MPC85XX_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 +#define MPC85XX_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 +#define MPC85XX_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 +#define MPC85XX_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 +#define MPC85XX_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 +#define MPC85XX_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 +#define MPC85XX_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 +#define MPC85XX_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 +#define MPC85XX_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 +#define MPC85XX_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 +#define MPC85XX_PMUXCR2_ANT2_RSVD 0x00000100 +#define MPC85XX_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 +#define MPC85XX_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 +#define MPC85XX_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 +#define MPC85XX_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 +#define MPC85XX_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 +#define MPC85XX_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 +#define MPC85XX_PMUXCR2_ANT3_AGC_GPO53 0x00000004 +#define MPC85XX_PMUXCR2_ANT3_DO_TDM 0x00000001 +#define MPC85XX_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 #endif u32 pmuxcr3; #if defined(CONFIG_ARCH_BSC9131) -#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 -#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 -#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 -#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 -#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 -#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 -#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 -#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 -#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 -#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 -#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 -#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 -#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 -#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 +#define MPC85XX_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 +#define MPC85XX_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 +#define MPC85XX_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 +#define MPC85XX_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 +#define MPC85XX_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 +#define MPC85XX_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 +#define MPC85XX_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 +#define MPC85XX_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 +#define MPC85XX_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 +#define MPC85XX_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 +#define MPC85XX_PMUXCR3_SPI2_CS2_GPO93 0x00100000 +#define MPC85XX_PMUXCR3_SPI2_CS3_GPO94 0x00040000 +#define MPC85XX_PMUXCR3_ANT2_AGC_RSVD 0x00010000 +#define MPC85XX_PMUXCR3_ANT2_GPO89 0x00030000 #endif #ifdef CONFIG_ARCH_BSC9132 -#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 -#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 -#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 -#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 +#define MPC85XX_PMUXCR3_USB_SEL_MASK 0x0000ff00 +#define MPC85XX_PMUXCR3_UART2_SEL 0x00005000 +#define MPC85XX_PMUXCR3_UART3_SEL_MASK 0xc0000000 +#define MPC85XX_PMUXCR3_UART3_SEL 0x40000000 #endif u32 pmuxcr4; #else u8 res6[8]; #endif u32 devdisr; /* Device disable control */ -#define MPC85xx_DEVDISR_PCI1 0x80000000 -#define MPC85xx_DEVDISR_PCI2 0x40000000 -#define MPC85xx_DEVDISR_PCIE 0x20000000 -#define MPC85xx_DEVDISR_LBC 0x08000000 -#define MPC85xx_DEVDISR_PCIE2 0x04000000 -#define MPC85xx_DEVDISR_PCIE3 0x02000000 -#define MPC85xx_DEVDISR_SEC 0x01000000 -#define MPC85xx_DEVDISR_SRIO 0x00080000 -#define MPC85xx_DEVDISR_RMSG 0x00040000 -#define MPC85xx_DEVDISR_DDR 0x00010000 -#define MPC85xx_DEVDISR_CPU 0x00008000 -#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU -#define MPC85xx_DEVDISR_TB 0x00004000 -#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB -#define MPC85xx_DEVDISR_CPU1 0x00002000 -#define MPC85xx_DEVDISR_TB1 0x00001000 -#define MPC85xx_DEVDISR_DMA 0x00000400 -#define MPC85xx_DEVDISR_TSEC1 0x00000080 -#define MPC85xx_DEVDISR_TSEC2 0x00000040 -#define MPC85xx_DEVDISR_TSEC3 0x00000020 -#define MPC85xx_DEVDISR_TSEC4 0x00000010 -#define MPC85xx_DEVDISR_I2C 0x00000004 -#define MPC85xx_DEVDISR_DUART 0x00000002 +#define MPC85XX_DEVDISR_PCI1 0x80000000 +#define MPC85XX_DEVDISR_PCI2 0x40000000 +#define MPC85XX_DEVDISR_PCIE 0x20000000 +#define MPC85XX_DEVDISR_LBC 0x08000000 +#define MPC85XX_DEVDISR_PCIE2 0x04000000 +#define MPC85XX_DEVDISR_PCIE3 0x02000000 +#define MPC85XX_DEVDISR_SEC 0x01000000 +#define MPC85XX_DEVDISR_SRIO 0x00080000 +#define MPC85XX_DEVDISR_RMSG 0x00040000 +#define MPC85XX_DEVDISR_DDR 0x00010000 +#define MPC85XX_DEVDISR_CPU 0x00008000 +#define MPC85XX_DEVDISR_CPU0 MPC85XX_DEVDISR_CPU +#define MPC85XX_DEVDISR_TB 0x00004000 +#define MPC85XX_DEVDISR_TB0 MPC85XX_DEVDISR_TB +#define MPC85XX_DEVDISR_CPU1 0x00002000 +#define MPC85XX_DEVDISR_TB1 0x00001000 +#define MPC85XX_DEVDISR_DMA 0x00000400 +#define MPC85XX_DEVDISR_TSEC1 0x00000080 +#define MPC85XX_DEVDISR_TSEC2 0x00000040 +#define MPC85XX_DEVDISR_TSEC3 0x00000020 +#define MPC85XX_DEVDISR_TSEC4 0x00000010 +#define MPC85XX_DEVDISR_I2C 0x00000004 +#define MPC85XX_DEVDISR_DUART 0x00000002 u8 res7[12]; u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; @@ -2457,36 +2457,36 @@ struct ccsr_pman { #define CFG_SYS_FSL_CPC_OFFSET 0x10000 #define CFG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CFG_SYS_FSL_PAMU_OFFSET 0x20000 -#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000 -#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000 -#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000 -#define CFG_SYS_MPC85xx_DMA_OFFSET CFG_SYS_MPC85xx_DMA1_OFFSET -#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x110000 -#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 -#define CFG_SYS_MPC85xx_LBC_OFFSET 0x124000 -#define CFG_SYS_MPC85xx_IFC_OFFSET 0x124000 -#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000 -#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000 +#define CFG_SYS_MPC85XX_DMA1_OFFSET 0x100000 +#define CFG_SYS_MPC85XX_DMA2_OFFSET 0x101000 +#define CFG_SYS_MPC85XX_DMA3_OFFSET 0x102000 +#define CFG_SYS_MPC85XX_DMA_OFFSET CFG_SYS_MPC85XX_DMA1_OFFSET +#define CFG_SYS_MPC85XX_ESPI_OFFSET 0x110000 +#define CFG_SYS_MPC85XX_ESDHC_OFFSET 0x114000 +#define CFG_SYS_MPC85XX_LBC_OFFSET 0x124000 +#define CFG_SYS_MPC85XX_IFC_OFFSET 0x124000 +#define CFG_SYS_MPC85XX_GPIO_OFFSET 0x130000 +#define CFG_SYS_MPC85XX_TDM_OFFSET 0x185000 +#define CFG_SYS_MPC85XX_QE_OFFSET 0x140000 #define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ !defined(CONFIG_ARCH_B4420) -#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 -#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 -#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 -#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 +#define CFG_SYS_MPC85XX_PCIE1_OFFSET 0x240000 +#define CFG_SYS_MPC85XX_PCIE2_OFFSET 0x250000 +#define CFG_SYS_MPC85XX_PCIE3_OFFSET 0x260000 +#define CFG_SYS_MPC85XX_PCIE4_OFFSET 0x270000 #else -#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 -#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 -#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 -#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#define CFG_SYS_MPC85XX_PCIE1_OFFSET 0x200000 +#define CFG_SYS_MPC85XX_PCIE2_OFFSET 0x201000 +#define CFG_SYS_MPC85XX_PCIE3_OFFSET 0x202000 +#define CFG_SYS_MPC85XX_PCIE4_OFFSET 0x203000 #endif -#define CFG_SYS_MPC85xx_USB1_OFFSET 0x210000 -#define CFG_SYS_MPC85xx_USB2_OFFSET 0x211000 -#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 -#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 -#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000 -#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 +#define CFG_SYS_MPC85XX_USB1_OFFSET 0x210000 +#define CFG_SYS_MPC85XX_USB2_OFFSET 0x211000 +#define CFG_SYS_MPC85XX_USB1_PHY_OFFSET 0x214000 +#define CFG_SYS_MPC85XX_USB2_PHY_OFFSET 0x214100 +#define CFG_SYS_MPC85XX_SATA1_OFFSET 0x220000 +#define CFG_SYS_MPC85XX_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 #define CFG_SYS_SEC_MON_OFFSET 0x314000 @@ -2515,34 +2515,34 @@ struct ccsr_pman { #define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 #define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else -#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000 +#define CFG_SYS_MPC85XX_ECM_OFFSET 0x0000 #define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000 -#define CFG_SYS_MPC85xx_LBC_OFFSET 0x5000 +#define CFG_SYS_MPC85XX_LBC_OFFSET 0x5000 #define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 -#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x7000 -#define CFG_SYS_MPC85xx_PCI1_OFFSET 0x8000 -#define CFG_SYS_MPC85xx_PCIX_OFFSET 0x8000 -#define CFG_SYS_MPC85xx_PCI2_OFFSET 0x9000 -#define CFG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 -#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 -#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 +#define CFG_SYS_MPC85XX_ESPI_OFFSET 0x7000 +#define CFG_SYS_MPC85XX_PCI1_OFFSET 0x8000 +#define CFG_SYS_MPC85XX_PCIX_OFFSET 0x8000 +#define CFG_SYS_MPC85XX_PCI2_OFFSET 0x9000 +#define CFG_SYS_MPC85XX_PCIX2_OFFSET 0x9000 +#define CFG_SYS_MPC85XX_PCIE1_OFFSET 0xa000 +#define CFG_SYS_MPC85XX_PCIE2_OFFSET 0x9000 #if defined(CONFIG_ARCH_P2020) -#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 +#define CFG_SYS_MPC85XX_PCIE3_OFFSET 0x8000 #else -#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 +#define CFG_SYS_MPC85XX_PCIE3_OFFSET 0xb000 #endif -#define CFG_SYS_MPC85xx_GPIO_OFFSET 0xF000 -#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x18000 -#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x19000 -#define CFG_SYS_MPC85xx_IFC_OFFSET 0x1e000 -#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 -#define CFG_SYS_MPC85xx_DMA_OFFSET 0x21000 -#define CFG_SYS_MPC85xx_USB1_OFFSET 0x22000 -#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000 -#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 -#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 +#define CFG_SYS_MPC85XX_GPIO_OFFSET 0xF000 +#define CFG_SYS_MPC85XX_SATA1_OFFSET 0x18000 +#define CFG_SYS_MPC85XX_SATA2_OFFSET 0x19000 +#define CFG_SYS_MPC85XX_IFC_OFFSET 0x1e000 +#define CFG_SYS_MPC85XX_L2_OFFSET 0x20000 +#define CFG_SYS_MPC85XX_DMA_OFFSET 0x21000 +#define CFG_SYS_MPC85XX_USB1_OFFSET 0x22000 +#define CFG_SYS_MPC85XX_USB2_OFFSET 0x23000 +#define CFG_SYS_MPC85XX_USB1_PHY_OFFSET 0xE5000 +#define CFG_SYS_MPC85XX_USB2_PHY_OFFSET 0xE5100 #define CFG_SYS_MDIO1_OFFSET 0x24000 -#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#define CFG_SYS_MPC85XX_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 #define CFG_SYS_FSL_JR0_OFFSET 0x81000 @@ -2550,8 +2550,8 @@ struct ccsr_pman { #define CFG_SYS_FSL_SEC_OFFSET 0x30000 #define CFG_SYS_FSL_JR0_OFFSET 0x31000 #endif -#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 -#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CFG_SYS_MPC85XX_SERDES2_OFFSET 0xE3100 +#define CFG_SYS_MPC85XX_SERDES1_OFFSET 0xE3000 #define CFG_SYS_SEC_MON_OFFSET 0xE6000 #define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 @@ -2562,8 +2562,8 @@ struct ccsr_pman { #define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif

-#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000 -#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CFG_SYS_MPC85XX_PIC_OFFSET 0x40000 +#define CFG_SYS_MPC85XX_GUTS_OFFSET 0xE0000 #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000

#define CFG_SYS_FSL_CPC_ADDR \ @@ -2580,16 +2580,16 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET) #define CFG_SYS_FSL_CORENET_RMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET) -#define CFG_SYS_MPC85xx_GUTS_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET) +#define CFG_SYS_MPC85XX_GUTS_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_GUTS_OFFSET) #define CFG_SYS_FSL_CORENET_CCM_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET) #define CFG_SYS_FSL_CORENET_CLK_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET) #define CFG_SYS_FSL_CORENET_RCPM_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET) -#define CFG_SYS_MPC85xx_ECM_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET) +#define CFG_SYS_MPC85XX_ECM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ECM_OFFSET) #define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) #define CFG_SYS_FSL_DDR2_ADDR \ @@ -2597,33 +2597,33 @@ struct ccsr_pman { #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) #define CFG_SYS_LBC_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_LBC_OFFSET) #define CFG_SYS_IFC_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) -#define CFG_SYS_MPC85xx_ESPI_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) -#define CFG_SYS_MPC85xx_PCIX_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET) -#define CFG_SYS_MPC85xx_PCIX2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET) -#define CFG_SYS_MPC85xx_GPIO_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET) -#define CFG_SYS_MPC85xx_SATA1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET) -#define CFG_SYS_MPC85xx_SATA2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET) -#define CFG_SYS_MPC85xx_L2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET) -#define CFG_SYS_MPC85xx_DMA_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET) -#define CFG_SYS_MPC85xx_ESDHC_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_IFC_OFFSET) +#define CFG_SYS_MPC85XX_ESPI_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ESPI_OFFSET) +#define CFG_SYS_MPC85XX_PCIX_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIX_OFFSET) +#define CFG_SYS_MPC85XX_PCIX2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIX2_OFFSET) +#define CFG_SYS_MPC85XX_GPIO_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_GPIO_OFFSET) +#define CFG_SYS_MPC85XX_SATA1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SATA1_OFFSET) +#define CFG_SYS_MPC85XX_SATA2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SATA2_OFFSET) +#define CFG_SYS_MPC85XX_L2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_L2_OFFSET) +#define CFG_SYS_MPC85XX_DMA_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_DMA_OFFSET) +#define CFG_SYS_MPC85XX_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_ESDHC_OFFSET) #define CFG_SYS_MPC8xxx_PIC_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET) -#define CFG_SYS_MPC85xx_SERDES1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET) -#define CFG_SYS_MPC85xx_SERDES2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PIC_OFFSET) +#define CFG_SYS_MPC85XX_SERDES1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SERDES1_OFFSET) +#define CFG_SYS_MPC85XX_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SERDES2_OFFSET) #define CFG_SYS_FSL_CORENET_SERDES_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET) #define CFG_SYS_FSL_CORENET_SERDES2_ADDR \ @@ -2632,14 +2632,14 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET) #define CFG_SYS_FSL_CORENET_SERDES4_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET) -#define CFG_SYS_MPC85xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET) -#define CFG_SYS_MPC85xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET) -#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET) -#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET) +#define CFG_SYS_MPC85XX_USB1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB1_OFFSET) +#define CFG_SYS_MPC85XX_USB2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB2_OFFSET) +#define CFG_SYS_MPC85XX_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB1_PHY_OFFSET) +#define CFG_SYS_MPC85XX_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_USB2_PHY_OFFSET) #define CFG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) #define CFG_SYS_FSL_JR0_ADDR \ @@ -2656,9 +2656,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)

#define CFG_SYS_PCIE1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIE1_OFFSET) #define CFG_SYS_PCIE2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PCIE2_OFFSET)

#define CFG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET) @@ -2736,9 +2736,9 @@ struct dcsr_dcfg_regs { u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ };

-#define CFG_SYS_MPC85xx_SCFG \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET) -#define CFG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +#define CFG_SYS_MPC85XX_SCFG \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_SCFG_OFFSET) +#define CFG_SYS_MPC85XX_SCFG_OFFSET 0xfc000 /* The supplement configuration unit register */ struct ccsr_scfg { u32 dpslpcr; /* 0x000 Deep Sleep Control register */ diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 0ed6beca387..2643eec7820 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);

/* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)

static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);

/* Read the requested values */ return in_be32(&gpio->gpdat) & mask; diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 3b13f7ff166..708cd3920cc 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -15,7 +15,7 @@ #if defined(CONFIG_MPC8xx) #include <asm/immap_8xx.h> #endif -#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX #include <mpc85xx.h> #include <asm/immap_85xx.h> #endif @@ -50,7 +50,7 @@ static inline uint get_svr(void) return mfspr(SVR); }

-#if defined(CONFIG_MPC85xx) || \ +#if defined(CONFIG_MPC85XX) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83XX) unsigned char in8(unsigned int); @@ -78,8 +78,8 @@ void ddr_enable_ecc(unsigned int dram_size); #endif #endif

-#if defined(CONFIG_MPC85xx) -typedef MPC85xx_SYS_INFO sys_info_t; +#if defined(CONFIG_MPC85XX) +typedef MPC85XX_SYS_INFO sys_info_t; void get_sys_info(sys_info_t *); void ft_fixup_cpu(void *, u64); void ft_fixup_num_cores(void *); diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index d80b7d75563..2bb2af2cb64 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -750,7 +750,7 @@ #define MAS7 SPRN_MAS7 #define MAS8 SPRN_MAS8

-#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) #define DAR_DEAR DEAR #else #define DAR_DEAR DAR @@ -1001,7 +1001,7 @@ #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/

/* whether MPC8xxxE (i.e. has SEC) */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) #define IS_E_PROCESSOR(svr) (svr & 0x80000) #else #if defined(CONFIG_MPC83XX) @@ -1156,7 +1156,7 @@ int fixup_cpu(void); int fsl_qoriq_core_to_cluster(unsigned int core); int fsl_qoriq_dsp_core_to_cluster(unsigned int core);

-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \ .mask = (1 << (nc)) - 1 } @@ -1176,7 +1176,7 @@ int prt_83xx_rsr(void);

#endif /* ndef ASSEMBLY*/

-#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) #define EPAPR_MAGIC (0x45504150) #else #define EPAPR_MAGIC (0x65504150) diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 7b392b06bcb..e5324bf8fc1 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -290,7 +290,7 @@ void boot_prep_vxworks(struct bootm_headers *images) fdt_fixup_memory(images->ft_addr, base, size);

#if defined(CONFIG_MP) -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) ft_fixup_cpu(images->ft_addr, base + size); ft_fixup_num_cores(images->ft_addr); #elif defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index e55025181f7..472548d494d 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -64,7 +64,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -88,7 +88,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index b47ce052516..fa71abad231 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -27,8 +27,8 @@ #include <asm/arch/immap_ls102xa.h> #endif

-#if defined(CONFIG_MPC85xx) -#define CFG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR +#if defined(CONFIG_MPC85XX) +#define CFG_DCFG_ADDR CFG_SYS_MPC85XX_GUTS_ADDR #else #define CFG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR #endif @@ -50,17 +50,17 @@ int fsl_check_boot_mode_secure(void) if (val == ITS_MASK) return 1;

-#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85XX) /* For PBL based platforms check the SB_EN bit in RCWSR */ val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; if (val == RCW_SB_EN_MASK) return 1; #endif

-#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_MPC85XX) && !defined(CONFIG_FSL_CORENET) /* For Non-PBL Platforms, check the Device Status register 2*/ - val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; - if (val != MPC85xx_PORDEVSR2_SBC_MASK) + val = gur_in32(&gur->pordevsr2) & MPC85XX_PORDEVSR2_SBC_MASK; + if (val != MPC85XX_PORDEVSR2_SBC_MASK) return 1;

#endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index bfe6357b0d6..451341ddc04 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -73,17 +73,17 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) }

/* This function returns the CSF Header Address of uboot - * For MPC85xx based platforms, the LAW mapping for NOR + * For MPC85XX based platforms, the LAW mapping for NOR * flash changes in uboot code. Hence the offset needs * to be calculated and added to the new NOR flash base * address */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) #include <flash.h>

int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); u32 flash_addr, addr; @@ -168,7 +168,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) #endif

/* IE Key Table is the first entry in the SG Table */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) *ie_addr = (uintptr_t)((sg_tbl->src_addr & ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index d3323b9ec1e..6d05935bf97 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -24,7 +24,7 @@ void __weak board_sleep_prepare(void)

bool is_warm_boot(void) { - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -46,7 +46,7 @@ static void dp_ddr_restore(void) { u64 *src, *dst; int i; - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85XX_SCFG;

/* get the address of ddr date from SPARECR3 */ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); @@ -80,7 +80,7 @@ int fsl_dp_resume(void) { u32 start_addr; void (*kernel_resume)(void); - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85XX_SCFG;

if (!is_warm_boot()) return 0; diff --git a/board/freescale/common/via.h b/board/freescale/common/via.h index 77cfacc5261..7f2f64668d2 100644 --- a/board/freescale/common/via.h +++ b/board/freescale/common/via.h @@ -1,4 +1,4 @@ -#ifndef _MPC85xx_VIA_H +#ifndef _MPC85XX_VIA_H void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);

/* Function 1, IDE */ @@ -15,4 +15,4 @@ void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct

/* Function 6, AC97 Interface */ void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); -#endif /* _MPC85xx_VIA_H */ +#endif /* _MPC85XX_VIA_H */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 5ec3f2a76b1..f35ec9902b6 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -542,7 +542,7 @@ int adjust_vdd(ulong vdd_override) struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = - (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif u8 vid; u32 fusesr; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ec6e3a2d0ab..48f9f6bbc62 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,8 +33,8 @@ void local_bus_init(void);

int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR);

/* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -68,7 +68,7 @@ int checkboard (void) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

uint clkdiv; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index d32274b2481..c6ad33018fb 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -82,7 +82,7 @@ struct cpld_data {

int board_early_init_f(void) { - ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); @@ -131,7 +131,7 @@ int board_early_init_r(void)

int config_board_mux(int ctrl_type) { - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u8 tmp;

#if CONFIG_IS_ENABLED(DM_I2C) @@ -625,21 +625,21 @@ void board_reset(void)

int misc_init_r(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | - MPC85xx_PMUXCR_CAN1_UART | - MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN2_UART); + clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN1_TDM | + MPC85XX_PMUXCR_CAN1_UART | + MPC85XX_PMUXCR_CAN2_TDM | + MPC85XX_PMUXCR_CAN2_UART); config_board_mux(MUX_TYPE_CAN); } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | - MPC85xx_PMUXCR_CAN1_UART); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN1_TDM); - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); + clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN2_UART | + MPC85XX_PMUXCR_CAN1_UART); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_CAN2_TDM | + MPC85XX_PMUXCR_CAN1_TDM); + clrbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_UART_GPIO); + setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_UART_TDM); config_board_mux(MUX_TYPE_TDM); } else { /* defaultly spi_cs_sel to flash */ @@ -652,7 +652,7 @@ int misc_init_r(void) config_board_mux(MUX_TYPE_IFC);

#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); + setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_GPIO01_DRVVBUS); #endif return 0; } diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index e450f626e0a..461ba372417 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -28,7 +28,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};

console_init_f(); @@ -37,11 +37,11 @@ void board_init_f(ulong bootflag) setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);

#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); + setbits_be32(&gur->pmuxcr2, MPC85XX_PMUXCR2_GPIO01_DRVVBUS); #endif

/* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;

diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 8f0dec4c0ab..54cd7b9aacd 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); @@ -28,7 +28,7 @@ void board_init_f(ulong bootflag) #endif

/* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 602b7f0156b..c3bd2837aa2 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -149,7 +149,7 @@ void board_cpld_init(void) void board_gpio_init(void) { #ifdef CONFIG_QE - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);

/* Enable VSC7385 switch */ @@ -159,7 +159,7 @@ void board_gpio_init(void) setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); #else

- ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR);

/* * GPIO10 DDR Reset, open drain @@ -197,17 +197,17 @@ void board_gpio_init(void)

int board_early_init_f(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SDHC_CD); #ifndef SDHC_WP_IS_GPIO - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SDHC_WP); #endif clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);

- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA); #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_TDM_ENA); #endif

board_gpio_init(); @@ -227,7 +227,7 @@ int board_early_init_f(void) int checkboard(void) { struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u8 in, out, invert, io_config, val; int bus_num = CONFIG_SYS_SPD_BUS_NUM;

@@ -306,7 +306,7 @@ int checkboard(void) puts("\n");

if (val & 0x1) { - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + setbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA); puts("SD/MMC : 8-bit Mode\n"); puts("eSPI : Disabled\n"); } else { @@ -368,7 +368,7 @@ int board_early_init_r(void) static void fix_max6370_watchdog(void *blob) { int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); - ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); u32 gpioval = in_be32(&pgpio->gpdat);

/* diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 6c3f82849e3..e107ddefb0f 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* * Call board_early_init_f() as early as possible as it workarounds @@ -42,17 +42,17 @@ void board_init_f(ulong bootflag) /* Set pmuxcr to allow both i2c1 and i2c2 */ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + in_be32(&gur->pmuxcr) | MPC85XX_PMUXCR_SD_DATA);

/* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr);

#ifdef CONFIG_SPL_SPI_BOOT - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + clrbits_be32(&gur->pmuxcr, MPC85XX_PMUXCR_SD_DATA); #endif

/* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; bus_clk = get_board_sys_clk() * plat_ratio; gd->bus_clk = bus_clk; diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index f9e0b5b25ab..7bc7393894c 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); @@ -27,7 +27,7 @@ void board_init_f(ulong bootflag) #endif

/* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio = in_be32(&gur->porpllsr) & MPC85XX_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 575259b19c0..b94aaa29f82 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -66,7 +66,7 @@ int checkboard(void)

int board_early_init_f(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ setbits_be32(&gur->ddrclkdr, 0x000f000f); @@ -81,7 +81,7 @@ int board_early_init_f(void)

void board_config_lanes_mux(void) { - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;

diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index ad78f72f98c..8ccae53c77d 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -33,7 +33,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_s1;

srds_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 9faf259af74..8a7c2309a15 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void) #define GPIO1_SD_SEL 0x00020000 int board_mmc_getcd(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);

/* GPIO1_14, 0: eMMC, 1: SD */ @@ -40,7 +40,7 @@ int board_mmc_getcd(struct mmc *mmc)

int board_mmc_getwp(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);

val &= GPIO1_SD_SEL; @@ -52,7 +52,7 @@ int board_mmc_getwp(struct mmc *mmc) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index baa59615b3e..2303aa8fb93 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -49,7 +49,7 @@ int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_s1;

srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -99,7 +99,7 @@ int checkboard(void) #ifdef CONFIG_TARGET_T1024RDB static void board_mux_lane(void) { - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_prtcl_s1; u8 reg = CPLD_READ(misc_ctl_status);

@@ -222,7 +222,7 @@ static void fdt_enable_nor(void *blob)

int board_mmc_getcd(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);

/* GPIO1_14, 0: eMMC, 1: SD/MMC */ @@ -233,7 +233,7 @@ int board_mmc_getcd(struct mmc *mmc)

int board_mmc_getwp(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);

val &= GPIO1_SD_SEL; @@ -243,8 +243,8 @@ int board_mmc_getwp(struct mmc *mmc)

static u32 t1023rdb_ctrl(u32 ctrl_type) { - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85XX_GPIO_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 val; u8 tmp; int bus_num = I2C_PCA6408_BUS_NUM; @@ -274,7 +274,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85XX_GPIO_ADDR + GPIO3_OFFSET); val = in_be32(&pgpio->gpdat); val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; @@ -323,7 +323,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85XX_GPIO_ADDR + GPIO3_OFFSET); val = in_be32(&pgpio->gpdat); val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index dd8283f3c60..621cd781114 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -33,7 +33,7 @@ void board_init_f(ulong bootflag) u32 porsr1, pinctl; u32 svr = get_svr(); #endif - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) if (IS_SVR_REV(svr, 1, 0)) { diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 8cec71217a7..abc8224e4ef 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -93,7 +93,7 @@ int board_early_init_r(void)

int misc_init_r(void) { - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_s1;

srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 569b193eab7..e1e21b950fe 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, const char *phyconn; int off;

- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #ifdef CONFIG_TARGET_T2080QDS serdes_corenet_t *srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; @@ -413,7 +413,7 @@ void fdt_fixup_board_enet(void *fdt) */ static void initialize_lane_to_slot(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;

@@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); u32 srds_s1;

diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 8866be54a66..0dcb1411e58 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -67,7 +67,7 @@ unsigned long get_board_ddr_clk(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 8be55e52e5f..cf70dda0e0a 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -88,7 +88,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)

int brd_mux_lane_to_slot(void) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_prtcl_s1;

srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 130cb8847c0..e6794aa06de 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -27,7 +27,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 2e52543847b..43011f1edc2 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -43,7 +43,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 srds_prtcl_s1, srds_prtcl_s2;

srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 779457d2964..b705b20809b 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -33,7 +33,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index a24d17cf8bf..7c80f1a0933 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -35,7 +35,7 @@ config KM_PHRAM config KM_RESERVED_PRAM hex "Reserved RAM" default 0x0 if MPC83XX - default 0x1000 if MPC85xx || ARCH_LS1021A + default 0x1000 if MPC85XX || ARCH_LS1021A depends on !ARCH_SOCFPGA help Reserved physical RAM area at the end of memory for special purposes. @@ -79,7 +79,7 @@ config SYS_CLIPS_BASE config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if MPC83XX - default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A + default n if MPC85XX || ARCH_SOCFPGA || ARCH_LS1021A help Use the Ethernet initialization implemented in common code that detects if a Piggy board is present. diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index ed552c57b5f..b75da715317 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -45,7 +45,7 @@ int checkboard(void) int board_early_init_f(void) { struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); bool cpuwd_flag = false;

/* board specific IFC configuration: increased bus turnaround time */ @@ -221,8 +221,8 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f); int misc_init_r(void) { serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG; - ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85XX_SCFG; + ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85XX_GUTS_ADDR;

/* check SERDES bank 0 reference clock */ u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 9c4dd186fca..107d3c53eba 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -35,7 +35,7 @@ ulong flash_get_size (ulong base, int banknum);

int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); char buf[64]; int f; int i = env_get_f("serial#", buf, sizeof(buf)); @@ -139,7 +139,7 @@ int misc_init_r (void) void local_bus_init (void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85XX_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; @@ -175,7 +175,7 @@ void local_bus_init (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* set and reset the GPIO pin 2 which will reset the W83782G chip */ out_8((unsigned char*)&gur->gpoutdr, 0x3F ); diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 002821916c4..6be05152aa4 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -5,6 +5,6 @@

obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o -obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o +obj-$(CONFIG_MPC85XX) += fsl_8xxx_misc.o board.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index c36b2afd50e..ef720c17240 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -12,8 +12,8 @@ */ unsigned long get_board_sys_clk(void) { -#if defined(CONFIG_MPC85xx) - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_MPC85XX) + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #elif defined(CONFIG_MPC86xx) immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -29,14 +29,14 @@ unsigned long get_board_sys_clk(void) #endif }

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX /* * Return DDR input clock - synchronous with SYSCLK or 66 MHz * Note: 86xx doesn't support asynchronous DDR clk */ unsigned long get_board_ddr_clk(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;

if (ddr_ratio == 0x7) diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index bc7e5c5764f..3082acaaa04 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -27,8 +27,8 @@ int board_flash_wp_on(void) */ uint get_board_derivative(void) { -#if defined(CONFIG_MPC85xx) - volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_MPC85XX) + volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR; #elif defined(CONFIG_MPC86xx) volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; diff --git a/boot/Kconfig b/boot/Kconfig index fdcfbae7b2c..4bb1af23ac5 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -673,12 +673,12 @@ config SYS_MONITOR_BASE when booting from flash.

config SPL_SYS_MONITOR_BASE - depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE + depends on MPC85XX && SPL && HAVE_SYS_MONITOR_BASE hex "Physical start address of SPL monitor code" default SPL_TEXT_BASE

config TPL_SYS_MONITOR_BASE - depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE + depends on MPC85XX && TPL && HAVE_SYS_MONITOR_BASE hex "Physical start address of TPL monitor code"

config DYNAMIC_SYS_CLK_FREQ diff --git a/common/Kconfig b/common/Kconfig index e3a5e1be1e9..99ff67cac6a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -709,7 +709,7 @@ config LAST_STAGE_INIT

config MISC_INIT_R bool "Execute Misc Init" - default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85xx + default y if ARCH_KEYSTONE || ARCH_SUNXI || MPC85XX default y if ARCH_OMAP2PLUS && !AM33XX help Enabling this option calls 'misc_init_r' function diff --git a/common/board_r.c b/common/board_r.c index 3618acad437..e4a5c88cdd4 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -130,7 +130,7 @@ static int initr_reloc_global_data(void) #elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; #endif -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) /* * The gd->cpu pointer is set to an address in flash before relocation. * We need to update it to point to the same CPU entry in RAM. diff --git a/common/memsize.c b/common/memsize.c index 66d5be6a1ff..e8acc2be7a6 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -96,7 +96,7 @@ phys_size_t __weak get_effective_memsize(void) { phys_size_t ram_size = gd->ram_size;

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX /* * Check for overflow and limit ram size to some representable value. * It is required that ram_base + ram_size must be representable by diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 05034ce2e46..d93039d461a 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 965c37e45ec..c34e3a26aba 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 004175c8048..447624a464d 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e0ffb164b5a..23a3650331e 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 71e17d90ec1..b52dd99c1e8 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 0df2a559594..5152d3d8008 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 086bfcb10e5..d2e3dc974b9 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index aa8aeda7580..1258d53aaa6 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 5807e8bdaa4..55f3b3e0232 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 30ff3ad322b..41da013efd6 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index d7d8219e947..e33e7d5e711 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 6e053870834..1a81df7b3b2 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7328c142f99..611052102f2 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 216e14cdacc..7f6b79da634 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 35943d10d77..40615cf9f88 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index c2c851ca57a..885db3d46a1 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -13,7 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 0f109c514c1..12d92ef8807 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index b8e0a92a935..e5d2caa0de0 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index f403e67b8fe..fc8ae9a3d6e 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_L2_CACHE=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 02f0f3cde99..c7a4ac8e519 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 84cc6bd38e5..7ded32bcae1 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 427b67c6722..76e2e54853a 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index e2373d04d74..fa13c807f88 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index e1e6af7fae0..57862fcea99 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index d9477f1c339..bba95ed33df 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index f27c9c3835d..419dd6f1b40 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index ca828eac03d..9ca1294c6ff 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 1d364fef2aa..a6c5f96f13c 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 4dc2457c1c7..641793143d1 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index bf6d2235b36..f023880f91c 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 5377aba4ef3..ec025fc332d 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 7646e9054b8..491f63e7bff 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 81512593da5..464c35a7d5e 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 3f106c60139..3b9e67e12ef 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index d266ce82a59..ddb20ca5181 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 11d59d14fe4..44056761a65 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 9416d93c533..d85b38e3d67 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 74d26f1f1a9..c5a226d06e5 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 4d5569c5549..d7f4449c556 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index bf3365a4800..39e909bf96f 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 69f30d427f7..db53a06b965 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index c2dc0f21eeb..ec0268dd745 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 306432e41b1..02cfe59feed 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index bedea018ddc..f8843df20c2 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index f06bb02a27c..4674d2bd669 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 4f91dce1094..24e6a6cb9e8 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index c9d771e44bf..acee4e2aef8 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -5,7 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index a55797eb9e4..700614e3a20 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 2f5a1a329d0..288f41b0020 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index afce81b1076..3c042483e59 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 29b240fc147..ee87a349fe1 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index ca960d368bd..a579998ef2a 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index eba73ee989f..e214fe55215 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index ae98a3586b7..dc4686c0818 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 76a1e583007..1933f2a8ed4 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index fe440a469f9..475cd65ca66 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index f4f90d5ab22..7c7f910eb2b 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_SYS_SRIO=y CONFIG_SRIO1=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 18baf568121..d8475fd4051 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index df98e33f971..e46e86a2389 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index efa48af3bf8..e8a978656a6 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 8e07b2a09c1..3051bbc3144 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 69bebfacb07..e228fcbda50 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 179fc63705a..4e56142e2ef 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 1d8a6b5f41c..99451afb592 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index a1332a99b43..a0ee406f769 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index d906035a2bf..f8122b04276 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T4240RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index d2b270dd44f..62150389ba1 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T4240RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index d9aae79bc2b..aa18a419c8d 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -7,7 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kmcent2" CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_ENV_ADDR=0xebf20000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMCENT2=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index a19d555f7d5..b853a6dbd2b 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -3,7 +3,7 @@ CONFIG_TEXT_BASE=0xf00000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_SYS_CLK_FREQ=33000000 -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_QEMU_PPCE500=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 46be662037e..ba80ee1b16e 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="socrates" CONFIG_ENV_ADDR=0xFFF40000 # CONFIG_SYS_PCI_64BIT is not set -CONFIG_MPC85xx=y +CONFIG_MPC85XX=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index 972101b29ce..9aad2c6e2ad 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -78,7 +78,7 @@ static int init_sata(struct fsl_ata_priv *priv, int dev) return -1; }

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX if ((dev == 0) && (!is_serdes_configured(SATA1))) { printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); return -1; diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 5c928689a30..170f758ade6 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -166,7 +166,7 @@ endchoice endmenu

config FSL_DMA - def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER + def_bool y if DDR_ECC && MPC85XX && !ECC_INIT_VIA_DDRCONTROLLER

config DDR_ECC bool "ECC DDR memory support" @@ -199,7 +199,7 @@ config SYS_FSL_DDR_INTLV_256B endif

menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" - depends on MCF52x2 || MPC8xx || MPC83XX || MPC85xx + depends on MCF52x2 || MPC8xx || MPC83XX || MPC85XX

config SYS_BR0_PRELIM_BOOL bool "Define Bank 0" diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8f8c2c864c3..e311d936383 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1854,7 +1854,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, /* clk_adjust in 5-bits on T-series and LS-series */ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22; else - /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ + /* clk_adjust in 4-bits on earlier MPC85XX and P-series */ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;

debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index b830e7cbd14..cadaaad01eb 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -20,8 +20,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;

-#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85XX) + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); uint svr; #endif

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 1c4a1cae4df..ff57423f57a 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -33,7 +33,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, int timeout; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 int timeout_save; - volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR; + volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85XX_ECM_ADDR; unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; #endif diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 4f264c83f0c..938ed4429f7 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -25,8 +25,8 @@

#if defined(CONFIG_MPC83XX) dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83XX_DMA_ADDR); -#elif defined(CONFIG_MPC85xx) -ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR); +#elif defined(CONFIG_MPC85XX) +ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85XX_DMA_ADDR); #elif defined(CONFIG_MPC86xx) ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); #else @@ -35,7 +35,7 @@ ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);

static void dma_sync(void) { -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) asm("sync; isync; msync"); #elif defined(CONFIG_MPC86xx) asm("sync; isync"); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 76e19918aad..70ed69b22e1 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -166,7 +166,7 @@ config SYS_I2C_FSL bool "Freescale I2C bus driver" help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and - MPC85xx processors. + MPC85XX processors.

if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_FSL_I2C_OFFSET diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 1c5543e3c87..0b7d208d704 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -25,7 +25,7 @@ u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -33,14 +33,14 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); } @@ -51,7 +51,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) u32 serdes2_prtcl; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif

if (is_device_disabled(port)) diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 9013b276bc9..a18e4e9b1f7 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -10,13 +10,13 @@ #include <asm/fsl_serdes.h>

static u32 port_to_devdisr[] = { - [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1, - [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2, + [FM1_DTSEC1] = MPC85XX_DEVDISR_TSEC1, + [FM1_DTSEC2] = MPC85XX_DEVDISR_TSEC2, };

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr);

return port_to_devdisr[port] & devdisr; @@ -24,7 +24,7 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -35,14 +35,14 @@ void fman_disable_port(enum fm_port port)

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr);

if (is_device_disabled(port)) @@ -52,8 +52,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC1) { if (is_serdes_configured(SGMII_FM1_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; - if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) { - if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC) + if (pordevsr & MPC85XX_PORDEVSR_SGMII1_DIS) { + if (pordevsr & MPC85XX_PORDEVSR_TSEC1_PRTC) return PHY_INTERFACE_MODE_RGMII; else return PHY_INTERFACE_MODE_RMII; @@ -64,7 +64,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC2) { if (is_serdes_configured(SGMII_FM1_DTSEC2)) return PHY_INTERFACE_MODE_SGMII; - if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS) + if (pordevsr & MPC85XX_PORDEVSR_SGMII2_DIS) return PHY_INTERFACE_MODE_RGMII; }

diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 7ad993221f7..3e4c2234357 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -24,7 +24,7 @@ static u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -32,7 +32,7 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -43,14 +43,14 @@ void fman_disable_port(enum fm_port port)

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);

if (is_device_disabled(port)) diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index f931491b112..86f8a55179b 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -20,7 +20,7 @@ static u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -28,7 +28,7 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -39,14 +39,14 @@ void fman_disable_port(enum fm_port port)

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);

if (is_device_disabled(port)) diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index ef9f4bcce4d..ca3e260082d 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -26,7 +26,7 @@ u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -34,7 +34,7 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -45,14 +45,14 @@ void fman_disable_port(enum fm_port port)

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);

if (is_device_disabled(port)) diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 70ab4610cdf..6e20c5d923d 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -20,7 +20,7 @@ u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -28,14 +28,14 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);

setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);

if (is_device_disabled(port)) diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 5c260bed7fd..1541d8a6a33 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -11,7 +11,7 @@

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);

/* handle RGMII first */ diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index 6174934d2b8..d1fec51baed 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -28,7 +28,7 @@ u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -36,14 +36,14 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);

setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);

if (is_device_disabled(port)) diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index f0a02bfe457..3d129d88362 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {

static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);

return port_to_devdisr[port] & devdisr2; @@ -43,21 +43,21 @@ static int is_device_disabled(enum fm_port port)

void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);

setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR);

clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }

phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85XX_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);

if (is_device_disabled(port)) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index ef328d26525..5ad5fe916d2 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -150,14 +150,14 @@ config PCIE_FSL select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 help Say Y here if you want to enable PCIe controller support on FSL - PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. + PowerPC MPC85XX, MPC86xx, B series, P series and T series SoCs. This driver does not support SRIO_PCIE_BOOT feature.

config PCI_MPC85XX bool "MPC85XX PowerPC PCI support" help Say Y here if you want to enable PCI controller support on FSL - PowerPC MPC85xx SoC. + PowerPC MPC85XX SoC.

config PCI_MSC01 bool "MSC01 PCI support" diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 2825dc6f9aa..2ea6b56516e 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -25,7 +25,7 @@ #include <asm/arch/cpu.h> #endif

-#define MPC85xx_DEVDISR_QE_DISABLE 0x1 +#define MPC85XX_DEVDISR_QE_DISABLE 0x1

qe_map_t *qe_immr; #ifdef CONFIG_QE @@ -469,7 +469,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) #ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #else - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif #endif if (!firmware) { @@ -485,7 +485,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) (hdr->magic[2] != 'F')) { printf("QE microcode not found\n"); #ifdef CONFIG_DEEP_SLEEP - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); + setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE); #endif return -EPERM; } @@ -609,7 +609,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) #ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #else - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #endif #endif if (!firmware) { @@ -625,7 +625,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); #ifdef CONFIG_DEEP_SLEEP - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); + setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE); #endif return -EPERM; } @@ -718,7 +718,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr) const u32 *code; #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_PPC - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR); #else struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #endif @@ -733,7 +733,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { #ifdef CONFIG_DEEP_SLEEP - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); + setbits_be32(&gur->devdisr, MPC85XX_DEVDISR_QE_DISABLE); #endif return -EPERM; } diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index b1d964d79d0..5ce9d73570b 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -390,7 +390,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!fsl) return NULL;

- fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR); + fsl->espi = (void *)(CFG_SYS_MPC85XX_ESPI_ADDR); fsl->mode = mode; fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; fsl->speed_hz = max_hz; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6213b3c95fa..930e6885cbb 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -291,7 +291,7 @@ config EHCI_HCD_INIT_AFTER_RESET config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" select EHCI_HCD_INIT_AFTER_RESET - select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ + select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85XX && \ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) ---help--- Enables support for the on-chip EHCI controller on FSL chips. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b5ac8f7f50d..9218de06e22 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -140,10 +140,10 @@ config WDT_BCM6345

config WDT_BOOKE bool "PowerPC Book-E watchdog driver" - depends on WDT && MPC85xx + depends on WDT && MPC85XX help Watchdog driver for PowerPC Book-E chips, such as the Freescale - MPC85xx SOCs and the IBM PowerPC 440. + MPC85XX SOCs and the IBM PowerPC 440.

config WDT_CDNS bool "Cadence watchdog timer support" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9efae58ce90..eec51744696 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -340,7 +340,7 @@ extern unsigned long get_sdram_size(void); #endif

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 28f53ae78a1..4f74a1695e0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -284,7 +284,7 @@ #endif

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 7ee46abffdb..22b1e750825 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -347,7 +347,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* Qman/Bman */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f196bd76e6e..e0d0436c197 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -304,7 +304,7 @@ */

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* Qman/Bman */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2023d7497f6..43fcf6ff13e 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -389,7 +389,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index f213d2de770..21f06e97a44 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -351,7 +351,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 506f1b7e268..e6daf0ef00c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -350,7 +350,7 @@ */

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f5bd0913449..7fd68c70fc6 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -373,7 +373,7 @@ */

#ifdef CONFIG_MMC -#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85XX_ESDHC_ADDR #endif

/* diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 2b35be83ec6..5e7317d30a3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -21,7 +21,7 @@ */

/* - * sysclk for MPC85xx + * sysclk for MPC85XX * * Two valid values are: * 33000000 diff --git a/include/e500.h b/include/e500.h index 9f68a834c2f..6343393e5f5 100644 --- a/include/e500.h +++ b/include/e500.h @@ -38,7 +38,7 @@ typedef struct #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK unsigned char diff_sysclk; #endif -} MPC85xx_SYS_INFO; +} MPC85XX_SYS_INFO;

#endif /* _ASMLANGUAGE */

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index c43f780e4cd..042faa8b2c3 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -465,7 +465,7 @@ int fsl_dp_resume(void); * The 85xx boards have a common prototype for fixed_sdram so put the * declaration here. */ -#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX extern phys_size_t fixed_sdram(void); #endif

diff --git a/include/fsl_fman.h b/include/fsl_fman.h index 74acdb25691..f1857a7ef96 100644 --- a/include/fsl_fman.h +++ b/include/fsl_fman.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * MPC85xx Internal Memory Map + * MPC85XX Internal Memory Map * * Copyright 2010-2011 Freescale Semiconductor, Inc. */ diff --git a/include/ioports.h b/include/ioports.h index 1cd3ceb37a5..f253e002b0e 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -23,7 +23,7 @@ typedef struct { * the internal memory map aligns the above structure on * a 0x20 byte boundary */ -#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) #else #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 636734dd3c6..e26e131114c 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -3,8 +3,8 @@ * Copyright(c) 2003 Motorola Inc. */

-#ifndef __MPC85xx_H__ -#define __MPC85xx_H__ +#ifndef __MPC85XX_H__ +#define __MPC85XX_H__

#if defined(CONFIG_E500) #include <e500.h> @@ -60,4 +60,4 @@ CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead." #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ CFG_SYS_CCSRBAR_PHYS_LOW)

-#endif /* __MPC85xx_H__ */ +#endif /* __MPC85XX_H__ */ diff --git a/include/pci.h b/include/pci.h index c55d6107a49..6e58cd9a10b 100644 --- a/include/pci.h +++ b/include/pci.h @@ -770,7 +770,7 @@ int pci_hose_find_ext_capability(struct pci_controller *hose, const char * pci_class_str(u8 class); int pci_last_busno(void);

-#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC85XX extern void pci_mpc85xx_init (struct pci_controller *hose); #endif

diff --git a/include/post.h b/include/post.h index 41120695064..6c036e4fffc 100644 --- a/include/post.h +++ b/include/post.h @@ -25,9 +25,9 @@ #include <linux/immap_qe.h> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)

-#elif defined (CONFIG_MPC85xx) +#elif defined (CONFIG_MPC85XX) #include <asm/immap_85xx.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \ +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MPC85XX_PIC_OFFSET + \ offsetof(ccsr_pic_t, tfrr)) #endif

diff --git a/include/serial.h b/include/serial.h index ceab714f541..22ac1043d36 100644 --- a/include/serial.h +++ b/include/serial.h @@ -27,7 +27,7 @@ extern struct serial_device serial_smh_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void);

-#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || \ +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ defined(CONFIG_MICROBLAZE) diff --git a/include/watchdog.h b/include/watchdog.h index ac5f11e376f..ddc81cd6c76 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -40,7 +40,7 @@ int init_func_watchdog_reset(void); void hw_watchdog_init(void); #endif

-#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85XX) void init_85xx_watchdog(void); #endif #endif /* _WATCHDOG_H_ */

This is not a Kconfig option so we should not be setting it in the Makefile. Rename it to use a CFS_ prefix, since this is still used in mxsimage.c

In general tools should support all the features without reference to CONFIG options, but this is left to the maintainer to look at.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

tools/Makefile | 4 ++-- tools/mxsimage.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/Makefile b/tools/Makefile index edfa40903d9..2ee43dff542 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -158,9 +158,9 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o file2include-objs := file2include.o

ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),) -# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +# Add CFG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . -HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS +HOSTCFLAGS_mxsimage.o += -DCFG_MXS endif

ifdef CONFIG_TOOLS_LIBCRYPTO diff --git a/tools/mxsimage.c b/tools/mxsimage.c index fee022aab46..fbe46c47fae 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -5,7 +5,7 @@ * Copyright (C) 2012-2013 Marek Vasut marex@denx.de */

-#ifdef CONFIG_MXS +#ifdef CFG_MXS

#include <errno.h> #include <fcntl.h>

This is not used since this commit:

8d1e3cb1400 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-By: Michael Trimarchi michael@amarulasolutions.com ---

(no changes since v1)

drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/fsl_upm.c | 187 --------------------------------- include/linux/mtd/fsl_upm.h | 44 -------- 3 files changed, 232 deletions(-) delete mode 100644 drivers/mtd/nand/raw/fsl_upm.c delete mode 100644 include/linux/mtd/fsl_upm.h

diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 4c59903aa8c..e8764cf358b 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,7 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c deleted file mode 100644 index 91cc1339537..00000000000 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov avorontsov@ru.mvista.com - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/fsl_upm.h> -#include <nand.h> - -static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) -{ - clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); - (void)in_be32(upm->mxmr); -} - -static void fsl_upm_end_pattern(struct fsl_upm *upm) -{ - clrbits_be32(upm->mxmr, MxMR_OP_RUNP); - - while (in_be32(upm->mxmr) & MxMR_OP_RUNP) - eieio(); -} - -static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, - void __iomem *io_addr, u32 mar) -{ - out_be32(upm->mar, mar); - (void)in_be32(upm->mar); - switch (width) { - case 8: - out_8(io_addr, 0x0); - break; - case 16: - out_be16(io_addr, 0x0); - break; - case 32: - out_be32(io_addr, 0x0); - break; - } -} - -static void fun_wait(struct fsl_upm_nand *fun) -{ - if (fun->dev_ready) { - while (!fun->dev_ready(fun->chip_nr)) - debug("unexpected busy state\n"); - } else { - /* - * If the R/B pin is not connected, - * a short delay is necessary. - */ - udelay(1); - } -} - -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 -static void fun_select_chip(struct mtd_info *mtd, int chip_nr) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - if (chip_nr >= 0) { - fun->chip_nr = chip_nr; - chip->IO_ADDR_R = chip->IO_ADDR_W = - fun->upm.io_addr + fun->chip_offset * chip_nr; - } else if (chip_nr == -1) { - chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); - } -} -#endif - -static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - void __iomem *io_addr; - u32 mar; - - if (!(ctrl & fun->last_ctrl)) { - fsl_upm_end_pattern(&fun->upm); - - if (cmd == NAND_CMD_NONE) - return; - - fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); - } - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_ALE) - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - else if (ctrl & NAND_CLE) - fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - } - - mar = cmd << (32 - fun->width); - io_addr = fun->upm.io_addr; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - if (fun->chip_nr > 0) { - io_addr += fun->chip_offset * fun->chip_nr; - if (fun->upm_mar_chip_offset) - mar |= fun->upm_mar_chip_offset * fun->chip_nr; - } -#endif - fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); - - /* - * Some boards/chips needs this. At least the MPC8360E-RDK - * needs it. Probably weird chip, because I don't see any - * need for this on MPC8555E + Samsung K9F1G08U0A. Usually - * here are 0-2 unexpected busy states per block read. - */ - if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) - fun_wait(fun); -} - -static u8 upm_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - return in_8(chip->IO_ADDR_R); -} - -static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - for (i = 0; i < len; i++) { - out_8(chip->IO_ADDR_W, buf[i]); - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) - fun_wait(fun); - } - - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) - fun_wait(fun); -} - -static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - - for (i = 0; i < len; i++) - buf[i] = in_8(chip->IO_ADDR_R); -} - -static int nand_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - return fun->dev_ready(fun->chip_nr); -} - -int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) -{ - if (fun->width != 8 && fun->width != 16 && fun->width != 32) - return -ENOSYS; - - fun->last_ctrl = NAND_CLE; - - nand_set_controller_data(chip, fun); - chip->chip_delay = fun->chip_delay; - chip->ecc.mode = NAND_ECC_SOFT; - chip->cmd_ctrl = fun_cmd_ctrl; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - chip->select_chip = fun_select_chip; -#endif - chip->read_byte = upm_nand_read_byte; - chip->read_buf = upm_nand_read_buf; - chip->write_buf = upm_nand_write_buf; - if (fun->dev_ready) - chip->dev_ready = nand_dev_ready; - - return 0; -} diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h deleted file mode 100644 index 9999993543b..00000000000 --- a/include/linux/mtd/fsl_upm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov avorontsov@ru.mvista.com - */ - -#ifndef __LINUX_MTD_NAND_FSL_UPM -#define __LINUX_MTD_NAND_FSL_UPM - -#include <linux/mtd/rawnand.h> - -#define FSL_UPM_WAIT_RUN_PATTERN 0x1 -#define FSL_UPM_WAIT_WRITE_BYTE 0x2 -#define FSL_UPM_WAIT_WRITE_BUFFER 0x4 - -struct fsl_upm { - void __iomem *mdr; - void __iomem *mxmr; - void __iomem *mar; - void __iomem *io_addr; -}; - -struct fsl_upm_nand { - struct fsl_upm upm; - - int width; - int upm_cmd_offset; - int upm_addr_offset; - int upm_mar_chip_offset; - int wait_flags; - int (*dev_ready)(int chip_nr); - int chip_delay; - int chip_offset; - int chip_nr; - - /* no need to fill */ - int last_ctrl; -}; - -extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); - -#endif

This is not used since time out of mind.

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/kb9202_nand.c | 134 ----------------------------- 2 files changed, 135 deletions(-) delete mode 100644 drivers/mtd/nand/raw/kb9202_nand.c

diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index f004eb39f3b..c25acb11804 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,7 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o diff --git a/drivers/mtd/nand/raw/kb9202_nand.c b/drivers/mtd/nand/raw/kb9202_nand.c deleted file mode 100644 index 9d26532c780..00000000000 --- a/drivers/mtd/nand/raw/kb9202_nand.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * KwikByte kb9200_dev@kwikbyte.com - * - * (C) Copyright 2009 - * Matthias Kaehlcke matthias@kaehlcke.net - */ - -#include <common.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/arch/hardware.h> - -#include <nand.h> - -/* - * hardware specific access to control-lines - */ - -#define MASK_ALE (1 << 22) /* our ALE is A22 */ -#define MASK_CLE (1 << 21) /* our CLE is A21 */ - -#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ -#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ - -#define KB9202_SMC2_NWS (1 << 2) -#define KB9202_SMC2_TDF (1 << 8) -#define KB9202_SMC2_RWSETUP (1 << 24) -#define KB9202_SMC2_RWHOLD (1 << 29) - -/* - * Board-specific function to access device control signals - */ -static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - /* clear ALE and CLE bits */ - IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); - - if (ctrl & NAND_CLE) - IO_ADDR_W |= MASK_CLE; - - if (ctrl & NAND_ALE) - IO_ADDR_W |= MASK_ALE; - - this->IO_ADDR_W = (void *) IO_ADDR_W; - - if (ctrl & NAND_NCE) - writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); - else - writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -/* - * Board-specific function to access the device ready signal. - */ -static int kb9202_nand_ready(struct mtd_info *mtd) -{ - return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; -} - - -/* - * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. - * - * struct nand_chip - NAND Private Flash Chip Data - * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device - * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device - * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines - * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line - * If set to NULL no access to ready/busy is available and the ready/busy information - * is read from the chip status register - * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only - * be provided if a hardware ECC is available - * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines - * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) - * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about - * special functionality. See the defines for further explanation -*/ -/* - * This routine initializes controller and GPIOs. - */ -int board_nand_init(struct nand_chip *nand) -{ - unsigned int value; - - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = kb9202_nand_hwcontrol; - nand->dev_ready = kb9202_nand_ready; - - /* in case running outside of bootloader */ - writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); - - /* setup nand flash access (allow ample margin) */ - /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ - writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | - AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, - AT91C_SMC_CSR3); - - /* enable internal NAND controller */ - value = readl(AT91C_EBI_CSA); - value |= AT91C_EBI_CS3A_SMC_SmartMedia; - writel(value, AT91C_EBI_CSA); - - /* enable SMOE/SMWE */ - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); - - /* set NCE to high */ - writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); - - /* disable output on pin connected to the busy line of the NAND */ - writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); - - /* enable the PIO to control NCE and BUSY */ - writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); - - /* enable output for NCE */ - writel(KB9202_NAND_NCE, AT91C_PIOC_OER); - - return (0); -}

This option does not exist, so drop the dead code.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Makefile | 4 ---- 1 file changed, 4 deletions(-)

diff --git a/Makefile b/Makefile index 400261606e3..d7a0121828c 100644 --- a/Makefile +++ b/Makefile @@ -2004,10 +2004,6 @@ dtbs: prepare3 scripts_dtc dtbs_install: $(Q)$(MAKE) $(dtbinst)=$(dtstree)

-ifdef CONFIG_OF_EARLY_FLATTREE -all: dtbs -endif - endif

# Check dtc and pylibfdt, if DTC is provided, else build them

This option does not exist, so the Makefile rule does nothing. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

Makefile | 1 - 1 file changed, 1 deletion(-)

diff --git a/Makefile b/Makefile index d7a0121828c..21d62f66367 100644 --- a/Makefile +++ b/Makefile @@ -956,7 +956,6 @@ endif # Always append INPUTS so that arch config.mk's can add custom ones INPUTS-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check

-INPUTS-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) INPUTS-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/mips/mach-octeon/octeon_fdt.c | 43 +--------- board/gdsys/a38x/hre.c | 1 - drivers/gpio/Makefile | 1 - drivers/gpio/pca9698.c | 127 ----------------------------- include/pca9698.h | 17 ---- 5 files changed, 1 insertion(+), 188 deletions(-) delete mode 100644 drivers/gpio/pca9698.c delete mode 100644 include/pca9698.h

diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c index 0ccfe149dcc..c74fe9d9fb8 100644 --- a/arch/mips/mach-octeon/octeon_fdt.c +++ b/arch/mips/mach-octeon/octeon_fdt.c @@ -30,9 +30,6 @@ #ifdef CONFIG_PCF857X #include <pcf857x.h> #endif -#ifdef CONFIG_PCA9698 -#include <pca9698.h> -#endif #ifdef CONFIG_PCA9554 #include <pca9554.h> #endif @@ -59,13 +56,6 @@ static const char * const pca9555_gpio_list[] = { }; #endif

-#ifdef CONFIG_PCA9698 -/** List of compatible strings supported by pca9698 driver */ -static const char * const pca9698_gpio_list[] = { - "nxp,pca9505", "pca9505", "nxp,pca9698", "pca9698", NULL, -}; -#endif - #ifdef CONFIG_PCA953X /** List of compatible strings supported by pca953x driver */ static const char * const pca953x_gpio_list[] = { @@ -807,19 +797,6 @@ int octeon_fdt_read_gpio(const void *fdt, int phandle, int pin) } value = (value >> pin) & 1; break; -#endif -#ifdef CONFIG_PCA9698 - case CVMX_GPIO_PIN_PCA9698: - node = fdt_node_offset_by_phandle(fdt, phandle); - if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) { - printf("%s: Could not get gpio bus and/or address\n", __func__); - return -1; - } - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(bus); - value = pca9698_get_value(addr, pin); - i2c_set_bus_num(old_bus); - break; #endif case CVMX_GPIO_PIN_OCTEON: value = gpio_get_value(pin); @@ -880,18 +857,6 @@ int octeon_fdt_set_gpio(const void *fdt, int phandle, int pin, int val) return -1; } return pcf957x_set_val(bus, addr, 1 << pin, val << pin); -#endif -#ifdef CONFIG_PCA9698 - case CVMX_GPIO_PIN_PCA9698: - if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) { - printf("%s: Could not get gpio bus and/or address\n", __func__); - return -1; - } - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(bus); - rc = pca9698_set_value(addr, pin, val); - i2c_set_bus_num(old_bus); - return rc; #endif case CVMX_GPIO_PIN_OCTEON: return gpio_set_value(pin, val); @@ -951,13 +916,7 @@ int octeon_fdt_get_gpio_info(int fdt_node, enum octeon_gpio_type *type, *type = GPIO_TYPE_PCA953X; } #endif -#ifdef CONFIG_PCA9698 - if (!octeon_fdt_node_check_compatible(fdt, fdt_node, pca9698_gpio_list)) { - debug("%s: Found PCA9698 compatible GPIO", __func__); - *type = GPIO_TYPE_PCA9698; - } -#endif -#if defined(CONFIG_PCA953X) || defined(CONFIG_PCA9698) || \ +#if defined(CONFIG_PCA953X) || \ defined(CONFIG_PCA9555) || defined(CONFIG_PCA9554) if (!i2c_addr || !i2c_bus) { printf("%s: Error: i2c_addr or i2c_bus is NULL\n", __func__); diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c index 2f16a4d3e11..d16233ed78e 100644 --- a/board/gdsys/a38x/hre.c +++ b/board/gdsys/a38x/hre.c @@ -15,7 +15,6 @@ #include <u-boot/sha1.h> #include <asm/byteorder.h> #include <asm/unaligned.h> -#include <pca9698.h>

#include "hre.h"

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 889a88dc885..fcd136367ac 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o -obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c deleted file mode 100644 index 11274c78101..00000000000 --- a/drivers/gpio/pca9698.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -/* - * Driver for NXP's pca9698 40 bit I2C gpio expander - */ - -#include <common.h> -#include <i2c.h> -#include <malloc.h> -#include <linux/errno.h> -#include <pca9698.h> - -/* - * The pca9698 registers - */ - -#define PCA9698_REG_INPUT 0x00 -#define PCA9698_REG_OUTPUT 0x08 -#define PCA9698_REG_POLARITY 0x10 -#define PCA9698_REG_CONFIG 0x18 - -#define PCA9698_BUFFER_SIZE 5 -#define PCA9698_GPIO_COUNT 40 - -static int pca9698_read40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static int pca9698_write40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value) -{ - unsigned byte = gpio / 8; - unsigned bit = gpio % 8; - - if (value) - buffer[byte] |= (1 << bit); - else - buffer[byte] &= ~(1 << bit); -} - -int pca9698_request(unsigned gpio, const char *label) -{ - if (gpio >= PCA9698_GPIO_COUNT) - return -EINVAL; - - return 0; -} - -void pca9698_free(unsigned gpio) -{ -} - -int pca9698_direction_input(u8 addr, unsigned gpio) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 1); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_direction_output(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_set_value(addr, gpio, value); - if (res) - return res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 0); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_get_value(u8 addr, unsigned gpio) -{ - unsigned config_byte = gpio / 8; - unsigned config_bit = gpio % 8; - unsigned value; - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_INPUT, data); - if (res) - return -1; - - value = data[config_byte] & (1 << config_bit); - - return !!value; -} - -int pca9698_set_value(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, value); - - return pca9698_write40(addr, PCA9698_REG_OUTPUT, data); -} diff --git a/include/pca9698.h b/include/pca9698.h deleted file mode 100644 index 48a5f756e28..00000000000 --- a/include/pca9698.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef __PCA9698_H_ -#define __PCA9698_H_ - -int pca9698_request(unsigned gpio, const char *label); -void pca9698_free(unsigned gpio); -int pca9698_direction_input(u8 addr, unsigned gpio); -int pca9698_direction_output(u8 addr, unsigned gpio, int value); -int pca9698_get_value(u8 addr, unsigned gpio); -int pca9698_set_value(u8 addr, unsigned gpio, int value); - -#endif /* __PCA9698_H_ */

This driver and bat_trats2 are not used. Drop them and the entire battery directory, since there is nothing left.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/power/Makefile | 1 - drivers/power/battery/Makefile | 7 --- drivers/power/battery/bat_trats.c | 91 ------------------------------ drivers/power/battery/bat_trats2.c | 65 --------------------- 4 files changed, 164 deletions(-) delete mode 100644 drivers/power/battery/Makefile delete mode 100644 drivers/power/battery/bat_trats.c delete mode 100644 drivers/power/battery/bat_trats2.c

diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 34a84808a9c..efdae3655ac 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -4,7 +4,6 @@ # Tom Rix <Tom.Rix at windriver.com>

obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ -obj-y += battery/ obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ obj-y += fuel_gauge/ obj-y += mfd/ diff --git a/drivers/power/battery/Makefile b/drivers/power/battery/Makefile deleted file mode 100644 index 370923a6ed9..00000000000 --- a/drivers/power/battery/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski l.majewski@samsung.com - -obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o -obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c deleted file mode 100644 index 54b2bf91e5c..00000000000 --- a/drivers/power/battery/bat_trats.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski l.majewski@samsung.com - */ - -#include <common.h> -#include <console.h> -#include <log.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max8997_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - struct battery *battery = p_bat->bat; - int k; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -1; - - for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && - bat->chrg->chrg_type(p_bat->muic) && - battery->state_of_chrg < 100; k++) { - udelay(2000000); - if (!(k % 5)) - puts("."); - bat->fg->fg_battery_update(p_bat->fg, bat); - - if (k == 200) { - debug(" %d [V]", battery->voltage_uV); - puts("\n"); - k = 0; - } - - if (ctrlc()) { - printf("\nCharging disabled on request.\n"); - goto exit; - } - } - exit: - bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); - - return 0; -} - -static int power_battery_init_trats(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats; - return 0; -} diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c deleted file mode 100644 index 1172970d1e0..00000000000 --- a/drivers/power/battery/bat_trats2.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek p.wilczek@samsung.com - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max77693_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -EINVAL; - - return 0; -} - -static int power_battery_init_trats2(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats2 = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats2, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS2"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats2; - return 0; -}

This driver is not used and has lain unconverted since:

fc47cf9d054 arm: exynos: i2c: Convert exynos boards to use DM_I2C

Drop it and the entire mfd directory, since there is nothing left.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/power/Makefile | 1 - drivers/power/mfd/Makefile | 6 --- drivers/power/mfd/muic_max77693.c | 77 ------------------------------- 3 files changed, 84 deletions(-) delete mode 100644 drivers/power/mfd/Makefile delete mode 100644 drivers/power/mfd/muic_max77693.c

diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 93003e97e01..ba64b2c5938 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -5,7 +5,6 @@

obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ -obj-y += mfd/ obj-y += pmic/ obj-y += regulator/

diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile deleted file mode 100644 index b5ec8f00bb0..00000000000 --- a/drivers/power/mfd/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Samsung Electronics -# Piotr Wilczek p.wilczek@samsung.com - -obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o diff --git a/drivers/power/mfd/muic_max77693.c b/drivers/power/mfd/muic_max77693.c deleted file mode 100644 index 36ee44b9a2c..00000000000 --- a/drivers/power/mfd/muic_max77693.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek p.wilczek@samsung.com - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/power_chrg.h> -#include <power/max77693_muic.h> -#include <i2c.h> -#include <errno.h> - -static int power_chrg_get_type(struct pmic *p) -{ - unsigned int val; - unsigned int charge_type, charger; - - /* if probe failed, return cable none */ - if (pmic_probe(p)) - return CHARGER_NO; - - pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val); - - charge_type = val & MAX77693_MUIC_CHG_MASK; - - switch (charge_type) { - case MAX77693_MUIC_CHG_NO: - charger = CHARGER_NO; - break; - case MAX77693_MUIC_CHG_USB: - case MAX77693_MUIC_CHG_USB_D: - charger = CHARGER_USB; - break; - case MAX77693_MUIC_CHG_TA: - case MAX77693_MUIC_CHG_TA_1A: - charger = CHARGER_TA; - break; - case MAX77693_MUIC_CHG_TA_500: - charger = CHARGER_TA_500; - break; - default: - charger = CHARGER_UNKNOWN; - break; - } - - return charger; -} - -static struct power_chrg power_chrg_muic_ops = { - .chrg_type = power_chrg_get_type, -}; - -int power_muic_init(unsigned int bus) -{ - static const char name[] = "MAX77693_MUIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Micro USB Interface Controller init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = MUIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_muic_ops; - - return 0; -}

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

board/freescale/common/Makefile | 1 - board/freescale/common/pq-mds-pib.c | 60 ----------------------------- board/freescale/common/pq-mds-pib.h | 9 ----- 3 files changed, 70 deletions(-) delete mode 100644 board/freescale/common/pq-mds-pib.c delete mode 100644 board/freescale/common/pq-mds-pib.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 9d5f38bb225..bd035d60a58 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -36,7 +36,6 @@ obj-$(I2C_COMMON) += i2c_common.o obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o obj-$(CONFIG_$(SPL_)VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o -obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c deleted file mode 100644 index 162c8a954f0..00000000000 --- a/board/freescale/common/pq-mds-pib.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Tony Li tony.li@freescale.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> - -#include "pq-mds-pib.h" - -int pib_init(void) -{ - u8 val8; - u8 orig_i2c_bus; - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; -#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) - /* Assign PIB PMC slot to desired PCI bus */ - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - - eieio(); - - printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); -#endif - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - return 0; -} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h deleted file mode 100644 index 67066fd118d..00000000000 --- a/board/freescale/common/pq-mds-pib.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -extern int pib_init(void);

These drivers are not used and have not been converted to driver model. Drop them and references to the non-existent CONFIG options they use.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/rtc/Makefile | 14 -- drivers/rtc/at91sam9_rtt.c | 78 ------- drivers/rtc/ds1302.c | 329 ---------------------------- drivers/rtc/ds1306.c | 438 ------------------------------------- drivers/rtc/ftrtc010.c | 122 ----------- drivers/rtc/imxdi.c | 223 ------------------- drivers/rtc/max6900.c | 105 --------- drivers/rtc/mk48t59.c | 175 --------------- drivers/rtc/mx27rtc.c | 64 ------ drivers/rtc/rs5c372.c | 256 ---------------------- drivers/rtc/s3c24x0_rtc.c | 149 ------------- drivers/rtc/x1205.c | 161 -------------- 12 files changed, 2114 deletions(-) delete mode 100644 drivers/rtc/at91sam9_rtt.c delete mode 100644 drivers/rtc/ds1302.c delete mode 100644 drivers/rtc/ds1306.c delete mode 100644 drivers/rtc/ftrtc010.c delete mode 100644 drivers/rtc/imxdi.c delete mode 100644 drivers/rtc/max6900.c delete mode 100644 drivers/rtc/mk48t59.c delete mode 100644 drivers/rtc/mx27rtc.c delete mode 100644 drivers/rtc/rs5c372.c delete mode 100644 drivers/rtc/s3c24x0_rtc.c delete mode 100644 drivers/rtc/x1205.c

diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index acfd130bbc9..447551e15aa 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -6,49 +6,35 @@

obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o

-obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o -obj-$(CONFIG_RTC_DS1302) += ds1302.o -obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o -obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o -obj-$(CONFIG_RTC_DS1388) += ds1337.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o -obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o -obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T62) += m41t62.o -obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o -obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o -obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MV) += mvrtc.o -obj-$(CONFIG_RTC_MX27) += mx27rtc.o obj-$(CONFIG_RTC_MXS) += mxsrtc.o obj-$(CONFIG_RTC_PCF8563) += pcf8563.o obj-$(CONFIG_RTC_PCF2127) += pcf2127.o obj-$(CONFIG_RTC_PL031) += pl031.o obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o -obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o obj-$(CONFIG_RTC_RV3028) += rv3028.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RV8803) += rv8803.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o -obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_RTC_STM32) += stm32_rtc.o obj-$(CONFIG_SANDBOX) += sandbox_rtc.o -obj-$(CONFIG_RTC_X1205) += x1205.o obj-$(CONFIG_RTC_ABX80X) += abx80x.o obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c deleted file mode 100644 index 6f92660ef1d..00000000000 --- a/drivers/rtc/at91sam9_rtt.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - */ - -/* - * Date & Time support for the internal Real-time Timer - * of AT91SAM9260 and compatibles. - * Compatible with the LinuX rtc driver workaround: - * The RTT cannot be written to, but only reset. - * The actual time is the sum of RTT and one of - * the four GPBR registers. - * - * The at91sam9260 has 4 GPBR (0-3). - * For their typical use see at91_gpbr.h ! - * - * make sure u-boot and kernel use the same GPBR ! - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_rtt.h> -#include <asm/arch/at91_gpbr.h> - -int rtc_get (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - ulong tim2; - ulong off; - - do { - tim = readl(&rtt->vr); - tim2 = readl(&rtt->vr); - } while (tim!=tim2); - off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* off==0 means time is invalid, but we ignore that */ - rtc_to_tm(tim+off, tmp); - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - - tim = rtc_mktime(tmp); - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; - return 0; -} - -void rtc_reset (void) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; -} diff --git a/drivers/rtc/ds1302.c b/drivers/rtc/ds1302.c deleted file mode 100644 index 189607c3e02..00000000000 --- a/drivers/rtc/ds1302.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip - * - * Rex G. Feany rfeany@zumanetworks.com - * - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <linux/delay.h> - -/* GPP Pins */ -#define DATA 0x200 -#define SCLK 0x400 -#define RST 0x800 - -/* Happy Fun Defines(tm) */ -#define RESET rtc_go_low(RST), rtc_go_low(SCLK) -#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK) - -#define CLOCK_HIGH rtc_go_high(SCLK) -#define CLOCK_LOW rtc_go_low(SCLK) - -#define DATA_HIGH rtc_go_high(DATA) -#define DATA_LOW rtc_go_low(DATA) -#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA) - -#undef RTC_DEBUG - -#ifdef RTC_DEBUG -# define DPRINTF(x,args...) printf("ds1302: " x , ##args) -static inline void DUMP(const char *ptr, int num) -{ - while (num--) printf("%x ", *ptr++); - printf("]\n"); -} -#else -# define DPRINTF(x,args...) -# define DUMP(ptr, num) -#endif - -/* time data format for DS1302 */ -struct ds1302_st -{ - unsigned char CH:1; /* clock halt 1=stop 0=start */ - unsigned char sec10:3; - unsigned char sec:4; - - unsigned char zero0:1; - unsigned char min10:3; - unsigned char min:4; - - unsigned char fmt:1; /* 1=12 hour 0=24 hour */ - unsigned char zero1:1; - unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */ - unsigned char hr:4; - - unsigned char zero2:2; - unsigned char date10:2; - unsigned char date:4; - - unsigned char zero3:3; - unsigned char month10:1; - unsigned char month:4; - - unsigned char zero4:5; - unsigned char day:3; /* day of week */ - - unsigned char year10:4; - unsigned char year:4; - - unsigned char WP:1; /* write protect 1=protect 0=unprot */ - unsigned char zero5:7; -}; - -static int ds1302_initted=0; - -/* Pin control */ -static inline void -rtc_go_high(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) | mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_low(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_input(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -static inline void -rtc_go_output(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -/* Access data in RTC */ - -static void -write_byte(unsigned char b) -{ - int i; - unsigned char mask=1; - - for(i=0;i<8;i++) { - CLOCK_LOW; /* Lower clock */ - (b&mask)?DATA_HIGH:DATA_LOW; /* set data */ - udelay(1); - CLOCK_HIGH; /* latch data with rising clock */ - udelay(1); - mask=mask<<1; - } -} - -static unsigned char -read_byte(void) -{ - int i; - unsigned char mask=1; - unsigned char b=0; - - for(i=0;i<8;i++) { - CLOCK_LOW; - udelay(1); - if (DATA_READ) b|=mask; /* if this bit is high, set in b */ - CLOCK_HIGH; /* clock out next bit */ - udelay(1); - mask=mask<<1; - } - return b; -} - -static void -read_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; -#ifdef RTC_DEBUG - char *foo = buf; -#endif - - DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); - - addr|=1; /* READ */ - N_RESET; - udelay(4); - write_byte(addr); - rtc_go_input(DATA); /* Put gpp pin into input mode */ - udelay(1); - for(i=0;i<count;i++) *(buf++)=read_byte(); - RESET; - rtc_go_output(DATA);/* Reset gpp for output */ - udelay(4); - - DUMP(foo, count); -} - -static void -write_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; - - DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr); - DUMP(buf, count); - - addr&=~1; /* WRITE */ - N_RESET; - udelay(4); - write_byte(addr); - for(i=0;i<count;i++) write_byte(*(buf++)); - RESET; - udelay(4); - -} - -void -rtc_init(void) -{ - struct ds1302_st bbclk; - unsigned char b; - int mod; - - DPRINTF("init\n"); - - rtc_go_output(DATA|SCLK|RST); - - /* disable write protect */ - b = 0; - write_ser_drv(0x8e,&b,1); - - /* enable trickle */ - b = 0xa5; /* 1010.0101 */ - write_ser_drv(0x90,&b,1); - - /* read burst */ - read_ser_drv(0xbe, (unsigned char *)&bbclk, 8); - - /* Sanity checks */ - mod = 0; - if (bbclk.CH) { - printf("ds1302: Clock was halted, starting clock\n"); - bbclk.CH=0; - mod=1; - } - - if (bbclk.fmt) { - printf("ds1302: Clock was in 12 hour mode, fixing\n"); - bbclk.fmt=0; - mod=1; - } - - if (bbclk.year>9) { - printf("ds1302: Year was corrupted, fixing\n"); - bbclk.year10=100/10; /* 2000 - why not? ;) */ - bbclk.year=0; - mod=1; - } - - /* Write out the changes if needed */ - if (mod) { - /* enable write protect */ - bbclk.WP = 1; - write_ser_drv(0xbe,(unsigned char *)&bbclk,8); - } else { - /* Else just turn write protect on */ - b = 0x80; - write_ser_drv(0x8e,&b,1); - } - DPRINTF("init done\n"); - - ds1302_initted=1; -} - -void -rtc_reset(void) -{ - if(!ds1302_initted) rtc_init(); - /* TODO */ -} - -int -rtc_get(struct rtc_time *tmp) -{ - int rel = 0; - struct ds1302_st bbclk; - - if(!ds1302_initted) rtc_init(); - - read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */ - - if (bbclk.CH) { - printf("ds1302: rtc_get: Clock was halted, clock probably " - "corrupt\n"); - rel = -1; - } - - tmp->tm_sec=10*bbclk.sec10+bbclk.sec; - tmp->tm_min=10*bbclk.min10+bbclk.min; - tmp->tm_hour=10*bbclk.hr10+bbclk.hr; - tmp->tm_wday=bbclk.day; - tmp->tm_mday=10*bbclk.date10+bbclk.date; - tmp->tm_mon=10*bbclk.month10+bbclk.month; - tmp->tm_year=10*bbclk.year10+bbclk.year + 1900; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); - - return rel; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct ds1302_st bbclk; - unsigned char b=0; - - if(!ds1302_initted) rtc_init(); - - DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - memset(&bbclk,0,sizeof(bbclk)); - bbclk.CH=0; /* dont halt */ - bbclk.WP=1; /* write protect when we're done */ - - bbclk.sec10=tmp->tm_sec/10; - bbclk.sec=tmp->tm_sec%10; - - bbclk.min10=tmp->tm_min/10; - bbclk.min=tmp->tm_min%10; - - bbclk.hr10=tmp->tm_hour/10; - bbclk.hr=tmp->tm_hour%10; - - bbclk.day=tmp->tm_wday; - - bbclk.date10=tmp->tm_mday/10; - bbclk.date=tmp->tm_mday%10; - - bbclk.month10=tmp->tm_mon/10; - bbclk.month=tmp->tm_mon%10; - - tmp->tm_year -= 1900; - bbclk.year10=tmp->tm_year/10; - bbclk.year=tmp->tm_year%10; - - write_ser_drv(0x8e,&b,1); /* disable write protect */ - write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */ - - return 0; -} diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c deleted file mode 100644 index 36d615812b2..00000000000 --- a/drivers/rtc/ds1306.c +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 SIXNET, dge@sixnetio.com. - * - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz linz@li-pro.net - */ - -/* - * Date & Time support for DS1306 RTC using SPI: - * - * - SXNI855T: it uses its own soft SPI here in this file - * - all other: use the external spi_xfer() function - * (see include/spi.h) - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <spi.h> -#include <linux/delay.h> - -#define RTC_SECONDS 0x00 -#define RTC_MINUTES 0x01 -#define RTC_HOURS 0x02 -#define RTC_DAY_OF_WEEK 0x03 -#define RTC_DATE_OF_MONTH 0x04 -#define RTC_MONTH 0x05 -#define RTC_YEAR 0x06 - -#define RTC_SECONDS_ALARM0 0x07 -#define RTC_MINUTES_ALARM0 0x08 -#define RTC_HOURS_ALARM0 0x09 -#define RTC_DAY_OF_WEEK_ALARM0 0x0a - -#define RTC_SECONDS_ALARM1 0x0b -#define RTC_MINUTES_ALARM1 0x0c -#define RTC_HOURS_ALARM1 0x0d -#define RTC_DAY_OF_WEEK_ALARM1 0x0e - -#define RTC_CONTROL 0x0f -#define RTC_STATUS 0x10 -#define RTC_TRICKLE_CHARGER 0x11 - -#define RTC_USER_RAM_BASE 0x20 - -/* ************************************************************************* */ -#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ - -static void soft_spi_send (unsigned char n); -static unsigned char soft_spi_read (void); -static void init_spi (void); - -/*----------------------------------------------------------------------- - * Definitions - */ - -#define PB_SPISCK 0x00000002 /* PB 30 */ -#define PB_SPIMOSI 0x00000004 /* PB 29 */ -#define PB_SPIMISO 0x00000008 /* PB 28 */ -#define PB_SPI_CE 0x00010000 /* PB 15 */ - -/* ------------------------------------------------------------------------- */ - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char spi_byte; /* Data Byte */ - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Shift out the address (0) of the time in the Clock Chip */ - soft_spi_send (0); - - /* Put the clock readings into the rtc_time structure */ - tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ - tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ - - /* Hours are trickier */ - spi_byte = soft_spi_read (); /* Read Hours into temporary value */ - if (spi_byte & 0x40) { - /* 12 hour mode bit is set (time is in 1-12 format) */ - if (spi_byte & 0x20) { - /* since PM we add 11 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; - } else { - /* since AM we subtract 1 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; - } - } else { - /* Otherwise, 0-23 hour format */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); - } - - soft_spi_read (); /* Read and discard Day of week */ - tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ - tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ - - /* Read Year and convert to this century */ - tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; - - /* Now we can disable the DS1306 RTC */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - rtc_calc_weekday(tmp); /* Determine the day of week */ - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time in DS1306 RTC and in MPC8xx RTC */ -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First disable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x00); /* send control register contents */ - - /* Now disable the DS1306 to terminate the write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay(10); - - /* Now enable the DS1306 to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Next, send the address of the clock time write registers */ - soft_spi_send (0x80); /* send address of the first time register */ - - /* Use Burst Mode to send all of the time data to the clock */ - bin2bcd (tmp->tm_sec); - soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ - soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ - soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ - soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ - soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ - soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ - soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ - - /* Now we can disable the Clock chip to terminate the burst write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Now we can enable the Clock chip to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First we Enable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x40); /* send out Control Register contents */ - - /* Now disable the DS1306 */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Set standard MPC8xx clock to the same time so Linux will - * see the time even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - - tim = rtc_mktime(tmp); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Initialize Port B for software SPI */ -static void init_spi (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Force output pins to begin at logic 0 */ - immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); - - /* Set these 3 signals as outputs */ - immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); - - immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay(10); -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ -static void soft_spi_send (unsigned char n) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to send, start with most significant bit */ - bitpos = 0x80; - - /* Send 8 bits to software SPI */ - for (i = 0; i < 8; i++) { /* Loop for 8 bits */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - - if (n & bitpos) - immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ - else - immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay(10); - - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - - bitpos >>= 1; /* Shift for next bit position */ - } -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ -static unsigned char soft_spi_read (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - unsigned char spi_byte = 0; /* Return value, assume success */ - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to receive, start with most significant bit */ - bitpos = 0x80; - - /* Read 8 bits here */ - for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay(10); - if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ - spi_byte |= bitpos; /* Set data accordingly */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - bitpos >>= 1; /* Shift for next bit position */ - } - - return spi_byte; /* Return the byte read */ -} - -/* ------------------------------------------------------------------------- */ - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#else /* not CONFIG_SXNI855T */ -/* ************************************************************************* */ - -static unsigned char rtc_read (unsigned char reg); -static void rtc_write (unsigned char reg, unsigned char val); - -static struct spi_slave *slave; - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - unsigned char sec, min, hour, mday, wday, mon, year; - - /* - * Assuming Vcc = 2.0V (lowest speed) - * - * REVISIT: If we add an rtc_init() function we can do this - * step just once. - */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DATE_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - spi_release_bus(slave); - - debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM0), - rtc_read (RTC_HOURS_ALARM0), - rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); - debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM1), - rtc_read (RTC_HOURS_ALARM1), - rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); - - tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ - tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ - - /* convert Hours */ - tmp->tm_hour = (hour & 0x40) - ? ((hour & 0x20) /* 12 hour mode */ - ? bcd2bin (hour & 0x1F) + 11 /* PM */ - : bcd2bin (hour & 0x1F) - 1 /* AM */ - ) - : bcd2bin (hour & 0x3F); /* 24 hour mode */ - - tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ - tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ - tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ - tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time from *tmp in DS1306 RTC */ -int rtc_set (struct rtc_time *tmp) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); - rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); - rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -/* reset the DS1306 */ -void rtc_reset (void) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - /* clear the control register */ - rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ - rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ - - /* reset all alarms */ - rtc_write (RTC_SECONDS_ALARM0, 0x00); - rtc_write (RTC_SECONDS_ALARM1, 0x00); - rtc_write (RTC_MINUTES_ALARM0, 0x00); - rtc_write (RTC_MINUTES_ALARM1, 0x00); - rtc_write (RTC_HOURS_ALARM0, 0x00); - rtc_write (RTC_HOURS_ALARM1, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned char rtc_read (unsigned char reg) -{ - int ret; - - ret = spi_w8r8(slave, reg); - return ret < 0 ? 0 : ret; -} - -/* ------------------------------------------------------------------------- */ - -static void rtc_write (unsigned char reg, unsigned char val) -{ - unsigned char dout[2]; /* SPI Output Data Bytes */ - unsigned char din[2]; /* SPI Input Data Bytes */ - - dout[0] = 0x80 | reg; - dout[1] = val; - - spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); -} - -#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c deleted file mode 100644 index e384922f473..00000000000 --- a/drivers/rtc/ftrtc010.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday FTRTC010 Real Time Clock - * - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang ratbert@faraday-tech.com - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <rtc.h> -#include <asm/io.h> - -struct ftrtc010 { - unsigned int sec; /* 0x00 */ - unsigned int min; /* 0x04 */ - unsigned int hour; /* 0x08 */ - unsigned int day; /* 0x0c */ - unsigned int alarm_sec; /* 0x10 */ - unsigned int alarm_min; /* 0x14 */ - unsigned int alarm_hour; /* 0x18 */ - unsigned int record; /* 0x1c */ - unsigned int cr; /* 0x20 */ - unsigned int wsec; /* 0x24 */ - unsigned int wmin; /* 0x28 */ - unsigned int whour; /* 0x2c */ - unsigned int wday; /* 0x30 */ - unsigned int intr; /* 0x34 */ - unsigned int div; /* 0x38 */ - unsigned int rev; /* 0x3c */ -}; - -/* - * RTC Control Register - */ -#define FTRTC010_CR_ENABLE (1 << 0) -#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ -#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ -#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ -#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ - -static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; - -static void ftrtc010_enable(void) -{ - writel(FTRTC010_CR_ENABLE, &rtc->cr); -} - -/* - * return current time in seconds - */ -static unsigned long ftrtc010_time(void) -{ - unsigned long day; - unsigned long hour; - unsigned long minute; - unsigned long second; - unsigned long second2; - - do { - second = readl(&rtc->sec); - day = readl(&rtc->day); - hour = readl(&rtc->hour); - minute = readl(&rtc->min); - second2 = readl(&rtc->sec); - } while (second != second2); - - return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; -} - -/* - * Get the current time from the RTC - */ - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - - debug("%s(): record register: %x\n", - __func__, readl(&rtc->record)); - -#ifdef CFG_FTRTC010_PCLK - now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; -#else /* CFG_FTRTC010_EXTCLK */ - now = ftrtc010_time() + readl(&rtc->record); -#endif - - rtc_to_tm(now, tmp); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set(struct rtc_time *tmp) -{ - unsigned long new; - unsigned long now; - - debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - __func__, - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - new = rtc_mktime(tmp); - - now = ftrtc010_time(); - - debug("%s(): write %lx to record register\n", __func__, new - now); - - writel(new - now, &rtc->record); - - return 0; -} - -void rtc_reset(void) -{ - debug("%s()\n", __func__); - ftrtc010_enable(); -} diff --git a/drivers/rtc/imxdi.c b/drivers/rtc/imxdi.c deleted file mode 100644 index e3a1393266c..00000000000 --- a/drivers/rtc/imxdi.c +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009-2012 ADVANSEE - * Benoît Thébaudeau benoit.thebaudeau@advansee.com - * - * Based on the Linux rtc-imxdi.c driver, which is: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2010 Orex Computed Radiography - */ - -/* - * Date & Time support for Freescale i.MX DryIce RTC - */ - -#include <common.h> -#include <command.h> -#include <linux/compat.h> -#include <rtc.h> -#include <linux/delay.h> - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -/* DryIce Register Definitions */ - -struct imxdi_regs { - u32 dtcmr; /* Time Counter MSB Reg */ - u32 dtclr; /* Time Counter LSB Reg */ - u32 dcamr; /* Clock Alarm MSB Reg */ - u32 dcalr; /* Clock Alarm LSB Reg */ - u32 dcr; /* Control Reg */ - u32 dsr; /* Status Reg */ - u32 dier; /* Interrupt Enable Reg */ -}; - -#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ - -#define DCR_TCE (1 << 3) /* Time Counter Enable */ - -#define DSR_WBF (1 << 10) /* Write Busy Flag */ -#define DSR_WNF (1 << 9) /* Write Next Flag */ -#define DSR_WCF (1 << 8) /* Write Complete Flag */ -#define DSR_WEF (1 << 7) /* Write Error Flag */ -#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ -#define DSR_NVF (1 << 1) /* Non-Valid Flag */ -#define DSR_SVF (1 << 0) /* Security Violation Flag */ - -#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ -#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ -#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ -#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ - -/* Driver Private Data */ - -struct imxdi_data { - struct imxdi_regs __iomem *regs; - int init_done; -}; - -static struct imxdi_data data; - -/* - * This function attempts to clear the dryice write-error flag. - * - * A dryice write error is similar to a bus fault and should not occur in - * normal operation. Clearing the flag requires another write, so the root - * cause of the problem may need to be fixed before the flag can be cleared. - */ -static void clear_write_error(void) -{ - int cnt; - - puts("### Warning: RTC - Register write error!\n"); - - /* clear the write error flag */ - __raw_writel(DSR_WEF, &data.regs->dsr); - - /* wait for it to take effect */ - for (cnt = 0; cnt < 1000; cnt++) { - if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) - return; - udelay(10); - } - puts("### Error: RTC - Cannot clear write-error flag!\n"); -} - -/* - * Write a dryice register and wait until it completes. - * - * Use interrupt flags to determine when the write has completed. - */ -#define DI_WRITE_WAIT(val, reg) \ -( \ - /* do the register write */ \ - __raw_writel((val), &data.regs->reg), \ - \ - di_write_wait((val), #reg) \ -) -static int di_write_wait(u32 val, const char *reg) -{ - int cnt; - int ret = 0; - int rc = 0; - - /* wait for the write to finish */ - for (cnt = 0; cnt < 100; cnt++) { - if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { - ret = 1; - break; - } - udelay(10); - } - if (ret == 0) - printf("### Warning: RTC - Write-wait timeout " - "val = 0x%.8x reg = %s\n", val, reg); - - /* check for write error */ - if (__raw_readl(&data.regs->dsr) & DSR_WEF) { - clear_write_error(); - rc = -1; - } - - return rc; -} - -/* - * Initialize dryice hardware - */ -static int di_init(void) -{ - int rc = 0; - - data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE; - - /* mask all interrupts */ - __raw_writel(0, &data.regs->dier); - - /* put dryice into valid state */ - if (__raw_readl(&data.regs->dsr) & DSR_NVF) { - rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr); - if (rc) - goto err; - } - - /* initialize alarm */ - rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr); - if (rc) - goto err; - rc = DI_WRITE_WAIT(0, dcalr); - if (rc) - goto err; - - /* clear alarm flag */ - if (__raw_readl(&data.regs->dsr) & DSR_CAF) { - rc = DI_WRITE_WAIT(DSR_CAF, dsr); - if (rc) - goto err; - } - - /* the timer won't count if it has never been written to */ - if (__raw_readl(&data.regs->dtcmr) == 0) { - rc = DI_WRITE_WAIT(0, dtcmr); - if (rc) - goto err; - } - - /* start keeping time */ - if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { - rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); - if (rc) - goto err; - } - - data.init_done = 1; - return 0; - -err: - return rc; -} - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - int rc = 0; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = __raw_readl(&data.regs->dtcmr); - rtc_to_tm(now, tmp); - -err: - return rc; -} - -int rtc_set(struct rtc_time *tmp) -{ - unsigned long now; - int rc; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = rtc_mktime(tmp); - /* zero the fractional part first */ - rc = DI_WRITE_WAIT(0, dtclr); - if (rc == 0) - rc = DI_WRITE_WAIT(now, dtcmr); - -err: - return rc; -} - -void rtc_reset(void) -{ - di_init(); -} diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c deleted file mode 100644 index e03a87f94da..00000000000 --- a/drivers/rtc/max6900.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * Date & Time support for MAXIM MAX6900 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> -#include <linux/delay.h> - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x50 -#endif - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read (uchar reg) -{ - return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); -} - -static void rtc_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); - udelay(2500); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, mday, wday, mon, cent, year; - int retry = 1; - - do { - sec = rtc_read (0x80); - min = rtc_read (0x82); - hour = rtc_read (0x84); - mday = rtc_read (0x86); - mon = rtc_read (0x88); - wday = rtc_read (0x8a); - year = rtc_read (0x8c); - cent = rtc_read (0x92); - /* - * Check for seconds rollover - */ - if ((sec != 59) || (rtc_read(0x80) == sec)){ - retry = 0; - } - } while (retry); - - debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, cent, mday, wday, - hour, min, sec ); - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100; - tmp->tm_wday = bcd2bin (wday & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (0x9E, 0x00); - rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */ - rtc_write (0x92, bin2bcd(tmp->tm_year / 100)); - rtc_write (0x8c, bin2bcd(tmp->tm_year % 100)); - rtc_write (0x8a, bin2bcd(tmp->tm_wday)); - rtc_write (0x88, bin2bcd(tmp->tm_mon)); - rtc_write (0x86, bin2bcd(tmp->tm_mday)); - rtc_write (0x84, bin2bcd(tmp->tm_hour)); - rtc_write (0x82, bin2bcd(tmp->tm_min )); - rtc_write (0x80, bin2bcd(tmp->tm_sec )); - - return 0; -} - -void rtc_reset (void) -{ -} diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c deleted file mode 100644 index 8c90a704076..00000000000 --- a/drivers/rtc/mk48t59.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel aheppel@sysgo.de - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - -#undef RTC_DEBUG - -#include <common.h> -#include <command.h> -#include <config.h> -#include <rtc.h> -#include <mk48t59.h> - -#if defined(CONFIG_BAB7xx) - -static uchar rtc_read (short reg) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - return in8(RTC_PORT_DATA); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - out8(RTC_PORT_DATA, val); -} - -#elif defined(CONFIG_EVAL5200) - -static uchar rtc_read (short reg) -{ - return in8(RTC(reg)); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC(reg),val); -} - -#else -# error Board specific rtc access functions should be supplied -#endif - -/* ------------------------------------------------------------------------- */ - -void *nvram_read(void *dest, const short src, size_t count) -{ - uchar *d = (uchar *) dest; - short s = src; - - while (count--) - *d++ = rtc_read(s++); - - return dest; -} - -void nvram_write(short dest, const void *src, size_t count) -{ - short d = dest; - uchar *s = (uchar *) src; - - while (count--) - rtc_write(d++, *s++); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - uchar sec, min, hour, mday, wday, mon, year; - - /* Simple: freeze the clock, read it and allow updates again */ - save_ctrl_a = rtc_read(RTC_CONTROLA); - - /* Set the register to read the value. */ - save_ctrl_a |= RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DAY_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - /* re-enable update */ - save_ctrl_a &= ~RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - -#ifdef RTC_DEBUG - printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year); - tmp->tm_wday = bcd2bin (wday & 0x07); - if(tmp->tm_year<70) - tmp->tm_year+=2000; - else - tmp->tm_year+=1900; - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - -#ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - save_ctrl_a = rtc_read(RTC_CONTROLA); - - save_ctrl_a |= RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */ - - rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); - rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); - - rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); - rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday)); - rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); - rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); - rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); - - save_ctrl_a &= ~RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */ - - return 0; -} - -void rtc_reset (void) -{ - uchar control_b; - - /* - * Start oscillator here. - */ - control_b = rtc_read(RTC_CONTROLB); - - control_b &= ~RTC_CB_STOP; - rtc_write(RTC_CONTROLB, control_b); -} - -void rtc_set_watchdog(short multi, short res) -{ - uchar wd_value; - - wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3); - rtc_write(RTC_WATCHDOG, wd_value); -} diff --git a/drivers/rtc/mx27rtc.c b/drivers/rtc/mx27rtc.c deleted file mode 100644 index 563e8a4a361..00000000000 --- a/drivers/rtc/mx27rtc.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale i.MX27 RTC Driver - * - * Copyright (C) 2012 Philippe Reynes tremyfr@yahoo.fr - */ - -#include <common.h> -#include <rtc.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#define HOUR_SHIFT 8 -#define HOUR_MASK 0x1f -#define MIN_SHIFT 0 -#define MIN_MASK 0x3f - -int rtc_get(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - day = readl(&rtc_regs->dayr); - hour = readl(&rtc_regs->hourmin); - sec = readl(&rtc_regs->seconds); - - min = (hour >> MIN_SHIFT) & MIN_MASK; - hour = (hour >> HOUR_SHIFT) & HOUR_MASK; - - sec += min * 60 + hour * 3600 + day * 24 * 3600; - - rtc_to_tm(sec, time); - - return 0; -} - -int rtc_set(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - sec = rtc_mktime(time); - - day = sec / (24 * 3600); - sec = sec % (24 * 3600); - hour = sec / 3600; - sec = sec % 3600; - min = sec / 60; - sec = sec % 60; - - hour = (hour & HOUR_MASK) << HOUR_SHIFT; - hour |= (min & MIN_MASK) << MIN_SHIFT; - - writel(day, &rtc_regs->dayr); - writel(hour, &rtc_regs->hourmin); - writel(sec, &rtc_regs->seconds); - - return 0; -} - -void rtc_reset(void) -{ - /* nothing to do */ -} diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c deleted file mode 100644 index 6b1c23ca5db..00000000000 --- a/drivers/rtc/rs5c372.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * rs5c372.c - * - * Device driver for Ricoh's Real Time Controller RS5C372A. - * - * Copyright (C) 2004 Gary Jennejohn garyj@denx.de - * - * Based in part in ds1307.c - - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com` - * Steven Scholz, steven.scholz@imc-berlin.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> - -/* - * Reads are always done starting with register 15, which requires some - * jumping-through-hoops to access the data correctly. - * - * Writes are always done starting with register 0. - */ - -#define DEBUG 0 - -#if DEBUG -static unsigned int rtc_debug = DEBUG; -#else -#define rtc_debug 0 /* gcc will remove all the debug code for us */ -#endif - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x32 -#endif - -#define RS5C372_RAM_SIZE 0x10 -#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */ -#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */ - -#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */ - -#define USE_24HOUR_MODE 0x20 -#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0) -#define HOURS_AP(n) (((n) >> 5) & 1) -#define HOURS_12(n) bcd2bin((n) & 0x1F) -#define HOURS_24(n) bcd2bin((n) & 0x3F) - - -static int setup_done = 0; - -static int -rs5c372_readram(unsigned char *buf, int len) -{ - int ret; - - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); - if (ret != 0) { - printf("%s: failed to read\n", __FUNCTION__); - return ret; - } - - if (buf[0] & STATUS_XPT) - printf("### Warning: RTC lost power\n"); - - return ret; -} - -static void -rs5c372_enable(void) -{ - unsigned char buf[RS5C372_RAM_SIZE + 1]; - int ret; - - /* note that this returns reg. 15 in buf[1] */ - ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - - buf[0] = 0; - /* we want to start writing at register 0 so we have to copy the */ - /* register contents up one slot */ - for (ret = 2; ret < 9; ret++) - buf[ret - 1] = buf[ret]; - /* registers 0 to 6 (time values) are not touched */ - buf[8] = RATE_32768HZ; /* reg. 7 */ - buf[9] = 0; /* reg. 8 */ - buf[10] = 0; /* reg. 9 */ - buf[11] = 0; /* reg. 10 */ - buf[12] = 0; /* reg. 11 */ - buf[13] = 0; /* reg. 12 */ - buf[14] = 0; /* reg. 13 */ - buf[15] = 0; /* reg. 14 */ - buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - setup_done = 1; - - return; -} - -static void -rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf) -{ - /* buf[0] is register 15 */ - dt->tm_sec = bcd2bin(buf[1]); - dt->tm_min = bcd2bin(buf[2]); - - if (TWELVE_HOUR_MODE(buf[0])) { - dt->tm_hour = HOURS_12(buf[3]); - if (HOURS_AP(buf[3])) /* PM */ - dt->tm_hour += 12; - } else /* 24-hour-mode */ - dt->tm_hour = HOURS_24(buf[3]); - - dt->tm_mday = bcd2bin(buf[5]); - dt->tm_mon = bcd2bin(buf[6]); - dt->tm_year = bcd2bin(buf[7]); - if (dt->tm_year >= 70) - dt->tm_year += 1900; - else - dt->tm_year += 2000; - /* 0 is Sunday */ - dt->tm_wday = bcd2bin(buf[4] & 0x07); - dt->tm_yday = 0; - dt->tm_isdst= 0; - - if(rtc_debug > 2) { - printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year); - printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon); - printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday); - printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour); - printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min); - printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec); - } -} - -/* - * Get the current time from the RTC - */ -int -rtc_get (struct rtc_time *tmp) -{ - unsigned char buf[RS5C372_RAM_SIZE]; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - memset(buf, 0, sizeof(buf)); - - /* note that this returns reg. 15 in buf[0] */ - ret = rs5c372_readram(buf, RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return -1; - } - - rs5c372_convert_to_time(tmp, buf); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set (struct rtc_time *tmp) -{ - unsigned char buf[8], reg15; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - if(rtc_debug > 2) { - printf("rtc_set: tm_year = %d\n", tmp->tm_year); - printf("rtc_set: tm_mon = %d\n", tmp->tm_mon); - printf("rtc_set: tm_mday = %d\n", tmp->tm_mday); - printf("rtc_set: tm_hour = %d\n", tmp->tm_hour); - printf("rtc_set: tm_min = %d\n", tmp->tm_min); - printf("rtc_set: tm_sec = %d\n", tmp->tm_sec); - } - - memset(buf, 0, sizeof(buf)); - - /* only read register 15 */ - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); - - if (ret == 0) { - /* need to save register 15 */ - reg15 = buf[0]; - buf[0] = 0; /* register address on RS5C372 */ - buf[1] = bin2bcd(tmp->tm_sec); - buf[2] = bin2bcd(tmp->tm_min); - /* need to handle 12 hour mode */ - if (TWELVE_HOUR_MODE(reg15)) { - if (tmp->tm_hour >= 12) { /* PM */ - /* 12 PM is a special case */ - if (tmp->tm_hour == 12) - buf[3] = bin2bcd(tmp->tm_hour); - else - buf[3] = bin2bcd(tmp->tm_hour - 12); - buf[3] |= 0x20; - } - } else { - buf[3] = bin2bcd(tmp->tm_hour); - } - - buf[4] = bin2bcd(tmp->tm_wday); - buf[5] = bin2bcd(tmp->tm_mday); - buf[6] = bin2bcd(tmp->tm_mon); - if (tmp->tm_year < 1970 || tmp->tm_year > 2069) - printf("WARNING: year should be between 1970 and 2069!\n"); - buf[7] = bin2bcd(tmp->tm_year % 100); - - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); - if (ret != 0) { - printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); - return -1; - } - } else { - return -1; - } - - return 0; -} - -/* - * Reset the RTC. - */ -void -rtc_reset (void) -{ - if (!setup_done) - rs5c372_enable(); -} diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c deleted file mode 100644 index 96ea3cf878e..00000000000 --- a/drivers/rtc/s3c24x0_rtc.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - */ - -/* - * Date & Time support for the built-in Samsung S3C24X0 RTC - */ - -#include <common.h> -#include <command.h> - -#include <asm/arch/s3c24x0_cpu.h> - -#include <rtc.h> -#include <asm/io.h> -#include <linux/compiler.h> - -typedef enum { - RTC_ENABLE, - RTC_DISABLE -} RTC_ACCESS; - - -static inline void SetRTC_Access(RTC_ACCESS a) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - switch (a) { - case RTC_ENABLE: - writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); - break; - - case RTC_DISABLE: - writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); - break; - } -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - __maybe_unused uchar a_sec, a_min, a_hour, a_date, - a_mon, a_year, a_armed; - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* read RTC registers */ - do { - sec = readb(&rtc->bcdsec); - min = readb(&rtc->bcdmin); - hour = readb(&rtc->bcdhour); - mday = readb(&rtc->bcddate); - wday = readb(&rtc->bcdday); - mon = readb(&rtc->bcdmon); - year = readb(&rtc->bcdyear); - } while (sec != readb(&rtc->bcdsec)); - - /* read ALARM registers */ - a_sec = readb(&rtc->almsec); - a_min = readb(&rtc->almmin); - a_hour = readb(&rtc->almhour); - a_date = readb(&rtc->almdate); - a_mon = readb(&rtc->almmon); - a_year = readb(&rtc->almyear); - a_armed = readb(&rtc->rtcalm); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - -#ifdef RTC_DEBUG - printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: " - "%02x min: %02x sec: %02x\n", - a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec); -#endif - - tmp->tm_sec = bcd2bin(sec & 0x7F); - tmp->tm_min = bcd2bin(min & 0x7F); - tmp->tm_hour = bcd2bin(hour & 0x3F); - tmp->tm_mday = bcd2bin(mday & 0x3F); - tmp->tm_mon = bcd2bin(mon & 0x1F); - tmp->tm_year = bcd2bin(year); - tmp->tm_wday = bcd2bin(wday & 0x07); - if (tmp->tm_year < 70) - tmp->tm_year += 2000; - else - tmp->tm_year += 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; -#ifdef RTC_DEBUG - printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - -#ifdef RTC_DEBUG - printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - year = bin2bcd(tmp->tm_year % 100); - mon = bin2bcd(tmp->tm_mon); - wday = bin2bcd(tmp->tm_wday); - mday = bin2bcd(tmp->tm_mday); - hour = bin2bcd(tmp->tm_hour); - min = bin2bcd(tmp->tm_min); - sec = bin2bcd(tmp->tm_sec); - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* write RTC registers */ - writeb(sec, &rtc->bcdsec); - writeb(min, &rtc->bcdmin); - writeb(hour, &rtc->bcdhour); - writeb(mday, &rtc->bcddate); - writeb(wday, &rtc->bcdday); - writeb(mon, &rtc->bcdmon); - writeb(year, &rtc->bcdyear); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - - return 0; -} - -void rtc_reset(void) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); - writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); -} diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c deleted file mode 100644 index 4a8d1c5903f..00000000000 --- a/drivers/rtc/x1205.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on a the Linux rtc-x1207.c driver which is: - * Copyright 2004 Karen Spearel - * Copyright 2005 Alessandro Zummo - * - * Information and datasheet: - * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html - */ - -/* - * Date & Time support for Xicor/Intersil X1205 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <rtc.h> -#include <i2c.h> - -#define CCR_SEC 0 -#define CCR_MIN 1 -#define CCR_HOUR 2 -#define CCR_MDAY 3 -#define CCR_MONTH 4 -#define CCR_YEAR 5 -#define CCR_WDAY 6 -#define CCR_Y2K 7 - -#define X1205_REG_SR 0x3F /* status register */ -#define X1205_REG_Y2K 0x37 -#define X1205_REG_DW 0x36 -#define X1205_REG_YR 0x35 -#define X1205_REG_MO 0x34 -#define X1205_REG_DT 0x33 -#define X1205_REG_HR 0x32 -#define X1205_REG_MN 0x31 -#define X1205_REG_SC 0x30 -#define X1205_REG_DTR 0x13 -#define X1205_REG_ATR 0x12 -#define X1205_REG_INT 0x11 -#define X1205_REG_0 0x10 -#define X1205_REG_Y2K1 0x0F -#define X1205_REG_DWA1 0x0E -#define X1205_REG_YRA1 0x0D -#define X1205_REG_MOA1 0x0C -#define X1205_REG_DTA1 0x0B -#define X1205_REG_HRA1 0x0A -#define X1205_REG_MNA1 0x09 -#define X1205_REG_SCA1 0x08 -#define X1205_REG_Y2K0 0x07 -#define X1205_REG_DWA0 0x06 -#define X1205_REG_YRA0 0x05 -#define X1205_REG_MOA0 0x04 -#define X1205_REG_DTA0 0x03 -#define X1205_REG_HRA0 0x02 -#define X1205_REG_MNA0 0x01 -#define X1205_REG_SCA0 0x00 - -#define X1205_CCR_BASE 0x30 /* Base address of CCR */ -#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ - -#define X1205_SR_RTCF 0x01 /* Clock failure */ -#define X1205_SR_WEL 0x02 /* Write Enable Latch */ -#define X1205_SR_RWEL 0x04 /* Register Write Enable */ - -#define X1205_DTR_DTR0 0x01 -#define X1205_DTR_DTR1 0x02 -#define X1205_DTR_DTR2 0x04 - -#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ - -static void rtc_write(int reg, u8 val) -{ - i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); -} - -/* - * In the routines that deal directly with the x1205 hardware, we use - * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch - * Epoch is initialized as 2000. Time is set to UTC. - */ -int rtc_get(struct rtc_time *tm) -{ - u8 buf[8]; - - i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); - - debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " - "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, - buf[0], buf[1], buf[2], buf[3], - buf[4], buf[5], buf[6], buf[7]); - - tm->tm_sec = bcd2bin(buf[CCR_SEC]); - tm->tm_min = bcd2bin(buf[CCR_MIN]); - tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ - tm->tm_mday = bcd2bin(buf[CCR_MDAY]); - tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ - tm->tm_year = bcd2bin(buf[CCR_YEAR]) - + (bcd2bin(buf[CCR_Y2K]) * 100); - tm->tm_wday = buf[CCR_WDAY]; - - debug("%s: tm is secs=%d, mins=%d, hours=%d, " - "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, - tm->tm_sec, tm->tm_min, tm->tm_hour, - tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); - - return 0; -} - -int rtc_set(struct rtc_time *tm) -{ - int i; - u8 buf[8]; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - buf[CCR_SEC] = bin2bcd(tm->tm_sec); - buf[CCR_MIN] = bin2bcd(tm->tm_min); - - /* set hour and 24hr bit */ - buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; - - buf[CCR_MDAY] = bin2bcd(tm->tm_mday); - - /* month, 1 - 12 */ - buf[CCR_MONTH] = bin2bcd(tm->tm_mon); - - /* year, since the rtc epoch*/ - buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); - buf[CCR_WDAY] = tm->tm_wday & 0x07; - buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); - - /* this sequence is required to unlock the chip */ - rtc_write(X1205_REG_SR, X1205_SR_WEL); - rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); - - /* write register's data */ - for (i = 0; i < 8; i++) - rtc_write(X1205_CCR_BASE + i, buf[i]); - - rtc_write(X1205_REG_SR, 0); - - return 0; -} - -void rtc_reset(void) -{ - /* - * Nothing to do - */ -}

This is not used since this commit:

76386d6195a arm: Remove cm_t35 board

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/video/Makefile | 1 - drivers/video/scf0403_lcd.c | 297 ------------------------------------ include/scf0403_lcd.h | 10 -- 3 files changed, 308 deletions(-) delete mode 100644 drivers/video/scf0403_lcd.c delete mode 100644 include/scf0403_lcd.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 12b68cdd068..ce2d61d56bc 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c deleted file mode 100644 index 54f0f88b4c9..00000000000 --- a/drivers/video/scf0403_lcd.c +++ /dev/null @@ -1,297 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * scf0403.c -- support for DataImage SCF0403 LCD - * - * Copyright (c) 2013 Adapted from Linux driver: - * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. - * Copyright (c) 2012 CompuLab, Ltd - * Dmitry Lifshitz lifshitz@compulab.co.il - * Ilya Ledvich ilya@compulab.co.il - * Inspired by Alberto Panizzo maramaopercheseimorto@gmail.com & - * Marek Vasut work in l4f00242t03.c - * - * U-Boot port: Nikita Kiryanov nikita@compulab.co.il - */ - -#include <common.h> -#include <malloc.h> -#include <asm/gpio.h> -#include <spi.h> -#include <linux/delay.h> - -struct scf0403_cmd { - u16 cmd; - u16 *params; - int count; -}; - -struct scf0403_initseq_entry { - struct scf0403_cmd cmd; - int delay_ms; -}; - -struct scf0403_priv { - struct spi_slave *spi; - unsigned int reset_gpio; - u32 rddid; - struct scf0403_initseq_entry *init_seq; - int seq_size; -}; - -struct scf0403_priv priv; - -#define SCF0403852GGU04_ID 0x000080 - -/* SCF0403526GGU20 model commands parameters */ -static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; -static u16 spiinttype_params_sn20[] = {0x60}; -static u16 bc_params_sn20[] = { - 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, - 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, - 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, -}; -static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; -static u16 be_params_sn20[] = { - 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, -}; -static u16 vcom_params_sn20[] = {0x74}; -static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; -static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; -static u16 lvglvolt_params_sn20[] = {0x08}; -static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; -static u16 dispfunc_params_sn20[] = {0xa0}; -static u16 dvddvolt_params_sn20[] = {0x74}; -static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; -static u16 panelres_params_sn20[] = {0x82}; -static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; -static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; -static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; -static u16 memaccess_params_sn20[] = {0x00}; -static u16 pixfmt_params_sn20[] = {0x66}; -static u16 pgamma_params_sn20[] = { - 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, - 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, -}; -static u16 ngamma_params_sn20[] = { - 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, - 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, -}; -static u16 tearing_params_sn20[] = {0x00}; - -/* SCF0403852GGU04 model commands parameters */ -static u16 memaccess_params_sn04[] = {0x08}; -static u16 pixfmt_params_sn04[] = {0x66}; -static u16 modectl_params_sn04[] = {0x01}; -static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; -static u16 vcom_params_sn04[] = {0x00, 0x6A}; -static u16 pgamma_params_sn04[] = { - 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, - 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, -}; -static u16 ngamma_params_sn04[] = { - 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, - 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, -}; -static u16 dispinv_params_sn04[] = {0x02}; - -/* Common commands */ -static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; -static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; - -/* SCF0403852GGU04 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { - {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, - {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, - {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, - {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, - {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, - {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, - {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, - {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, -}; - -/* SCF0403526GGU20 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { - {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, - {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, - {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, - {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, - {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, - {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, - {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, - {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, - {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, - {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, - {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, - {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, - {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, - {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, - {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, - {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, - {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, - {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, - {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, - {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, - {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, - {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, -}; - -static void scf0403_gpio_reset(unsigned int gpio) -{ - if (!gpio_is_valid(gpio)) - return; - - gpio_set_value(gpio, 1); - mdelay(100); - gpio_set_value(gpio, 0); - mdelay(40); - gpio_set_value(gpio, 1); - mdelay(100); -} - -static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) -{ - int error = 0; - u8 ids_buf = 0x00; - u16 dummy_buf = 0x00; - u16 cmd = 0x04; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - /* Here 9 bits required to transmit a command */ - error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); - if (error) - return error; - - /* - * Here 8 + 1 bits required to arrange extra clock cycle - * before the first data bit. - * According to the datasheet - first parameter is the dummy data. - */ - error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); - if (error) - return error; - - error = spi_set_wordlen(spi, 8); - if (error) - return error; - - /* Read rest of the data */ - error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); - if (error) - return error; - - *rddid = ids_buf; - - return 0; -} - -static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) -{ - int i, error; - u32 command = cmd->cmd; - u32 msg; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); - if (error) - return error; - - for (i = 0; i < cmd->count; i++) { - msg = (cmd->params[i] | 0x100); - error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); - if (error) - return error; - } - - return 0; -} - -static void scf0403_lcd_init(struct scf0403_priv *priv) -{ - int i; - - /* reset LCD */ - scf0403_gpio_reset(priv->reset_gpio); - - for (i = 0; i < priv->seq_size; i++) { - if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) - puts("SPI transfer failed\n"); - - mdelay(priv->init_seq[i].delay_ms); - } -} - -static int scf0403_request_reset_gpio(unsigned gpio) -{ - int err = gpio_request(gpio, "lcd reset"); - - if (err) - return err; - - err = gpio_direction_output(gpio, 0); - if (err) - gpio_free(gpio); - - return err; -} - -int scf0403_init(int reset_gpio) -{ - int error; - - if (gpio_is_valid(reset_gpio)) { - error = scf0403_request_reset_gpio(reset_gpio); - if (error) { - printf("Failed requesting reset GPIO%d: %d\n", - reset_gpio, error); - return error; - } - } - - priv.reset_gpio = reset_gpio; - priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); - error = spi_claim_bus(priv.spi); - if (error) - goto bus_claim_fail; - - /* reset LCD */ - scf0403_gpio_reset(reset_gpio); - - error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); - if (error) { - puts("IDs read failed\n"); - goto readid_fail; - } - - if (priv.rddid == SCF0403852GGU04_ID) { - priv.init_seq = scf0403_initseq_sn04; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); - } else { - priv.init_seq = scf0403_initseq_sn20; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); - } - - scf0403_lcd_init(&priv); - - /* Start operation */ - scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); - mdelay(100); - scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); - spi_release_bus(priv.spi); - - return 0; - -readid_fail: - spi_release_bus(priv.spi); -bus_claim_fail: - if (gpio_is_valid(priv.reset_gpio)) - gpio_free(priv.reset_gpio); - - return error; -} diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h deleted file mode 100644 index 07f8c643ba5..00000000000 --- a/include/scf0403_lcd.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Compulab Inc. - */ -#ifndef SCF0403_LCD_H_ -#define SCF0403_LCD_H_ - -int scf0403_init(int reset_gpio); - -#endif

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/sh/include/asm/pci.h | 2 - drivers/pci/Makefile | 1 - drivers/pci/pci_sh7780.c | 92 --------------------------------------- 3 files changed, 95 deletions(-) delete mode 100644 drivers/pci/pci_sh7780.c

diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 5d79d0ec58e..18b95ff5cfb 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -13,8 +13,6 @@ #include <pci.h> #if defined(CONFIG_SH7751_PCI) int pci_sh7751_init(struct pci_controller *hose); -#elif defined(CONFIG_SH7780_PCI) -int pci_sh7780_init(struct pci_controller *hose); #else #error "Not support PCI." #endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index d393f1ba031..49506e7ba59 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o -obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c deleted file mode 100644 index 7533286c015..00000000000 --- a/drivers/pci/pci_sh7780.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SH7780 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu iwamatsu@nigauri.org - * (C) 2008 Yusuke Goda goda.yusuke@renesas.com - */ - -#include <common.h> -#include <linux/delay.h> - -#include <pci.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <asm/io.h> - -#define SH7780_VENDOR_ID 0x1912 -#define SH7780_DEVICE_ID 0x0002 -#define SH7780_PCICR_PREFIX 0xA5000000 -#define SH7780_PCICR_PFCS 0x00000800 -#define SH7780_PCICR_FTO 0x00000400 -#define SH7780_PCICR_PFE 0x00000200 -#define SH7780_PCICR_TBS 0x00000100 -#define SH7780_PCICR_ARBM 0x00000040 -#define SH7780_PCICR_IOCS 0x00000004 -#define SH7780_PCICR_PRST 0x00000002 -#define SH7780_PCICR_CFIN 0x00000001 - -#define p4_in(addr) (*(vu_long *)addr) -#define p4_out(data, addr) (*(vu_long *)addr) = (data) -#define p4_inw(addr) (*(vu_short *)addr) -#define p4_outw(data, addr) (*(vu_short *)addr) = (data) - -int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 *value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - *value = p4_in(SH7780_PCIPDR); - - return 0; -} - -int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - p4_out(value, SH7780_PCIPDR); - return 0; -} - -int pci_sh7780_init(struct pci_controller *hose) -{ - p4_out(0x01, SH7780_PCIECR); - - if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID - && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) { - printf("PCI: Unknown PCI host bridge.\n"); - return -1; - } - printf("PCI: SH7780 PCI host bridge found.\n"); - - /* Toggle PCI reset pin */ - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR); - udelay(100000); - p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR); - p4_outw(0x0047, SH7780_PCICMD); - - p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0); - p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0); - p4_out(0x00000000, SH7780_PCILSR1); - p4_out(0, SH7780_PCILAR1); - p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0); - p4_out(0x00000000, SH7780_PCIMBAR1); - - p4_out(0xFD000000, SH7780_PCIMBR0); - p4_out(0x00FC0000, SH7780_PCIMBMR0); - - /* if use Operand Cache then enable PCICSCR Soonp bits. */ - p4_out(0x08000000, SH7780_PCICSAR0); - p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */ - - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM - | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE), - SH7780_PCICR); - - pci_sh4_init(hose); - return 0; -}

CONFIG options must not use lower-case letter. Convert this and related ones to upper case.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/arm/dts/Makefile | 2 +- arch/arm/mach-stm32mp/Kconfig | 4 ++-- arch/arm/mach-stm32mp/Kconfig.13x | 4 ++-- arch/arm/mach-stm32mp/Makefile | 2 +- arch/arm/mach-stm32mp/cmd_stm32key.c | 10 +++++----- arch/arm/mach-stm32mp/fdt.c | 4 ++-- arch/arm/mach-stm32mp/include/mach/stm32.h | 6 +++--- board/st/common/Kconfig | 2 +- board/st/stm32mp1/Kconfig | 2 +- configs/stm32mp13_defconfig | 4 ++-- drivers/clk/stm32/Kconfig | 2 +- 11 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cd5b56034d5..85adbf0cb2a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1216,7 +1216,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb

dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb

-dtb-$(CONFIG_STM32MP13x) += \ +dtb-$(CONFIG_STM32MP13X) += \ stm32mp135f-dk.dtb

dtb-$(CONFIG_STM32MP15x) += \ diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index db47baba6d1..cf3196b3b3a 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -37,7 +37,7 @@ choice prompt "Select STMicroelectronics STM32MPxxx Soc" default STM32MP15x

-config STM32MP13x +config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" select ARM_SMCCC select CPU_V7A @@ -103,7 +103,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2

config STM32_ETZPC bool "STM32 Extended TrustZone Protection" - depends on STM32MP15x || STM32MP13x + depends on STM32MP15x || STM32MP13X default y imply BOOTP_SERVERIP help diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x index acc02a5a187..4d74b35055b 100644 --- a/arch/arm/mach-stm32mp/Kconfig.13x +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -1,10 +1,10 @@ -if STM32MP13x +if STM32MP13X

choice prompt "STM32MP13x board select" optional

-config TARGET_ST_STM32MP13x +config TARGET_ST_STM32MP13X bool "STMicroelectronics STM32MP13x boards" imply BOOTSTAGE imply CMD_BOOTSTAGE diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a19b2797c8b..90c7c121ec4 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -8,7 +8,7 @@ obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o

-obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15x) += stm32mp15x.o

obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 85be8e23bdb..96407cd9b18 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -18,7 +18,7 @@ * STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device */ #define STM32_OTP_CLOSE_ID 0 -#define STM32_OTP_STM32MP13x_CLOSE_MASK 0x3F +#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F #define STM32_OTP_STM32MP15x_CLOSE_MASK BIT(6)

/* PKH is the first element of the key list */ @@ -60,7 +60,7 @@ static u8 stm32key_index;

static u8 get_key_nb(void) { - if (IS_ENABLED(CONFIG_STM32MP13x)) + if (IS_ENABLED(CONFIG_STM32MP13X)) return ARRAY_SIZE(stm32mp13_list);

if (IS_ENABLED(CONFIG_STM32MP15x)) @@ -69,7 +69,7 @@ static u8 get_key_nb(void)

static const struct stm32key *get_key(u8 index) { - if (IS_ENABLED(CONFIG_STM32MP13x)) + if (IS_ENABLED(CONFIG_STM32MP13X)) return &stm32mp13_list[index];

if (IS_ENABLED(CONFIG_STM32MP15x)) @@ -78,8 +78,8 @@ static const struct stm32key *get_key(u8 index)

static u32 get_otp_close_mask(void) { - if (IS_ENABLED(CONFIG_STM32MP13x)) - return STM32_OTP_STM32MP13x_CLOSE_MASK; + if (IS_ENABLED(CONFIG_STM32MP13X)) + return STM32_OTP_STM32MP13X_CLOSE_MASK;

if (IS_ENABLED(CONFIG_STM32MP15x)) return STM32_OTP_STM32MP15x_CLOSE_MASK; diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index 3b4c05d7451..6b69542ecfc 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -270,7 +270,7 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB];

- if (IS_ENABLED(CONFIG_STM32MP13x)) { + if (IS_ENABLED(CONFIG_STM32MP13X)) { array = stm32mp13_ip_addr; array_size = ARRAY_SIZE(stm32mp13_ip_addr); } @@ -491,7 +491,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) cpu = get_cpu_type(); get_soc_name(name);

- if (IS_ENABLED(CONFIG_STM32MP13x)) + if (IS_ENABLED(CONFIG_STM32MP13X)) stm32mp13_fdt_fixup(blob, soc, cpu, name);

if (IS_ENABLED(CONFIG_STM32MP15x)) { diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index c85ae6a34ee..1e1f694cb62 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -32,7 +32,7 @@ #define STM32_USART1_BASE 0x5C000000 #define STM32_USART2_BASE 0x4000E000 #endif -#ifdef CONFIG_STM32MP13x +#ifdef CONFIG_STM32MP13X #define STM32_USART1_BASE 0x4c000000 #define STM32_USART2_BASE 0x4c001000 #endif @@ -130,7 +130,7 @@ enum boot_device { #define TAMP_COPRO_STATE_CRASH 5 #endif

-#ifdef CONFIG_STM32MP13x +#ifdef CONFIG_STM32MP13X #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif @@ -167,7 +167,7 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 59 #endif -#ifdef CONFIG_STM32MP13x +#ifdef CONFIG_STM32MP13X #define BSEC_OTP_RPN 1 #define BSEC_OTP_SERIAL 13 #define BSEC_OTP_MAC 57 diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index aba3590866e..ba17d3158d1 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -1,7 +1,7 @@ config CMD_STBOARD bool "stboard - command for OTP board information" depends on ARCH_STM32MP - default y if TARGET_ST_STM32MP15x || TARGET_ST_STM32MP13x + default y if TARGET_ST_STM32MP15x || TARGET_ST_STM32MP13X help This compile the stboard command to read and write the board in the OTP. diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 6ab8f80fa45..7d0d41bfea0 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -12,7 +12,7 @@ config SYS_CONFIG_NAME source "board/st/common/Kconfig" endif

-if TARGET_ST_STM32MP13x +if TARGET_ST_STM32MP13X

config SYS_BOARD default "stm32mp1" diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index ab824808f9d..7b9718400e8 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -5,10 +5,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x180000 CONFIG_ENV_OFFSET=0x900000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_STM32MP13x=y +CONFIG_STM32MP13X=y CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_CMD_STM32KEY=y -CONFIG_TARGET_ST_STM32MP13x=y +CONFIG_TARGET_ST_STM32MP13X=y CONFIG_ENV_OFFSET_REDUND=0x940000 # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index 7a34ea23c38..7dbddd032b8 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -31,7 +31,7 @@ config CLK_STM32MP1 config CLK_STM32MP13 bool "Enable RCC clock driver for STM32MP13" depends on ARCH_STM32MP && CLK - default y if STM32MP13x + default y if STM32MP13X select CLK_STM32_CORE help Enable the STM32 clock (RCC) driver. Enable support for

The SPL_TPL part is in the wrong place. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org Fixes: 71d4393f846 ("sysreset: Add Atmel/Microchip sysreset driver") Reviewed-by: Claudiu Beznea claudiu.beznea@microchip.com ---

(no changes since v1)

drivers/sysreset/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0ed3bbf356a..40c876764af 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -20,6 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o -obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de ---

(no changes since v1)

drivers/i2c/Makefile | 1 - drivers/i2c/kona_i2c.c | 728 ----------------------------------------- 2 files changed, 729 deletions(-) delete mode 100644 drivers/i2c/kona_i2c.c

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 920aafb91c5..cde0597290c 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,7 +25,6 @@ obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o -obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c deleted file mode 100644 index b9b0ff1c39e..00000000000 --- a/drivers/i2c/kona_i2c.c +++ /dev/null @@ -1,728 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.rst for instructions. - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include <i2c.h> - -/* Hardware register offsets and field defintions */ -#define CS_OFFSET 0x00000020 -#define CS_ACK_SHIFT 3 -#define CS_ACK_MASK 0x00000008 -#define CS_ACK_CMD_GEN_START 0x00000000 -#define CS_ACK_CMD_GEN_RESTART 0x00000001 -#define CS_CMD_SHIFT 1 -#define CS_CMD_CMD_NO_ACTION 0x00000000 -#define CS_CMD_CMD_START_RESTART 0x00000001 -#define CS_CMD_CMD_STOP 0x00000002 -#define CS_EN_SHIFT 0 -#define CS_EN_CMD_ENABLE_BSC 0x00000001 - -#define TIM_OFFSET 0x00000024 -#define TIM_PRESCALE_SHIFT 6 -#define TIM_P_SHIFT 3 -#define TIM_NO_DIV_SHIFT 2 -#define TIM_DIV_SHIFT 0 - -#define DAT_OFFSET 0x00000028 - -#define TOUT_OFFSET 0x0000002c - -#define TXFCR_OFFSET 0x0000003c -#define TXFCR_FIFO_FLUSH_MASK 0x00000080 -#define TXFCR_FIFO_EN_MASK 0x00000040 - -#define IER_OFFSET 0x00000044 -#define IER_READ_COMPLETE_INT_MASK 0x00000010 -#define IER_I2C_INT_EN_MASK 0x00000008 -#define IER_FIFO_INT_EN_MASK 0x00000002 -#define IER_NOACK_EN_MASK 0x00000001 - -#define ISR_OFFSET 0x00000048 -#define ISR_RESERVED_MASK 0xffffff60 -#define ISR_CMDBUSY_MASK 0x00000080 -#define ISR_READ_COMPLETE_MASK 0x00000010 -#define ISR_SES_DONE_MASK 0x00000008 -#define ISR_ERR_MASK 0x00000004 -#define ISR_TXFIFOEMPTY_MASK 0x00000002 -#define ISR_NOACK_MASK 0x00000001 - -#define CLKEN_OFFSET 0x0000004c -#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 -#define CLKEN_M_SHIFT 4 -#define CLKEN_N_SHIFT 1 -#define CLKEN_CLKEN_MASK 0x00000001 - -#define FIFO_STATUS_OFFSET 0x00000054 -#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 -#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 - -#define HSTIM_OFFSET 0x00000058 -#define HSTIM_HS_MODE_MASK 0x00008000 -#define HSTIM_HS_HOLD_SHIFT 10 -#define HSTIM_HS_HIGH_PHASE_SHIFT 5 -#define HSTIM_HS_SETUP_SHIFT 0 - -#define PADCTL_OFFSET 0x0000005c -#define PADCTL_PAD_OUT_EN_MASK 0x00000004 - -#define RXFCR_OFFSET 0x00000068 -#define RXFCR_NACK_EN_SHIFT 7 -#define RXFCR_READ_COUNT_SHIFT 0 -#define RXFIFORDOUT_OFFSET 0x0000006c - -/* Locally used constants */ -#define MAX_RX_FIFO_SIZE 64U /* bytes */ -#define MAX_TX_FIFO_SIZE 64U /* bytes */ - -#define I2C_TIMEOUT 100000 /* usecs */ - -#define WAIT_INT_CHK 100 /* usecs */ -#if I2C_TIMEOUT % WAIT_INT_CHK -#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK -#endif - -/* Operations that can be commanded to the controller */ -enum bcm_kona_cmd_t { - BCM_CMD_NOACTION = 0, - BCM_CMD_START, - BCM_CMD_RESTART, - BCM_CMD_STOP, -}; - -/* Internal divider settings for standard mode, fast mode and fast mode plus */ -struct bus_speed_cfg { - uint8_t time_m; /* Number of cycles for setup time */ - uint8_t time_n; /* Number of cycles for hold time */ - uint8_t prescale; /* Prescale divider */ - uint8_t time_p; /* Timing coefficient */ - uint8_t no_div; /* Disable clock divider */ - uint8_t time_div; /* Post-prescale divider */ -}; - -static const struct bus_speed_cfg std_cfg_table[] = { - [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, - [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, - [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, -}; - -struct bcm_kona_i2c_dev { - void *base; - uint speed; - const struct bus_speed_cfg *std_cfg; -}; - -/* Keep these two defines in sync */ -#define DEF_SPD I2C_SPEED_STANDARD_RATE -#define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD - -#define DEF_DEVICE(num) \ -{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} - -static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_DEVICE(0), -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_DEVICE(1), -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_DEVICE(2), -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_DEVICE(3), -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_DEVICE(4), -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_DEVICE(5), -#endif -}; - -#define I2C_M_TEN 0x0010 /* ten bit address */ -#define I2C_M_RD 0x0001 /* read data */ -#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ - -struct kona_i2c_msg { - uint16_t addr; - uint16_t flags; - uint16_t len; - uint8_t *buf; -}; - -static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - debug("%s, %d\n", __func__, cmd); - - switch (cmd) { - case BCM_CMD_NOACTION: - writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_START: - writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_RESTART: - writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_STOP: - writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - default: - printf("Unknown command %d\n", cmd); - } -} - -static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -/* Wait until at least one of the mask bit(s) are set */ -static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, - unsigned long time_left, - uint32_t mask) -{ - uint32_t status; - - while (time_left) { - status = readl(dev->base + ISR_OFFSET); - - if ((status & ~ISR_RESERVED_MASK) == 0) { - debug("Bogus I2C interrupt 0x%x\n", status); - continue; - } - - /* Must flush the TX FIFO when NAK detected */ - if (status & ISR_NOACK_MASK) - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); - - if (status & mask) { - /* We are done since one of the mask bits are set */ - return time_left; - } - udelay(WAIT_INT_CHK); - time_left -= WAIT_INT_CHK; - } - return 0; -} - -/* Send command to I2C bus */ -static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - int rc = 0; - unsigned long time_left = I2C_TIMEOUT; - - /* Send the command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); - - /* Wait for transaction to finish or timeout */ - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - printf("controller timed out\n"); - rc = -ETIMEDOUT; - } - - /* Clear command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - return rc; -} - -/* Read a single RX FIFO worth of data from the i2c bus */ -static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len, - unsigned int last_byte_nak) -{ - unsigned long time_left = I2C_TIMEOUT; - - /* Start the RX FIFO */ - writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | - (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); - - /* Wait for FIFO read to complete */ - time_left = - wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); - - if (!time_left) { - printf("RX FIFO time out\n"); - return -EREMOTEIO; - } - - /* Read data from FIFO */ - for (; len > 0; len--, buf++) - *buf = readl(dev->base + RXFIFORDOUT_OFFSET); - - return 0; -} - -/* Read any amount of data using the RX FIFO from the i2c bus */ -static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; - unsigned int last_byte_nak = 0; - unsigned int bytes_read = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_read < msg->len) { - if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { - last_byte_nak = 1; /* NAK last byte of transfer */ - bytes_to_read = msg->len - bytes_read; - } - - rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, - last_byte_nak); - if (rc < 0) - return -EREMOTEIO; - - bytes_read += bytes_to_read; - tmp_buf += bytes_to_read; - } - - return 0; -} - -/* Write a single byte of data to the i2c bus */ -static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, - unsigned int nak_expected) -{ - unsigned long time_left = I2C_TIMEOUT; - unsigned int nak_received; - - /* Clear pending session done interrupt */ - writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); - - /* Send one byte of data */ - writel(data, dev->base + DAT_OFFSET); - - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - debug("controller timed out\n"); - return -ETIMEDOUT; - } - - nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; - - if (nak_received ^ nak_expected) { - debug("unexpected NAK/ACK\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write a single TX FIFO worth of data to the i2c bus */ -static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len) -{ - int k; - unsigned long time_left = I2C_TIMEOUT; - unsigned int fifo_status; - - /* Write data into FIFO */ - for (k = 0; k < len; k++) - writel(buf[k], (dev->base + DAT_OFFSET)); - - /* Wait for FIFO to empty */ - do { - time_left = - wait_for_int_timeout(dev, time_left, - (IER_FIFO_INT_EN_MASK | - IER_NOACK_EN_MASK)); - fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); - } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); - - /* Check if there was a NAK */ - if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { - printf("unexpected NAK\n"); - return -EREMOTEIO; - } - - /* Check if a timeout occurred */ - if (!time_left) { - printf("completion timed out\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write any amount of data using TX FIFO to the i2c bus */ -static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; - unsigned int bytes_written = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_written < msg->len) { - if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) - bytes_to_write = msg->len - bytes_written; - - rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, - bytes_to_write); - if (rc < 0) - return -EREMOTEIO; - - bytes_written += bytes_to_write; - tmp_buf += bytes_to_write; - } - - return 0; -} - -/* Send i2c address */ -static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned char addr; - - if (msg->flags & I2C_M_TEN) { - /* First byte is 11110XX0 where XX is upper 2 bits */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7); - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - /* Second byte is the remaining 8 bits */ - addr = msg->addr & 0xff; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - if (msg->flags & I2C_M_RD) { - /* For read, send restart command */ - if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) - return -EREMOTEIO; - - /* Then re-send the first byte with the read bit set */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - } else { - addr = msg->addr << 1; - - if (msg->flags & I2C_M_RD) - addr |= 1; - - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - - return 0; -} - -static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, - dev->base + HSTIM_OFFSET); - - writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | - (dev->std_cfg->time_p << TIM_P_SHIFT) | - (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | - (dev->std_cfg->time_div << TIM_DIV_SHIFT), - dev->base + TIM_OFFSET); - - writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | - (dev->std_cfg->time_n << CLKEN_N_SHIFT) | - CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); -} - -/* Master transfer function */ -static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg msgs[], int num) -{ - struct kona_i2c_msg *pmsg; - int rc = 0; - int i; - - /* Enable pad output */ - writel(0, dev->base + PADCTL_OFFSET); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Send start command */ - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); - if (rc < 0) { - printf("Start command failed rc = %d\n", rc); - goto xfer_disable_pad; - } - - /* Loop through all messages */ - for (i = 0; i < num; i++) { - pmsg = &msgs[i]; - - /* Send restart for subsequent messages */ - if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); - if (rc < 0) { - printf("restart cmd failed rc = %d\n", rc); - goto xfer_send_stop; - } - } - - /* Send slave address */ - if (!(pmsg->flags & I2C_M_NOSTART)) { - rc = bcm_kona_i2c_do_addr(dev, pmsg); - if (rc < 0) { - debug("NAK from addr %2.2x msg#%d rc = %d\n", - pmsg->addr, i, rc); - goto xfer_send_stop; - } - } - - /* Perform data transfer */ - if (pmsg->flags & I2C_M_RD) { - rc = bcm_kona_i2c_read_fifo(dev, pmsg); - if (rc < 0) { - printf("read failure\n"); - goto xfer_send_stop; - } - } else { - rc = bcm_kona_i2c_write_fifo(dev, pmsg); - if (rc < 0) { - printf("write failure"); - goto xfer_send_stop; - } - } - } - - rc = num; - -xfer_send_stop: - /* Send a STOP command */ - bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); - -xfer_disable_pad: - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); - - /* Stop internal clock */ - bcm_kona_i2c_disable_clock(dev); - - return rc; -} - -static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, - uint speed) -{ - switch (speed) { - case I2C_SPEED_STANDARD_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD]; - break; - case I2C_SPEED_FAST_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST]; - break; - case I2C_SPEED_FAST_PLUS_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS]; - break; - default: - printf("%d hz bus speed not supported\n", speed); - return -EINVAL; - } - dev->speed = speed; - return 0; -} - -static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) -{ - /* Parse bus speed */ - bcm_kona_i2c_assign_bus_speed(dev, dev->speed); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Configure internal dividers */ - bcm_kona_i2c_config_timing(dev); - - /* Disable timeout */ - writel(0, dev->base + TOUT_OFFSET); - - /* Enable autosense */ - bcm_kona_i2c_enable_autosense(dev); - - /* Enable TX FIFO */ - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - /* Mask all interrupts */ - writel(0, dev->base + IER_OFFSET); - - /* Clear all pending interrupts */ - writel(ISR_CMDBUSY_MASK | - ISR_READ_COMPLETE_MASK | - ISR_SES_DONE_MASK | - ISR_ERR_MASK | - ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); - - /* Enable the controller but leave it idle */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); -} - -/* - * uboot layer - */ -struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) -{ - return &g_i2c_devs[adap->hwadapnr]; -} - -static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - if (clk_bsc_enable(dev->base)) - return; - - bcm_kona_i2c_init(dev); -} - -static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - /* msg[0] writes the addr, msg[1] reads the data */ - struct kona_i2c_msg msg[2]; - unsigned char msgbuf0[64]; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ - - msg[1].addr = chip; - msg[1].flags = I2C_M_RD; - /* msg[1].buf dest ptr increments each read */ - - msgbuf0[0] = (unsigned char)addr; - msg[1].buf = buffer; - msg[1].len = len; - if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { - /* Sending 2 i2c messages */ - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C read: I/O error\n"); - return -EIO; - } - return 0; -} - -static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - struct kona_i2c_msg msg[1]; - unsigned char msgbuf0[64]; - unsigned int i; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 2; /* addr byte plus data */ - msg[0].buf = msgbuf0; - - for (i = 0; i < len; i++) { - msgbuf0[0] = addr++; - msgbuf0[1] = buffer[i]; - if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C write: I/O error\n"); - return -EIO; - } - } - return 0; -} - -static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) -{ - uchar tmp; - - /* - * read addr 0x0 of the given chip. - */ - return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); -} - -static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - return bcm_kona_i2c_assign_bus_speed(dev, speed); -} - -/* - * Register kona i2c adapters. Keep the order below so - * that the bus number matches the adapter number. - */ -#define DEF_ADAPTER(num) \ -U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ - kona_i2c_read, kona_i2c_write, \ - kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) - -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_ADAPTER(0) -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_ADAPTER(1) -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_ADAPTER(2) -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_ADAPTER(3) -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_ADAPTER(4) -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_ADAPTER(5) -#endif

This option as well as CONFIG_TARGET_P1022DS and CONFIG_TARGET_P5020DS are not defined anywhere. Drop them.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

board/freescale/common/Makefile | 3 --- 1 file changed, 3 deletions(-)

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index bd035d60a58..5f0503faf8d 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -51,8 +51,6 @@ endif

obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o

-obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o @@ -75,7 +73,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ -obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/

obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o

CONFIG_UBOOT_PAD_TO is not defined anywhere. Drop this dead code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Stefan Roese sr@denx.de ---

(no changes since v1)

Makefile | 11 ----------- 1 file changed, 11 deletions(-)

diff --git a/Makefile b/Makefile index 20a20e00d60..8150ca69e82 100644 --- a/Makefile +++ b/Makefile @@ -1648,17 +1648,6 @@ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE $(call if_changed,pad_cat)

-# PPC4xx needs the SPL at the end of the image, since the reset vector -# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target -# and need to introduce a new build target with the full blown U-Boot -# at the start padded up to the start of the SPL image. And then concat -# the SPL image to the end. - -OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ - --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff -u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE - $(call if_changed,pad_cat) - quiet_cmd_u-boot-elf ?= LD $@ cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \ $(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

common/usb_hub.c | 18 ---- drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-faraday.c | 144 -------------------------------- drivers/usb/host/ehci-hcd.c | 5 -- include/usb/fusbh200.h | 59 ------------- 5 files changed, 227 deletions(-) delete mode 100644 drivers/usb/host/ehci-faraday.c delete mode 100644 include/usb/fusbh200.h

diff --git a/common/usb_hub.c b/common/usb_hub.c index f7fd12c0450..a36350f846c 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -506,24 +506,6 @@ static int usb_scan_port(struct usb_device_scan *usb_scan) if (portchange & USB_PORT_STAT_C_ENABLE) { debug("port %d enable change, status %x\n", i + 1, portstatus); usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE); - /* - * The following hack causes a ghost device problem - * to Faraday EHCI - */ -#ifndef CONFIG_USB_EHCI_FARADAY - /* - * EM interference sometimes causes bad shielded USB - * devices to be shutdown by the hub, this hack enables - * them again. Works at least with mouse driver - */ - if (!(portstatus & USB_PORT_STAT_ENABLE) && - (portstatus & USB_PORT_STAT_CONNECTION) && - usb_device_has_child_on_port(dev, i)) { - debug("already running port %i disabled by hub (EMI?), re-enabling...\n", - i + 1); - usb_hub_port_connect_change(dev, i); - } -#endif }

if (portstatus & USB_PORT_STAT_SUSPEND) { diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 1f59e910d3b..cce78846d98 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_USB_OHCI_NPCM) += ohci-npcm.o obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o -obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c deleted file mode 100644 index 85a35269601..00000000000 --- a/drivers/usb/host/ehci-faraday.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su dantesu@faraday-tech.com - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <usb.h> -#include <linux/delay.h> -#include <usb/fusbh200.h> -#include <usb/fotg210.h> - -#include "ehci.h" - -#ifndef CFG_USB_EHCI_BASE_LIST -#define CFG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE } -#endif - -union ehci_faraday_regs { - struct fusbh200_regs usb; - struct fotg210_regs otg; -}; - -static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs) -{ - return !readl(&regs->usb.easstr); -} - -void faraday_ehci_set_usbmode(struct ehci_ctrl *ctrl) -{ - /* nothing needs to be done */ -} - -int faraday_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) -{ - int spd, ret = PORTSC_PSPD_HS; - union ehci_faraday_regs *regs; - - ret = (void __iomem *)((ulong)ctrl->hcor - 0x10); - if (ehci_is_fotg2xx(regs)) - spd = OTGCSR_SPD(readl(&regs->otg.otgcsr)); - else - spd = BMCSR_SPD(readl(&regs->usb.bmcsr)); - - switch (spd) { - case 0: /* full speed */ - ret = PORTSC_PSPD_FS; - break; - case 1: /* low speed */ - ret = PORTSC_PSPD_LS; - break; - case 2: /* high speed */ - ret = PORTSC_PSPD_HS; - break; - default: - printf("ehci-faraday: invalid device speed\n"); - break; - } - - return ret; -} - -uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) -{ - /* Faraday EHCI has one and only one portsc register */ - if (port) { - /* Printing the message would cause a scan failure! */ - debug("The request port(%d) is not configured\n", port); - return NULL; - } - - /* Faraday EHCI PORTSC register offset is 0x20 from hcor */ - return (uint32_t *)((uint8_t *)ctrl->hcor + 0x20); -} - -static const struct ehci_ops faraday_ehci_ops = { - .set_usb_mode = faraday_ehci_set_usbmode, - .get_port_speed = faraday_ehci_get_port_speed, - .get_portsc_register = faraday_ehci_get_portsc_register, -}; - -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) -{ - struct ehci_hccr *hccr; - struct ehci_hcor *hcor; - union ehci_faraday_regs *regs; - uint32_t base_list[] = CFG_USB_EHCI_BASE_LIST; - - if (index < 0 || index >= ARRAY_SIZE(base_list)) - return -1; - ehci_set_controller_priv(index, NULL, &faraday_ehci_ops); - regs = (void __iomem *)base_list[index]; - hccr = (struct ehci_hccr *)&regs->usb.hccr; - hcor = (struct ehci_hcor *)&regs->usb.hcor; - - if (ehci_is_fotg2xx(regs)) { - /* A-device bus reset */ - /* ... Power off A-device */ - setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drop vbus and bus traffic */ - clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* ... Power on A-device */ - clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drive vbus and bus traffic */ - setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* Disable OTG & DEV interrupts, triggered at level-high */ - writel(IMR_IRQLH | IMR_OTG | IMR_DEV, &regs->otg.imr); - /* Clear all interrupt status */ - writel(ISR_HOST | ISR_OTG | ISR_DEV, &regs->otg.isr); - } else { - /* Interrupt=level-high */ - setbits_le32(&regs->usb.bmcsr, BMCSR_IRQLH); - /* VBUS on */ - clrbits_le32(&regs->usb.bmcsr, BMCSR_VBUS_OFF); - /* Disable all interrupts */ - writel(0x00, &regs->usb.bmier); - writel(0x1f, &regs->usb.bmisr); - } - - *ret_hccr = hccr; - *ret_hcor = hcor; - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9139d61dd0c..9839aa17492 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -705,12 +705,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken); } else { dev->act_len = 0; -#ifndef CONFIG_USB_EHCI_FARADAY debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), ehci_readl(&ctrl->hcor->or_portsc[0]), ehci_readl(&ctrl->hcor->or_portsc[1])); -#endif }

free(qtd); @@ -1189,9 +1187,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); if (rc) return rc; -#endif -#ifdef CONFIG_USB_EHCI_FARADAY - tweaks |= EHCI_TWEAK_NO_INIT_CF; #endif rc = ehci_common_init(ctrl, tweaks); if (rc) diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h deleted file mode 100644 index 6ae1d848801..00000000000 --- a/include/usb/fusbh200.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su dantesu@faraday-tech.com - */ - -#ifndef _FUSBH200_H -#define _FUSBH200_H - -struct fusbh200_regs { - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ - uint32_t rsvd[2]; - uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ - uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ - uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ -}; - -/* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ -#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ -#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* Bus Monitor Control Status Register */ -#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) -#define BMCSR_SPD_FULL (0 << 9) -#define BMCSR_SPD_MASK (3 << 9) -#define BMCSR_SPD_SHIFT 9 -#define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ -#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ -#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ -#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ -#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ - -/* Bus Monitor Interrupt Status Register */ -/* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ - -#endif

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

.../mach-rmobile/include/mach/ehci-rmobile.h | 146 ------------------ drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-rmobile.c | 129 ---------------- 3 files changed, 276 deletions(-) delete mode 100644 arch/arm/mach-rmobile/include/mach/ehci-rmobile.h delete mode 100644 drivers/usb/host/ehci-rmobile.c

diff --git a/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h b/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h deleted file mode 100644 index ca8c5f37063..00000000000 --- a/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - */ - -#ifndef __EHCI_RMOBILE_H__ -#define __EHCI_RMOBILE_H__ - -/* Register offset */ -#define OHCI_OFFSET 0x00 -#define OHCI_SIZE 0x1000 -#define EHCI_OFFSET 0x1000 -#define EHCI_SIZE 0x1000 - -#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) - -/* USBCTR */ -#define DIRPD (1 << 8) -#define PLL_RST (1 << 2) -#define PCICLK_MASK (1 << 1) -#define USBH_RST (1 << 0) - -/* CMND_STS */ -#define SERREN (1 << 8) -#define PERREN (1 << 6) -#define MASTEREN (1 << 2) -#define MEMEN (1 << 1) - -/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ -#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) - -/* AHBPCI_WIN1_CTR */ -#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) -#define AHB_CFG_AHBPCI 0x40000000 -#define AHB_CFG_HOST 0x80000000 - -/* AHBPCI_WIN2_CTR */ -#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) - -/* PCI_INT_ENABLE */ -#define USBH_PMEEN (1 << 19) -#define USBH_INTBEN (1 << 17) -#define USBH_INTAEN (1 << 16) - -/* AHB_BUS_CTR */ -#define SMODE_READY_CTR (1 << 17) -#define SMODE_READ_BURST (1 << 16) -#define MMODE_HBUSREQ (1 << 7) -#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) -#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) -#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) -#define MMODE_WR_INCR (1 << 2) -#define MMODE_BYTE_BURST (1 << 1) -#define MMODE_HTRANS (1 << 0) - -/* PCI_ARBITER_CTR */ -#define PCIBUS_PARK_TIMER 0x00FF0000 -#define PCIBUS_PARK_TIMER_SET 0x00070000 -#define PCIBP_MODE (1 << 12) -#define PCIREQ7 (1 << 7) -#define PCIREQ6 (1 << 6) -#define PCIREQ5 (1 << 5) -#define PCIREQ4 (1 << 4) -#define PCIREQ3 (1 << 3) -#define PCIREQ2 (1 << 2) -#define PCIREQ1 (1 << 1) -#define PCIREQ0 (1 << 0) - -#define SMSTPCR7 0xE615014C -#define SMSTPCR703 (1 << 3) - -/* Init AHB master and slave functions of the host logic */ -#define AHB_BUS_CTR_INIT \ - (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ - MMODE_BYTE_BURST | MMODE_HTRANS) - -#define USBCTR_WIN_SIZE_1GB 0x800 - -/* PCI Configuration Registers */ -#define PCI_CONF_OHCI_OFFSET 0x10000 -#define PCI_CONF_EHCI_OFFSET 0x10100 -struct ahb_pciconf { - u32 vid_did; - u32 cmnd_sts; - u32 rev; - u32 cache_line; - u32 basead; -}; - -/* PCI Configuration Registers for AHB-PCI Bridge Registers */ -#define PCI_CONF_AHBPCI_OFFSET 0x10000 -struct ahbconf_pci_bridge { - u32 vid_did; /* 0x00 */ - u32 cmnd_sts; - u32 revid_cc; - u32 cls_lt_ht_bist; - u32 basead; /* 0x10 */ - u32 win1_basead; - u32 win2_basead; - u32 dummy0[5]; - u32 ssvdi_ssid; /* 0x2C */ - u32 dummy1[4]; - u32 intr_line_pin; -}; - -/* AHB-PCI Bridge PCI Communication Registers */ -#define AHBPCI_OFFSET 0x10800 -struct ahbcom_pci_bridge { - u32 pciahb_win1_ctr; /* 0x00 */ - u32 pciahb_win2_ctr; - u32 pciahb_dct_ctr; - u32 dummy0; - u32 ahbpci_win1_ctr; /* 0x10 */ - u32 ahbpci_win2_ctr; - u32 dummy1; - u32 ahbpci_dct_ctr; - u32 pci_int_enable; /* 0x20 */ - u32 pci_int_status; - u32 dummy2[2]; - u32 ahb_bus_ctr; /* 0x30 */ - u32 usbctr; - u32 dummy3[2]; - u32 pci_arbiter_ctr; /* 0x40 */ - u32 dummy4; - u32 pci_unit_rev; /* 0x48 */ -}; - -struct rmobile_ehci_reg { - u32 hciversion; /* hciversion/caplength */ - u32 hcsparams; /* hcsparams */ - u32 hccparams; /* hccparams */ - u32 hcsp_portroute; /* hcsp_portroute */ - u32 usbcmd; /* usbcmd */ - u32 usbsts; /* usbsts */ - u32 usbintr; /* usbintr */ - u32 frindex; /* frindex */ - u32 ctrldssegment; /* ctrldssegment */ - u32 periodiclistbase; /* periodiclistbase */ - u32 asynclistaddr; /* asynclistaddr */ - u32 dummy[9]; - u32 configflag; /* configflag */ - u32 portsc; /* portsc */ -}; - -#endif /* __EHCI_RMOBILE_H__ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cce78846d98..3d3dd5f279f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o -obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o

# xhci diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c deleted file mode 100644 index 60525f22867..00000000000 --- a/drivers/usb/host/ehci-rmobile.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * EHCI HCD (Host Controller Driver) for USB. - * - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ehci-rmobile.h> -#include <linux/delay.h> -#include "ehci.h" - -#if defined(CONFIG_R8A7740) -static u32 usb_base_address[] = { - 0xC6700000 -}; -#elif defined(CONFIG_R8A7790) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0A0000, /* USB1 */ - 0xEE0C0000, /* USB2 */ -}; -#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0C0000, /* USB1 */ -}; -#else -#error rmobile EHCI USB driver not supported on this platform -#endif - -int ehci_hcd_stop(int index) -{ - int i; - u32 base; - struct ahbcom_pci_bridge *ahbcom_pci; - - base = usb_base_address[index]; - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - writel(0, &ahbcom_pci->ahb_bus_ctr); - - /* reset ehci */ - setbits_le32(base + EHCI_USBCMD, CMD_RESET); - for (i = 100; i > 0; i--) { - if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) - break; - udelay(100); - } - - if (!i) - printf("error : ehci(%d) reset failed.\n", index); - - if (index == (ARRAY_SIZE(usb_base_address) - 1)) - setbits_le32(SMSTPCR7, SMSTPCR703); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - u32 base; - u32 phys_base; - struct rmobile_ehci_reg *rehci; - struct ahbcom_pci_bridge *ahbcom_pci; - struct ahbconf_pci_bridge *ahbconf_pci; - struct ahb_pciconf *ahb_pciconf_ohci; - struct ahb_pciconf *ahb_pciconf_ehci; - uint32_t cap_base; - - base = usb_base_address[index]; - phys_base = base; - if (index == 0) - clrbits_le32(SMSTPCR7, SMSTPCR703); - - rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - ahbconf_pci = - (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); - ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); - ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); - - /* Clock & Reset & Direct Power Down */ - clrsetbits_le32(&ahbcom_pci->usbctr, - (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); - clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); - - /* AHB-PCI Bridge Communication Registers */ - writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win1_ctr); - writel(0xf0000000 | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win2_ctr); - writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); - - setbits_le32(&ahbcom_pci->pci_arbiter_ctr, - PCIBP_MODE | PCIREQ1 | PCIREQ0); - - /* PCI Configuration Registers for AHBPCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, - &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); - writel(0xf0000000, &ahbconf_pci->win2_basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahbconf_pci->cmnd_sts); - - /* PCI Configuration Registers for EHCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); - writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ohci->cmnd_sts); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ehci->cmnd_sts); - - /* Enable PCI interrupt */ - setbits_le32(&ahbcom_pci->pci_int_enable, - USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); - - *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); - cap_base = ehci_readl(&(*hccr)->cr_capbase); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); - - return 0; -}

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/usb/host/Makefile | 1 - drivers/usb/host/sl811-hcd.c | 714 ----------------------------------- drivers/usb/host/sl811.h | 104 ----- 3 files changed, 819 deletions(-) delete mode 100644 drivers/usb/host/sl811-hcd.c delete mode 100644 drivers/usb/host/sl811.h

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 3e5ba2bd0ba..8dad36f9369 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o obj-$(CONFIG_USB_ATMEL) += ohci-at91.o obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o -obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c deleted file mode 100644 index 7c823f241a8..00000000000 --- a/drivers/usb/host/sl811-hcd.c +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This code is based on linux driver for sl811hs chip, source at - * drivers/usb/host/sl811.c: - * - * SL811 Host Controller Interface driver for USB. - * - * Copyright (c) 2003/06, Courage Co., Ltd. - * - * Based on: - * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, - * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, - * Adam Richter, Gregory P. Smith; - * 2.Original SL811 driver (hc_sl811.o) by Pei Liu pbl@cypress.com - * 3.Rewrited as sl811.o by Yin Aihua yinah:couragetech.com.cn - */ - -#include <common.h> -#include <mpc8xx.h> -#include <usb.h> -#include <linux/delay.h> -#include "sl811.h" - -#include "../../../board/kup/common/kup.h" - -#ifdef __PPC__ -# define EIEIO __asm__ volatile ("eieio") -#else -# define EIEIO /* nothing */ -#endif - -#define SL811_ADR (0x50000000) -#define SL811_DAT (0x50000001) - -#ifdef SL811_DEBUG -static int debug = 9; -#endif - -static int root_hub_devnum = 0; -static struct usb_port_status rh_status = { 0 };/* root hub port status */ - -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd); - -static void sl811_write (__u8 index, __u8 data) -{ - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - *(volatile unsigned char *) (SL811_DAT) = data; - EIEIO; -} - -static __u8 sl811_read (__u8 index) -{ - __u8 data; - - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - data = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - return (data); -} - -/* - * Read consecutive bytes of data from the SL811H/SL11H buffer - */ -static void inline sl811_read_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *buf++ = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - } -} - -/* - * Write consecutive bytes of data to the SL811H/SL11H buffer - */ -static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *(volatile unsigned char *) (SL811_DAT) = *buf++; - EIEIO; - } -} - -int usb_init_kup4x (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - unsigned char tmp; - - memctl = &immap->im_memctl; - memctl->memc_or7 = 0xFFFF8726; - memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ - /* BP 14 low = USB ON */ - immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); - /* PB 14 nomal port */ - immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); - /* output */ - immap->im_cpm.cp_pbdir |= (BP_USB_VCC); - - puts ("USB: "); - - for (i = 0x10; i < 0xff; i++) { - sl811_write(i, i); - tmp = (sl811_read(i)); - if (tmp != i) { - printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); - return (-1); - } - } - printf ("SL811 ready\n"); - return (0); -} - -/* - * This function resets SL811HS controller and detects the speed of - * the connecting device - * - * Return: 0 = no device attached; 1 = USB device attached - */ -static int sl811_hc_reset(void) -{ - int status ; - - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - - mdelay(20); - - /* Disable hardware SOF generation, clear all irq status. */ - sl811_write(SL811_CTRL1, 0); - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_INTRSTS); - - if (status & SL811_INTR_NOTPRESENT) { - /* Device is not present */ - PDEBUG(0, "Device not present\n"); - rh_status.wPortStatus &= ~(USB_PORT_STAT_CONNECTION | USB_PORT_STAT_ENABLE); - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, SL811_INTR_INSRMV); - return 0; - } - - /* Send SOF to address 0, endpoint 0. */ - sl811_write(SL811_LEN_B, 0); - sl811_write(SL811_PIDEP_B, PIDEP(USB_PID_SOF, 0)); - sl811_write(SL811_DEV_B, 0x00); - sl811_write(SL811_SOFLOW, SL811_12M_LOW); - - if (status & SL811_INTR_SPEED_FULL) { - /* full speed device connect directly to root hub */ - PDEBUG (0, "Full speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION; - rh_status.wPortStatus &= ~USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } else { - /* slow speed device connect directly to root-hub */ - PDEBUG(0, "Low speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_CTL2_DSWAP | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SPEED_LOW | SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION | USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } - - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, /*SL811_INTR_INSRMV*/SL811_INTR_DONE_A); - - return 1; -} - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - root_hub_devnum = 0; - sl811_hc_reset(); - return 0; -} - -int usb_lowlevel_stop(int index) -{ - sl811_hc_reset(); - return 0; -} - -static int calc_needed_buswidth(int bytes, int need_preamble) -{ - return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048; -} - -static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len) -{ - __u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE; - __u16 status = 0; - int err = 0, time_start = get_timer(0); - int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - (dev->speed == USB_SPEED_LOW); - - if (len > 239) - return -1; - - if (usb_pipeout(pipe)) - ctrl |= SL811_USB_CTRL_DIR_OUT; - if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) - ctrl |= SL811_USB_CTRL_TOGGLE_1; - if (need_preamble) - ctrl |= SL811_USB_CTRL_PREAMBLE; - - sl811_write(SL811_INTRSTS, 0xff); - - while (err < 3) { - sl811_write(SL811_ADDR_A, 0x10); - sl811_write(SL811_LEN_A, len); - if (usb_pipeout(pipe) && len) - sl811_write_buf(0x10, buffer, len); - - if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble)) - ctrl |= SL811_USB_CTRL_SOF; - else - ctrl &= ~SL811_USB_CTRL_SOF; - - sl811_write(SL811_CTRL_A, ctrl); - while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { - if (5*CONFIG_SYS_HZ < get_timer(time_start)) { - printf("USB transmit timed out\n"); - return -USB_ST_CRC_ERR; - } - } - - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_STS_A); - - if (status & SL811_USB_STS_ACK) { - int remainder = sl811_read(SL811_CNT_A); - if (remainder) { - PDEBUG(0, "usb transfer remainder = %d\n", remainder); - len -= remainder; - } - if (usb_pipein(pipe) && len) - sl811_read_buf(0x10, buffer, len); - return len; - } - - if ((status & SL811_USB_STS_NAK) == SL811_USB_STS_NAK) - continue; - - PDEBUG(0, "usb transfer error %#x\n", (int)status); - err++; - } - - err = 0; - - if (status & SL811_USB_STS_ERROR) - err |= USB_ST_BUF_ERR; - if (status & SL811_USB_STS_TIMEOUT) - err |= USB_ST_CRC_ERR; - if (status & SL811_USB_STS_STALL) - err |= USB_ST_STALLED; - - return -err; -} - -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len) -{ - int dir_out = usb_pipeout(pipe); - int ep = usb_pipeendpoint(pipe); - int max = usb_maxpacket(dev, pipe); - int done = 0; - - PDEBUG(7, "dev = %ld pipe = %ld buf = %p size = %d dir_out = %d\n", - usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); - - dev->status = 0; - - sl811_write(SL811_DEV_A, usb_pipedevice(pipe)); - sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep)); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - dev->status = -res; - return res; - } - - if (!dir_out && res < max) /* short packet */ - break; - - done += res; - usb_dotoggle(dev, ep, dir_out); - } - - dev->act_len = done; - - return 0; -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len,struct devrequest *setup) -{ - int done = 0; - int devnum = usb_pipedevice(pipe); - int ep = usb_pipeendpoint(pipe); - - dev->status = 0; - - if (devnum == root_hub_devnum) - return sl811_rh_submit_urb(dev, pipe, buffer, len, setup); - - PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n", - devnum, ep, buffer, len, (int)setup->requesttype, - (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64); - - sl811_write(SL811_DEV_A, devnum); - sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep)); - /* setup phase */ - usb_settoggle(dev, ep, 1, 0); - if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep), - (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) { - int dir_in = usb_pipein(pipe); - int max = usb_maxpacket(dev, pipe); - - /* data phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, usb_pipeout(pipe), 1); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - PDEBUG(0, "status data failed!\n"); - dev->status = -res; - return 0; - } - done += res; - usb_dotoggle(dev, ep, usb_pipeout(pipe)); - if (dir_in && res < max) /* short packet */ - break; - } - - /* status phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, !usb_pipeout(pipe), 1); - if (sl811_send_packet(dev, - !dir_in ? usb_rcvctrlpipe(dev, ep) : - usb_sndctrlpipe(dev, ep), - 0, 0) < 0) { - PDEBUG(0, "status phase failed!\n"); - dev->status = -1; - } - } else { - PDEBUG(0, "setup phase failed!\n"); - dev->status = -1; - } - - dev->act_len = done; - - return done; -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len, int interval, bool nonblock) -{ - PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe, - buffer, len, interval); - return -1; -} - -/* - * SL811 Virtual Root Hub - */ - -/* Device descriptor */ -static __u8 sl811_rh_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x02, /* __u8 iProduct; */ - 0x01, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 sl811_rh_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, - 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -/* root hub class descriptor*/ -static __u8 sl811_rh_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x01, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x50, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0xfc, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -/* - * helper routine for returning string descriptors in UTF-16LE - * input can actually be ISO-8859-1; ASCII is its 7-bit subset - */ -static int ascii2utf (char *s, u8 *utf, int utfmax) -{ - int retval; - - for (retval = 0; *s && utfmax > 1; utfmax -= 2, retval += 2) { - *utf++ = *s++; - *utf++ = 0; - } - return retval; -} - -/* - * root_hub_string is used by each host controller's root hub code, - * so that they're identified consistently throughout the system. - */ -static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len) -{ - char buf [30]; - - /* assert (len > (2 * (sizeof (buf) + 1))); - assert (strlen (type) <= 8);*/ - - /* language ids */ - if (id == 0) { - *data++ = 4; *data++ = 3; /* 4 bytes data */ - *data++ = 0; *data++ = 0; /* some language id */ - return 4; - - /* serial number */ - } else if (id == 1) { - sprintf (buf, "%#x", serial); - - /* product description */ - } else if (id == 2) { - sprintf (buf, "USB %s Root Hub", type); - - /* id 3 == vendor description */ - - /* unsupported IDs --> "stall" */ - } else - return 0; - - ascii2utf (buf, data + 2, len - 2); - data [0] = 2 + strlen(buf) * 2; - data [1] = 3; - return data [0]; -} - -/* helper macro */ -#define OK(x) len = (x); break - -/* - * This function handles all USB request to the the virtual root hub - */ -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd) -{ - __u8 data_buf[16]; - __u8 *bufp = data_buf; - int len = 0; - int status = 0; - __u16 bmRType_bReq; - __u16 wValue = le16_to_cpu (cmd->value); - __u16 wLength = le16_to_cpu (cmd->length); -#ifdef SL811_DEBUG - __u16 wIndex = le16_to_cpu (cmd->index); -#endif - - if (usb_pipeint(pipe)) { - PDEBUG(0, "interrupt transfer unimplemented!\n"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - - PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", - bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); - - /* Request Destination: - without flags: Device, - USB_RECIP_INTERFACE: interface, - USB_RECIP_ENDPOINT: endpoint, - USB_TYPE_CLASS means HUB here, - USB_RECIP_OTHER | USB_TYPE_CLASS almost ever means HUB_PORT here - */ - switch (bmRType_bReq) { - case RH_GET_STATUS: - *(__u16 *)bufp = cpu_to_le16(1); - OK(2); - - case RH_GET_STATUS | USB_RECIP_INTERFACE: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_RECIP_ENDPOINT: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(0); - OK(4); - - case RH_GET_STATUS | USB_RECIP_OTHER | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(rh_status.wPortChange<<16 | rh_status.wPortStatus); - OK(4); - - case RH_CLEAR_FEATURE | USB_RECIP_ENDPOINT: - switch (wValue) { - case 1: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_TYPE_CLASS: - switch (wValue) { - case C_HUB_LOCAL_POWER: - OK(0); - - case C_HUB_OVER_CURRENT: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus &= ~USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus &= ~USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus &= ~USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_C_CONNECTION: - rh_status.wPortChange &= ~USB_PORT_STAT_C_CONNECTION; - OK(0); - - case USB_PORT_FEAT_C_ENABLE: - rh_status.wPortChange &= ~USB_PORT_STAT_C_ENABLE; - OK(0); - - case USB_PORT_FEAT_C_SUSPEND: - rh_status.wPortChange &= ~USB_PORT_STAT_C_SUSPEND; - OK(0); - - case USB_PORT_FEAT_C_OVER_CURRENT: - rh_status.wPortChange &= ~USB_PORT_STAT_C_OVERCURRENT; - OK(0); - - case USB_PORT_FEAT_C_RESET: - rh_status.wPortChange &= ~USB_PORT_STAT_C_RESET; - OK(0); - } - break; - - case RH_SET_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus |= USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_RESET: - rh_status.wPortStatus |= USB_PORT_STAT_RESET; - rh_status.wPortChange = 0; - rh_status.wPortChange |= USB_PORT_STAT_C_RESET; - rh_status.wPortStatus &= ~USB_PORT_STAT_RESET; - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus |= USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - } - break; - - case RH_SET_ADDRESS: - root_hub_devnum = wValue; - OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case USB_DT_DEVICE: - len = sizeof(sl811_rh_dev_des); - bufp = sl811_rh_dev_des; - OK(len); - - case USB_DT_CONFIG: - len = sizeof(sl811_rh_config_des); - bufp = sl811_rh_config_des; - OK(len); - - case USB_DT_STRING: - len = usb_root_hub_string(wValue & 0xff, (int)(long)0, "SL811HS", data, wLength); - if (len > 0) { - bufp = data; - OK(len); - } - - default: - status = -32; - } - break; - - case RH_GET_DESCRIPTOR | USB_TYPE_CLASS: - len = sizeof(sl811_rh_hub_des); - bufp = sl811_rh_hub_des; - OK(len); - - case RH_GET_CONFIGURATION: - bufp[0] = 0x01; - OK(1); - - case RH_SET_CONFIGURATION: - OK(0); - - default: - PDEBUG(1, "unsupported root hub command\n"); - status = -32; - } - - len = min(len, buf_len); - if (data != bufp) - memcpy(data, bufp, len); - - PDEBUG(5, "len = %d, status = %d\n", len, status); - - usb_dev->status = status; - usb_dev->act_len = len; - - return status == 0 ? len : status; -} diff --git a/drivers/usb/host/sl811.h b/drivers/usb/host/sl811.h deleted file mode 100644 index c1f9f013bd1..00000000000 --- a/drivers/usb/host/sl811.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __UBOOT_SL811_H -#define __UBOOT_SL811_H - -#undef SL811_DEBUG - -#ifdef SL811_DEBUG - #define PDEBUG(level, fmt, args...) \ - if (debug >= (level)) printf("[%s:%d] " fmt, \ - __PRETTY_FUNCTION__, __LINE__ , ## args) -#else - #define PDEBUG(level, fmt, args...) do {} while(0) -#endif - -/* Sl811 host control register */ -#define SL811_CTRL_A 0x00 -#define SL811_ADDR_A 0x01 -#define SL811_LEN_A 0x02 -#define SL811_STS_A 0x03 /* read */ -#define SL811_PIDEP_A 0x03 /* write */ -#define SL811_CNT_A 0x04 /* read */ -#define SL811_DEV_A 0x04 /* write */ -#define SL811_CTRL1 0x05 -#define SL811_INTR 0x06 -#define SL811_CTRL_B 0x08 -#define SL811_ADDR_B 0x09 -#define SL811_LEN_B 0x0A -#define SL811_STS_B 0x0B /* read */ -#define SL811_PIDEP_B 0x0B /* write */ -#define SL811_CNT_B 0x0C /* read */ -#define SL811_DEV_B 0x0C /* write */ -#define SL811_INTRSTS 0x0D /* write clears bitwise */ -#define SL811_HWREV 0x0E /* read */ -#define SL811_SOFLOW 0x0E /* write */ -#define SL811_SOFCNTDIV 0x0F /* read */ -#define SL811_CTRL2 0x0F /* write */ - -/* USB control register bits (addr 0x00 and addr 0x08) */ -#define SL811_USB_CTRL_ARM 0x01 -#define SL811_USB_CTRL_ENABLE 0x02 -#define SL811_USB_CTRL_DIR_OUT 0x04 -#define SL811_USB_CTRL_ISO 0x10 -#define SL811_USB_CTRL_SOF 0x20 -#define SL811_USB_CTRL_TOGGLE_1 0x40 -#define SL811_USB_CTRL_PREAMBLE 0x80 - -/* USB status register bits (addr 0x03 and addr 0x0B) */ -#define SL811_USB_STS_ACK 0x01 -#define SL811_USB_STS_ERROR 0x02 -#define SL811_USB_STS_TIMEOUT 0x04 -#define SL811_USB_STS_TOGGLE_1 0x08 -#define SL811_USB_STS_SETUP 0x10 -#define SL811_USB_STS_OVERFLOW 0x20 -#define SL811_USB_STS_NAK 0x40 -#define SL811_USB_STS_STALL 0x80 - -/* Control register 1 bits (addr 0x05) */ -#define SL811_CTRL1_SOF 0x01 -#define SL811_CTRL1_RESET 0x08 -#define SL811_CTRL1_JKSTATE 0x10 -#define SL811_CTRL1_SPEED_LOW 0x20 -#define SL811_CTRL1_SUSPEND 0x40 - -/* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */ -#define SL811_INTR_DONE_A 0x01 -#define SL811_INTR_DONE_B 0x02 -#define SL811_INTR_SOF 0x10 -#define SL811_INTR_INSRMV 0x20 -#define SL811_INTR_DETECT 0x40 -#define SL811_INTR_NOTPRESENT 0x40 -#define SL811_INTR_SPEED_FULL 0x80 /* only in status reg */ - -/* HW rev and SOF lo register bits (addr 0x0E) */ -#define SL811_HWR_HWREV 0xF0 - -/* SOF counter and control reg 2 (addr 0x0F) */ -#define SL811_CTL2_SOFHI 0x3F -#define SL811_CTL2_DSWAP 0x40 -#define SL811_CTL2_HOST 0x80 - -/* Set up for 1-ms SOF time. */ -#define SL811_12M_LOW 0xE0 -#define SL811_12M_HI 0x2E - -#define SL811_DATA_START 0x10 -#define SL811_DATA_LIMIT 240 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 - - -#define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep)) - -#endif /* __UBOOT_SL811_H */

This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

board/freescale/common/Makefile | 1 - board/freescale/common/vsc3316_3308.c | 530 -------------------------- 2 files changed, 531 deletions(-) delete mode 100644 board/freescale/common/vsc3316_3308.c

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 5f0503faf8d..c200cf4d403 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -54,7 +54,6 @@ obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o -obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_ZM7300) += zm7300.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c deleted file mode 100644 index c51f3c5aca2..00000000000 --- a/board/freescale/common/vsc3316_3308.c +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include "vsc3316_3308.h" -#include <log.h> - -#define REVISION_ID_REG 0x7E -#define INTERFACE_MODE_REG 0x79 -#define CURRENT_PAGE_REGISTER 0x7F -#define CONNECTION_CONFIG_PAGE 0x00 -#define INPUT_STATE_REG 0x13 -#define GLOBAL_INPUT_ISE1 0x51 -#define GLOBAL_INPUT_ISE2 0x52 -#define GLOBAL_INPUT_GAIN 0x53 -#define GLOBAL_INPUT_LOS 0x55 -#define GLOBAL_OUTPUT_PE1 0x56 -#define GLOBAL_OUTPUT_PE2 0x57 -#define GLOBAL_OUTPUT_LEVEL 0x58 -#define GLOBAL_OUTPUT_TERMINATION 0x5A -#define GLOBAL_CORE_CNTRL 0x5D -#define OUTPUT_MODE_PAGE 0x23 -#define CORE_CONTROL_PAGE 0x25 -#define CORE_CONFIG_REG 0x75 - -int vsc_if_enable(unsigned int vsc_addr) -{ - u8 data; - - debug("VSC:Configuring VSC at I2C address 0x%2x" - " for 2-wire interface\n", vsc_addr); - - /* enable 2-wire Serial InterFace (I2C) */ - data = 0x02; -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); -#else - return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); -#endif -} - -int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3316 at I2C address 0x%2x" - " for Tx\n", vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); - -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - - vsc_wp_config(vsc_addr); - - return 0; -} - -#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR -int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", - vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); - else - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 2, 0); - dm_i2c_reg_write(dev, 3, 0); - } else { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } else { - dm_i2c_reg_write(dev, 3, 0); - dm_i2c_reg_write(dev, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4); - else - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 2, 0); - i2c_reg_write(vsc_addr, 3, 0); - } else { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } else { - i2c_reg_write(vsc_addr, 3, 0); - i2c_reg_write(vsc_addr, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} -#endif - -int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x" - " for Tx\n", vsc_addr); -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} - -void vsc_wp_config(unsigned int vsc_addr) -{ - debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr); - - /* For new crosspoint configuration to occur, WP bit of - * CORE_CONFIG_REG should be set 1 and then reset to 0 */ -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); -#else - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); -#endif -}

This is very old and does not appear to be used. The CONFIG option enabling it is no-longer present. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

README | 7 ------- tools/Makefile | 4 ---- tools/xway-swap-bytes.c | 38 -------------------------------------- 3 files changed, 49 deletions(-) delete mode 100644 tools/xway-swap-bytes.c

diff --git a/README b/README index edce7890c0f..dee0332b0a8 100644 --- a/README +++ b/README @@ -286,13 +286,6 @@ The following options need to be configured: same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs.

-- MIPS CPU options: - CONFIG_XWAY_SWAP_BYTES - - Enable compilation of tools/xway-swap-bytes needed for Lantiq - XWAY SoCs for booting from NOR flash. The U-Boot image needs to - be swapped if a flash programmer is used. - - ARM options: CFG_SYS_EXCEPTION_VECTORS_HIGH

diff --git a/tools/Makefile b/tools/Makefile index 0eadd8154a7..041c437e65b 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -27,7 +27,6 @@ ifneq ($(HOST_TOOLS_ALL),) CONFIG_ARCH_KIRKWOOD = y CONFIG_CMD_LOADS = y CONFIG_CMD_NET = y -CONFIG_XWAY_SWAP_BYTES = y CONFIG_NETCONSOLE = y CONFIG_ARCH_SUNXI = y endif @@ -61,9 +60,6 @@ HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic hostprogs-$(CONFIG_CMD_LOADS) += img2srec HOSTCFLAGS_img2srec.o := -pedantic

-hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes -HOSTCFLAGS_xway-swap-bytes.o := -pedantic - hostprogs-y += mkenvimage mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o

diff --git a/tools/xway-swap-bytes.c b/tools/xway-swap-bytes.c deleted file mode 100644 index 3a6d82d54a0..00000000000 --- a/tools/xway-swap-bytes.c +++ /dev/null @@ -1,38 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> - -#ifndef BUFSIZ -# define BUFSIZ 4096 -#endif - -#undef BUFSIZ -# define BUFSIZ 64 -int main (void) -{ - short ibuff[BUFSIZ], obuff[BUFSIZ]; - int rc, i, len; - - while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { - memset (obuff, 0, sizeof (obuff)); - for (i = 0; i < (rc + 1) / 2; i++) { - obuff[i] = ibuff[i ^ 1]; - } - - len = (rc + 1) & ~1; - - if (write (1, obuff, len) != len) { - perror ("read error"); - return (EXIT_FAILURE); - } - - memset (ibuff, 0, sizeof (ibuff)); - } - - if (rc < 0) { - perror ("read error"); - return (EXIT_FAILURE); - } - return (EXIT_SUCCESS); -}

These are only present in SPL. Drop the references to non-SPL versions.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Drop patch "treewide: Correct invalid Kconfig syntax and warnings"

dts/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/dts/Kconfig b/dts/Kconfig index bc5f22029ff..44cc6bf1f6f 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -21,8 +21,8 @@ menu "Device Tree Control"

config OF_CONTROL bool "Run-time configuration via Device Tree" - select OF_LIBFDT if !OF_PLATDATA - select OF_REAL if !OF_PLATDATA + select OF_LIBFDT + select OF_REAL help This feature provides for run-time configuration of U-Boot via a flattened device tree.