Signed-off-by: Tom Warren twarren@nvidia.com --- arch/arm/include/asm/arch-tegra2/clk_rst.h | 5 + arch/arm/include/asm/arch-tegra2/pinmux.h | 6 + board/nvidia/common/board.c | 147 ++++++++ board/nvidia/common/board.h | 1 + drivers/mmc/Makefile | 1 + drivers/mmc/tegra2_mmc.c | 510 ++++++++++++++++++++++++++++ drivers/mmc/tegra2_mmc.h | 81 +++++ 7 files changed, 751 insertions(+), 0 deletions(-) create mode 100644 drivers/mmc/tegra2_mmc.c create mode 100644 drivers/mmc/tegra2_mmc.h

diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index bd8ad2c..36e27b5 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -191,4 +191,9 @@ struct clk_rst_ctlr {

#define CPCON (1 << 8)

+#define SWR_SDMMC4_RST (1 << 15) +#define CLK_ENB_SDMMC4 (1 << 15) +#define SWR_SDMMC3_RST (1 << 5) +#define CLK_ENB_SDMMC3 (1 << 5) + #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index 8b4bd8d..cce936d 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -51,5 +51,11 @@ struct pmux_tri_ctlr { #define Z_GMC (1 << 29) #define Z_IRRX (1 << 20) #define Z_IRTX (1 << 19) +#define Z_GMA (1 << 28) +#define Z_GME (1 << 0) +#define Z_ATB (1 << 1) +#define Z_SDB (1 << 15) +#define Z_SDC (1 << 1) +#define Z_SDD (1 << 2)

#endif /* PINMUX_H */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 3d6c248..627e061 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -32,6 +32,10 @@ #include <asm/arch/uart.h> #include "board.h"

+#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + DECLARE_GLOBAL_DATA_PTR;

const struct tegra2_sysinfo sysinfo = { @@ -171,6 +175,116 @@ static void pin_mux_uart(void) }

/* + * Routine: clock_init_mmc + * Description: init the PLL and clocks for the SDMMC controllers + */ +static void clock_init_mmc(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* Do the SDMMC resets/clock enables */ + + /* Assert Reset to SDMMC4 */ + reg = readl(&clkrst->crc_rst_dev_l); + reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */ + writel(reg, &clkrst->crc_rst_dev_l); + + /* Enable clk to SDMMC4 */ + reg = readl(&clkrst->crc_clk_out_enb_l); + reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */ + writel(reg, &clkrst->crc_clk_out_enb_l); + + /* Enable pllp_out0 to SDMMC4 */ + reg = readl(&clkrst->crc_clk_src_sdmmc4); + reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */ + reg |= (10 << 1); /* n-1, 11-1 shl 1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc4); + + /* + * As per the Tegra2 TRM, section 5.3.4: + * 'Wait 2 us for the clock to flush through the pipe/logic' + */ + udelay(2); + + /* De-assert reset to SDMMC4 */ + reg = readl(&clkrst->crc_rst_dev_l); + reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */ + writel(reg, &clkrst->crc_rst_dev_l); + + /* Assert Reset to SDMMC3 */ + reg = readl(&clkrst->crc_rst_dev_u); + reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */ + writel(reg, &clkrst->crc_rst_dev_u); + + /* Enable clk to SDMMC3 */ + reg = readl(&clkrst->crc_clk_out_enb_u); + reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */ + writel(reg, &clkrst->crc_clk_out_enb_u); + + /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */ + reg = readl(&clkrst->crc_clk_src_sdmmc3); + reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */ + reg |= (10 << 1); /* n-1, 11-1 shl 1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc3); + + /* wait for 2us */ + udelay(2); + + /* De-assert reset to SDMMC3 */ + reg = readl(&clkrst->crc_rst_dev_u); + reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */ + writel(reg, &clkrst->crc_rst_dev_u); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 reg; + + /* SDMMC4 */ + /* config 2, x8 on 2nd set of pins */ + reg = readl(&pmt->pmt_ctl_a); + reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_a); + reg = readl(&pmt->pmt_ctl_b); + reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_b); + reg = readl(&pmt->pmt_ctl_d); + reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_d); + + reg = readl(&pmt->pmt_tri_a); + reg &= ~Z_ATB; /* Z_ATB = normal (0) */ + reg &= ~Z_GMA; /* Z_GMA = normal (0) */ + writel(reg, &pmt->pmt_tri_a); + reg = readl(&pmt->pmt_tri_b); + reg &= ~Z_GME; /* Z_GME = normal (0) */ + writel(reg, &pmt->pmt_tri_b); + + /* SDMMC3 */ + /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ + reg = readl(&pmt->pmt_ctl_d); + reg &= 0xFFFF03FF; + reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */ + reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */ + reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ + writel(reg, &pmt->pmt_ctl_d); + + reg = readl(&pmt->pmt_tri_b); + reg &= ~Z_SDC; /* Z_SDC = normal (0) */ + reg &= ~Z_SDD; /* Z_SDD = normal (0) */ + writel(reg, &pmt->pmt_tri_b); + reg = readl(&pmt->pmt_tri_d); + reg &= ~Z_SDB; /* Z_SDB = normal (0) */ + writel(reg, &pmt->pmt_tri_d); +} + +/* * Routine: clock_init * Description: Do individual peripheral clock reset/enables */ @@ -210,3 +324,36 @@ int board_init(void)

return 0; } + +#ifdef CONFIG_TEGRA2_MMC +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + /* Enable clocks, muxes, etc. for SDMMC controllers */ + clock_init_mmc(); + pin_mux_mmc(); + + debug("board_mmc_init: init eMMC\n"); + /* init dev 0, eMMC chip, with 4-bit bus */ + tegra2_mmc_init(0, 4); + + debug("board_mmc_init: init SD slot\n"); + /* init dev 1, SD slot, with 4-bit bus */ + tegra2_mmc_init(1, 4); + + return 0; +} + +/* this is a weak define that we are overriding */ +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + debug("board_mmc_getcd called\n"); + /* + * Hard-code CD presence for now. Need to add GPIO inputs + * for Seaboard & Harmony (& Kaen/Aebl/Wario?) + */ + *cd = 1; + return 0; +} +#endif diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 350bc57..4334c02 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -29,5 +29,6 @@ void clock_init(void); void pinmux_init(void); void gpio_init(void); void gpio_config_uart(void); +int tegra2_mmc_init(int dev_index, int bus_width);

#endif /* BOARD_H */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a8fe17a..dce373d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o +COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c new file mode 100644 index 0000000..8b6f829 --- /dev/null +++ b/drivers/mmc/tegra2_mmc.c @@ -0,0 +1,510 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang mk7.kang@samsung.com + * Jaehoon Chung jh80.chung@samsung.com + * Portions Copyright 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clk_rst.h> +#include "tegra2_mmc.h" + +/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct mmc_host mmc_host[4]; + +static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index) +{ + unsigned long offset; + debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index); + + switch (dev_index) { + case 0: + offset = TEGRA2_SDMMC4_BASE; + break; + case 1: + offset = TEGRA2_SDMMC3_BASE; + break; + case 2: + offset = TEGRA2_SDMMC2_BASE; + break; + case 3: + offset = TEGRA2_SDMMC1_BASE; + break; + default: + offset = TEGRA2_SDMMC4_BASE; + break; + } + + return (struct tegra2_mmc *)(offset); +} + +static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) +{ + unsigned char ctrl; + + debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n", + (u32)data->dest, data->blocks, data->blocksize); + + writel((u32)data->dest, &host->reg->sysad); + /* + * DMASEL[4:3] + * 00 = Selects SDMA + * 01 = Reserved + * 10 = Selects 32-bit Address ADMA2 + * 11 = Selects 64-bit Address ADMA2 + */ + ctrl = readb(&host->reg->hostctl); + ctrl &= ~(3 << 3); /* SDMA */ + writeb(ctrl, &host->reg->hostctl); + + /* We do not handle DMA boundaries, so set it to max (512 KiB) */ + writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); + writew(data->blocks, &host->reg->blkcnt); +} + +static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) +{ + unsigned short mode; + debug(" mmc_set_transfer_mode called\n"); + /* + * TRNMOD + * MUL1SIN0[5] : Multi/Single Block Select + * RD1WT0[4] : Data Transfer Direction Select + * 1 = read + * 0 = write + * ENACMD12[2] : Auto CMD12 Enable + * ENBLKCNT[1] : Block Count Enable + * ENDMA[0] : DMA Enable + */ + mode = (1 << 1) | (1 << 0); + if (data->blocks > 1) + mode |= (1 << 5); + if (data->flags & MMC_DATA_READ) + mode |= (1 << 4); + + writew(mode, &host->reg->trnmod); +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + int flags, i; + unsigned int timeout; + unsigned int mask; + unsigned int retry = 0x100000; + debug(" mmc_send_cmd called\n"); + + /* Wait max 10 ms */ + timeout = 10; + + /* + * PRNSTS + * CMDINHDAT[1] : Command Inhibit (DAT) + * CMDINHCMD[0] : Command Inhibit (CMD) + */ + mask = (1 << 0); + if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY)) + mask |= (1 << 1); + + /* + * We shouldn't wait for data inhibit for stop commands, even + * though they might use busy signaling + */ + if (data) + mask &= ~(1 << 1); + + while (readl(&host->reg->prnsts) & mask) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return -1; + } + timeout--; + udelay(1000); + } + + if (data) + mmc_prepare_data(host, data); + + debug("cmd->arg: %08x\n", cmd->cmdarg); + writel(cmd->cmdarg, &host->reg->argument); + + if (data) + mmc_set_transfer_mode(host, data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + /* + * CMDREG + * CMDIDX[13:8] : Command index + * DATAPRNT[5] : Data Present Select + * ENCMDIDX[4] : Command Index Check Enable + * ENCMDCRC[3] : Command CRC Check Enable + * RSPTYP[1:0] + * 00 = No Response + * 01 = Length 136 + * 10 = Length 48 + * 11 = Length 48 Check busy after response + */ + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = 0; + else if (cmd->resp_type & MMC_RSP_136) + flags = (1 << 0); + else if (cmd->resp_type & MMC_RSP_BUSY) + flags = (3 << 0); + else + flags = (2 << 0); + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= (1 << 3); + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= (1 << 4); + if (data) + flags |= (1 << 5); + + debug("cmd: %d\n", cmd->cmdidx); + + writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); + + for (i = 0; i < retry; i++) { + mask = readl(&host->reg->norintsts); + /* Command Complete */ + if (mask & (1 << 0)) { + if (!data) + writel(mask, &host->reg->norintsts); + break; + } + } + + if (i == retry) { + printf("%s: waiting for status update\n", __func__); + return TIMEOUT; + } + + if (mask & (1 << 16)) { + /* Timeout Error */ + debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); + return TIMEOUT; + } else if (mask & (1 << 15)) { + /* Error Interrupt */ + debug("error: %08x cmd %d\n", mask, cmd->cmdidx); + return -1; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + unsigned int offset = + (unsigned int)(&host->reg->rspreg3 - i); + cmd->response[i] = readl(offset) << 8; + + if (i != 3) { + cmd->response[i] |= + readb(offset - 1); + } + debug("cmd->resp[%d]: %08x\n", + i, cmd->response[i]); + } + } else if (cmd->resp_type & MMC_RSP_BUSY) { + for (i = 0; i < retry; i++) { + /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ + if (readl(&host->reg->prnsts) + & (1 << 20)) /* DAT[0] */ + break; + } + + if (i == retry) { + printf("%s: card is still busy\n", __func__); + return TIMEOUT; + } + + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } else { + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } + } + + if (data) { + while (1) { + mask = readl(&host->reg->norintsts); + + if (mask & (1 << 15)) { + /* Error Interrupt */ + writel(mask, &host->reg->norintsts); + printf("%s: error during transfer: 0x%08x\n", + __func__, mask); + return -1; + } else if (mask & (1 << 3)) { + /* DMA Interrupt */ + debug("DMA end\n"); + break; + } else if (mask & (1 << 1)) { + /* Transfer Complete */ + debug("r/w is done\n"); + break; + } + } + writel(mask, &host->reg->norintsts); + } + + udelay(1000); + return 0; +} + +static void mmc_change_clock(struct mmc_host *host, uint clock) +{ + int div, hw_div; + unsigned short clk; + unsigned long timeout; + unsigned int reg, hostbase; + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + debug(" mmc_change_clock called\n"); + + /* Change Tegra2 SDMMCx clock divisor here */ + /* Source is 216MHz, PLLP_OUT0 */ + if (clock == 0) + goto out; + + div = 1; + if (clock <= 400000) { + hw_div = ((9-1)<<1); /* Best match is 375KHz */ + div = 64; + } else if (clock <= 20000000) + hw_div = ((11-1)<<1); /* Best match is 19.6MHz */ + else if (clock <= 26000000) + hw_div = ((9-1)<<1); /* Use 24MHz */ + else + hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */ + + debug("mmc_change_clock: hw_div = %d, card clock div = %d\n", + hw_div, div); + + /* Change SDMMCx divisor */ + + hostbase = readl(&host->base); + debug("mmc_change_clock: hostbase = %08X\n", hostbase); + + if (hostbase == TEGRA2_SDMMC1_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc1); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc1); + } else if (hostbase == TEGRA2_SDMMC2_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc2); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc2); + } else if (hostbase == TEGRA2_SDMMC3_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc3); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc3); + } else { + reg = readl(&clkrst->crc_clk_src_sdmmc4); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc4); + } + + writew(0, &host->reg->clkcon); + + div >>= 1; + /* + * CLKCON + * SELFREQ[15:8] : base clock divided by value + * ENSDCLK[2] : SD Clock Enable + * STBLINTCLK[1] : Internal Clock Stable + * ENINTCLK[0] : Internal Clock Enable + */ + clk = (div << 8) | (1 << 0); + writew(clk, &host->reg->clkcon); + + /* Wait max 10 ms */ + timeout = 10; + while (!(readw(&host->reg->clkcon) & (1 << 1))) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } + + clk |= (1 << 2); + writew(clk, &host->reg->clkcon); + + debug("mmc_change_clock: clkcon = %08X\n", clk); + debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg); + +out: + host->clock = clock; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct mmc_host *host = mmc->priv; + unsigned char ctrl; + debug(" mmc_set_ios called\n"); + + debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); + + /* Change clock first */ + + mmc_change_clock(host, mmc->clock); + + ctrl = readb(&host->reg->hostctl); + + /* + * WIDE8[5] + * 0 = Depend on WIDE4 + * 1 = 8-bit mode + * WIDE4[1] + * 1 = 4-bit mode + * 0 = 1-bit mode + */ + if (mmc->bus_width == 8) + ctrl |= (1 << 5); + else if (mmc->bus_width == 4) + ctrl |= (1 << 1); + else + ctrl &= ~(1 << 1); + + writeb(ctrl, &host->reg->hostctl); + debug("mmc_set_ios: hostctl = %08X\n", ctrl); +} + +static void mmc_reset(struct mmc_host *host) +{ + unsigned int timeout; + debug(" mmc_reset called\n"); + + /* + * RSTALL[0] : Software reset for all + * 1 = reset + * 0 = work + */ + writeb((1 << 0), &host->reg->swrst); + + host->clock = 0; + + /* Wait max 100 ms */ + timeout = 100; + + /* hw clears the bit when it's done */ + while (readb(&host->reg->swrst) & (1 << 0)) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + unsigned int mask; + debug(" mmc_core_init called\n"); + + mmc_reset(host); + + host->version = readw(&host->reg->hcver); + debug("host version = %x\n", host->version); + + /* mask all */ + writel(0xffffffff, &host->reg->norintstsen); + writel(0xffffffff, &host->reg->norintsigen); + + writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ + /* + * NORMAL Interrupt Status Enable Register init + * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable + * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable + * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable + * [0] ENSTACMDCMPLT : Command Complete Status Enable + */ + mask = readl(&host->reg->norintstsen); + mask &= ~(0xffff); + mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0); + writel(mask, &host->reg->norintstsen); + + /* + * NORMAL Interrupt Signal Enable Register init + * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable + */ + mask = readl(&host->reg->norintsigen); + mask &= ~(0xffff); + mask |= (1 << 1); + writel(mask, &host->reg->norintsigen); + + return 0; +} + +static int tegra2_mmc_initialize(int dev_index, int bus_width) +{ + struct mmc *mmc; + + debug(" mmc_initialize called\n"); + + mmc = &mmc_dev[dev_index]; + + sprintf(mmc->name, "Tegra2 SD/MMC"); + mmc->priv = &mmc_host[dev_index]; + mmc->send_cmd = mmc_send_cmd; + mmc->set_ios = mmc_set_ios; + mmc->init = mmc_core_init; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + if (bus_width == 8) + mmc->host_caps = MMC_MODE_8BIT; + else + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + /* + * min freq is for card identification, and is the highest + * low-speed SDIO card frequency (actually 400KHz) + * max freq is highest HS eMMC clock as per the SD/MMC spec + * (actually 52MHz) + * Both of these are the closest equivalents w/216MHz source + * clock and Tegra2 SDMMC divisors. + */ + mmc->f_min = 375000; + mmc->f_max = 48000000; + + mmc_host[dev_index].clock = 0; + mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index); + mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg; + mmc_register(mmc); + + return 0; +} + +int tegra2_mmc_init(int dev_index, int bus_width) +{ + debug(" tegra2_mmc_init: index %d, bus width %d\n", + dev_index, bus_width); + return tegra2_mmc_initialize(dev_index, bus_width); +} diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h new file mode 100644 index 0000000..4b80f9f --- /dev/null +++ b/drivers/mmc/tegra2_mmc.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang mk7.kang@samsung.com + * Portions Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __TEGRA2_MMC_H_ +#define __TEGRA2_MMC_H_ + +#define TEGRA2_SDMMC1_BASE 0xC8000000 +#define TEGRA2_SDMMC2_BASE 0xC8000200 +#define TEGRA2_SDMMC3_BASE 0xC8000400 +#define TEGRA2_SDMMC4_BASE 0xC8000600 + +#ifndef __ASSEMBLY__ +struct tegra2_mmc { + unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ + unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ + unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ + unsigned int argument; /* _ARGUMENT_0 */ + unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ + unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ + unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ + unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ + unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ + unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ + unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ + unsigned int prnsts; /* _PRESENT_STATE_0 */ + unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ + unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ + unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ + unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ + unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ + unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ + unsigned char swrst; /* _SW_RESET_ 31:24 */ + unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ + unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ + unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ + unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ + unsigned char res1[2]; /* _RESERVED 31:16 */ + unsigned int capareg; /* _CAPABILITIES_0 */ + unsigned char res2[4]; /* RESERVED, offset 44h-47h */ + unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ + unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ + unsigned short setacmd12err; /* offset 50h */ + unsigned short setinterr; /* offset 52h */ + unsigned char admaerr; /* offset 54h */ + unsigned char res4[3]; /* RESERVED, offset 55h-57h */ + unsigned long admaaddr; /* offset 58h-5Fh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned short slotintstatus; /* offset FCh */ + unsigned short hcver; /* HOST Version */ + unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ +}; + +struct mmc_host { + struct tegra2_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + unsigned int base; /* Base address, SDMMC1/2/3/4 */ +}; + +int tegra2_mmc_init(int dev_index, int bus_width); + +#endif /* __ASSEMBLY__ */ +#endif /* __TEGRA2_MMC_H_ */