[U-Boot] [PATCH 0/16] x86: dm: Convert x86 to use driver model more fully
At present x86 does not use driver model for SPI or LPC (low-pin-count, a bus used to talk to the EC on Chromebooks).
This series: - moves the ICH SPI driver over to driver model - moves the cros_ec LPC driver to driver model - removes non-driver-model cros_ec code (since now I2C, SPI and LPC are converted over) - makes some use of the PCI uclass for x86 init, by no means complete - fixes up the keyboard to work on chromebook_link (previously it would only work when started from coreboot)
Simon Glass (16): dm: sf: Add driver model read/write/erase methods dm: x86: spi: Convert ICH SPI driver to driver model dm: x86: Add a uclass for a Platform Controller Hub dm: x86: Add a uclass for an Low Pin Count (LPC) device x86: chromebook_link: dts: Add PCH and LPC devices dm: cros_ec: Convert cros_ec LPC driver to driver model cros_ec: Reinit the cros_ec device when 'crosec init' is used cros_ec: Drop unused CONFIG_DM_CROS_EC sandbox: cros_ec: Drop unnecessary init x86: cros_ec: Drop unnecessary init exynos: cros_ec: Drop unnecessary init cros_ec: Remove unused cros_ec_board_init() function fdt: cros_ec: Drop compatible string in fdtdec fdt: Drop LPC compatible string in fdtdec cros_ec: exynos: Match up device tree with kernel version i8042: Add keyboard enable logic in kbd_reset()
README | 8 - arch/arm/dts/exynos5250-snow.dts | 7 +- arch/arm/dts/exynos5420-peach-pit.dts | 5 +- arch/arm/dts/exynos5800-peach-pi.dts | 4 +- arch/sandbox/Kconfig | 3 - arch/sandbox/dts/cros-ec-keyboard.dtsi | 105 +++++ arch/sandbox/dts/sandbox.dts | 115 ++---- arch/x86/Kconfig | 6 + arch/x86/cpu/ivybridge/bd82x6x.c | 9 - arch/x86/cpu/ivybridge/cpu.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 13 +- arch/x86/cpu/ivybridge/mrccache.c | 7 +- arch/x86/cpu/ivybridge/sdram.c | 17 +- arch/x86/dts/chromebook_link.dts | 70 ++-- arch/x86/include/asm/arch-ivybridge/mrccache.h | 4 +- arch/x86/lib/Makefile | 2 + arch/x86/lib/init_helpers.c | 8 - arch/x86/lib/lpc-uclass.c | 28 ++ arch/x86/lib/pch-uclass.c | 28 ++ board/coreboot/coreboot/coreboot.c | 5 - board/google/chromebook_link/link.c | 3 - board/samsung/common/board.c | 12 - board/samsung/smdk5420/Kconfig | 6 - board/sandbox/sandbox.c | 12 - common/board_r.c | 3 - common/cros_ec.c | 33 -- drivers/input/cros_ec_keyb.c | 2 +- drivers/input/i8042.c | 7 + drivers/misc/Kconfig | 9 - drivers/misc/cros_ec.c | 250 +----------- drivers/misc/cros_ec_i2c.c | 4 +- drivers/misc/cros_ec_lpc.c | 29 +- drivers/misc/cros_ec_sandbox.c | 77 +--- drivers/misc/cros_ec_spi.c | 4 +- drivers/mtd/spi/sf-uclass.c | 16 + drivers/spi/ich.c | 519 +++++++++++++------------ include/configs/exynos5420-common.h | 2 - include/configs/sandbox.h | 1 - include/configs/snow.h | 2 - include/configs/x86-common.h | 1 - include/cros_ec.h | 137 ------- include/dm/uclass-id.h | 1 + include/fdtdec.h | 4 +- include/spi_flash.h | 47 ++- lib/fdtdec.c | 4 +- 45 files changed, 649 insertions(+), 982 deletions(-) create mode 100644 arch/sandbox/dts/cros-ec-keyboard.dtsi create mode 100644 arch/x86/lib/lpc-uclass.c create mode 100644 arch/x86/lib/pch-uclass.c
Permit use of a udevice to talk to SPI flash. Ultimately we would like to retire the use of 'struct spi_flash' for this purpose, so create the new API for those who want to move to it.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/mtd/spi/sf-uclass.c | 16 +++++++++++++++ include/spi_flash.h | 47 +++++++++++++++++++++++++++++++++++++++------ 2 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index fcf67e0..4b25902 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -11,6 +11,22 @@ #include <dm/device-internal.h> #include "sf_internal.h"
+int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) +{ + return sf_get_ops(dev)->read(dev, offset, len, buf); +} + +int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len, + const void *buf) +{ + return sf_get_ops(dev)->write(dev, offset, len, buf); +} + +int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len) +{ + return sf_get_ops(dev)->erase(dev, offset, len); +} + /* * TODO(sjg@chromium.org): This is an old-style function. We should remove * it when all SPI flash drivers use dm diff --git a/include/spi_flash.h b/include/spi_flash.h index 5913b39..218283f 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -118,6 +118,41 @@ struct dm_spi_flash_ops { #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
#ifdef CONFIG_DM_SPI_FLASH +/** + * spi_flash_read_dm() - Read data from SPI flash + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to read from + * @len: Number of bytes to read + * @buf: Buffer to put the data that is read + * @return 0 if OK, -ve on error + */ +int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf); + +/** + * spi_flash_write_dm() - Write data to SPI flash + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to write to + * @len: Number of bytes to write + * @buf: Buffer containing bytes to write + * @return 0 if OK, -ve on error + */ +int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len, + const void *buf); + +/** + * spi_flash_erase_dm() - Erase blocks of the SPI flash + * + * Note that @len must be a muiltiple of the flash sector size. + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to start erasing + * @len: Number of bytes to erase + * @return 0 if OK, -ve on error + */ +int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len); + int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode, struct udevice **devp); @@ -132,21 +167,21 @@ void spi_flash_free(struct spi_flash *flash); int spi_flash_remove(struct udevice *flash);
static inline int spi_flash_read(struct spi_flash *flash, u32 offset, - size_t len, void *buf) + size_t len, void *buf) { - return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf); + return spi_flash_read_dm(flash->dev, offset, len, buf); }
static inline int spi_flash_write(struct spi_flash *flash, u32 offset, - size_t len, const void *buf) + size_t len, const void *buf) { - return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf); + return spi_flash_write_dm(flash->dev, offset, len, buf); }
static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, - size_t len) + size_t len) { - return sf_get_ops(flash->dev)->erase(flash->dev, offset, len); + return spi_flash_erase_dm(flash->dev, offset, len); }
struct sandbox_state;
Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function.
Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/Kconfig | 6 + arch/x86/cpu/ivybridge/mrccache.c | 7 +- arch/x86/cpu/ivybridge/sdram.c | 17 +- arch/x86/include/asm/arch-ivybridge/mrccache.h | 4 +- arch/x86/lib/init_helpers.c | 8 - common/board_r.c | 3 - drivers/spi/ich.c | 519 +++++++++++++------------ include/configs/x86-common.h | 1 - 8 files changed, 287 insertions(+), 278 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d6176d2..86b7832 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -90,6 +90,12 @@ config DM_GPIO config DM_SERIAL default y
+config DM_SPI + default y + +config DM_SPI_FLASH + default y + config SYS_MALLOC_F default y
diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c index 0f1a64b..9205494 100644 --- a/arch/x86/cpu/ivybridge/mrccache.c +++ b/arch/x86/cpu/ivybridge/mrccache.c @@ -105,7 +105,7 @@ static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, return cache; }
-int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur) { struct mrc_data_container *cache; @@ -135,7 +135,7 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, debug("Erasing the MRC cache region of %x bytes at %x\n", entry->length, entry->offset);
- ret = spi_flash_erase(sf, entry->offset, entry->length); + ret = spi_flash_erase_dm(sf, entry->offset, entry->length); if (ret) { debug("Failed to erase flash region\n"); return ret; @@ -146,7 +146,8 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, /* Write the data out */ offset = (ulong)cache - base_addr + entry->offset; debug("Write MRC cache update to flash at %lx\n", offset); - ret = spi_flash_write(sf, offset, cur->data_size + sizeof(*cur), cur); + ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur), + cur); if (ret) { debug("Failed to write to SPI flash\n"); return ret; diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 672d069..9a6da37 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -89,11 +89,12 @@ void dram_init_banksize(void) } }
-static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) +static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) { const void *blob = gd->fdt_blob; int node, spi_node, mrc_node; int upto; + int ret;
/* Find the flash chip within the SPI controller node */ upto = 0; @@ -112,10 +113,13 @@ static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) return -EINVAL;
- if (sfp) { - *sfp = spi_flash_probe_fdt(blob, node, spi_node); - if (!*sfp) - return -EBADF; + if (devp) { + debug("getting sf\n"); + ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + devp); + debug("ret = %d\n", ret); + if (ret) + return ret; }
return 0; @@ -246,7 +250,7 @@ static int sdram_save_mrc_data(void) { struct mrc_data_container *data; struct fmap_entry entry; - struct spi_flash *sf; + struct udevice *sf; int ret;
if (!gd->arch.mrc_output_len) @@ -266,7 +270,6 @@ static int sdram_save_mrc_data(void)
free(data); err_data: - spi_flash_free(sf); err_entry: if (ret) debug("%s: Failed: %d\n", __func__, ret); diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h index 968b2ef..1d50ebb 100644 --- a/arch/x86/include/asm/arch-ivybridge/mrccache.h +++ b/arch/x86/include/asm/arch-ivybridge/mrccache.h @@ -20,7 +20,7 @@ __packed struct mrc_data_container { };
struct fmap_entry; -struct spi_flash; +struct udevice;
/** * mrccache_find_current() - find the latest MRC cache record @@ -45,7 +45,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); * @return 0 if updated, -EEXIST if the record is the same as the latest * record, other error if SPI write failed */ -int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur);
#endif diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 5097ca2..4fd47fc 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -89,11 +89,3 @@ int init_bd_struct_r(void)
return 0; } - -int init_func_spi(void) -{ - puts("SPI: "); - spi_init(); - puts("ready\n"); - return 0; -} diff --git a/common/board_r.c b/common/board_r.c index 19e3f3c..bce5329 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -761,9 +761,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_PPC initr_spi, #endif -#if defined(CONFIG_X86) && defined(CONFIG_SPI) - init_func_spi, -#endif #ifdef CONFIG_CMD_NAND initr_nand, #endif diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 9848e0b..50354fd 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -7,6 +7,7 @@ */
#include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <spi.h> @@ -19,154 +20,99 @@ #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b
-struct ich_ctlr { +struct ich_spi_platdata { pci_dev_t dev; /* PCI device number */ int ich_version; /* Controller version, 7 or 9 */ bool use_sbase; /* Use SBASE instead of RCB */ +}; + +struct ich_spi_priv { int ichspi_lock; int locked; - uint8_t *opmenu; + int opmenu; int menubytes; void *base; /* Base of register set */ - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + int preop; + int optype; + int addr; + int data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; + int status; + int control; + int bbar; uint32_t *pr; /* only for ich9 */ - uint8_t *speed; /* pointer to speed control */ + int speed; /* pointer to speed control */ ulong max_speed; /* Maximum bus speed in MHz */ + ulong cur_speed; /* Current bus speed */ + struct spi_trans trans; /* current transaction in progress */ };
-struct ich_ctlr ctlr; - -static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) -{ - return container_of(slave, struct ich_spi_slave, slave); -} - -static unsigned int ich_reg(const void *addr) -{ - return (unsigned)(addr - ctlr.base) & 0xffff; -} - -static u8 ich_readb(const void *addr) +static u8 ich_readb(struct ich_spi_priv *priv, int reg) { - u8 value = readb(addr); + u8 value = readb(priv->base + reg);
- debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); + debug("read %2.2x from %4.4x\n", value, reg);
return value; }
-static u16 ich_readw(const void *addr) +static u16 ich_readw(struct ich_spi_priv *priv, int reg) { - u16 value = readw(addr); + u16 value = readw(priv->base + reg);
- debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); + debug("read %4.4x from %4.4x\n", value, reg);
return value; }
-static u32 ich_readl(const void *addr) +static u32 ich_readl(struct ich_spi_priv *priv, int reg) { - u32 value = readl(addr); + u32 value = readl(priv->base + reg);
- debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); + debug("read %8.8x from %4.4x\n", value, reg);
return value; }
-static void ich_writeb(u8 value, void *addr) +static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) { - writeb(value, addr); - debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); + writeb(value, priv->base + reg); + debug("wrote %2.2x to %4.4x\n", value, reg); }
-static void ich_writew(u16 value, void *addr) +static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) { - writew(value, addr); - debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); + writew(value, priv->base + reg); + debug("wrote %4.4x to %4.4x\n", value, reg); }
-static void ich_writel(u32 value, void *addr) +static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) { - writel(value, addr); - debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); + writel(value, priv->base + reg); + debug("wrote %8.8x to %4.4x\n", value, reg); }
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(struct ich_spi_priv *priv, const void *value, + int dest_reg, uint32_t size) { - memcpy_toio(dest, value, size); + memcpy_toio(priv->base + dest_reg, value, size); }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, + uint32_t size) { - memcpy_fromio(value, src, size); + memcpy_fromio(value, priv->base + src_reg, size); }
-static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) +static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) { const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar;
minaddr &= bbar_mask; - ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; + ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - ich_writel(ichspi_bbar, ctlr->bbar); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - puts("spi_cs_is_valid used but not implemented\n"); - return 0; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ich_spi_slave *ich; - - ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); - if (!ich) { - puts("ICH SPI: Out of memory\n"); - return NULL; - } - - /* - * Yes this controller can only write a small number of bytes at - * once! The limit is typically 64 bytes. - */ - ich->slave.max_write_size = ctlr.databytes; - ich->speed = max_hz; - - /* - * ICH 7 SPI controller only supports array read command - * and byte program command for SST flash - */ - if (ctlr.ich_version == 7 || ctlr.use_sbase) { - ich->slave.op_mode_rx = SPI_OPM_RX_AS; - ich->slave.op_mode_tx = SPI_OPM_TX_BP; - } - - return &ich->slave; -} - -struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, - int spi_node) -{ - /* We only support a single SPI at present */ - return spi_setup_slave(0, 0, 20000000, 0); -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct ich_spi_slave *ich = to_ich_spi(slave); - - free(ich); + ich_writel(ctlr, ichspi_bbar, ctlr->bbar); }
/* @@ -209,7 +155,7 @@ static int ich9_can_do_33mhz(pci_dev_t dev) return speed == 1; }
-static int ich_find_spi_controller(struct ich_ctlr *ich) +static int ich_find_spi_controller(struct ich_spi_platdata *ich) { int last_bus = pci_last_busno(); int bus; @@ -242,131 +188,77 @@ static int ich_find_spi_controller(struct ich_ctlr *ich) return -ENODEV; }
-static int ich_init_controller(struct ich_ctlr *ctlr) +static int ich_init_controller(struct ich_spi_platdata *plat, + struct ich_spi_priv *ctlr) { uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint32_t sbase_addr; uint8_t *sbase;
- pci_read_config_dword(ctlr->dev, 0xf0, &rcba); + pci_read_config_dword(plat->dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000);
/* SBASE is similar */ - pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr); + pci_read_config_dword(plat->dev, 0x54, &sbase_addr); sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
- if (ctlr->ich_version == 7) { + if (plat->ich_version == 7) { struct ich7_spi_regs *ich7_spi;
ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); - ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; - ctlr->opmenu = ich7_spi->opmenu; + ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; + ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); - ctlr->optype = &ich7_spi->optype; - ctlr->addr = &ich7_spi->spia; - ctlr->data = (uint8_t *)ich7_spi->spid; + ctlr->optype = offsetof(struct ich7_spi_regs, optype); + ctlr->addr = offsetof(struct ich7_spi_regs, spia); + ctlr->data = offsetof(struct ich7_spi_regs, spid); ctlr->databytes = sizeof(ich7_spi->spid); - ctlr->status = (uint8_t *)&ich7_spi->spis; - ctlr->control = &ich7_spi->spic; - ctlr->bbar = &ich7_spi->bbar; - ctlr->preop = &ich7_spi->preop; + ctlr->status = offsetof(struct ich7_spi_regs, spis); + ctlr->control = offsetof(struct ich7_spi_regs, spic); + ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); + ctlr->preop = offsetof(struct ich7_spi_regs, preop); ctlr->base = ich7_spi; - } else if (ctlr->ich_version == 9) { + } else if (plat->ich_version == 9) { struct ich9_spi_regs *ich9_spi;
- if (ctlr->use_sbase) + if (plat->use_sbase) ich9_spi = (struct ich9_spi_regs *)sbase; else ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); - ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; - ctlr->opmenu = ich9_spi->opmenu; + ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; + ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); - ctlr->optype = &ich9_spi->optype; - ctlr->addr = &ich9_spi->faddr; - ctlr->data = (uint8_t *)ich9_spi->fdata; + ctlr->optype = offsetof(struct ich9_spi_regs, optype); + ctlr->addr = offsetof(struct ich9_spi_regs, faddr); + ctlr->data = offsetof(struct ich9_spi_regs, fdata); ctlr->databytes = sizeof(ich9_spi->fdata); - ctlr->status = &ich9_spi->ssfs; - ctlr->control = (uint16_t *)ich9_spi->ssfc; - ctlr->speed = ich9_spi->ssfc + 2; - ctlr->bbar = &ich9_spi->bbar; - ctlr->preop = &ich9_spi->preop; + ctlr->status = offsetof(struct ich9_spi_regs, ssfs); + ctlr->control = offsetof(struct ich9_spi_regs, ssfc); + ctlr->speed = ctlr->control + 2; + ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); + ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->pr = &ich9_spi->pr[0]; ctlr->base = ich9_spi; } else { - debug("ICH SPI: Unrecognized ICH version %d.\n", - ctlr->ich_version); - return -1; + debug("ICH SPI: Unrecognised ICH version %d\n", + plat->ich_version); + return -EINVAL; }
/* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; - if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) + if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev)) ctlr->max_speed = 33000000; debug("ICH SPI: Version %d detected at %p, speed %ld\n", - ctlr->ich_version, ctlr->base, ctlr->max_speed); + plat->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
return 0; }
-void spi_init(void) -{ - uint8_t bios_cntl; - - if (ich_find_spi_controller(&ctlr)) { - printf("ICH SPI: Cannot find device\n"); - return; - } - - if (ich_init_controller(&ctlr)) { - printf("ICH SPI: Cannot setup controller\n"); - return; - } - - /* - * Disable the BIOS write protect so write commands are allowed. On - * v9, deassert SMM BIOS Write Protect Disable. - */ - if (ctlr.use_sbase) { - struct ich9_spi_regs *ich9_spi; - - ich9_spi = (struct ich9_spi_regs *)ctlr.base; - bios_cntl = ich_readb(&ich9_spi->bcr); - bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ - bios_cntl |= 1; /* Write Protect Disable (WPD) */ - ich_writeb(bios_cntl, &ich9_spi->bcr); - } else { - pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); - if (ctlr.ich_version == 9) - bios_cntl &= ~(1 << 5); - pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); - } -} - -int spi_claim_bus(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) { trans->out += bytes; @@ -412,19 +304,19 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes) } }
-static int spi_setup_opcode(struct spi_trans *trans) +static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) { uint16_t optypes; - uint8_t opmenu[ctlr.menubytes]; + uint8_t opmenu[ctlr->menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ctlr.ichspi_lock) { + if (!ctlr->ichspi_lock) { /* The lock is off, so just use index 0. */ - ich_writeb(trans->opcode, ctlr.opmenu); - optypes = ich_readw(ctlr.optype); + ich_writeb(ctlr, trans->opcode, ctlr->opmenu); + optypes = ich_readw(ctlr, ctlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - ich_writew(optypes, ctlr.optype); + ich_writew(ctlr, optypes, ctlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ @@ -435,20 +327,20 @@ static int spi_setup_opcode(struct spi_trans *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0;
- read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ctlr.menubytes; + read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < ctlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; }
- if (opcode_index == ctlr.menubytes) { + if (opcode_index == ctlr->menubytes) { printf("ICH SPI: Opcode %x not found\n", trans->opcode); - return -1; + return -EINVAL; }
- optypes = ich_readw(ctlr.optype); + optypes = ich_readw(ctlr, ctlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -459,7 +351,7 @@ static int spi_setup_opcode(struct spi_trans *trans) if (optype != trans->type) { printf("ICH SPI: Transaction doesn't fit type %d\n", optype); - return -1; + return -ENOSPC; } return opcode_index; } @@ -481,7 +373,7 @@ static int spi_setup_offset(struct spi_trans *trans) return 1; default: printf("Unrecognized SPI transaction type %#x\n", trans->type); - return -1; + return -EPROTO; } }
@@ -492,16 +384,19 @@ static int spi_setup_offset(struct spi_trans *trans) * * Return the last read status value on success or -1 on failure. */ -static int ich_status_poll(u16 bitmask, int wait_til_set) +static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, + int wait_til_set) { int timeout = 600000; /* This will result in 6s */ u16 status = 0;
while (timeout--) { - status = ich_readw(ctlr.status); + status = ich_readw(ctlr, ctlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - ich_writew((status & bitmask), ctlr.status); + if (wait_til_set) { + ich_writew(ctlr, status & bitmask, + ctlr->status); + } return status; } udelay(10); @@ -509,30 +404,28 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
printf("ICH SPI: SCIP timeout, read %x, expected %x\n", status, bitmask); - return -1; + return -ETIMEDOUT; }
-/* -int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) -*/ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - struct ich_spi_slave *ich = to_ich_spi(slave); + struct udevice *bus = dev_get_parent(dev); + struct ich_spi_priv *ctlr = dev_get_priv(bus); uint16_t control; int16_t opcode_index; int with_address; int status; int bytes = bitlen / 8; - struct spi_trans *trans = &ich->trans; + struct spi_trans *trans = &ctlr->trans; unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); int using_cmd = 0; + int ret;
/* Ee don't support writing partial bytes. */ if (bitlen % 8) { debug("ICH SPI: Accessing partial bytes not supported\n"); - return -1; + return -EPROTONOSUPPORT; }
/* An empty end transaction can be ignored */ @@ -546,7 +439,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (dout && type == SPI_XFER_BEGIN) { if (bytes > ICH_MAX_CMD_LEN) { debug("ICH SPI: Command length limit exceeded\n"); - return -1; + return -ENOSPC; } memcpy(trans->cmd, dout, bytes); trans->cmd_len = bytes; @@ -577,21 +470,22 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* There has to always at least be an opcode. */ if (!trans->bytesout) { debug("ICH SPI: No opcode for transfer\n"); - return -1; + return -EPROTO; }
- if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; + ret = ich_status_poll(ctlr, SPIS_SCIP, 0); + if (ret < 0) + return ret;
- ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); + ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
spi_setup_type(trans, using_cmd ? bytes : 0); - opcode_index = spi_setup_opcode(trans); + opcode_index = spi_setup_opcode(ctlr, trans); if (opcode_index < 0) - return -1; + return -EINVAL; with_address = spi_setup_offset(trans); if (with_address < 0) - return -1; + return -EINVAL;
if (trans->opcode == SPI_OPCODE_WREN) { /* @@ -599,20 +493,20 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - if (!ctlr.ichspi_lock) - ich_writew(trans->opcode, ctlr.preop); + if (!ctlr->ichspi_lock) + ich_writew(ctlr, trans->opcode, ctlr->preop); return 0; }
- if (ctlr.speed && ctlr.max_speed >= 33000000) { + if (ctlr->speed && ctlr->max_speed >= 33000000) { int byte;
- byte = ich_readb(ctlr.speed); - if (ich->speed >= 33000000) + byte = ich_readb(ctlr, ctlr->speed); + if (ctlr->cur_speed >= 33000000) byte |= SSFC_SCF_33MHZ; else byte &= ~SSFC_SCF_33MHZ; - ich_writeb(byte, ctlr.speed); + ich_writeb(ctlr, byte, ctlr->speed); }
/* See if we have used up the command data */ @@ -623,35 +517,36 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, }
/* Preset control fields */ - control = ich_readw(ctlr.control); + control = ich_readw(ctlr, ctlr->control); control &= ~SSFC_RESERVED; control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
/* Issue atomic preop cycle if needed */ - if (ich_readw(ctlr.preop)) + if (ich_readw(ctlr, ctlr->preop)) control |= SPIC_ACS;
if (!trans->bytesout && !trans->bytesin) { /* SPI addresses are 24 bit only */ - if (with_address) - ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); - + if (with_address) { + ich_writel(ctlr, trans->offset & 0x00FFFFFF, + ctlr->addr); + } /* * This is a 'no data' command (like Write Enable), its * bitesout size was 1, decremented to zero while executing * spi_setup_opcode() above. Tell the chip to send the * command. */ - ich_writew(control, ctlr.control); + ich_writew(ctlr, control, ctlr->control);
/* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; + status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); + if (status < 0) + return status;
if (status & SPIS_FCERR) { debug("ICH SPI: Command transaction error\n"); - return -1; + return -EIO; }
return 0; @@ -664,9 +559,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans->bytesout > ctlr.databytes) { + if (trans->bytesout > ctlr->databytes) { debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); - return -1; + return -EPROTO; }
/* @@ -677,41 +572,41 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, uint32_t data_length;
/* SPI addresses are 24 bit only */ - ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); + ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
if (trans->bytesout) - data_length = min(trans->bytesout, ctlr.databytes); + data_length = min(trans->bytesout, ctlr->databytes); else - data_length = min(trans->bytesin, ctlr.databytes); + data_length = min(trans->bytesin, ctlr->databytes);
/* Program data into FDATA0 to N */ if (trans->bytesout) { - write_reg(trans->out, ctlr.data, data_length); + write_reg(ctlr, trans->out, ctlr->data, data_length); spi_use_out(trans, data_length); if (with_address) trans->offset += data_length; }
/* Add proper control fields' values */ - control &= ~((ctlr.databytes - 1) << 8); + control &= ~((ctlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8;
/* write it */ - ich_writew(control, ctlr.control); + ich_writew(ctlr, control, ctlr->control);
/* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; + status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); + if (status < 0) + return status;
if (status & SPIS_FCERR) { debug("ICH SPI: Data transaction error\n"); - return -1; + return -EIO; }
if (trans->bytesin) { - read_reg(ctlr.data, trans->in, data_length); + read_reg(ctlr, ctlr->data, trans->in, data_length); spi_use_in(trans, data_length); if (with_address) trans->offset += data_length; @@ -719,7 +614,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, }
/* Clear atomic preop now that xfer is done */ - ich_writew(0, ctlr.preop); + ich_writew(ctlr, 0, ctlr->preop);
return 0; } @@ -731,15 +626,18 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's * done elsewhere. */ -int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) +int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, + uint32_t length, int hint) { + struct udevice *bus = dev->parent; + struct ich_spi_priv *ctlr = dev_get_priv(bus); uint32_t tmplong; uint32_t upper_limit;
- if (!ctlr.pr) { + if (!ctlr->pr) { printf("%s: operation not supported on this chipset\n", __func__); - return -1; + return -ENOSYS; }
if (length == 0 || @@ -747,7 +645,7 @@ int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) hint < 0 || hint > 4) { printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, lower_limit, length, hint); - return -1; + return -EPERM; }
upper_limit = lower_limit + length - 1; @@ -766,8 +664,121 @@ int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) ((lower_limit & 0x01fff000) >> 12);
printf("%s: writing 0x%08x to %p\n", __func__, tmplong, - &ctlr.pr[hint]); - ctlr.pr[hint] = tmplong; + &ctlr->pr[hint]); + ctlr->pr[hint] = tmplong; + + return 0; +} + +static int ich_spi_probe(struct udevice *bus) +{ + struct ich_spi_platdata *plat = dev_get_platdata(bus); + struct ich_spi_priv *priv = dev_get_priv(bus); + uint8_t bios_cntl; + int ret; + + ret = ich_init_controller(plat, priv); + if (ret) + return ret; + /* + * Disable the BIOS write protect so write commands are allowed. On + * v9, deassert SMM BIOS Write Protect Disable. + */ + if (plat->use_sbase) { + struct ich9_spi_regs *ich9_spi; + + ich9_spi = priv->base; + bios_cntl = ich_readb(priv, ich9_spi->bcr); + bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl |= 1; /* Write Protect Disable (WPD) */ + ich_writeb(priv, bios_cntl, ich9_spi->bcr); + } else { + pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); + if (plat->ich_version == 9) + bios_cntl &= ~(1 << 5); + pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); + } + + priv->cur_speed = priv->max_speed; + + return 0; +} + +static int ich_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct ich_spi_platdata *plat = dev_get_platdata(bus); + int ret; + + ret = ich_find_spi_controller(plat); + if (ret) + return ret;
return 0; } + +static int ich_spi_set_speed(struct udevice *bus, uint speed) +{ + struct ich_spi_priv *priv = dev_get_priv(bus); + + priv->cur_speed = speed; + + return 0; +} + +static int ich_spi_set_mode(struct udevice *bus, uint mode) +{ + debug("%s: mode=%d\n", __func__, mode); + + return 0; +} + +static int ich_spi_child_pre_probe(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct ich_spi_platdata *plat = dev_get_platdata(bus); + struct ich_spi_priv *priv = dev_get_priv(bus); + struct spi_slave *slave = dev_get_parentdata(dev); + + /* + * Yes this controller can only write a small number of bytes at + * once! The limit is typically 64 bytes. + */ + slave->max_write_size = priv->databytes; + /* + * ICH 7 SPI controller only supports array read command + * and byte program command for SST flash + */ + if (plat->ich_version == 7) { + slave->op_mode_rx = SPI_OPM_RX_AS; + slave->op_mode_tx = SPI_OPM_TX_BP; + } + + return 0; +} + +static const struct dm_spi_ops ich_spi_ops = { + .xfer = ich_spi_xfer, + .set_speed = ich_spi_set_speed, + .set_mode = ich_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id ich_spi_ids[] = { + { .compatible = "intel,ich-spi" }, + { } +}; + +U_BOOT_DRIVER(ich_spi) = { + .name = "ich_spi", + .id = UCLASS_SPI, + .of_match = ich_spi_ids, + .ops = &ich_spi_ops, + .ofdata_to_platdata = ich_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), + .priv_auto_alloc_size = sizeof(struct ich_spi_priv), + .child_pre_probe = ich_spi_child_pre_probe, + .probe = ich_spi_probe, +}; diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 994874c..c046529 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -204,7 +204,6 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI -#define CONFIG_OF_SPI_FLASH
/*----------------------------------------------------------------------- * Environment configuration
Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device.
The device can have children, so make it scan the device tree for these.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/bd82x6x.c | 9 --------- arch/x86/lib/Makefile | 1 + arch/x86/lib/pch-uclass.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 9 deletions(-) create mode 100644 arch/x86/lib/pch-uclass.c
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 7b74282..ca8cccf 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -157,12 +157,3 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .of_match = bd82x6x_ids, .probe = bd82x6x_probe, }; - -/* - * TODO(sjg@chromium.org): Move this to arch/x86/lib or similar when other - * boards also use a PCH - */ -UCLASS_DRIVER(pch) = { - .id = UCLASS_PCH, - .name = "pch", -}; diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 67a34d8..fe022f6 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o ifndef CONFIG_DM_PCI obj-$(CONFIG_PCI) += pci_type1.o endif +obj-y += pch-uclass.o obj-y += relocate.o obj-y += physmem.o obj-$(CONFIG_X86_RAMTEST) += ramtest.o diff --git a/arch/x86/lib/pch-uclass.c b/arch/x86/lib/pch-uclass.c new file mode 100644 index 0000000..d1082e1 --- /dev/null +++ b/arch/x86/lib/pch-uclass.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +static int pch_uclass_post_bind(struct udevice *bus) +{ + /* + * Scan the device tree for devices + * + * Before relocation, only bind devices marked for pre-relocation + * use. + */ + return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + +UCLASS_DRIVER(pch) = { + .id = UCLASS_PCH, + .name = "pch", + .post_bind = pch_uclass_post_bind, +};
On x86 systems this device is commonly used to provide legacy port access. It is sort-of a replacement for the old ISA bus.
Add a uclass for this, and allow it to have child devices.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/lib/Makefile | 1 + arch/x86/lib/lpc-uclass.c | 28 ++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + 3 files changed, 30 insertions(+) create mode 100644 arch/x86/lib/lpc-uclass.c
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index fe022f6..6c571dd 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_HAVE_FSP) += cmd_hob.o obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o +obj-y += lpc-uclass.o obj-y += cmd_mtrr.o obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c new file mode 100644 index 0000000..6aeb4d4 --- /dev/null +++ b/arch/x86/lib/lpc-uclass.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +static int lpc_uclass_post_bind(struct udevice *bus) +{ + /* + * Scan the device tree for devices + * + * Before relocation, only bind devices marked for pre-relocation + * use. + */ + return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + +UCLASS_DRIVER(lpc) = { + .id = UCLASS_LPC, + .name = "lpc", + .post_bind = lpc_uclass_post_bind, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 047ac15..458c322 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -38,6 +38,7 @@ enum uclass_id { UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ UCLASS_PCH, /* x86 platform controller hub */ + UCLASS_LPC, /* x86 'low pin count' interface */
UCLASS_COUNT, UCLASS_INVALID = -1,
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also.
Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/cpu.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 13 +++++++- arch/x86/dts/chromebook_link.dts | 70 ++++++++++++++++++++++------------------ include/fdtdec.h | 1 + lib/fdtdec.c | 3 +- 5 files changed, 55 insertions(+), 34 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 795787d..b2413d3 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -142,7 +142,7 @@ int x86_post_cpu_init(void) /* TODO(sjg@chromium.org): Get rid of gd->hose */ gd->hose = hose;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index c20e180..bc1a0f0 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -510,7 +510,7 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev) pci_write_bar32(hose, dev, 3, 0x800); pci_write_bar32(hose, dev, 4, 0x900);
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT;
@@ -568,3 +568,14 @@ void lpc_enable(pci_dev_t dev) writew(0x0010, RCB_REG(DISPBDF)); setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); } + +static const struct udevice_id bd82x6x_lpc_ids[] = { + { .compatible = "intel,bd82x6x-lpc" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_lpc_drv) = { + .name = "lpc", + .id = UCLASS_LPC, + .of_match = bd82x6x_lpc_ids, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 0a845f2..b450c3c 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -8,7 +8,7 @@ compatible = "google,link", "intel,celeron-ivybridge";
aliases { - spi0 = "/spi"; + spi0 = "/pci/pch/spi"; };
config { @@ -151,26 +151,6 @@ }; };
- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #size-cells = <1>; - #address-cells = <1>; - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - /* Alignment: 4k (for updating) */ - reg = <0x003e0000 0x00010000>; - type = "wiped"; - wipe-value = [ff]; - }; - }; - }; - pci { compatible = "intel,pci-ivybridge", "pci-x86"; #address-cells = <3>; @@ -199,9 +179,10 @@ intel,pch-backlight = <0x04000000>; };
- lpc { + pch { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x"; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; gen-dec = <0x800 0xfc 0x900 0xfc>; @@ -212,17 +193,44 @@ 1 0 0 0 0 0 0 0>; /* Enable EC SMI source */ intel,alt-gp-smi-enable = <0x0100>; + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + };
- cros-ec@200 { - compatible = "google,cros-ec"; - reg = <0x204 1 0x200 1 0x880 0x80>; - - /* Describes the flash memory within the EC */ + lpc { + compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; - #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0xff>; + #size-cells = <0>; + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* + * Describes the flash memory within + * the EC + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; }; }; }; diff --git a/include/fdtdec.h b/include/fdtdec.h index 3213895..665d1ef 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -168,6 +168,7 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_INTEL_PCH, /* Intel PCH */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 2a48243..15663da 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -67,7 +67,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), - COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x"), + COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"), COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(MEMORY_SPD, "memory-spd"), COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), @@ -76,6 +76,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(INTEL_ICH_SPI, "intel,ich-spi"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), + COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
This is the last driver to be converted. It requires an LPC bus and a special check_version() method.
Signed-off-by: Simon Glass sjg@chromium.org ---
configs/chromebook_link_defconfig | 1 + drivers/misc/cros_ec.c | 12 ++++++++++++ drivers/misc/cros_ec_lpc.c | 29 +++++++++++++++++++++++++++-- 3 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index f3196fd..0ffdaee 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -10,3 +10,4 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_DM_PCI=y +CONFIG_DM_CROS_EC=y diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 1c29ba8..efcad89 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -681,11 +681,23 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) struct ec_params_hello req; struct ec_response_hello *resp;
+#ifdef CONFIG_DM_CROS_EC + struct dm_cros_ec_ops *ops; + int ret; + + ops = dm_cros_ec_get_ops(dev->dev); + if (ops->check_version) { + ret = ops->check_version(dev->dev); + if (ret) + return ret; + } +#else #ifdef CONFIG_CROS_EC_LPC /* LPC has its own way of doing this */ if (dev->interface == CROS_EC_IF_LPC) return cros_ec_lpc_check_version(dev); #endif +#endif
/* * TODO(sjg@chromium.org). diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 07624a1..ef6e682 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -14,6 +14,7 @@ */
#include <common.h> +#include <dm.h> #include <command.h> #include <cros_ec.h> #include <asm/io.h> @@ -40,10 +41,11 @@ static int wait_for_sync(struct cros_ec_dev *dev) return 0; }
-int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, +int cros_ec_lpc_command(struct udevice *udev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len) { + struct cros_ec_dev *dev = dev_get_uclass_priv(udev); const int cmd_addr = EC_LPC_ADDR_HOST_CMD; const int data_addr = EC_LPC_ADDR_HOST_DATA; const int args_addr = EC_LPC_ADDR_HOST_ARGS; @@ -178,7 +180,7 @@ int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob) * seeing whether the EC sets the EC_HOST_ARGS_FLAG_FROM_HOST flag * in args when it responds. */ -int cros_ec_lpc_check_version(struct cros_ec_dev *dev) +static int cros_ec_lpc_check_version(struct udevice *dev) { if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) == 'E' && inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) @@ -192,3 +194,26 @@ int cros_ec_lpc_check_version(struct cros_ec_dev *dev) printf("%s: ERROR: old EC interface not supported\n", __func__); return -1; } + +static int cros_ec_probe(struct udevice *dev) +{ + return cros_ec_register(dev); +} + +static struct dm_cros_ec_ops cros_ec_ops = { + .command = cros_ec_lpc_command, + .check_version = cros_ec_lpc_check_version, +}; + +static const struct udevice_id cros_ec_ids[] = { + { .compatible = "google,cros-ec" }, + { } +}; + +U_BOOT_DRIVER(cros_ec_lpc) = { + .name = "cros_ec", + .id = UCLASS_CROS_EC, + .of_match = cros_ec_ids, + .probe = cros_ec_probe, + .ops = &cros_ec_ops, +};
This command is supposed to reinit the device. At present with driver model is does nothing. Implement this feature.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/misc/cros_ec.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index efcad89..6d4d045 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -1606,13 +1606,19 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = argv[1]; if (0 == strcmp("init", cmd)) { -#ifndef CONFIG_DM_CROS_EC +#ifdef CONFIG_DM_CROS_EC + /* Remove any existing device */ + ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev); + if (!ret) + device_remove(udev); + ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); +#else ret = cros_ec_init(gd->fdt_blob, &dev); +#endif if (ret) { printf("Could not init cros_ec device (err %d)\n", ret); return 1; } -#endif return 0; }
Since all supported boards enable this option now, we can remove it along with the old code.
Signed-off-by: Simon Glass sjg@chromium.org ---
README | 8 -- arch/sandbox/Kconfig | 3 - board/samsung/smdk5420/Kconfig | 6 - common/cros_ec.c | 30 +---- configs/chromebook_link_defconfig | 1 - drivers/misc/Kconfig | 9 -- drivers/misc/cros_ec.c | 240 -------------------------------------- drivers/misc/cros_ec_sandbox.c | 73 ------------ include/configs/snow.h | 1 - include/cros_ec.h | 130 --------------------- 10 files changed, 1 insertion(+), 500 deletions(-)
diff --git a/README b/README index ba57dc5..ca4b2b3 100644 --- a/README +++ b/README @@ -708,14 +708,6 @@ The following options need to be configured: enabled together (it is not possible to use driver model for one and not the other).
- CONFIG_DM_CROS_EC - - Enable driver model for the Chrome OS EC interface. This - allows the cros_ec SPI driver to operate with CONFIG_DM_SPI - but otherwise makes few changes. Since cros_ec also supports - I2C and LPC (which don't support driver model yet), a full - conversion is not yet possible. -
** Code size options: The following options are enabled by default except in SPL. Enable them explicitly to get these diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 477a20a..7ea6de7 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -19,9 +19,6 @@ config DM_GPIO config DM_SERIAL default y
-config DM_CROS_EC - default y - config DM_SPI default y
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index 576abae..a9d62ff 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -22,9 +22,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pi"
-config DM_CROS_EC - default y - endif
if TARGET_PEACH_PIT @@ -38,9 +35,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pit"
-config DM_CROS_EC - default y - endif
if TARGET_SMDK5420 diff --git a/common/cros_ec.c b/common/cros_ec.c index 64b4679..f9c74ca 100644 --- a/common/cros_ec.c +++ b/common/cros_ec.c @@ -15,18 +15,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_CROS_EC -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; - -static struct local_info local; -#endif - struct cros_ec_dev *board_get_cros_ec_dev(void) { -#ifdef CONFIG_DM_CROS_EC struct udevice *dev; int ret;
@@ -36,30 +26,15 @@ struct cros_ec_dev *board_get_cros_ec_dev(void) return NULL; } return dev_get_uclass_priv(dev); -#else - return local.cros_ec_dev; -#endif -} - -static int board_init_cros_ec_devices(const void *blob) -{ -#ifndef CONFIG_DM_CROS_EC - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ -#endif - - return 0; }
int cros_ec_board_init(void) { - return board_init_cros_ec_devices(gd->fdt_blob); + return 0; }
int cros_ec_get_error(void) { -#ifdef CONFIG_DM_CROS_EC struct udevice *dev; int ret;
@@ -68,7 +43,4 @@ int cros_ec_get_error(void) return ret;
return 0; -#else - return local.cros_ec_err; -#endif } diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 0ffdaee..f3196fd 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -10,4 +10,3 @@ CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_DM_PCI=y -CONFIG_DM_CROS_EC=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 813d1c2..e69de29 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -1,9 +0,0 @@ -config DM_CROS_EC - bool "Enable Driver Model for Chrome OS EC" - depends on DM - help - Enable driver model for the Chrome OS EC interface. This - allows the cros_ec SPI driver to operate with CONFIG_DM_SPI - but otherwise makes few changes. Since cros_ec also supports - I2C and LPC (which don't support driver model yet), a full - conversion is not yet possible. diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 6d4d045..982bac7 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -41,10 +41,6 @@ enum { CROS_EC_CMD_HASH_TIMEOUT_MS = 2000, };
-#ifndef CONFIG_DM_CROS_EC -static struct cros_ec_dev static_dev, *last_dev; -#endif - DECLARE_GLOBAL_DATA_PTR;
/* Note: depends on enum ec_current_image */ @@ -211,9 +207,7 @@ static int send_command_proto3(struct cros_ec_dev *dev, const void *dout, int dout_len, uint8_t **dinp, int din_len) { -#ifdef CONFIG_DM_CROS_EC struct dm_cros_ec_ops *ops; -#endif int out_bytes, in_bytes; int rv;
@@ -228,28 +222,8 @@ static int send_command_proto3(struct cros_ec_dev *dev, if (in_bytes < 0) return in_bytes;
-#ifdef CONFIG_DM_CROS_EC ops = dm_cros_ec_get_ops(dev->dev); rv = ops->packet ? ops->packet(dev->dev, out_bytes, in_bytes) : -ENOSYS; -#else - switch (dev->interface) { -#ifdef CONFIG_CROS_EC_SPI - case CROS_EC_IF_SPI: - rv = cros_ec_spi_packet(dev, out_bytes, in_bytes); - break; -#endif -#ifdef CONFIG_CROS_EC_SANDBOX - case CROS_EC_IF_SANDBOX: - rv = cros_ec_sandbox_packet(dev, out_bytes, in_bytes); - break; -#endif - case CROS_EC_IF_NONE: - /* TODO: support protocol 3 for LPC, I2C; for now fall through */ - default: - debug("%s: Unsupported interface\n", __func__); - rv = -1; - } -#endif if (rv < 0) return rv;
@@ -261,9 +235,7 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { -#ifdef CONFIG_DM_CROS_EC struct dm_cros_ec_ops *ops; -#endif int ret = -1;
/* Handle protocol version 3 support */ @@ -272,38 +244,9 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, dout, dout_len, dinp, din_len); }
-#ifdef CONFIG_DM_CROS_EC ops = dm_cros_ec_get_ops(dev->dev); ret = ops->command(dev->dev, cmd, cmd_version, (const uint8_t *)dout, dout_len, dinp, din_len); -#else - switch (dev->interface) { -#ifdef CONFIG_CROS_EC_SPI - case CROS_EC_IF_SPI: - ret = cros_ec_spi_command(dev, cmd, cmd_version, - (const uint8_t *)dout, dout_len, - dinp, din_len); - break; -#endif -#ifdef CONFIG_CROS_EC_I2C - case CROS_EC_IF_I2C: - ret = cros_ec_i2c_command(dev, cmd, cmd_version, - (const uint8_t *)dout, dout_len, - dinp, din_len); - break; -#endif -#ifdef CONFIG_CROS_EC_LPC - case CROS_EC_IF_LPC: - ret = cros_ec_lpc_command(dev, cmd, cmd_version, - (const uint8_t *)dout, dout_len, - dinp, din_len); - break; -#endif - case CROS_EC_IF_NONE: - default: - ret = -1; - } -#endif
return ret; } @@ -681,7 +624,6 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) struct ec_params_hello req; struct ec_response_hello *resp;
-#ifdef CONFIG_DM_CROS_EC struct dm_cros_ec_ops *ops; int ret;
@@ -691,13 +633,6 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) if (ret) return ret; } -#else -#ifdef CONFIG_CROS_EC_LPC - /* LPC has its own way of doing this */ - if (dev->interface == CROS_EC_IF_LPC) - return cros_ec_lpc_check_version(dev); -#endif -#endif
/* * TODO(sjg@chromium.org). @@ -1027,76 +962,6 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state) return 0; }
-#ifndef CONFIG_DM_CROS_EC -/** - * Decode EC interface details from the device tree and allocate a suitable - * device. - * - * @param blob Device tree blob - * @param node Node to decode from - * @param devp Returns a pointer to the new allocated device - * @return 0 if ok, -1 on error - */ -static int cros_ec_decode_fdt(const void *blob, int node, - struct cros_ec_dev **devp) -{ - enum fdt_compat_id compat; - struct cros_ec_dev *dev; - int parent; - - /* See what type of parent we are inside (this is expensive) */ - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -1; - } - - dev = &static_dev; - dev->node = node; - dev->parent_node = parent; - - compat = fdtdec_lookup(blob, parent); - switch (compat) { -#ifdef CONFIG_CROS_EC_SPI - case COMPAT_SAMSUNG_EXYNOS_SPI: - dev->interface = CROS_EC_IF_SPI; - if (cros_ec_spi_decode_fdt(dev, blob)) - return -1; - break; -#endif -#ifdef CONFIG_CROS_EC_I2C - case COMPAT_SAMSUNG_S3C2440_I2C: - dev->interface = CROS_EC_IF_I2C; - if (cros_ec_i2c_decode_fdt(dev, blob)) - return -1; - break; -#endif -#ifdef CONFIG_CROS_EC_LPC - case COMPAT_INTEL_LPC: - dev->interface = CROS_EC_IF_LPC; - break; -#endif -#ifdef CONFIG_CROS_EC_SANDBOX - case COMPAT_SANDBOX_HOST_EMULATION: - dev->interface = CROS_EC_IF_SANDBOX; - break; -#endif - default: - debug("%s: Unknown compat id %d\n", __func__, compat); - return -1; - } - - gpio_request_by_name_nodev(blob, node, "ec-interrupt", 0, &dev->ec_int, - GPIOD_IS_IN); - dev->optimise_flash_write = fdtdec_get_bool(blob, node, - "optimise-flash-write"); - *devp = dev; - - return 0; -} -#endif - -#ifdef CONFIG_DM_CROS_EC int cros_ec_register(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); @@ -1125,94 +990,6 @@ int cros_ec_register(struct udevice *dev)
return 0; } -#else -int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) -{ - struct cros_ec_dev *dev; - char id[MSG_BYTES]; -#ifdef CONFIG_DM_CROS_EC - struct udevice *udev; - int ret; - - ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev); - if (!ret) - device_remove(udev); - ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); - if (ret) - return ret; - dev = dev_get_uclass_priv(udev); - return 0; -#else - int node = 0; - - *cros_ecp = NULL; - do { - node = fdtdec_next_compatible(blob, node, - COMPAT_GOOGLE_CROS_EC); - if (node < 0) { - debug("%s: Node not found\n", __func__); - return 0; - } - } while (!fdtdec_get_is_enabled(blob, node)); - - if (cros_ec_decode_fdt(blob, node, &dev)) { - debug("%s: Failed to decode device.\n", __func__); - return -CROS_EC_ERR_FDT_DECODE; - } - - switch (dev->interface) { -#ifdef CONFIG_CROS_EC_SPI - case CROS_EC_IF_SPI: - if (cros_ec_spi_init(dev, blob)) { - debug("%s: Could not setup SPI interface\n", __func__); - return -CROS_EC_ERR_DEV_INIT; - } - break; -#endif -#ifdef CONFIG_CROS_EC_I2C - case CROS_EC_IF_I2C: - if (cros_ec_i2c_init(dev, blob)) - return -CROS_EC_ERR_DEV_INIT; - break; -#endif -#ifdef CONFIG_CROS_EC_LPC - case CROS_EC_IF_LPC: - if (cros_ec_lpc_init(dev, blob)) - return -CROS_EC_ERR_DEV_INIT; - break; -#endif -#ifdef CONFIG_CROS_EC_SANDBOX - case CROS_EC_IF_SANDBOX: - if (cros_ec_sandbox_init(dev, blob)) - return -CROS_EC_ERR_DEV_INIT; - break; -#endif - case CROS_EC_IF_NONE: - default: - return 0; - } -#endif - - if (cros_ec_check_version(dev)) { - debug("%s: Could not detect CROS-EC version\n", __func__); - return -CROS_EC_ERR_CHECK_VERSION; - } - - if (cros_ec_read_id(dev, id, sizeof(id))) { - debug("%s: Could not read KBC ID\n", __func__); - return -CROS_EC_ERR_READ_ID; - } - - /* Remember this device for use by the cros_ec command */ - *cros_ecp = dev; -#ifndef CONFIG_DM_CROS_EC - last_dev = dev; -#endif - debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id); - - return 0; -} -#endif
int cros_ec_decode_region(int argc, char * const argv[]) { @@ -1595,9 +1372,7 @@ static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag, static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct cros_ec_dev *dev; -#ifdef CONFIG_DM_CROS_EC struct udevice *udev; -#endif const char *cmd; int ret = 0;
@@ -1606,15 +1381,11 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = argv[1]; if (0 == strcmp("init", cmd)) { -#ifdef CONFIG_DM_CROS_EC /* Remove any existing device */ ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev); if (!ret) device_remove(udev); ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); -#else - ret = cros_ec_init(gd->fdt_blob, &dev); -#endif if (ret) { printf("Could not init cros_ec device (err %d)\n", ret); return 1; @@ -1622,21 +1393,12 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
-#ifdef CONFIG_DM_CROS_EC ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); if (ret) { printf("Cannot get cros-ec device (err=%d)\n", ret); return 1; } dev = dev_get_uclass_priv(udev); -#else - /* Just use the last allocated device; there should be only one */ - if (!last_dev) { - printf("No CROS-EC device available\n"); - return 1; - } - dev = last_dev; -#endif if (0 == strcmp("id", cmd)) { char id[MSG_BYTES];
@@ -1894,10 +1656,8 @@ U_BOOT_CMD( ); #endif
-#ifdef CONFIG_DM_CROS_EC UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros_ec", .per_device_auto_alloc_size = sizeof(struct cros_ec_dev), }; -#endif diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 282d8d8..fa7d669 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -467,17 +467,10 @@ static int process_cmd(struct ec_state *ec, return len; }
-#ifdef CONFIG_DM_CROS_EC int cros_ec_sandbox_packet(struct udevice *udev, int out_bytes, int in_bytes) { struct cros_ec_dev *dev = dev_get_uclass_priv(udev); struct ec_state *ec = dev_get_priv(dev->dev); -#else -int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, - int in_bytes) -{ - struct ec_state *ec = &s_state; -#endif struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout; const void *req_data = req_hdr + 1; struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din; @@ -500,18 +493,9 @@ int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, return in_bytes; }
-int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob) -{ - return 0; -} - void cros_ec_check_keyboard(struct cros_ec_dev *dev) { -#ifdef CONFIG_DM_CROS_EC struct ec_state *ec = dev_get_priv(dev->dev); -#else - struct ec_state *ec = &s_state; -#endif ulong start;
printf("Press keys for EC to detect on reset (ESC=recovery)..."); @@ -525,7 +509,6 @@ void cros_ec_check_keyboard(struct cros_ec_dev *dev) } }
-#ifdef CONFIG_DM_CROS_EC int cros_ec_probe(struct udevice *dev) { struct ec_state *ec = dev->priv; @@ -569,61 +552,6 @@ int cros_ec_probe(struct udevice *dev) return cros_ec_register(dev); }
-#else - -/** - * Initialize sandbox EC emulation. - * - * @param dev CROS_EC device - * @param blob Device tree blob - * @return 0 if ok, -1 on error - */ -int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob) -{ - struct ec_state *ec = &s_state; - int node; - int err; - - node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC); - if (node < 0) { - debug("Failed to find chrome-ec node'\n"); - return -1; - } - - err = cros_ec_decode_ec_flash(blob, node, &ec->ec_config); - if (err) - return err; - - node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB); - if (node < 0) { - debug("%s: No cros_ec keyboard found\n", __func__); - } else if (keyscan_read_fdt_matrix(ec, blob, node)) { - debug("%s: Could not read key matrix\n", __func__); - return -1; - } - - /* If we loaded EC data, check that the length matches */ - if (ec->flash_data && - ec->flash_data_len != ec->ec_config.flash.length) { - printf("EC data length is %x, expected %x, discarding data\n", - ec->flash_data_len, ec->ec_config.flash.length); - os_free(ec->flash_data); - ec->flash_data = NULL; - } - - /* Otherwise allocate the memory */ - if (!ec->flash_data) { - ec->flash_data_len = ec->ec_config.flash.length; - ec->flash_data = os_malloc(ec->flash_data_len); - if (!ec->flash_data) - return -ENOMEM; - } - - return 0; -} -#endif - -#ifdef CONFIG_DM_CROS_EC struct dm_cros_ec_ops cros_ec_ops = { .packet = cros_ec_sandbox_packet, }; @@ -641,4 +569,3 @@ U_BOOT_DRIVER(cros_ec_sandbox) = { .priv_auto_alloc_size = sizeof(struct ec_state), .ops = &cros_ec_ops, }; -#endif diff --git a/include/configs/snow.h b/include/configs/snow.h index ce6676e..7eaa586 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -22,7 +22,6 @@
#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C -#define CONFIG_DM_CROS_EC
#define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R diff --git a/include/cros_ec.h b/include/cros_ec.h index 8457c80..850c09e 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -15,31 +15,9 @@ #include <cros_ec_message.h> #include <asm/gpio.h>
-#ifndef CONFIG_DM_CROS_EC -/* Which interface is the device on? */ -enum cros_ec_interface_t { - CROS_EC_IF_NONE, - CROS_EC_IF_SPI, - CROS_EC_IF_I2C, - CROS_EC_IF_LPC, /* Intel Low Pin Count interface */ - CROS_EC_IF_SANDBOX, -}; -#endif - /* Our configuration information */ struct cros_ec_dev { -#ifdef CONFIG_DM_CROS_EC struct udevice *dev; /* Transport device */ -#else - enum cros_ec_interface_t interface; - struct spi_slave *spi; /* Our SPI slave, if using SPI */ - int node; /* Our node */ - int parent_node; /* Our parent node (interface) */ - unsigned int cs; /* Our chip select */ - unsigned int addr; /* Device address (for I2C) */ - unsigned int bus_num; /* Bus number (for I2C) */ - unsigned int max_frequency; /* Maximum interface frequency */ -#endif struct gpio_desc ec_int; /* GPIO used as EC interrupt line */ int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ @@ -240,8 +218,6 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, */ struct cros_ec_dev *board_get_cros_ec_dev(void);
-#ifdef CONFIG_DM_CROS_EC - struct dm_cros_ec_ops { int (*check_version)(struct udevice *dev); int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version, @@ -255,112 +231,6 @@ struct dm_cros_ec_ops {
int cros_ec_register(struct udevice *dev);
-#else /* !CONFIG_DM_CROS_EC */ - -/* Internal interfaces */ -int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the i2c cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the spi cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the sandbox cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Check whether the LPC interface supports new-style commands. - * - * LPC has its own way of doing this, which involves checking LPC values - * visible to the host. Do this, and update dev->protocol_version accordingly. - * - * @param dev CROS-EC device to check - */ -int cros_ec_lpc_check_version(struct cros_ec_dev *dev); - -/** - * Send a command to an I2C CROS-EC device and return the reply. - * - * This rather complicated function deals with sending both old-style and - * new-style commands. The old ones have just a command byte and arguments. - * The new ones have version, command, arg-len, [args], chksum so are 3 bytes - * longer. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS-EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Returns pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -/** - * Send a command to a LPC CROS-EC device and return the reply. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS-EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Returns pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -/** - * Send a packet to a CROS-EC device and return the response packet. - * - * Expects the request packet to be stored in dev->dout. Stores the response - * packet in dev->din. - * - * @param dev CROS-EC device - * @param out_bytes Size of request packet to output - * @param in_bytes Maximum size of response packet to receive - * @return number of bytes in response packet, or <0 on error - */ -int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); -int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, - int in_bytes); -#endif - /** * Dump a block of data for a command. *
Since driver model will probe the EC when it is first used, we do not need to init it explicitly.
Signed-off-by: Simon Glass sjg@chromium.org ---
board/sandbox/sandbox.c | 12 ------------ include/configs/sandbox.h | 1 - 2 files changed, 13 deletions(-)
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index e4d4e02..2227f1c 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -53,18 +53,6 @@ int board_early_init_f(void) } #endif
-int arch_early_init_r(void) -{ -#ifdef CONFIG_CROS_EC - if (cros_ec_board_init()) { - printf("%s: Failed to init EC\n", __func__); - return 0; - } -#endif - - return 0; -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 6a4b701..e0e2d72 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -148,7 +148,6 @@ #define CONFIG_CROS_EC #define CONFIG_CMD_CROS_EC #define CONFIG_CROS_EC_SANDBOX -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT
#define CONFIG_SOUND
Since driver model will probe the EC when it is first used, we do not need to init it explicitly.
Signed-off-by: Simon Glass sjg@chromium.org ---
board/coreboot/coreboot/coreboot.c | 5 ----- board/google/chromebook_link/link.c | 3 --- 2 files changed, 8 deletions(-)
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index e076ea6..7110f35 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -10,11 +10,6 @@
int arch_early_init_r(void) { -#ifdef CONFIG_CROS_EC - if (cros_ec_board_init()) - return -1; -#endif - return 0; }
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 5158e3b..4b74479 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -22,9 +22,6 @@ int arch_early_init_r(void) if (ret) return ret;
- if (cros_ec_board_init()) - return -1; - return 0; }
Since driver model will probe the EC when it is first used, we do not need to init it explicitly.
Signed-off-by: Simon Glass sjg@chromium.org ---
board/samsung/common/board.c | 12 ------------ include/configs/exynos5420-common.h | 2 -- include/configs/snow.h | 1 - 3 files changed, 15 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index da2245f..593548c 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -323,18 +323,6 @@ int board_late_init(void) } #endif
-int arch_early_init_r(void) -{ -#ifdef CONFIG_CROS_EC - if (cros_ec_board_init()) { - printf("%s: Failed to init EC\n", __func__); - return 0; - } -#endif - - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index fe72bd0..3f15e73 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -15,8 +15,6 @@
#include <configs/exynos5-common.h>
-#define CONFIG_ARCH_EARLY_INIT_R - #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
diff --git a/include/configs/snow.h b/include/configs/snow.h index 7eaa586..fea7157 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -24,7 +24,6 @@ #define CONFIG_POWER_TPS65090_I2C
#define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS
Now that driver model handles cros_ec init, we can drop this special code.
Signed-off-by: Simon Glass sjg@chromium.org ---
common/cros_ec.c | 5 ----- include/cros_ec.h | 7 ------- 2 files changed, 12 deletions(-)
diff --git a/common/cros_ec.c b/common/cros_ec.c index f9c74ca..7a4f785 100644 --- a/common/cros_ec.c +++ b/common/cros_ec.c @@ -28,11 +28,6 @@ struct cros_ec_dev *board_get_cros_ec_dev(void) return dev_get_uclass_priv(dev); }
-int cros_ec_board_init(void) -{ - return 0; -} - int cros_ec_get_error(void) { struct udevice *dev; diff --git a/include/cros_ec.h b/include/cros_ec.h index 850c09e..3b2be2c 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -363,13 +363,6 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state); int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state);
/** - * Initialize the Chrome OS EC at board initialization time. - * - * @return 0 if ok, -ve on error - */ -int cros_ec_board_init(void); - -/** * Get access to the error reported when cros_ec_board_init() was called * * This permits delayed reporting of the EC error if it failed during
This is not needed now that we have moved to driver model.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 665d1ef..51a9471 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -134,7 +134,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */ COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ COMPAT_SAMSUNG_EXYNOS5_XHCI, /* Exynos5 XHCI controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 15663da..bfcf7f9 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -42,7 +42,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"), COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"), - COMPAT(GOOGLE_CROS_EC, "google,cros-ec"), COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"), COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), COMPAT(SAMSUNG_EXYNOS5_XHCI, "samsung,exynos5250-xhci"),
This is not needed now that we have moved chromebook_link and cros_ec to driver model.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 51a9471..2732e97 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -158,7 +158,6 @@ enum fdt_compat_id { COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ - COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index bfcf7f9..5f51403 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,7 +66,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), - COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"), COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(MEMORY_SPD, "memory-spd"), COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
The U-Boot device trees are slightly different in a few places. Adjust them to remove most of the differences. Note that U-Boot does not support the concept of interrupts as distinct from GPIOs, so this difference remains.
For sandbox, use the same keyboard file as for ARM boards and drop the host emulation bus which seems redundant.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/dts/exynos5250-snow.dts | 7 +- arch/arm/dts/exynos5420-peach-pit.dts | 5 +- arch/arm/dts/exynos5800-peach-pi.dts | 4 +- arch/sandbox/dts/cros-ec-keyboard.dtsi | 105 ++++++++++++++++++++++++++++++ arch/sandbox/dts/sandbox.dts | 115 +++++++-------------------------- drivers/input/cros_ec_keyb.c | 2 +- drivers/misc/cros_ec_i2c.c | 4 +- drivers/misc/cros_ec_lpc.c | 4 +- drivers/misc/cros_ec_sandbox.c | 4 +- drivers/misc/cros_ec_spi.c | 4 +- include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 12 files changed, 146 insertions(+), 110 deletions(-) create mode 100644 arch/sandbox/dts/cros-ec-keyboard.dtsi
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 7d8be69..c71cea9 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -65,9 +65,10 @@ spi@131b0000 { spi-max-frequency = <1000000>; spi-deactivate-delay = <100>; - cros_ec: cros-ec@0 { - reg = <0>; - compatible = "google,cros-ec"; + + cros_ec: embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; spi-max-frequency = <5000000>; ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; optimise-flash-write; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index b801de9..4aaf4f6 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -102,12 +102,11 @@ spi@12d40000 { /* spi2 */ spi-max-frequency = <4000000>; spi-deactivate-delay = <200>; + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; reg = <0>; - compatible = "google,cros-ec"; - spi-half-duplex; spi-max-timeout-ms = <1100>; - spi-frame-header = <0xec>; ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/* diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100..b3b1233 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -97,11 +97,9 @@ spi-max-frequency = <4000000>; spi-deactivate-delay = <200>; cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; reg = <0>; - compatible = "google,cros-ec"; - spi-half-duplex; spi-max-timeout-ms = <1100>; - spi-frame-header = <0xec>; ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/* diff --git a/arch/sandbox/dts/cros-ec-keyboard.dtsi b/arch/sandbox/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000..9c7fb0a --- /dev/null +++ b/arch/sandbox/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/input/input.h> + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 42a1f21..b1c9576 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -36,36 +36,31 @@ sides = <6>; };
- host@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "sandbox,host-emulation"; - cros-ec@0 { - reg = <0>; - compatible = "google,cros-ec"; + cros_ec: cros-ec@0 { + reg = <0 0>; + compatible = "google,cros-ec-sandbox";
- /* - * This describes the flash memory within the EC. Note - * that the STM32L flash erases to 0, not 0xff. - */ + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; #address-cells = <1>; #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0>; - #address-cells = <1>; - #size-cells = <1>; - - /* Information for sandbox */ - ro { - reg = <0 0xf000>; - }; - wp-ro { - reg = <0xf000 0x1000>; - }; - rw { - reg = <0x10000 0x10000>; - }; + + /* Information for sandbox */ + ro { + reg = <0 0xf000>; + }; + wp-ro { + reg = <0xf000 0x1000>; + }; + rw { + reg = <0x10000 0x10000>; }; }; }; @@ -76,59 +71,6 @@ yres = <600>; };
- cros-ec-keyb { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,ghost-filter; - /* - * Keymap entries take the form of 0xRRCCKKKK where - * RR=Row CC=Column KKKK=Key Code - * The values below are for a US keyboard layout and - * are taken from the Linux driver. Note that the - * 102ND key is not used for US keyboards. - */ - linux,keymap = < - /* CAPSLCK F1 B F10 */ - 0x0001003a 0x0002003b 0x00030030 0x00040044 - /* N = R_ALT ESC */ - 0x00060031 0x0008000d 0x000a0064 0x01010001 - /* F4 G F7 H */ - 0x0102003e 0x01030022 0x01040041 0x01060023 - /* ' F9 BKSPACE L_CTRL */ - 0x01080028 0x01090043 0x010b000e 0x0200001d - /* TAB F3 T F6 */ - 0x0201000f 0x0202003d 0x02030014 0x02040040 - /* ] Y 102ND [ */ - 0x0205001b 0x02060015 0x02070056 0x0208001a - /* F8 GRAVE F2 5 */ - 0x02090042 0x03010029 0x0302003c 0x03030006 - /* F5 6 - \ */ - 0x0304003f 0x03060007 0x0308000c 0x030b002b - /* R_CTRL A D F */ - 0x04000061 0x0401001e 0x04020020 0x04030021 - /* S K J ; */ - 0x0404001f 0x04050025 0x04060024 0x04080027 - /* L ENTER Z C */ - 0x04090026 0x040b001c 0x0501002c 0x0502002e - /* V X , M */ - 0x0503002f 0x0504002d 0x05050033 0x05060032 - /* L_SHIFT / . SPACE */ - 0x0507002a 0x05080035 0x05090034 0x050B0039 - /* 1 3 4 2 */ - 0x06010002 0x06020004 0x06030005 0x06040003 - /* 8 7 0 9 */ - 0x06050009 0x06060008 0x0608000b 0x0609000a - /* L_ALT DOWN RIGHT Q */ - 0x060a0038 0x060b006c 0x060c006a 0x07010010 - /* E R W I */ - 0x07020012 0x07030013 0x07040011 0x07050017 - /* U R_SHIFT P O */ - 0x07060016 0x07070036 0x07080019 0x07090018 - /* UP LEFT */ - 0x070b0067 0x070c0069>; - }; - gpio_a: gpios@0 { gpio-controller; compatible = "sandbox,gpio"; @@ -168,7 +110,7 @@ reg = <0 0>; compatible = "sandbox,spi"; cs-gpios = <0>, <&gpio_a 0>; - flash@0 { + firmware_storage_spi: flash@0 { reg = <0>; compatible = "spansion,m25p16", "sandbox,spi-flash"; spi-max-frequency = <40000000>; @@ -176,15 +118,6 @@ }; };
- cros-ec@0 { - compatible = "google,cros-ec"; - #address-cells = <1>; - #size-cells = <1>; - firmware_storage_spi: flash@0 { - reg = <0 0x400000>; - }; - }; - pci: pci-controller { compatible = "sandbox,pci"; device_type = "pci"; @@ -202,3 +135,5 @@ };
}; + +#include "cros-ec-keyboard.dtsi" diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index 49ee7b2..a31aa77 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -198,7 +198,7 @@ static int cros_ec_keyb_decode_fdt(const void *blob, int node, return -1; } config->ghost_filter = fdtdec_get_bool(blob, node, - "google,ghost-filter"); + "google,needs-ghost-filter"); return 0; }
diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c index cee9a0f..3de18b2 100644 --- a/drivers/misc/cros_ec_i2c.c +++ b/drivers/misc/cros_ec_i2c.c @@ -139,12 +139,12 @@ static struct dm_cros_ec_ops cros_ec_ops = { };
static const struct udevice_id cros_ec_ids[] = { - { .compatible = "google,cros-ec" }, + { .compatible = "google,cros-ec-i2c" }, { } };
U_BOOT_DRIVER(cros_ec_i2c) = { - .name = "cros_ec", + .name = "cros_ec_i2c", .id = UCLASS_CROS_EC, .of_match = cros_ec_ids, .probe = cros_ec_probe, diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index ef6e682..7837841 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -206,12 +206,12 @@ static struct dm_cros_ec_ops cros_ec_ops = { };
static const struct udevice_id cros_ec_ids[] = { - { .compatible = "google,cros-ec" }, + { .compatible = "google,cros-ec-lpc" }, { } };
U_BOOT_DRIVER(cros_ec_lpc) = { - .name = "cros_ec", + .name = "cros_ec_lpc", .id = UCLASS_CROS_EC, .of_match = cros_ec_ids, .probe = cros_ec_probe, diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index fa7d669..df41e82 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -557,12 +557,12 @@ struct dm_cros_ec_ops cros_ec_ops = { };
static const struct udevice_id cros_ec_ids[] = { - { .compatible = "google,cros-ec" }, + { .compatible = "google,cros-ec-sandbox" }, { } };
U_BOOT_DRIVER(cros_ec_sandbox) = { - .name = "cros_ec", + .name = "cros_ec_sandbox", .id = UCLASS_CROS_EC, .of_match = cros_ec_ids, .probe = cros_ec_probe, diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 98e8f60..ac2ee86 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -165,12 +165,12 @@ static struct dm_cros_ec_ops cros_ec_ops = { };
static const struct udevice_id cros_ec_ids[] = { - { .compatible = "google,cros-ec" }, + { .compatible = "google,cros-ec-spi" }, { } };
U_BOOT_DRIVER(cros_ec_spi) = { - .name = "cros_ec", + .name = "cros_ec_spi", .id = UCLASS_CROS_EC, .of_match = cros_ec_ids, .probe = cros_ec_probe, diff --git a/include/fdtdec.h b/include/fdtdec.h index 2732e97..8119eaa 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -152,7 +152,6 @@ enum fdt_compat_id { COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */ COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ - COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5f51403..6820654 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -60,7 +60,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"), COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"), COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), - COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"), COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), COMPAT(TI_TPS65090, "ti,tps65090"), COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
This code appears to be missing a piece that is needed on some keyboards to enable the keyboard. Add this in.
This makes the keyboard work correctly on chromebook_link.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/input/i8042.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index ca1604c..1769c5e 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -698,7 +698,14 @@ static int kbd_reset(void)
/* Enable Keyboard */ out8(I8042_COMMAND_REG, 0xae); + if (kbd_input_empty() == 0) + return -1; + + out8(I8042_COMMAND_REG, 0x60); + if (kbd_input_empty() == 0) + return -1;
+ out8(I8042_DATA_REG, 0xf4); if (kbd_input_empty() == 0) return -1;
participants (1)
-
Simon Glass