I'm trying to configure L2 cache in MPC8540 as SRAM. I'm using the following code to do this.

volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; volatile ccsr_dma_t *dma = &immap->im_dma; int i;

asm("mbar;isync"); l2cache->l2ctl = 0x68010000; asm("mbar"); l2cache->l2srbar0 = CFG_L2_SRAM_BASE; asm("mbar;isync"); l2cache->l2ctl = 0xa8010000; asm("mbar");

/* Use DMA to fill memory-mapped SRAM */ dma->satr0 = 0x00040000; dma->sar0 = 0; dma->datr0 = 0x00050000; dma->bcr0 = CFG_L2_SRAM_SIZE; dma->mr0 = 0x0f009404; dma->dar0 = CFG_L2_SRAM_BASE; udelay(1000);

I've added TLB entries for SRAM address range in init.S file.

After this I'm trying to write to SRAM. But while running from BDI2000 I'm able to write to this SRAM. (i.e) when I execute 'go 0xffffffc' in the BDI prompt I'm able to write and read to SRAM. While booting the board without BDI, U-boot hangs while SRAM is being accessed. Any ideas? Here is part of my BDI configuration file.

[INIT] ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL (256k) WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 (256k) WM32 0xFF720000 0xA8010000 ;L2CTL (256k) ; ; Clear L2SRAM with DMA WM32 0xff721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop WM32 0xff721114 0xff700004 ;SAR0 Dummy source register WM32 0xff721118 0x00050000 ;DATR0 DWRITETTTYPE=Write, snoop local processor WM32 0xff721120 0x00040000 ;BCR0 Size WM32 0xff721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 WM32 0xff72111c 0xfffc0000 ;DAR0 which sets CS=1 DELAY 200 ;let DMA complete WM32 0xff721100 0x00000000 ;MR0 reset condition ; ; load and execute boot code (needed if STARTUP HALT) WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc 1000 ; WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; EXEC 0xfffff000

[TARGET] CPUTYPE 8540 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 4000 ;let boot code setup the system ;STARTUP LOOP ;use boot loop in L2SRAM STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWPB uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses SIO 7 115200

-Selva