[PATCH 01/17] global: Move remaining CONFIG_SYS_NOR_* to CFG_SYS_NOR_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- board/freescale/ls1043aqds/ls1043aqds.c | 48 +++++++------- board/freescale/ls1043ardb/ls1043ardb.c | 32 +++++----- board/freescale/ls1046aqds/ls1046aqds.c | 48 +++++++------- board/freescale/ls1088a/ls1088a.c | 26 ++++---- include/configs/P1010RDB.h | 42 ++++++------- include/configs/T102xRDB.h | 38 +++++------ include/configs/T104xRDB.h | 48 +++++++------- include/configs/T208xQDS.h | 60 +++++++++--------- include/configs/T208xRDB.h | 36 +++++------ include/configs/T4240RDB.h | 48 +++++++------- include/configs/km/pg-wcom-ls102xa.h | 24 +++---- include/configs/kmcent2.h | 34 +++++----- include/configs/ls1021aqds.h | 60 +++++++++--------- include/configs/ls1021atwr.h | 24 +++---- include/configs/ls1043aqds.h | 84 ++++++++++++------------- include/configs/ls1043ardb.h | 64 +++++++++---------- include/configs/ls1046aqds.h | 84 ++++++++++++------------- include/configs/ls1088aqds.h | 66 +++++++++---------- include/configs/ls1088ardb.h | 26 ++++---- include/configs/ls2080aqds.h | 66 +++++++++---------- include/configs/ls2080ardb.h | 38 +++++------ 21 files changed, 498 insertions(+), 498 deletions(-)
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 481d3a5d9bd9..5fe40c4bdb25 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -59,13 +59,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 },
}, @@ -73,13 +73,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { @@ -128,26 +128,26 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 7f3212819885..a8a7263a6538 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -33,15 +33,15 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor", - CONFIG_SYS_NOR_CSPR, - CONFIG_SYS_NOR_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 },
}, @@ -89,15 +89,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor", - CONFIG_SYS_NOR_CSPR, - CONFIG_SYS_NOR_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index de6828673b50..97d71dbf2adb 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -43,13 +43,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 },
}, @@ -57,13 +57,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { @@ -112,26 +112,26 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index b70c198188bf..ff3abc830229 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -43,13 +43,13 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR_EARLY, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, 0, CONFIG_SYS_NOR0_CSPR, @@ -59,17 +59,17 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR_EARLY, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK_EARLY, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK_EARLY, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, 0, CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR_AMASK, + CFG_SYS_NOR_AMASK, }, { "nand", diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3288969ce8ca..154bf584f29f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -144,22 +144,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +#define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ +#define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -244,21 +244,21 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6eaa4144959d..978cc6714ec6 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -139,26 +139,26 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */ #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) #endif -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -247,21 +247,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a9e6cfad4bc1..f26e9d6e8692 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -100,12 +100,12 @@ #define CONFIG_SYS_FLASH_BASE 0xe8000000 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0xf) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* * TDM Definition @@ -113,18 +113,18 @@ #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -221,23 +221,23 @@ #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 47f499031e89..62f07108126d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -109,21 +109,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -211,37 +211,37 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 111f2e6245f9..0616f8a86dff 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -98,22 +98,22 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -187,21 +187,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b8232986be68..2eb4e73efa9e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -175,21 +175,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -242,21 +242,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK @@ -268,12 +268,12 @@ #endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
/* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index d883b188ce3a..cc8c37ec0bf5 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -41,25 +41,25 @@ CSPR_TE | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ CSOR_NOR_ADM_SHIFT(0x4) | \ CSOR_NOR_NOR_MODE_ASYNC_NOR | \ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TWPH(0x6) | \ FTIM2_NOR_TWP(0xb)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -69,12 +69,12 @@
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* NAND Flash Definitions */ #define CFG_SYS_NAND_BASE 0x68000000 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 51ee68655333..16fd6d562d41 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -193,38 +193,38 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0x0f) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD)
/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TWP(0xb) | \ FTIM2_NOR_TWPH(0x6)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* More NOR Flash params */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7d89b5389522..6b23134ecc99 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -44,21 +44,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_WRITE_SWAPPED_DATA @@ -166,20 +166,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -191,20 +191,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2c96b6f77895..1ac59a2d4597 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -74,23 +74,23 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) | \ FTIM2_NOR_TWPH(0x0e)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -126,12 +126,12 @@ #define CONFIG_SYS_FPGA_FTIM3 0x0 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 21263705c803..3b51cb8f174a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -54,21 +54,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} @@ -174,20 +174,20 @@ #ifdef CONFIG_TFABOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -216,20 +216,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -241,20 +241,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 51667f202580..76251fde57cc 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -18,29 +18,29 @@ /* * NOR Flash Definitions */ -#define CONFIG_SYS_NOR_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSPR \ +#define CFG_SYS_NOR_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V)
/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0xc)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ FTIM1_NOR_TRAD_NOR(0xb) | \ FTIM1_NOR_TSEQRAD_NOR(0x9)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_SYS_IFC_CCR 0x01000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } @@ -117,14 +117,14 @@
/* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR @@ -145,23 +145,23 @@ #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d51209c60f2d..d565492f1d1c 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -69,22 +69,22 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} @@ -190,20 +190,20 @@ #ifdef CONFIG_TFABOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -232,20 +232,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -257,20 +257,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index ae452075ac0d..b75d4ccf5cfd 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -23,8 +23,8 @@ */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -46,19 +46,19 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH @@ -158,22 +158,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -214,22 +214,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 2ca1384c2315..27510adae677 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -21,8 +21,8 @@
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
#define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -34,16 +34,16 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH @@ -153,12 +153,12 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index d9e11cc19179..7315790f1fe1 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -26,8 +26,8 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -49,18 +49,18 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH @@ -147,22 +147,22 @@ #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK @@ -178,22 +178,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 086c46902c86..daca3be16c51 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -33,8 +33,8 @@ #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -46,18 +46,18 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH @@ -140,12 +140,12 @@ #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK @@ -160,12 +160,12 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 2 +- drivers/serial/ns16550.c | 8 ++++---- drivers/serial/serial_ns16550.c | 4 ++-- include/configs/P1010RDB.h | 4 +--- include/configs/p1_p2_rdb_pc.h | 4 +--- scripts/config_whitelist.txt | 2 +- 6 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/README b/README index f5407576276c..f71832b689ed 100644 --- a/README +++ b/README @@ -1619,7 +1619,7 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state.
-- CONFIG_NS16550_MIN_FUNCTIONS: +- CONFIG_SPL_NS16550_MIN_FUNCTIONS: Define this if you desire to only have use of the NS16550_init and NS16550_putc functions for the serial driver located at drivers/serial/ns16550.c. This option is useful for saving diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 7592979cab5d..5a693d2f02ae 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -272,7 +272,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor) #endif }
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) { serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); @@ -281,7 +281,7 @@ void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); ns16550_setbrg(com_port, baud_divisor); } -#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
void ns16550_putc(struct ns16550 *com_port, char c) { @@ -299,7 +299,7 @@ void ns16550_putc(struct ns16550 *com_port, char c) schedule(); }
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) char ns16550_getc(struct ns16550 *com_port) { while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { @@ -317,7 +317,7 @@ int ns16550_tstc(struct ns16550 *com_port) return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; }
-#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
#ifdef CONFIG_DEBUG_UART_NS16550
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 97b6a4ff40d2..76aa1e5afb42 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -11,7 +11,7 @@ #include <asm/global_data.h> #include <linux/compiler.h>
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
DECLARE_GLOBAL_DATA_PTR;
@@ -251,4 +251,4 @@ void ns16550_serial_initialize(void) #endif }
-#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 154bf584f29f..9afd834f9faf 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -325,9 +325,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 38f360b53ca0..838c62c67111 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -322,9 +322,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 68f334847179..d96e5be1f76c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -186,7 +186,6 @@ CONFIG_NETMASK CONFIG_NEVER_ASSERT_ODT_TO_CPU CONFIG_NOBQFMAN CONFIG_NORBOOT -CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN CONFIG_OTHBOOTARGS @@ -278,6 +277,7 @@ CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET +CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
On Wed, 16 Nov 2022 at 11:10, Tom Rini trini@konsulko.com wrote:
This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig.
Signed-off-by: Tom Rini trini@konsulko.com
README | 2 +- drivers/serial/ns16550.c | 8 ++++---- drivers/serial/serial_ns16550.c | 4 ++-- include/configs/P1010RDB.h | 4 +--- include/configs/p1_p2_rdb_pc.h | 4 +--- scripts/config_whitelist.txt | 2 +- 6 files changed, 10 insertions(+), 14 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
Signed-off-by: Tom Rini trini@konsulko.com --- README | 7 --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 4 -- arch/arm/include/asm/arch-bcmnsp/configs.h | 3 -- configs/10m50_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/SBx81LIFKW_defconfig | 1 + configs/SBx81LIFXCAT_defconfig | 1 + configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/bcm7260_defconfig | 1 + configs/bcm7445_defconfig | 1 + configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/d2net_v2_defconfig | 1 + configs/dns325_defconfig | 1 + configs/dockstar_defconfig | 1 + configs/dreamplug_defconfig | 1 + configs/ds109_defconfig | 1 + configs/eaidk-610-rk3399_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/elgin-rv1108_defconfig | 1 + configs/evb-px30_defconfig | 1 + configs/evb-px5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3308_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/evb-rk3568_defconfig | 1 + configs/evb-rv1108_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-px30_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/geekbox_defconfig | 1 + configs/goflexhome_defconfig | 1 + configs/guruplug_defconfig | 1 + configs/hsdk_4xd_defconfig | 1 + configs/hsdk_defconfig | 1 + configs/ib62x0_defconfig | 1 + configs/iconnect_defconfig | 1 + configs/inetspace_v2_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mk808_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/nas220_defconfig | 1 + configs/net2big_v2_defconfig | 1 + configs/netspace_lite_v2_defconfig | 1 + configs/netspace_max_v2_defconfig | 1 + configs/netspace_mini_v2_defconfig | 1 + configs/netspace_v2_defconfig | 1 + configs/nsa310s_defconfig | 1 + configs/odroid-go2_defconfig | 1 + configs/openrd_base_defconfig | 1 + configs/openrd_client_defconfig | 1 + configs/openrd_ultimate_defconfig | 1 + configs/orangepi-rk3399_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pogo_e02_defconfig | 1 + configs/pogo_v4_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/px30-core-ctouch2-of10-px30_defconfig | 1 + configs/px30-core-ctouch2-px30_defconfig | 1 + configs/px30-core-edimm2.2-px30_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + configs/sheep-rk3368_defconfig | 1 + configs/sheevaplug_defconfig | 1 + configs/slimbootloader_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/xtfpga_defconfig | 1 + drivers/serial/Kconfig | 47 +++++++++++++++---- include/configs/10m50_devboard.h | 1 - include/configs/MPC837XERDB.h | 2 - include/configs/MPC8548CDS.h | 2 - include/configs/P1010RDB.h | 3 -- include/configs/P2041RDB.h | 2 - include/configs/SBx81LIFKW.h | 2 - include/configs/SBx81LIFXCAT.h | 2 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/T208xQDS.h | 2 - include/configs/T208xRDB.h | 2 - include/configs/T4240RDB.h | 2 - include/configs/am43xx_evm.h | 4 -- include/configs/ax25-ae350.h | 4 -- include/configs/axs10x.h | 2 - include/configs/bcmstb.h | 2 - include/configs/bur_am335x_common.h | 2 - include/configs/chromebook_coral.h | 3 -- include/configs/cm_t43.h | 4 -- include/configs/dfi-bt700.h | 1 - include/configs/galileo.h | 1 - .../configs/gardena-smart-gateway-mt7688.h | 2 - include/configs/hsdk-4xd.h | 2 - include/configs/hsdk.h | 2 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 - include/configs/legoev3.h | 1 - include/configs/linkit-smart-7688.h | 2 - include/configs/ls1012a_common.h | 2 - include/configs/ls1021aiot.h | 2 - include/configs/ls1021aqds.h | 4 -- include/configs/ls1021atsn.h | 4 -- include/configs/ls1021atwr.h | 4 -- include/configs/ls1028a_common.h | 2 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls1088a_common.h | 2 - include/configs/ls2080a_common.h | 2 - include/configs/malta.h | 1 - include/configs/mt7621.h | 2 - include/configs/mt7628.h | 2 - include/configs/mt8183.h | 3 -- include/configs/mt8516.h | 3 -- include/configs/mv-common.h | 2 - include/configs/nokia_rx51.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 -- include/configs/px30_common.h | 2 - include/configs/rk3308_common.h | 2 - include/configs/rockchip-common.h | 2 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 5 -- include/configs/socfpga_arria10_socdk.h | 1 - include/configs/socfpga_chameleonv3.h | 1 - include/configs/socfpga_soc64_common.h | 1 - include/configs/sunxi-common.h | 2 - include/configs/tb100.h | 1 - include/configs/theadorable-x86-dfi-bt700.h | 1 - include/configs/ti814x_evm.h | 2 - include/configs/ti816x_evm.h | 2 - include/configs/ti_am335x_common.h | 6 --- include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap3_common.h | 4 -- include/configs/ti_omap4_common.h | 2 - include/configs/ti_omap5_common.h | 4 -- include/configs/vocore2.h | 2 - include/configs/x530.h | 2 - include/configs/x86-common.h | 1 - include/configs/xtfpga.h | 2 - include/ns16550.h | 2 +- 226 files changed, 193 insertions(+), 172 deletions(-)
diff --git a/README b/README index f71832b689ed..9086207954ea 100644 --- a/README +++ b/README @@ -1619,13 +1619,6 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state.
-- CONFIG_SPL_NS16550_MIN_FUNCTIONS: - Define this if you desire to only have use of the NS16550_init - and NS16550_putc functions for the serial driver located at - drivers/serial/ns16550.c. This option is useful for saving - space for already greatly restricted images, including but not - limited to NAND_SPL configurations. - - CONFIG_DISPLAY_BOARDINFO Display information about the board that U-Boot is running on when U-Boot starts up. The board function checkboard() is called diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 327c0e06977b..0c7262352d53 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,10 +11,6 @@ /* uArchitecture specifics */
/* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_NS16550_CLK 100000000 #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 05fa9b9612d5..44699476b08b 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,9 +11,6 @@ /* uArchitecture specifics */
/* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - #define CONFIG_SYS_NS16550_CLK 0x03b9aca0 #define CONFIG_SYS_NS16550_COM1 0x18000300
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index dd88d10274c1..28966e0d0a41 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -47,5 +47,6 @@ CONFIG_PHY_GIGE=y CONFIG_ALTERA_TSE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_ALTERA_TIMER=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e15ca5ea2b5d..0690582cdfee 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -130,6 +130,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b3af4450d00f..785f2d86f189 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index a61f4d017a68..696cb7e77fbe 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -133,6 +133,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 7f7870d82c52..ee8c2bebd4b2 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -132,6 +132,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 3f93b318c92f..f2eb7ed737b7 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -143,6 +143,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f3fc4c82a54d..1f12338bc35d 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -142,6 +142,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index cc02fe6a8ac9..4682677471ad 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -145,6 +145,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 9162774ad70c..d917c5470b1b 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -148,6 +148,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1269d22f90c6..89d366c96a43 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -147,6 +147,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 73ef73c484ef..0df58f4419af 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -64,6 +64,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9fa0fda84f26..d68bccdf162d 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_FIXED=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a5436db7ac72..85a70c0996b2 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 7fbec63c58f1..00d43e24c5a5 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f43f4c0ee90..90a734fcdad0 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -59,6 +59,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 920e8828460e..25703cf67cea 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -41,4 +41,5 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_MTD=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 # CONFIG_EFI_LOADER is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index b44eabaa4251..9c64baaa19b3 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_BCMSTB_SPI=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 06987ab82860..321121e3f729 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 59ae29a80e02..2240988dd0db 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -94,6 +94,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3d2f40fb9554..d768e11db51e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 45905c6792b8..a38b3b78c08a 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -102,6 +102,7 @@ CONFIG_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index ffa8070cb39e..150dba140865 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -97,6 +97,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e8ec8855dda3..94d14d012da2 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -93,6 +93,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b645cba90709..570c4e82a473 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -79,6 +79,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 541b7fadead4..43cf53045b40 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_INTEL=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ca453ac8b9d0..08e1e5be415c 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -96,6 +96,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 27bf046f991a..aa3d6f2b9d19 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index e9222648758b..77735739b825 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -91,6 +91,7 @@ CONFIG_CROS_EC_LPC=y # CONFIG_SPL_PINCTRL is not set # CONFIG_TPL_PINCTRL is not set CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 92018fb78eef..d5aaee9dde17 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -95,6 +95,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b78e98c2045a..e83f2dfe7f39 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -59,6 +59,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 0d904675f73f..31979f32bc5f 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6fed3f2ecda9..18d58bec2010 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 20c0c1816968..e4da59bae927 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -61,6 +61,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index d8c5be66ad7b..e297494663e0 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -55,6 +55,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 094b21666e16..203eff8e165a 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -53,6 +53,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 4521172f42bf..cb0f0d7c8d02 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -57,6 +57,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SPI=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 5eea1ec9a724..e3e0accac5df 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 16a866f6b475..9d5fa0e247d4 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -60,6 +60,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 6c805f41568c..4f79942c378a 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -56,6 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 86fe0692a0a3..0339759d2d97 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -63,6 +63,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 93aef472b54d..b914808515c0 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -57,6 +57,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 5abdadf2d56f..c364c9ecc8df 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 83f532d6e543..8d1fc22eb93c 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 28aaff69e978..89e6d1febc8b 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 1f4ca01c50f8..36f57d58128b 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -48,6 +48,7 @@ CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 6bc777c51c16..bb6f21b2e634 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -101,6 +101,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index f41c7580b4c6..2e3bff8cf04e 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -78,6 +78,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 8ef40d847c77..289f47f4ae89 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index ce10750857ee..06a044b93496 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f8ca1f6597be..33202e48fe76 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 7c0b856ca567..8f8d34c7038f 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -81,6 +81,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 8502fcc51e62..0aeaf01d9a70 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9421845b0377..8a6d19a1769e 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -88,6 +88,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e7da9c4e5ff7..3050fd59922c 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index db3acf5be53f..7374ee42fb19 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -63,5 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 5de5de465cb0..aab322311162 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -42,6 +42,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index d48dcc1a0ece..3aee6b647136 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 1f91118426e7..2a6d2edbab02 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 63c53a0248f2..26967a67cc94 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index a37870628c65..547517253288 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 1d7832b9591c..c23d0549a4a2 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -27,5 +27,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 6fdb3ea68003..cc59e2c7762a 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -63,6 +63,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 794cf4b23d7a..482f76d99a9f 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -62,6 +62,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 8c6ad5a0d17d..bba406726850 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 9543c785bba9..4715f9d9d7d0 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 9290cb7af688..6a879f568500 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -60,6 +60,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index ce5a089d3270..c130d522d9c9 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -60,6 +60,7 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 42f812c31f0e..7dce414a1c58 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 25007793b3a0..96bcba6e94ff 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 6c8a284e7c70..0d1c97dd4b09 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 6182101f1197..bded09788026 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index fd169c3e957a..a851d8508221 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -70,6 +70,7 @@ CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index fec29f2c9119..b0069fd60b01 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index f6ac484f2e85..9ca26ae61f51 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 13d612ac3fb6..153abb7eb936 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -93,6 +93,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 59ec3a6346f3..2990a702d999 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -71,6 +71,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index dff052230846..754fd4e3c6d5 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 5a8b69c0f94a..7518f7f2edef 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index f54a610a2748..4c4301a9e7c5 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 1ad635daa985..646f0086c6e3 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -60,6 +60,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index a8326f03a23f..5a958ee36a3f 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 1ace7b795a09..ee401b763d90 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -97,6 +97,7 @@ CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 054c5e6d618e..b635c651aaea 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -45,3 +45,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 55f624bbeeb9..243213cb8197 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -47,3 +47,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 53762a94e2a3..ed41e298f443 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -44,3 +44,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 8b86d74dc41a..63e5fcb6a5ce 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -46,3 +46,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 66f3036313c4..52ed763424a8 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -65,6 +65,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0811e70dcefe..9346cafc64c6 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 403a84befdc3..7ba8338add5a 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -99,6 +99,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 03fa857996ce..8fad8c643f22 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 67ca98563b5f..c5f13c060be4 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index afa51bc8fa3b..b6a604b6943d 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index d02eb1851a7a..767befe2d2c9 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d2d9bf91c564..383ec1f39eee 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 82264de90889..40d3117b4f08 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -91,6 +91,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 2185f87d7d06..40a45a0f4bbe 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -52,6 +52,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 9cebc704ce98..e54809c781fc 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -64,6 +64,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index c10e1a501394..c294789440e0 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 75907e05c57f..f6748e12ea4e 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index db08ca576339..4525604b4390 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index dda3b6b5f93d..bf9bbd4e5e79 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 21534c59fde7..f505f4368ea7 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index afa0cad0418f..4c4a8aad566f 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 4705f61e4243..33adcc952cf0 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -104,6 +104,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index c2e879c9bde8..49617dae1a85 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -62,5 +62,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 01bfaed978b9..34a0fc3c3b1a 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -63,5 +63,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 7c641038178f..b1343cea590b 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -63,5 +63,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 39245e8784b2..0980d8156965 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8a274187d093..0632a928bc0a 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 528b7bb69f24..dfbf5e70f4a1 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -80,6 +80,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index d0071f3af521..e7e6e73d3ea2 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -56,6 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 3b08cb7b1d14..28fee390fd38 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -75,6 +75,7 @@ CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index f6c49da574c5..91123784b544 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2b0b39c7b2c..9a5be3e91390 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 9175c7c85ae1..9c36750bde03 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 0aa7cca7b8b6..db1ceaa31f37 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index d731b9687886..d2cca48304d3 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 8433b5734f62..0f4811e5d7a5 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f82f628d5bb7..a8222122fc9d 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 670211e2e9d7..0a029c4098f7 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 7f1259d82c1f..8172ed0ad228 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -95,6 +95,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 3cdcc729f853..6827c98ed9f1 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -71,6 +71,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e03442afa462..cf4a58de1c5a 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -68,6 +68,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83721cedf3dd..54a400405bec 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac9a3f983066..e74ba07e4467 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0c1ebf34025..0ffb073f3137 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -96,6 +96,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index fcb3a681ca00..2443f292469e 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -63,6 +63,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 4ed98c0a511d..18c6d1b92253 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -74,6 +74,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 38a5f3a80c0f..54d01456b1ef 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -77,6 +77,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e75011bee5f4..73a4f06eb9b1 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -92,6 +92,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 6ed5ef868e5e..f2c914f41f5d 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index bd6183ba5b8d..26638405bf73 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -63,6 +63,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index ba48d021f4fc..5b8d678f6bb5 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -79,6 +79,7 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 01f104a97d03..40cd91c045c1 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -29,5 +29,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 52f5aba8cab5..74b6e1a0ea77 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -66,6 +66,7 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index b6b9f88c00bb..f5d16f64d734 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -31,5 +31,6 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 68440926c078..9269eccf17ab 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index de9ebd072263..48fb06722323 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 7642498ea9ca..da4545effff8 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 08ae6c502b41..4e2dc0c9857e 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 478efc59ea91..00c4cf30089a 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -29,6 +29,7 @@ CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y CONFIG_MMC_DW=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 0feda3b04f75..4d856d535a3d 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -81,6 +81,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index fa19f555f20a..1056932cd35e 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 12e8ebf0138f..a6714b265e18 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 5ee9f5ff9da7..e0e6b2d04610 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index f689105695c1..919863270f83 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -80,6 +80,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 5d401e6c2d7e..5b724697123e 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -60,6 +60,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 22544c0913aa..440c170c6b1e 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 8741ecbb2d71..b91c3b135479 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 85d94a6ea89f..5976a84491e4 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 7dfbad808383..078f829c2dff 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index cbae60f98768..0c9d61b8053c 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 31483296802c..d4e8d7586353 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -46,5 +46,6 @@ CONFIG_SYS_MAX_FLASH_SECT=1027 CONFIG_PHYLIB=y CONFIG_ETHOC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SYSRESET=y CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index de02e08a2996..45a34495dfb9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -720,8 +720,12 @@ config PIC32_SERIAL help Support for the UART found on Microchip PIC32 SoC's.
+config SYS_NS16550_SERIAL + bool + config SYS_NS16550 bool "NS16550 UART or compatible" + select SYS_NS16550_SERIAL help Support NS16550 UART or compatible. This can be enabled in the device tree with the correct input clock frequency. If the input @@ -732,25 +736,52 @@ config SYS_NS16550
config NS16550_DYNAMIC bool "Allow NS16550 to be configured at runtime" + depends on SYS_NS16550 default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER help Enable this option to allow device-tree control of the driver.
Normally this driver is controlled by the following options:
- CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for - access. If not enabled, then the UART is memory-mapped. - CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit - access should be used (instead of 8-bit) - CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also - endianness. If positive, big-endian access is used. If negative, - little-endian is used. - It is not a good practice for a driver to be statically configured, since it prevents the same driver being used for different types of UARTs in a system. This option avoids this problem at the cost of a slightly increased code size.
+config SYS_NS16550_MEM32 + bool "If memory-mapped, 32bit access is needed for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, if memory-mapped, indicates that 32-bit access should be + used (instead of 8-bit) for register access. + +config SYS_NS16550_PORT_MAPPED + bool "Port I/O is used for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, port I/O is used for ns16550 register access. If not + enabled, then the UART is memory-mapped. + +config SYS_NS16550_REG_SIZE + int "ns16550 register width and endianness" + depends on SYS_NS16550 && (!DM_SERIAL || (SPL && !SPL_DM_SERIAL)) + range -4 4 + default -4 if ARCH_OMAP2PLUS || ARCH_SUNXI + default 1 + help + Indicates register width and also endianness. If positive, big-endian + access is used. If negative, little-endian is used. + +config SPL_NS16550_MIN_FUNCTIONS + bool "Only provide NS16550_init and NS16550_putc in SPL" + depends on SYS_NS16550 && PPC && SPL_SERIAL + help + Enable this if you desire to only have use of the NS16550_init and + NS16550_putc functions for the serial driver located at + drivers/serial/ns16550.c. This option is useful for saving space for + already greatly restricted images, including but not limited to + NAND_SPL configurations. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index afd7cc89bf8e..719caf7b0c3b 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -15,7 +15,6 @@ /* * SERIAL */ -#define CONFIG_SYS_NS16550_MEM32
/* * Flash diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c4cde1cc512e..b8cbdc36754b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,8 +151,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b241939fc387..dba15dae749b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,8 +235,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9afd834f9faf..fd721f30b3aa 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,10 +322,7 @@ extern unsigned long get_sdram_size(void);
/* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b9311fc5e4f9..173f6205e08f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,8 +163,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 9629d735a271..c99e6ba781a4 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 67e42b94c117..8b43fe0c9939 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 978cc6714ec6..7cb10b205db1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,8 +294,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f26e9d6e8692..3fa2d01dcc2a 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,8 +267,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 62f07108126d..c5a28fadb004 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,8 +269,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0616f8a86dff..795120c02a87 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,8 +229,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2eb4e73efa9e..e3cbc649fa19 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,8 +89,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a0951fbf6235..b61c8005c33f 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -15,10 +15,6 @@
/* NS16550 Configuration */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif
/* I2C Configuration */
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index cf5125fdfa63..7224bd8d1f49 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,10 +33,6 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_CLK 19660800
/* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index f2357b5785a1..c0429ae15c4c 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,9 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 5aa720da3d74..481baff11d9a 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,8 +97,6 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a6de28a42b2e..773ce3f6a6f8 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,6 @@
/* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000
diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index 0eeea80b32f4..d14c1d445b25 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -18,7 +18,4 @@ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0"
-#define CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 9061eba6686a..0641d5c0a238 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,12 +14,8 @@ #include <asm/arch/omap.h>
/* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif
/* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 4297047e8ce2..52f2d50118a4 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -14,7 +14,6 @@
#ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #endif
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 545408a4baa5..472f236b9b6e 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h>
/* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 965fa87c6577..0d61724db8c4 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,9 +20,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 4af845ea9c2d..bfc0fa5c442c 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,9 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ce65e7755ea..ce3cb20732db 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,9 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index cc8c37ec0bf5..7acdb0fa038e 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 16fd6d562d41..30ba6065253e 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,6 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f0ae9248af34..5434c4f7679f 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 9eedd47c07e5..b9c853d7dfef 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,9 +20,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00
#endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 77f84e1c9eaa..148598fab465 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,8 +26,6 @@
/* GPIO */
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 885774f63d47..3f2dfa640c9c 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,8 +47,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6b23134ecc99..bd2f74c1262a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,10 +227,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index fce91192dff7..8c43f652ab65 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,10 +60,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1ac59a2d4597..06830f401a31 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,10 +145,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 43dbeea1b3bd..7dd5649005b7 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,8 +28,6 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 47367845a07f..2fc06c1dd2dc 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 07ec2c956379..40b4cb964d11 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index dec661d6b194..5668e07d1354 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,8 +45,6 @@
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d8997208e973..895c566fea2f 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,8 +37,6 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* diff --git a/include/configs/malta.h b/include/configs/malta.h index 30c2e41eec53..2dd34ea7313c 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -33,7 +33,6 @@ /* * Serial driver */ -#define CONFIG_SYS_NS16550_PORT_MAPPED
/* * Flash configuration diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 9b1ba3655e82..1f733d112dd7 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,9 +22,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xbe000c00 #endif
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 43527017d84a..da16e3b21a4b 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,9 +14,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif
diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1a6..eaffe0bf4c95 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,9 +12,6 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e42884..347598868bb5 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,9 +12,6 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4fff3820c1..4f1067c23bbc 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,10 +32,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index a88cfe77d50c..6f16e336d146 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,7 +40,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 838c62c67111..065820689caf 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,10 +319,7 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebdd7..8b151ef18836 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,8 +8,6 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_NS16550_MEM32 - /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 200b34b35bae..263d1bd180c5 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,8 +8,6 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 4c964cc37708..1f6b82f2d022 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -7,8 +7,6 @@ #define _ROCKCHIP_COMMON_H_ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_MEM32 - /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */
#ifndef CONFIG_SPL_BUILD diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index d071f590f106..5765f2ccb5e7 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_SYS_NS16550_COM4 0x481a6000 diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 0187fca5f0d9..c29bc448eed6 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,11 +52,6 @@ * Serial */
-#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c86..49883ea7a3cc 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/* diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 75d2081fac88..7012097276c7 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 86cc3771ba59..029f898b64ff 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -76,7 +76,6 @@ * Serial / UART configurations */ #define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32
/* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d9e4c8b699f4..1ed0a262bc61 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -16,7 +16,6 @@ #include <linux/stringify.h>
/* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ @@ -25,7 +24,6 @@ #define CONFIG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 16bdc39b750e..38a43b726f03 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,6 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666
/* diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h index bb3186e21921..663a49e7b6c5 100644 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ b/include/configs/theadorable-x86-dfi-bt700.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h>
/* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED
/* Set the board specific parameters */ #define DEF_ENV_TFTPDIR "theadorable-x86-dfi" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 97166e010f7d..60632c58c67d 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index efd3a0db04eb..f2dbe3544a5d 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5d5df6b10191..fb017771688e 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,12 +17,6 @@ #include <asm/arch/omap.h>
/* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif #define CONFIG_SYS_NS16550_CLK 48000000
/* diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index a4a45fad9dc8..aaeea77281b6 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,7 +34,6 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
/* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 6cc443c8e9cb..80d2a011f0fe 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,10 +27,6 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200}
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 0568946fc824..eb930341c3a8 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -29,8 +29,6 @@ */ #define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM3 UART3_BASE #endif
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 24bbf9e7c2c6..a1efb57f1b09 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -30,10 +30,6 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif
/* * Environment setup diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 6f36d6964b9b..84e5ba39f148 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00
/* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 0add626e81a5..318e3680a6e1 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,10 +13,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 8e22d6e5d876..f76c1f8be0fd 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,7 +21,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550_PORT_MAPPED
/* * Miscellaneous configurable options diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 58d01f4bb428..7090fcef6804 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,8 +127,6 @@ /* Serial Driver Info */ /*====================*/
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ diff --git a/include/ns16550.h b/include/ns16550.h index 3d9002d9f151..0ee5c4d6de75 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@
#include <linux/types.h>
-#ifdef CONFIG_DM_SERIAL +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver
On Wed, 16 Nov 2022 at 11:14, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
Signed-off-by: Tom Rini trini@konsulko.com
README | 7 --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 4 -- arch/arm/include/asm/arch-bcmnsp/configs.h | 3 -- configs/10m50_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/SBx81LIFKW_defconfig | 1 + configs/SBx81LIFXCAT_defconfig | 1 + configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/bcm7260_defconfig | 1 + configs/bcm7445_defconfig | 1 + configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/d2net_v2_defconfig | 1 + configs/dns325_defconfig | 1 + configs/dockstar_defconfig | 1 + configs/dreamplug_defconfig | 1 + configs/ds109_defconfig | 1 + configs/eaidk-610-rk3399_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/elgin-rv1108_defconfig | 1 + configs/evb-px30_defconfig | 1 + configs/evb-px5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3308_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/evb-rk3568_defconfig | 1 + configs/evb-rv1108_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-px30_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/geekbox_defconfig | 1 + configs/goflexhome_defconfig | 1 + configs/guruplug_defconfig | 1 + configs/hsdk_4xd_defconfig | 1 + configs/hsdk_defconfig | 1 + configs/ib62x0_defconfig | 1 + configs/iconnect_defconfig | 1 + configs/inetspace_v2_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mk808_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/nas220_defconfig | 1 + configs/net2big_v2_defconfig | 1 + configs/netspace_lite_v2_defconfig | 1 + configs/netspace_max_v2_defconfig | 1 + configs/netspace_mini_v2_defconfig | 1 + configs/netspace_v2_defconfig | 1 + configs/nsa310s_defconfig | 1 + configs/odroid-go2_defconfig | 1 + configs/openrd_base_defconfig | 1 + configs/openrd_client_defconfig | 1 + configs/openrd_ultimate_defconfig | 1 + configs/orangepi-rk3399_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pogo_e02_defconfig | 1 + configs/pogo_v4_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/px30-core-ctouch2-of10-px30_defconfig | 1 + configs/px30-core-ctouch2-px30_defconfig | 1 + configs/px30-core-edimm2.2-px30_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + configs/sheep-rk3368_defconfig | 1 + configs/sheevaplug_defconfig | 1 + configs/slimbootloader_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/xtfpga_defconfig | 1 + drivers/serial/Kconfig | 47 +++++++++++++++---- include/configs/10m50_devboard.h | 1 - include/configs/MPC837XERDB.h | 2 - include/configs/MPC8548CDS.h | 2 - include/configs/P1010RDB.h | 3 -- include/configs/P2041RDB.h | 2 - include/configs/SBx81LIFKW.h | 2 - include/configs/SBx81LIFXCAT.h | 2 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/T208xQDS.h | 2 - include/configs/T208xRDB.h | 2 - include/configs/T4240RDB.h | 2 - include/configs/am43xx_evm.h | 4 -- include/configs/ax25-ae350.h | 4 -- include/configs/axs10x.h | 2 - include/configs/bcmstb.h | 2 - include/configs/bur_am335x_common.h | 2 - include/configs/chromebook_coral.h | 3 -- include/configs/cm_t43.h | 4 -- include/configs/dfi-bt700.h | 1 - include/configs/galileo.h | 1 - .../configs/gardena-smart-gateway-mt7688.h | 2 - include/configs/hsdk-4xd.h | 2 - include/configs/hsdk.h | 2 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 - include/configs/legoev3.h | 1 - include/configs/linkit-smart-7688.h | 2 - include/configs/ls1012a_common.h | 2 - include/configs/ls1021aiot.h | 2 - include/configs/ls1021aqds.h | 4 -- include/configs/ls1021atsn.h | 4 -- include/configs/ls1021atwr.h | 4 -- include/configs/ls1028a_common.h | 2 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls1088a_common.h | 2 - include/configs/ls2080a_common.h | 2 - include/configs/malta.h | 1 - include/configs/mt7621.h | 2 - include/configs/mt7628.h | 2 - include/configs/mt8183.h | 3 -- include/configs/mt8516.h | 3 -- include/configs/mv-common.h | 2 - include/configs/nokia_rx51.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 -- include/configs/px30_common.h | 2 - include/configs/rk3308_common.h | 2 - include/configs/rockchip-common.h | 2 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 5 -- include/configs/socfpga_arria10_socdk.h | 1 - include/configs/socfpga_chameleonv3.h | 1 - include/configs/socfpga_soc64_common.h | 1 - include/configs/sunxi-common.h | 2 - include/configs/tb100.h | 1 - include/configs/theadorable-x86-dfi-bt700.h | 1 - include/configs/ti814x_evm.h | 2 - include/configs/ti816x_evm.h | 2 - include/configs/ti_am335x_common.h | 6 --- include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap3_common.h | 4 -- include/configs/ti_omap4_common.h | 2 - include/configs/ti_omap5_common.h | 4 -- include/configs/vocore2.h | 2 - include/configs/x530.h | 2 - include/configs/x86-common.h | 1 - include/configs/xtfpga.h | 2 - include/ns16550.h | 2 +- 226 files changed, 193 insertions(+), 172 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini trini@konsulko.com --- Changes in v2: - Rework the logic a log as this wasn't right the first time but the uncmd_spl logic "saved" the mistake. --- README | 7 --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 4 -- arch/arm/include/asm/arch-bcmnsp/configs.h | 3 -- configs/10m50_defconfig | 1 + configs/MPC837XERDB_defconfig | 2 +- configs/MPC8548CDS_36BIT_defconfig | 2 +- configs/MPC8548CDS_defconfig | 2 +- configs/MPC8548CDS_legacy_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_defconfig | 2 +- configs/P1020RDB-PC_NAND_defconfig | 3 +- configs/P1020RDB-PC_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_defconfig | 2 +- configs/P1020RDB-PD_NAND_defconfig | 3 +- configs/P1020RDB-PD_SDCARD_defconfig | 2 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 3 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/SBx81LIFKW_defconfig | 3 +- configs/SBx81LIFXCAT_defconfig | 3 +- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig | 2 +- configs/T1042D4RDB_SDCARD_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 2 +- configs/T1042D4RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T2080RDB_revD_NAND_defconfig | 2 +- configs/T2080RDB_revD_SDCARD_defconfig | 2 +- configs/T2080RDB_revD_SPIFLASH_defconfig | 2 +- configs/T2080RDB_revD_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 2 +- configs/T4240RDB_defconfig | 2 +- configs/am43xx_evm_qspiboot_defconfig | 2 +- configs/am43xx_hs_evm_qspi_defconfig | 2 +- configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/bcm7260_defconfig | 3 +- configs/bcm7445_defconfig | 3 +- configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/d2net_v2_defconfig | 3 +- configs/dns325_defconfig | 3 +- configs/dockstar_defconfig | 3 +- configs/dreamplug_defconfig | 3 +- configs/ds109_defconfig | 3 +- configs/eaidk-610-rk3399_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/elgin-rv1108_defconfig | 1 + configs/evb-px30_defconfig | 1 + configs/evb-px5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3308_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/evb-rk3568_defconfig | 1 + configs/evb-rv1108_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-px30_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/geekbox_defconfig | 1 + configs/goflexhome_defconfig | 3 +- configs/guruplug_defconfig | 3 +- configs/hsdk_4xd_defconfig | 1 + configs/hsdk_defconfig | 1 + configs/ib62x0_defconfig | 3 +- configs/iconnect_defconfig | 3 +- configs/inetspace_v2_defconfig | 3 +- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/ls1012a2g5rdb_qspi_defconfig | 2 +- configs/ls1012a2g5rdb_tfa_defconfig | 2 +- configs/ls1012afrdm_qspi_defconfig | 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_qspi_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_defconfig | 2 +- configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 2 +- configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_qspi_spl_defconfig | 2 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_defconfig | 2 +- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080aqds_sdcard_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_defconfig | 2 +- configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mk808_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/nas220_defconfig | 3 +- configs/net2big_v2_defconfig | 3 +- configs/netspace_lite_v2_defconfig | 3 +- configs/netspace_max_v2_defconfig | 3 +- configs/netspace_mini_v2_defconfig | 3 +- configs/netspace_v2_defconfig | 3 +- configs/nsa310s_defconfig | 3 +- configs/odroid-go2_defconfig | 1 + configs/omap4_panda_defconfig | 2 +- configs/omap4_sdp4430_defconfig | 2 +- configs/omap5_uevm_defconfig | 2 +- configs/openrd_base_defconfig | 3 +- configs/openrd_client_defconfig | 3 +- configs/openrd_ultimate_defconfig | 3 +- configs/orangepi-rk3399_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pogo_e02_defconfig | 3 +- configs/pogo_v4_defconfig | 3 +- configs/popmetal-rk3288_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/px30-core-ctouch2-of10-px30_defconfig | 1 + configs/px30-core-ctouch2-px30_defconfig | 1 + configs/px30-core-edimm2.2-px30_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + configs/sheep-rk3368_defconfig | 1 + configs/sheevaplug_defconfig | 3 +- configs/slimbootloader_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + configs/ten64_tfa_defconfig | 2 +- ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/ti816x_evm_defconfig | 2 +- configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/xtfpga_defconfig | 3 +- drivers/serial/Kconfig | 54 ++++++++++++++++--- drivers/serial/Makefile | 2 +- include/configs/10m50_devboard.h | 1 - include/configs/MPC837XERDB.h | 2 - include/configs/MPC8548CDS.h | 2 - include/configs/P1010RDB.h | 3 -- include/configs/P2041RDB.h | 2 - include/configs/SBx81LIFKW.h | 2 - include/configs/SBx81LIFXCAT.h | 2 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/T208xQDS.h | 2 - include/configs/T208xRDB.h | 2 - include/configs/T4240RDB.h | 2 - include/configs/am43xx_evm.h | 4 -- include/configs/ax25-ae350.h | 4 -- include/configs/axs10x.h | 2 - include/configs/bcmstb.h | 2 - include/configs/bur_am335x_common.h | 2 - include/configs/chromebook_coral.h | 3 -- include/configs/cm_t43.h | 4 -- include/configs/dfi-bt700.h | 1 - include/configs/galileo.h | 1 - .../configs/gardena-smart-gateway-mt7688.h | 2 - include/configs/hsdk-4xd.h | 2 - include/configs/hsdk.h | 2 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 - include/configs/legoev3.h | 1 - include/configs/linkit-smart-7688.h | 2 - include/configs/ls1012a_common.h | 2 - include/configs/ls1021aiot.h | 2 - include/configs/ls1021aqds.h | 4 -- include/configs/ls1021atsn.h | 4 -- include/configs/ls1021atwr.h | 4 -- include/configs/ls1028a_common.h | 2 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls1088a_common.h | 2 - include/configs/ls2080a_common.h | 2 - include/configs/malta.h | 1 - include/configs/mt7621.h | 2 - include/configs/mt7628.h | 2 - include/configs/mt8183.h | 3 -- include/configs/mt8516.h | 3 -- include/configs/mv-common.h | 2 - include/configs/nokia_rx51.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 -- include/configs/px30_common.h | 2 - include/configs/rk3308_common.h | 2 - include/configs/rockchip-common.h | 2 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 5 -- include/configs/socfpga_arria10_socdk.h | 1 - include/configs/socfpga_chameleonv3.h | 1 - include/configs/socfpga_soc64_common.h | 1 - include/configs/sunxi-common.h | 2 - include/configs/tb100.h | 1 - include/configs/theadorable-x86-dfi-bt700.h | 1 - include/configs/ti814x_evm.h | 2 - include/configs/ti816x_evm.h | 2 - include/configs/ti_am335x_common.h | 6 --- include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap3_common.h | 4 -- include/configs/ti_omap4_common.h | 2 - include/configs/ti_omap5_common.h | 4 -- include/configs/vocore2.h | 2 - include/configs/x530.h | 2 - include/configs/x86-common.h | 1 - include/configs/xtfpga.h | 2 - include/ns16550.h | 2 +- 386 files changed, 397 insertions(+), 369 deletions(-)
diff --git a/README b/README index f71832b689ed..9086207954ea 100644 --- a/README +++ b/README @@ -1619,13 +1619,6 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state.
-- CONFIG_SPL_NS16550_MIN_FUNCTIONS: - Define this if you desire to only have use of the NS16550_init - and NS16550_putc functions for the serial driver located at - drivers/serial/ns16550.c. This option is useful for saving - space for already greatly restricted images, including but not - limited to NAND_SPL configurations. - - CONFIG_DISPLAY_BOARDINFO Display information about the board that U-Boot is running on when U-Boot starts up. The board function checkboard() is called diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 327c0e06977b..0c7262352d53 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,10 +11,6 @@ /* uArchitecture specifics */
/* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_NS16550_CLK 100000000 #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 05fa9b9612d5..44699476b08b 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,9 +11,6 @@ /* uArchitecture specifics */
/* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - #define CONFIG_SYS_NS16550_CLK 0x03b9aca0 #define CONFIG_SYS_NS16550_COM1 0x18000300
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index dd88d10274c1..28966e0d0a41 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -47,5 +47,6 @@ CONFIG_PHY_GIGE=y CONFIG_ALTERA_TSE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_ALTERA_TIMER=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 675b2de151c7..7054333d7373 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -206,7 +206,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index e5c45a1bffab..85b055a93ffe 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -85,5 +85,5 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_ADDR_MAP=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 85ec76a59714..0d21b893d8bb 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 852ac9a6eeb3..b01919ec675a 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e15ca5ea2b5d..a3d9a8b4b76c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -129,7 +129,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index dcf74f5d6af5..2ca02503993f 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 230c6d02831c..5d57aa3ba4bc 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -114,7 +114,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 982420db74c4..a13b48c20ece 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b3af4450d00f..a9c7652fab08 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -128,7 +128,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 537d8bf576b0..a0277d0aa61b 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -92,7 +92,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index dd9120970bab..f43a5a0c5428 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -113,7 +113,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index ff7cfa246159..ef52f948827e 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index a61f4d017a68..2b2744dd74ed 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -132,7 +132,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 92a7e0966936..29b7d8480958 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -95,7 +95,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 84e2d3c587a4..98164d2bade1 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index b883b81e0cd8..d74fbecfaa12 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -118,7 +118,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 7f7870d82c52..efd0a7eb8966 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 3e16470608e5..44e98b9520f5 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index e985f8cd75d0..9c6504376602 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 9f4ae14e0b23..4b967352f4de 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -117,7 +117,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 3f93b318c92f..b65e65187873 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -142,7 +142,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 3b3cf1ee7a5e..034a971bc8b4 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -124,7 +124,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index aba5b9cedd43..9476c28e98b1 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ce0ba0e37574..ecd5e978c8b2 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f3fc4c82a54d..80f4d22518c4 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -141,7 +141,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 25eb5d5da74a..50fc0c124e83 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 054320f356cd..dafb430e4c0c 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -125,7 +125,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index aae886b75c4e..411b4f05a44c 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -103,7 +103,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index cc02fe6a8ac9..8b0b6e4e6808 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -144,7 +144,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index dc82da81b816..6a17f085a7f5 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 7b80edeeeb92..2738b208f16f 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 5fecb6684735..fdd7703f72cf 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -106,7 +106,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 9162774ad70c..5904aa54b291 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -147,7 +147,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index fd143b610b98..938148df93af 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -129,7 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index edb8b9958eae..c4a41c4c0ebf 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,7 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b1dbca6e7ea3..a4ed8fb39cd4 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -109,7 +109,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1269d22f90c6..9b4ca39d34f3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -146,7 +146,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index b5394d05b7ff..a6d98b42ce1c 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 431ca31302c9..b3e4a1f0d0eb 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 1ee46f9fbe9f..f1a9c058caac 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -108,7 +108,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 2ba566644627..0eec5089332d 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -98,7 +98,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 9a2796fc7fce..f9f4c31ddb6c 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -93,7 +93,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 8cb00d5d316b..6a974370088c 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -95,7 +95,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index c0bd16bd61f8..1725a8a5a9cc 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -90,7 +90,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 73ef73c484ef..fa7c35b9ef77 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9fa0fda84f26..125871301e34 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -61,7 +61,8 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x300 CONFIG_PHY_FIXED=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 2aada043e83a..f21c53d59f1e 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index e5661b0b6052..6f9f5a2603a8 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 320f22e348ea..76a59604f2f4 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 1f571b6e6fa0..a4825909e7ad 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 4088d40de30d..1aa0e9eec17f 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 5a6f9a8d248f..ba1820e93a29 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 2d03b4eb1424..98cd9b71e035 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 8f283fa8fd26..f6301a57cfd9 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index beb0259488de..dd7473ef7fd7 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 7ee5fb4f476b..364aab584778 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c050e310c8fb..c6710a0413c3 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 0ff651ae6880..a705542eea70 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 98065da77d6d..d6d6ec0fbf0d 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 88e943d4d0d2..802213de2b9e 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -105,7 +105,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 23f6ee6e431c..a881488dbea1 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index c2d95c10ab0b..562a79955c4d 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 2194ff6c5171..00018033a358 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 7f57b004d576..0cb359de9478 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -104,7 +104,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 5d4573a7f9d5..cbe1bb4e3f62 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -138,7 +138,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 7ca9a8b036ec..80a2c003e6a9 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -132,7 +132,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 39fcd2dad392..99bee8e5ead5 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -135,7 +135,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 8d1011d06c5d..aa6a053209ef 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -106,7 +106,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 9b082674d60d..b445b6bde1f1 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -119,7 +119,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 662edc32c619..a807ac834742 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 0b759c8c2c40..fc6cad59cf45 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -53,7 +53,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 68a96518878b..08cac404c6e2 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -55,7 +55,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a5436db7ac72..85a70c0996b2 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 7fbec63c58f1..00d43e24c5a5 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f43f4c0ee90..90a734fcdad0 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -59,6 +59,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 920e8828460e..f8e0327d8f58 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -40,5 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_MTD=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 # CONFIG_EFI_LOADER is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index b44eabaa4251..81433b02cbcf 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -44,7 +44,8 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_BCMSTB_SPI=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 06987ab82860..321121e3f729 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 59ae29a80e02..2240988dd0db 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -94,6 +94,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3d2f40fb9554..d768e11db51e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 45905c6792b8..a38b3b78c08a 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -102,6 +102,7 @@ CONFIG_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index ffa8070cb39e..150dba140865 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -97,6 +97,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e8ec8855dda3..94d14d012da2 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -93,6 +93,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b645cba90709..570c4e82a473 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -79,6 +79,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 541b7fadead4..43cf53045b40 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_INTEL=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ca453ac8b9d0..08e1e5be415c 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -96,6 +96,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 27bf046f991a..aa3d6f2b9d19 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index e9222648758b..77735739b825 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -91,6 +91,7 @@ CONFIG_CROS_EC_LPC=y # CONFIG_SPL_PINCTRL is not set # CONFIG_TPL_PINCTRL is not set CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 92018fb78eef..d5aaee9dde17 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -95,6 +95,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b78e98c2045a..e83f2dfe7f39 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -59,6 +59,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 0d904675f73f..31979f32bc5f 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6fed3f2ecda9..18d58bec2010 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 20c0c1816968..e4da59bae927 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -61,6 +61,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index d8c5be66ad7b..e297494663e0 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -55,6 +55,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 094b21666e16..203eff8e165a 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -53,6 +53,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 4521172f42bf..cb0f0d7c8d02 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -57,6 +57,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SPI=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 5eea1ec9a724..71c57ed5aba0 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 16a866f6b475..6c35f31a29d7 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 6c805f41568c..a17d01f3fd27 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 86fe0692a0a3..6deb05575c1c 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 93aef472b54d..9088fffb25e2 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -56,7 +56,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 5abdadf2d56f..c364c9ecc8df 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 83f532d6e543..8d1fc22eb93c 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 28aaff69e978..89e6d1febc8b 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 1f4ca01c50f8..36f57d58128b 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -48,6 +48,7 @@ CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 6bc777c51c16..bb6f21b2e634 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -101,6 +101,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index f41c7580b4c6..2e3bff8cf04e 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -78,6 +78,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 8ef40d847c77..289f47f4ae89 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index ce10750857ee..06a044b93496 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f8ca1f6597be..33202e48fe76 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 7c0b856ca567..8f8d34c7038f 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -81,6 +81,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 8502fcc51e62..0aeaf01d9a70 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9421845b0377..8a6d19a1769e 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -88,6 +88,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e7da9c4e5ff7..3050fd59922c 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index db3acf5be53f..7374ee42fb19 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -63,5 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 5de5de465cb0..aab322311162 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -42,6 +42,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index d48dcc1a0ece..3aee6b647136 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 1f91118426e7..2a6d2edbab02 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 63c53a0248f2..26967a67cc94 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index a37870628c65..547517253288 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 1d7832b9591c..c23d0549a4a2 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -27,5 +27,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 6fdb3ea68003..8ee11833095d 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 794cf4b23d7a..1889743f081f 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -61,7 +61,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 8c6ad5a0d17d..bba406726850 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 9543c785bba9..4715f9d9d7d0 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 9290cb7af688..beee58962a5c 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -59,7 +59,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index ce5a089d3270..f536dd3bcb55 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 42f812c31f0e..1fa1a5afa78f 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 25007793b3a0..96bcba6e94ff 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 6c8a284e7c70..0d1c97dd4b09 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 6182101f1197..bded09788026 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index fd169c3e957a..a851d8508221 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -70,6 +70,7 @@ CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index fec29f2c9119..b0069fd60b01 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index f6ac484f2e85..9ca26ae61f51 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 13d612ac3fb6..153abb7eb936 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -93,6 +93,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 59ec3a6346f3..2990a702d999 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -71,6 +71,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index dff052230846..754fd4e3c6d5 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 5a8b69c0f94a..7518f7f2edef 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index f54a610a2748..4c4301a9e7c5 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 1ad635daa985..646f0086c6e3 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -60,6 +60,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index a8326f03a23f..5a958ee36a3f 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 1ace7b795a09..ee401b763d90 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -97,6 +97,7 @@ CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index dbb0ce0221f1..b551f5bdee07 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -60,7 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index a8b4ce2bab98..21ccc5557391 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -58,7 +58,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1a4fc999db7e..f1c9169a72da 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -58,7 +58,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 7e9076a1f99b..f40ede127b59 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -56,7 +56,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 7bfe1f7cae50..ff5e323d57cb 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -61,7 +61,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 2327d8924376..3b073241e45c 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 250440a70acc..238886d0dfdf 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -59,7 +59,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index f1600c4005b6..ccd8fb9801fc 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -62,7 +62,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index e4a26dc0ab2f..fcef5e5d5bbe 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -85,7 +85,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index c9fa1099303c..c2996a1372e1 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -75,7 +75,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 773a3e6b2b6d..a1709f4525b2 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index c9f0635de17b..3639b4dd93db 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -65,7 +65,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index c1c21cb187c7..4fc7b3873468 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -67,7 +67,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 503fe95c88dc..f162111d0bea 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 727d10ffaaa8..cc640461cf4d 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 72129a70a8ca..e6cd6a7d19c4 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c67f329f92ea..d5d335445707 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xf40000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 14aa19fe726e..c3c6678bb494 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 2f1b41f06869..40228acaa896 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 1c38d99dfca1..ebf6fdb463c6 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -84,7 +84,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 4a642f4a6c29..07d52c249d01 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 1b5d8229c664..6834a696b630 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 877a771b51cb..e5e732a50863 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -69,7 +69,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 9695164a93f2..29dc23e179e2 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -96,7 +96,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 290d53f852c1..86060806fe45 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index b3a93179c226..ed7e91e9b5fc 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -77,7 +77,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index cb3d1580d35b..f84f4dd66093 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index c53827c63760..40a0ea703256 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -111,7 +111,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 46ab9a26f0f1..621a0238d449 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -105,7 +105,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 753583d47b44..525c7df6d0f4 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index b5e243bc0e9b..dde204eaa0df 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index fad07863db58..b8df245025f3 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 20354f7e86bf..5b1cf988cf07 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 9b3c77fe56b6..a7e9583c735e 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 29cbac313547..774d41308ba5 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 21bb036ee8c7..f759baf36db6 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -100,7 +100,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index fd7f3bb69b3c..e7dbf41b972e 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 14931f72197d..627abc81c9c5 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 22844636e27d..f4dcbd4a926b 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b75c75230fcd..307fbfcbb7db 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 21199b9d0681..667fc2123a24 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -107,7 +107,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index df227d80371e..7d980c3c4691 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 0e2fa0284dcb..b345d13caa02 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 6b9971f138a0..d4546348bbd0 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 0aa046a425b7..f0f8cbf34e0e 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -117,7 +117,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index a6c33de39712..529cd93bd248 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ddf280a5628f..bfe9260d1b72 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 7ca5457c2d28..391e95a48d5f 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -84,7 +84,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 5fe6bae3a1ba..2ebde25bd93c 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -90,7 +90,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 7d9f5330016b..0df5b85869b6 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -67,7 +67,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 03e944fa7a15..a095bbcb82ee 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -76,7 +76,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index e9cf20d5f743..2bf8a9492561 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 0e2f4094f792..5fe73bc8ac70 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 75851ad390d7..7c8a1e70fad2 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 552bb43f7a1d..937581536af9 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -91,7 +91,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 312464484dac..4d3c0580a1b7 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 344899ef6f21..480ab0379538 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -118,7 +118,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 0a363533ff2f..a0d57b19354f 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 26fc4592a966..e08af4d1a2cf 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -109,7 +109,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index d9c716ebabde..1a09fdadd3b8 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 61b7244ff22f..346a954760f1 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 05115ea71e45..4361cd223dba 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index ac2cede0d3d3..560362695ff5 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -119,7 +119,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 6074b6b3142b..cdcfa63bf458 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -109,7 +109,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 07b077767ace..e0442390db0d 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 2432154f77b2..da6c2431bf72 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 0aa2792c3c4c..f9aab31acff3 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -85,7 +85,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 8556c003555c..aecd74d15b9b 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index d4f2268041f0..8d1fc5f20418 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index af63278bb3c4..7c6e6b7637c3 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -96,7 +96,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 6b42170ffbd6..64296dbe0b2e 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -121,7 +121,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index dedefb3a0a3f..2b4712e07e3d 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -116,7 +116,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 60f26f018308..c8ab5723539a 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -118,7 +118,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index a819ebfefffa..18213e5cc5cf 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -89,7 +89,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index c56975333813..eb88cec6e029 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 2b96382f2482..33aedcfbd20a 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -111,7 +111,7 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 426363538408..db28ae196f64 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 2e812943fd39..0ec80be2ea6a 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -90,7 +90,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 9c12f2be9ce0..27323be40890 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -96,7 +96,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 817ae8d728b3..f66f5298366e 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index b3e75847cca3..d601c083e28c 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index effcd33629b8..e2b6044d1fae 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -112,7 +112,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index eb57948414df..8abd58d53eb6 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e5702b815923..389b32b2d6db 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -106,7 +106,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index face1e05320a..e4d15dda14d0 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -94,7 +94,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index ba6f5090d471..4030fd4693bf 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -97,7 +97,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 500029003031..b6e154b78b5c 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -116,7 +116,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 58bae66baa00..fc43c535b5c4 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -86,7 +86,7 @@ CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9c6012460b37..09df15154e78 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 6e1fe901ff4a..8cdfe5cc0bdc 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -82,7 +82,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 8441814f13f5..84c9f1526652 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index dc9a47463f49..3ac03305c7a9 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -100,7 +100,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 361098568097..41891d83ace1 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -108,7 +108,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 054c5e6d618e..b635c651aaea 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -45,3 +45,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 55f624bbeeb9..243213cb8197 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -47,3 +47,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 53762a94e2a3..ed41e298f443 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -44,3 +44,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 8b86d74dc41a..63e5fcb6a5ce 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -46,3 +46,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 66f3036313c4..52ed763424a8 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -65,6 +65,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0811e70dcefe..9346cafc64c6 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 403a84befdc3..7ba8338add5a 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -99,6 +99,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 03fa857996ce..8fad8c643f22 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 67ca98563b5f..c5f13c060be4 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index afa51bc8fa3b..b6a604b6943d 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index d02eb1851a7a..767befe2d2c9 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d2d9bf91c564..383ec1f39eee 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 82264de90889..40d3117b4f08 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -91,6 +91,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 2185f87d7d06..40a45a0f4bbe 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -52,6 +52,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 9cebc704ce98..0590fc95c47c 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index c10e1a501394..b3278142c837 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 75907e05c57f..dfdb06b2378d 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index db08ca576339..995c0ccb1b77 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index dda3b6b5f93d..877a39cfa7c2 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -65,7 +65,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 21534c59fde7..24f7d8b4bce0 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index afa0cad0418f..e7d6ffd9259c 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -53,7 +53,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 4705f61e4243..33adcc952cf0 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -104,6 +104,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 2c4e26c290a7..0cae1c61508e 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -46,7 +46,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OMAP3=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 2315a84285ec..e15c6d5cb13a 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_OMAP3=y CONFIG_USB_GADGET=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index bd0ede759cb9..d12199766ad3 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -56,7 +56,7 @@ CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index c2e879c9bde8..45bd307a1c42 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -61,6 +61,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 01bfaed978b9..9c9f6c463d65 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 7c641038178f..fbcdf4b3630b 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 39245e8784b2..0980d8156965 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8a274187d093..0632a928bc0a 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 528b7bb69f24..dfbf5e70f4a1 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -80,6 +80,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index d0071f3af521..116e5d0ed3e7 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 3b08cb7b1d14..018c2f50331f 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -74,7 +74,8 @@ CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index f6c49da574c5..91123784b544 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2b0b39c7b2c..9a5be3e91390 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 9175c7c85ae1..9c36750bde03 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 0aa7cca7b8b6..db1ceaa31f37 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index d731b9687886..d2cca48304d3 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 8433b5734f62..0f4811e5d7a5 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f82f628d5bb7..a8222122fc9d 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 670211e2e9d7..0a029c4098f7 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 7f1259d82c1f..8172ed0ad228 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -95,6 +95,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 3cdcc729f853..6827c98ed9f1 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -71,6 +71,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e03442afa462..cf4a58de1c5a 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -68,6 +68,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83721cedf3dd..54a400405bec 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac9a3f983066..e74ba07e4467 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0c1ebf34025..0ffb073f3137 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -96,6 +96,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index fcb3a681ca00..2443f292469e 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -63,6 +63,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 4ed98c0a511d..18c6d1b92253 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -74,6 +74,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 38a5f3a80c0f..54d01456b1ef 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -77,6 +77,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e75011bee5f4..73a4f06eb9b1 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -92,6 +92,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 6ed5ef868e5e..f2c914f41f5d 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index bd6183ba5b8d..26638405bf73 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -63,6 +63,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index ba48d021f4fc..5b8d678f6bb5 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -79,6 +79,7 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 01f104a97d03..40cd91c045c1 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -29,5 +29,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 52f5aba8cab5..79f36c036040 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -65,7 +65,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index b6b9f88c00bb..f5d16f64d734 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -31,5 +31,6 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 68440926c078..9269eccf17ab 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index de9ebd072263..48fb06722323 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 7642498ea9ca..da4545effff8 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 08ae6c502b41..4e2dc0c9857e 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 478efc59ea91..00c4cf30089a 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -29,6 +29,7 @@ CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y CONFIG_MMC_DW=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 0feda3b04f75..4d856d535a3d 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -81,6 +81,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index fa19f555f20a..1056932cd35e 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 12e8ebf0138f..a6714b265e18 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 5ee9f5ff9da7..e0e6b2d04610 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index f689105695c1..919863270f83 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -80,6 +80,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 5d401e6c2d7e..5b724697123e 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -60,6 +60,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index 48b2ffc7521d..0209f62d2f56 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -81,7 +81,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_RX8025=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 22544c0913aa..440c170c6b1e 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 8741ecbb2d71..b91c3b135479 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 47dbf342776a..bab7b29bf896 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -77,6 +77,6 @@ CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y # CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 85d94a6ea89f..5976a84491e4 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 7dfbad808383..078f829c2dff 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index cbae60f98768..0c9d61b8053c 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 31483296802c..c58514669dde 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=1027 CONFIG_PHYLIB=y CONFIG_ETHOC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SYSRESET=y CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index de02e08a2996..18dcc09ee5e2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -720,6 +720,17 @@ config PIC32_SERIAL help Support for the UART found on Microchip PIC32 SoC's.
+config SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver" + depends on !DM_SERIAL + select SYS_NS16550 + +config SPL_SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver in SPL" + depends on SPL && !SPL_DM_SERIAL + default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS + select SYS_NS16550 + config SYS_NS16550 bool "NS16550 UART or compatible" help @@ -732,25 +743,52 @@ config SYS_NS16550
config NS16550_DYNAMIC bool "Allow NS16550 to be configured at runtime" + depends on SYS_NS16550 default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER help Enable this option to allow device-tree control of the driver.
Normally this driver is controlled by the following options:
- CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for - access. If not enabled, then the UART is memory-mapped. - CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit - access should be used (instead of 8-bit) - CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also - endianness. If positive, big-endian access is used. If negative, - little-endian is used. - It is not a good practice for a driver to be statically configured, since it prevents the same driver being used for different types of UARTs in a system. This option avoids this problem at the cost of a slightly increased code size.
+config SYS_NS16550_MEM32 + bool "If memory-mapped, 32bit access is needed for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, if memory-mapped, indicates that 32-bit access should be + used (instead of 8-bit) for register access. + +config SYS_NS16550_PORT_MAPPED + bool "Port I/O is used for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, port I/O is used for ns16550 register access. If not + enabled, then the UART is memory-mapped. + +config SYS_NS16550_REG_SIZE + int "ns16550 register width and endianness" + depends on SYS_NS16550_SERIAL || SPL_SYS_NS16550_SERIAL + range -4 4 + default -4 if ARCH_OMAP2PLUS || ARCH_SUNXI + default 1 + help + Indicates register width and also endianness. If positive, big-endian + access is used. If negative, little-endian is used. + +config SPL_NS16550_MIN_FUNCTIONS + bool "Only provide NS16550_init and NS16550_putc in SPL" + depends on SPL_SYS_NS16550_SERIAL && PPC + help + Enable this if you desire to only have use of the NS16550_init and + NS16550_putc functions for the serial driver located at + drivers/serial/ns16550.c. This option is useful for saving space for + already greatly restricted images, including but not limited to + NAND_SPL configurations. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index eb7b8f23ee90..45cf94c74c61 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ ifdef CONFIG_DM_SERIAL obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o else obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o -obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o +obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index afd7cc89bf8e..719caf7b0c3b 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -15,7 +15,6 @@ /* * SERIAL */ -#define CONFIG_SYS_NS16550_MEM32
/* * Flash diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c4cde1cc512e..b8cbdc36754b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,8 +151,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b241939fc387..dba15dae749b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,8 +235,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9afd834f9faf..fd721f30b3aa 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,10 +322,7 @@ extern unsigned long get_sdram_size(void);
/* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b9311fc5e4f9..173f6205e08f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,8 +163,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 9629d735a271..c99e6ba781a4 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 67e42b94c117..8b43fe0c9939 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 978cc6714ec6..7cb10b205db1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,8 +294,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f26e9d6e8692..3fa2d01dcc2a 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,8 +267,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 62f07108126d..c5a28fadb004 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,8 +269,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0616f8a86dff..795120c02a87 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,8 +229,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2eb4e73efa9e..e3cbc649fa19 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,8 +89,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a0951fbf6235..b61c8005c33f 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -15,10 +15,6 @@
/* NS16550 Configuration */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif
/* I2C Configuration */
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index cf5125fdfa63..7224bd8d1f49 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,10 +33,6 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_CLK 19660800
/* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index f2357b5785a1..c0429ae15c4c 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,9 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 5aa720da3d74..481baff11d9a 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,8 +97,6 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a6de28a42b2e..773ce3f6a6f8 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,6 @@
/* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000
diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index 0eeea80b32f4..d14c1d445b25 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -18,7 +18,4 @@ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0"
-#define CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 9061eba6686a..0641d5c0a238 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,12 +14,8 @@ #include <asm/arch/omap.h>
/* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif
/* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 4297047e8ce2..52f2d50118a4 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -14,7 +14,6 @@
#ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #endif
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 545408a4baa5..472f236b9b6e 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h>
/* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 965fa87c6577..0d61724db8c4 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,9 +20,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 4af845ea9c2d..bfc0fa5c442c 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,9 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ce65e7755ea..ce3cb20732db 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,9 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32
/* * Ethernet PHY configuration diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index cc8c37ec0bf5..7acdb0fa038e 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 16fd6d562d41..30ba6065253e 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,6 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f0ae9248af34..5434c4f7679f 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 9eedd47c07e5..b9c853d7dfef 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,9 +20,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00
#endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 77f84e1c9eaa..148598fab465 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,8 +26,6 @@
/* GPIO */
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 885774f63d47..3f2dfa640c9c 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,8 +47,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6b23134ecc99..bd2f74c1262a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,10 +227,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index fce91192dff7..8c43f652ab65 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,10 +60,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1ac59a2d4597..06830f401a31 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,10 +145,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 43dbeea1b3bd..7dd5649005b7 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,8 +28,6 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 47367845a07f..2fc06c1dd2dc 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 07ec2c956379..40b4cb964d11 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index dec661d6b194..5668e07d1354 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,8 +45,6 @@
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d8997208e973..895c566fea2f 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,8 +37,6 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
/* diff --git a/include/configs/malta.h b/include/configs/malta.h index 30c2e41eec53..2dd34ea7313c 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -33,7 +33,6 @@ /* * Serial driver */ -#define CONFIG_SYS_NS16550_PORT_MAPPED
/* * Flash configuration diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 9b1ba3655e82..1f733d112dd7 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,9 +22,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xbe000c00 #endif
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 43527017d84a..da16e3b21a4b 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,9 +14,7 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif
diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1a6..eaffe0bf4c95 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,9 +12,6 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e42884..347598868bb5 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,9 +12,6 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4fff3820c1..4f1067c23bbc 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,10 +32,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 99a020c3c71d..310bdde7cb55 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,7 +40,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 838c62c67111..065820689caf 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,10 +319,7 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebdd7..8b151ef18836 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,8 +8,6 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_NS16550_MEM32 - /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 200b34b35bae..263d1bd180c5 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,8 +8,6 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 4c964cc37708..1f6b82f2d022 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -7,8 +7,6 @@ #define _ROCKCHIP_COMMON_H_ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_MEM32 - /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */
#ifndef CONFIG_SPL_BUILD diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index d071f590f106..5765f2ccb5e7 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_SYS_NS16550_COM4 0x481a6000 diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 0187fca5f0d9..c29bc448eed6 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,11 +52,6 @@ * Serial */
-#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c86..49883ea7a3cc 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/* diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 75d2081fac88..7012097276c7 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 86cc3771ba59..029f898b64ff 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -76,7 +76,6 @@ * Serial / UART configurations */ #define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32
/* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d9e4c8b699f4..1ed0a262bc61 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -16,7 +16,6 @@ #include <linux/stringify.h>
/* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ @@ -25,7 +24,6 @@ #define CONFIG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 16bdc39b750e..38a43b726f03 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,6 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666
/* diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h index bb3186e21921..663a49e7b6c5 100644 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ b/include/configs/theadorable-x86-dfi-bt700.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h>
/* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED
/* Set the board specific parameters */ #define DEF_ENV_TFTPDIR "theadorable-x86-dfi" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 97166e010f7d..60632c58c67d 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index efd3a0db04eb..f2dbe3544a5d 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5d5df6b10191..fb017771688e 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,12 +17,6 @@ #include <asm/arch/omap.h>
/* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif #define CONFIG_SYS_NS16550_CLK 48000000
/* diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index a4a45fad9dc8..aaeea77281b6 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,7 +34,6 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
/* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 6cc443c8e9cb..80d2a011f0fe 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,10 +27,6 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200}
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 0568946fc824..eb930341c3a8 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -29,8 +29,6 @@ */ #define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM3 UART3_BASE #endif
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 24bbf9e7c2c6..a1efb57f1b09 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -30,10 +30,6 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif
/* * Environment setup diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 6f36d6964b9b..84e5ba39f148 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00
/* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 0add626e81a5..318e3680a6e1 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,10 +13,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 8e22d6e5d876..f76c1f8be0fd 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,7 +21,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550_PORT_MAPPED
/* * Miscellaneous configurable options diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 58d01f4bb428..7090fcef6804 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,8 +127,6 @@ /* Serial Driver Info */ /*====================*/
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ diff --git a/include/ns16550.h b/include/ns16550.h index 3d9002d9f151..0ee5c4d6de75 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@
#include <linux/types.h>
-#ifdef CONFIG_DM_SERIAL +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver
On 12/4/22 15:39, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini trini@konsulko.com
Since this patch (which was with branch next after v2023.01) there is no UART output from main U-Boot on pinea64-lts_defconfig. SPL output is ok.
Best regards
Heinrich
On Fri, 20 Jan 2023 17:09:01 +0100 Heinrich Schuchardt xypron.glpk@gmx.de wrote:
Hi Heinrich,
On 12/4/22 15:39, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini trini@konsulko.com
Since this patch (which was with branch next after v2023.01) there is no UART output from main U-Boot on pinea64-lts_defconfig. SPL output is ok.
Indeed, see this thread: https://lore.kernel.org/u-boot/20230117120938.818180-1-andre.przywara@arm.co...
I believe Tom is about to queue the proper fix?
Thanks for the report!
Cheers, Andre
On Fri, 20 Jan 2023 16:24:36 +0000 Andre Przywara andre.przywara@arm.com wrote:
On Fri, 20 Jan 2023 17:09:01 +0100 Heinrich Schuchardt xypron.glpk@gmx.de wrote:
Hi Heinrich,
On 12/4/22 15:39, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini trini@konsulko.com
Since this patch (which was with branch next after v2023.01) there is no UART output from main U-Boot on pinea64-lts_defconfig. SPL output is ok.
Indeed, see this thread: https://lore.kernel.org/u-boot/20230117120938.818180-1-andre.przywara@arm.co...
I am just seeing that the eventual patch is not in this thread, but here: https://lore.kernel.org/u-boot/20230110161946.3816866-5-trini@konsulko.com/
Cheers, Andre
On Fri, Jan 20, 2023 at 04:32:00PM +0000, Andre Przywara wrote:
On Fri, 20 Jan 2023 16:24:36 +0000 Andre Przywara andre.przywara@arm.com wrote:
On Fri, 20 Jan 2023 17:09:01 +0100 Heinrich Schuchardt xypron.glpk@gmx.de wrote:
Hi Heinrich,
On 12/4/22 15:39, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini trini@konsulko.com
Since this patch (which was with branch next after v2023.01) there is no UART output from main U-Boot on pinea64-lts_defconfig. SPL output is ok.
Indeed, see this thread: https://lore.kernel.org/u-boot/20230117120938.818180-1-andre.przywara@arm.co...
I am just seeing that the eventual patch is not in this thread, but here: https://lore.kernel.org/u-boot/20230110161946.3816866-5-trini@konsulko.com/
Yes, and I'll go and bring that whole series in today. I wanted to have it out a bit longer in case there was yet another problem with the conversion that still wasn't fixed.
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 +- arch/arm/include/asm/arch-bcmnsp/configs.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch2.h | 8 +-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 4 +- arch/arm/mach-davinci/da850_lowlevel.c | 6 +- arch/arm/mach-davinci/spl.c | 4 +- arch/arm/mach-keystone/init.c | 4 +- arch/arm/mach-lpc32xx/devices.c | 8 +-- arch/arm/mach-omap2/am33xx/board.c | 32 +++++----- arch/arm/mach-tegra/board.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 12 ++-- arch/powerpc/include/asm/config.h | 2 +- board/Synology/ds109/ds109.c | 10 +-- board/eets/pdu001/mux.c | 12 ++-- board/emulation/qemu-ppce500/qemu-ppce500.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/nokia/rx51/rx51.c | 4 +- drivers/serial/Kconfig | 2 +- drivers/serial/ns16550.c | 8 +-- drivers/serial/serial_mtk.c | 40 ++++++------ drivers/serial/serial_ns16550.c | 64 +++++++++---------- drivers/serial/serial_omap.c | 6 +- include/configs/MPC837XERDB.h | 6 +- include/configs/MPC8548CDS.h | 6 +- include/configs/P1010RDB.h | 6 +- include/configs/P2041RDB.h | 10 +-- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 10 +-- include/configs/T104xRDB.h | 10 +-- include/configs/T208xQDS.h | 10 +-- include/configs/T208xRDB.h | 10 +-- include/configs/T4240RDB.h | 10 +-- include/configs/am335x_evm.h | 12 ++-- include/configs/am335x_guardian.h | 12 ++-- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 12 ++-- include/configs/am335x_sl50.h | 12 ++-- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-tk1.h | 2 +- include/configs/apalis_t30.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 12 ++-- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beaver.h | 2 +- include/configs/bur_am335x_common.h | 4 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/chiliboard.h | 12 ++-- include/configs/ci20.h | 2 +- include/configs/cm_t43.h | 4 +- include/configs/colibri_t20.h | 2 +- include/configs/colibri_t30.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/dra7xx_evm.h | 6 +- .../configs/gardena-smart-gateway-mt7688.h | 4 +- include/configs/harmony.h | 4 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron_sl28.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/linkit-smart-7688.h | 4 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/mt7621.h | 4 +- include/configs/mt7628.h | 4 +- include/configs/mt8183.h | 4 +- include/configs/mt8516.h | 4 +- include/configs/mv-common.h | 4 +- include/configs/nokia_rx51.h | 4 +- include/configs/nyan-big.h | 2 +- include/configs/omap5_uevm.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/p1_p2_rdb_pc.h | 6 +- include/configs/paz00.h | 2 +- include/configs/pdu001.h | 12 ++-- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/siemens-am33x-common.h | 6 +- include/configs/sniper.h | 4 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/sunxi-common.h | 14 ++-- include/configs/tb100.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/ti814x_evm.h | 4 +- include/configs/ti816x_evm.h | 4 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +-- include/configs/ti_omap3_common.h | 8 +-- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- include/configs/vocore2.h | 4 +- include/configs/x530.h | 4 +- include/configs/xtfpga.h | 4 +- 134 files changed, 347 insertions(+), 347 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index c01cebbf9859..0e7d5fa06dc6 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif
sysclk_path = fdt_get_alias(blob, "sysclk"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ee734577fca7..4f91db49eebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 0c7262352d53..fd8dad394ad8 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,8 +11,8 @@ /* uArchitecture specifics */
/* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_CLK_DIV 54 -#define CONFIG_SYS_NS16550_COM3 0x18023000 +#define CFG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK_DIV 54 +#define CFG_SYS_NS16550_COM3 0x18023000
#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 44699476b08b..0d4baf3c0074 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,7 +11,7 @@ /* uArchitecture specifics */
/* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 -#define CONFIG_SYS_NS16550_COM1 0x18000300 +#define CFG_SYS_NS16550_CLK 0x03b9aca0 +#define CFG_SYS_NS16550_COM1 0x18000300
#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index e8bd8d27136c..aef615873343 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -26,10 +26,10 @@ #define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f1ffb2327d63..bad18d778aa0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -35,8 +35,8 @@ #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 #define CFG_SYS_FSL_TIMER_ADDR 0x023e0000 #define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 5dd90b47f939..6de431f6bbbc 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -19,8 +19,8 @@ #endif #endif
-#if !defined(CONFIG_SYS_NS16550_CLK) -#define CONFIG_SYS_NS16550_CLK 13000000 +#if !defined(CFG_SYS_NS16550_CLK) +#define CFG_SYS_NS16550_CLK 13000000 #endif
#define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e85918eb7ec5..033341dbfb63 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -30,8 +30,8 @@ #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000 diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 759c93747c75..2319ac6d5631 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -290,8 +290,8 @@ int arch_cpu_init(void) board_gpio_init();
#if !CONFIG_IS_ENABLED(DM_SERIAL) - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif /* * Fix Power and Emulation Management Register @@ -299,7 +299,7 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), -#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) +#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) &davinci_uart0_ctrl_regs->pwremu_mgmt); #else &davinci_uart2_ctrl_regs->pwremu_mgmt); diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 54aff78894a5..5f5b9ebbf97a 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -27,9 +27,9 @@ void puts(const char *str) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r'); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r');
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c); } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 5b95f6050019..1954e69e9f0d 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -185,8 +185,8 @@ int arch_cpu_init(void) * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif
return 0; diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 0a4fef295a36..3fcf8facb411 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -44,13 +44,13 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART5_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART6_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, };
#if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index f393ff91441f..44d5214a3df1 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -87,29 +87,29 @@ int dram_init_banksize(void)
#if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM2 + { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM3 + { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # endif # endif };
U_BOOT_DRVINFOS(am33xx_uarts) = { { "ns16550_serial", &am33xx_serial[0] }, -# ifdef CONFIG_SYS_NS16550_COM2 +# ifdef CFG_SYS_NS16550_COM2 { "ns16550_serial", &am33xx_serial[1] }, -# ifdef CONFIG_SYS_NS16550_COM3 +# ifdef CFG_SYS_NS16550_COM3 { "ns16550_serial", &am33xx_serial[2] }, { "ns16550_serial", &am33xx_serial[3] }, { "ns16550_serial", &am33xx_serial[4] }, diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 95d6555a0d25..f8b61a2b3e3b 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -259,9 +259,9 @@ void board_init_uart_f(void)
#if !CONFIG_IS_ENABLED(OF_CONTROL) static struct ns16550_plat ns16550_com1_pdata = { - .base = CONFIG_SYS_NS16550_COM1, + .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, };
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1161938d304f..6dd61caf1c47 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -649,7 +649,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif
#ifdef CONFIG_FSL_CORENET @@ -751,7 +751,7 @@ static void msg(const char *name, uint64_t uaddr, uint64_t daddr) * This function compares several CONFIG_xxx macros that contain physical * addresses with the corresponding nodes in the device tree, to see if * the physical addresses are all correct. For example, if - * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address * of the first UART. We convert this to a physical address and compare * that with the physical address of the first ns16550-compatible node * in the device tree. If they don't match, then we display a warning. @@ -796,15 +796,15 @@ int ft_verify_fdt(void *fdt) */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { -#ifdef CONFIG_SYS_NS16550_COM1 +#ifdef CFG_SYS_NS16550_COM1 if (!fdt_verify_alias_address(fdt, aliases, "serial0", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1))) return 0; #endif
-#ifdef CONFIG_SYS_NS16550_COM2 +#ifdef CFG_SYS_NS16550_COM2 if (!fdt_verify_alias_address(fdt, aliases, "serial1", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2))) return 0; #endif } diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 79fe567b5875..b0ad7d7aa728 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -52,7 +52,7 @@ * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif
#endif /* _ASM_CONFIG_H_ */ diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index 9e7f6ac6c792..5c3f46e23f46 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -101,17 +101,17 @@ int board_init(void) #include <ns16550.h> #define SOFTWARE_SHUTDOWN 0x31 #define SOFTWARE_REBOOT 0x43 -#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE +#define CFG_SYS_NS16550_COM2 KW_UART1_BASE void reset_misc(void) { int b_d; printf("Synology reset..."); udelay(50000);
- b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2, - CONFIG_SYS_NS16550_CLK, 9600); - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2, + b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2, + CFG_SYS_NS16550_CLK, 9600); + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2, SOFTWARE_REBOOT); }
diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index f0f9e262ebdb..886fef60b0af 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -92,22 +92,22 @@ void enable_uart5_pin_mux(void) void enable_uart_pin_mux(u32 addr) { switch (addr) { - case CONFIG_SYS_NS16550_COM1: + case CFG_SYS_NS16550_COM1: enable_uart0_pin_mux(); break; - case CONFIG_SYS_NS16550_COM2: + case CFG_SYS_NS16550_COM2: enable_uart1_pin_mux(); break; - case CONFIG_SYS_NS16550_COM3: + case CFG_SYS_NS16550_COM3: enable_uart2_pin_mux(); break; - case CONFIG_SYS_NS16550_COM4: + case CFG_SYS_NS16550_COM4: enable_uart3_pin_mux(); break; - case CONFIG_SYS_NS16550_COM5: + case CFG_SYS_NS16550_COM5: enable_uart4_pin_mux(); break; - case CONFIG_SYS_NS16550_COM6: + case CFG_SYS_NS16550_COM6: enable_uart5_pin_mux(); break; } diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 99edaa3b4215..a4254250bbf3 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -343,7 +343,7 @@ void *board_fdt_blob_setup(int *err) return get_fdt_virt(); }
-/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ +/* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ int get_serial_clock(void) { return get_bus_freq(0); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index c39df462e3bb..ab3b2e3e69b5 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -587,7 +587,7 @@ void fdt_disable_uart1(void *blob) int nodeoff;
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CONFIG_SYS_NS16550_COM2); + CFG_SYS_NS16550_COM2);
if (nodeoff > 0) { fdt_status_disabled(blob, nodeoff); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 0db11f4c5f79..9bf948cb5c96 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -45,7 +45,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 9cd46c966410..8f0dec4c0ab7 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -32,7 +32,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... "); @@ -54,9 +54,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); }
void puts(const char *str) diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index e7d4428d7c22..6c3f82849e3a 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -57,7 +57,7 @@ void board_init_f(ulong bootflag) bus_clk = get_board_sys_clk() * plat_ratio; gd->bus_clk = bus_clk;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 2fd8a2874333..f9e0b5b25ab7 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -31,7 +31,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... "); @@ -52,9 +52,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); }
void puts(const char *str) diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 3ba94fecaa24..9faf259af74d 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -73,7 +73,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index c7fb4272c63b..66a142b3ad03 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -72,7 +72,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; uart_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, uart_clk / 16 / CONFIG_BAUDRATE);
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 8b68329b9864..8866be54a661 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -82,7 +82,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 3f9b1faa853e..130cb8847c0f 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -42,7 +42,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 72d3b80b19b2..779457d29640 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -51,7 +51,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE);
puts("\nSD boot...\n"); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index c1b4b91b6070..fa95886fa3b6 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -795,9 +795,9 @@ U_BOOT_DRVINFOS(rx51_kp) = { };
static const struct ns16550_plat rx51_serial = { - .base = CONFIG_SYS_NS16550_COM3, + .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, };
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 45a34495dfb9..12dbb3d35fd7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -730,7 +730,7 @@ config SYS_NS16550 Support NS16550 UART or compatible. This can be enabled in the device tree with the correct input clock frequency. If the input clock frequency is not defined in the device tree, the macro - CONFIG_SYS_NS16550_CLK defined in a legacy board header file will + CFG_SYS_NS16550_CLK defined in a legacy board header file will be used. It can be a constant or a function to get clock, eg, get_serial_clock().
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 5a693d2f02ae..772dd6fef8f3 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -92,8 +92,8 @@ static inline int serial_in_shift(void *addr, int shift)
#if CONFIG_IS_ENABLED(DM_SERIAL)
-#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif
/* @@ -567,9 +567,9 @@ int ns16550_serial_of_to_plat(struct udevice *dev)
if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) - plat->clock = CONFIG_SYS_NS16550_CLK; + plat->clock = CFG_SYS_NS16550_CLK; if (!plat->clock) { debug("ns16550 clock not defined\n"); return -EINVAL; diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 03b9e86bfc20..6fb4cb65c29f 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -284,8 +284,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define DECLARE_HSUART_PRIV(port) \ static struct mtk_serial_priv mtk_hsuart##port = { \ - .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \ - .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \ + .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \ + .fixed_clk_rate = CFG_SYS_NS16550_CLK \ };
#define DECLARE_HSUART_FUNCTIONS(port) \ @@ -356,36 +356,36 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif
-#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_HSUART(1, "mtk-hsuart0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_HSUART(2, "mtk-hsuart1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_HSUART(3, "mtk-hsuart2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_HSUART(4, "mtk-hsuart3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_HSUART(5, "mtk-hsuart4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_HSUART(6, "mtk-hsuart5"); #endif
@@ -410,22 +410,22 @@ __weak struct serial_device *default_serial_console(void)
void mtk_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&mtk_hsuart1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&mtk_hsuart2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&mtk_hsuart3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&mtk_hsuart4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&mtk_hsuart5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&mtk_hsuart6_device); #endif } diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 76aa1e5afb42..4014f6820400 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -20,17 +20,17 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif
@@ -38,33 +38,33 @@ DECLARE_GLOBAL_DATA_PTR; * the array is 0 based. */ static struct ns16550 *serial_ports[6] = { -#ifdef CONFIG_SYS_NS16550_COM1 - (struct ns16550 *)CONFIG_SYS_NS16550_COM1, +#ifdef CFG_SYS_NS16550_COM1 + (struct ns16550 *)CFG_SYS_NS16550_COM1, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM2 - (struct ns16550 *)CONFIG_SYS_NS16550_COM2, +#ifdef CFG_SYS_NS16550_COM2 + (struct ns16550 *)CFG_SYS_NS16550_COM2, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM3 - (struct ns16550 *)CONFIG_SYS_NS16550_COM3, +#ifdef CFG_SYS_NS16550_COM3 + (struct ns16550 *)CFG_SYS_NS16550_COM3, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM4 - (struct ns16550 *)CONFIG_SYS_NS16550_COM4, +#ifdef CFG_SYS_NS16550_COM4 + (struct ns16550 *)CFG_SYS_NS16550_COM4, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM5 - (struct ns16550 *)CONFIG_SYS_NS16550_COM5, +#ifdef CFG_SYS_NS16550_COM5 + (struct ns16550 *)CFG_SYS_NS16550_COM5, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM6 - (struct ns16550 *)CONFIG_SYS_NS16550_COM6 +#ifdef CFG_SYS_NS16550_COM6 + (struct ns16550 *)CFG_SYS_NS16550_COM6 #else NULL #endif @@ -78,7 +78,7 @@ static struct ns16550 *serial_ports[6] = { { \ int clock_divisor; \ clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \ - CONFIG_SYS_NS16550_CLK, gd->baudrate); \ + CFG_SYS_NS16550_CLK, gd->baudrate); \ ns16550_init(serial_ports[port - 1], clock_divisor); \ return 0 ; \ } \ @@ -144,7 +144,7 @@ static void _serial_setbrg(const int port) { int clock_divisor;
- clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK, + clock_divisor = ns16550_calc_divisor(PORT, CFG_SYS_NS16550_CLK, gd->baudrate); ns16550_reinit(PORT, clock_divisor); } @@ -179,32 +179,32 @@ serial_setbrg_dev(unsigned int dev_index) _serial_setbrg(dev_index); }
-#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_ESERIAL_FUNCTIONS(1); struct serial_device eserial1_device = INIT_ESERIAL_STRUCTURE(1, "eserial0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_ESERIAL_FUNCTIONS(2); struct serial_device eserial2_device = INIT_ESERIAL_STRUCTURE(2, "eserial1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_ESERIAL_FUNCTIONS(3); struct serial_device eserial3_device = INIT_ESERIAL_STRUCTURE(3, "eserial2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = INIT_ESERIAL_STRUCTURE(4, "eserial3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_ESERIAL_FUNCTIONS(5); struct serial_device eserial5_device = INIT_ESERIAL_STRUCTURE(5, "eserial4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_ESERIAL_FUNCTIONS(6); struct serial_device eserial6_device = INIT_ESERIAL_STRUCTURE(6, "eserial5"); @@ -231,22 +231,22 @@ __weak struct serial_device *default_serial_console(void)
void ns16550_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&eserial1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&eserial2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&eserial3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&eserial4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&eserial5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&eserial6_device); #endif } diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index e9ff61a0bac5..904f7d21bf03 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -15,8 +15,8 @@ #include <clk.h> #include <linux/err.h>
-#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif
#ifdef CONFIG_DEBUG_UART_OMAP @@ -128,7 +128,7 @@ static int omap_serial_of_to_plat(struct udevice *dev)
if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) { debug("omap serial clock not defined\n"); return -EINVAL; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b8cbdc36754b..059885ecb54f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,13 +151,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* SERDES */ #define CONFIG_FSL_SERDES diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dba15dae749b..bde8fa8df4dd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,13 +235,13 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* * I2C diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index fd721f30b3aa..05c097759f62 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,13 +322,13 @@ extern unsigned long get_sdram_size(void);
/* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */ #define I2C_PCA9557_ADDR1 0x18 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 173f6205e08f..132786a42368 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,15 +163,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index c99e6ba781a4..824190a41234 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/* * Serial Port configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 8b43fe0c9939..e67da1fe1dc2 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/* * Serial Port configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 7cb10b205db1..b8f3d70e5953 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,15 +294,15 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 3fa2d01dcc2a..777a64eceee0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,15 +267,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index c5a28fadb004..710f105cfad9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,13 +269,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* * I2C diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 795120c02a87..4c60364f7e78 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,13 +229,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* * I2C diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index e3cbc649fa19..ba4a989fc5f7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,15 +89,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 13b1ff3bce6e..25d9c96e164f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,12 +158,12 @@ #endif
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index cb649b598fed..7c5e7ce475ef 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -83,12 +83,12 @@ #define CONSOLE_COLOR_RED 0x001F
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index b7b1cb0cfe19..abd868c14538 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -88,7 +88,7 @@ "echo WARNING: Could not determine device tree to use; fi; \0"
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Ethernet support */
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 08bae9b886f2..452887d6995c 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -136,11 +136,11 @@ #endif /* Regular Boot */
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 7df5f1405512..4af9edafca8f 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -36,12 +36,12 @@ BOOTENV
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b61c8005c33f..4ff8528cf8ad 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -14,7 +14,7 @@ #include <asm/arch/omap.h>
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000
/* I2C Configuration */
@@ -41,7 +41,7 @@ #define V_SCLK (V_OSCK)
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d8b0531673f1..c3b6a3fbda2c 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,9 +16,9 @@
#define CONFIG_IODELAY_RECALIBRATION
-#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_SYS_OMAP_ABE_SYSCK
diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 0eed8db23bd9..3114cf0c4fba 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */
diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 712471111909..f0674456fd0c 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 6a4092a83e2e..f0a02ae17953 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -14,7 +14,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 84bd88f835ae..4f00b3bad3f4 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -21,7 +21,7 @@ * Apalis UART4: NVIDIA UARTC */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 7224bd8d1f49..e3b6956eb5a2 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,7 +33,7 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_CLK 19660800 +#define CFG_SYS_NS16550_CLK 19660800
/* Init Stack Pointer */
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index c0429ae15c4c..1932713f453a 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,7 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33333333 +#define CFG_SYS_NS16550_CLK 33333333
/* * Ethernet PHY configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 31f107a465c1..f29729d09bac 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -181,12 +181,12 @@ /*DFUARGS*/
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index 1bae49e15f35..cba109b74a9f 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_NS16550_COM1 0xf040c000 +#define CFG_SYS_NS16550_COM1 0xf040c000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index 4b41dc220b15..a07f1b7ad0f1 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_NS16550_COM1 0xf040ab00 +#define CFG_SYS_NS16550_COM1 0xf040ab00
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 795de469384c..76189a4d31f7 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -26,7 +26,7 @@ /* 12MB Malloc size */
/* console configuration */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000
/* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 481baff11d9a..9f51b9ca59d2 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,7 +97,7 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK
/* * Serial console configuration. diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1d51bb4e4c48..6b5f650811b8 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -18,7 +18,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 773ce3f6a6f8..1bf6baf75c23 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,8 @@
/* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000
#endif /* CONFIG_DM */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index f3416b534b23..35c5a4f12261 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -22,7 +22,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 0672b7dbbe93..55e2d744c4a0 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -20,7 +20,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index bfa076b5cc98..1e5154af0a15 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -97,12 +97,12 @@ NANDARGS
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* SPL */
diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 63dac1d4a79d..b7511adc09ad 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000
/* Ethernet: davicom DM9000 */ #define CONFIG_DM9000_BASE 0xb6000000 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 0641d5c0a238..8f058213e9e7 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,8 +14,8 @@ #include <asm/arch/omap.h>
/* Serial support */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_COM1 0x44e09000
/* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index b758086b86d5..2ba3c3bc87db 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -13,7 +13,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* NAND support */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index c9d384e2bdbe..ffed71a2e828 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -22,7 +22,7 @@ * Colibri UART-C: NVIDIA UARTB */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f8ba4e828194..4f0188dd19ed 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -94,7 +94,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index e03a24adca4a..24cf554649ba 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -15,7 +15,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 93201be485d6..e1d18a778306 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -27,9 +27,9 @@ #elif (CONFIG_CONS_INDEX == 3) #define CONSOLEDEV "ttyS2" #endif -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_SYS_OMAP_ABE_SYSCK
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 0d61724db8c4..a1400eba1ada 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,8 +20,8 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif
/* UART */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index fe4b02c0ce2c..211dab4d2337 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -17,10 +17,10 @@ #define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif
/* NAND support */ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index bfc0fa5c442c..1d7b171da75a 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,7 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000
/* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index ce3cb20732db..9e092e16ea04 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,7 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000
/* * Ethernet PHY configuration diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 69aa55f86c5f..b846889541c7 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7acdb0fa038e..57b0fc906979 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock()
/* * I2C diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 30ba6065253e..e6e54fba898b 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,8 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif
#ifndef __ASSEMBLY__ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 38860bfd5ca8..7ed1f153c232 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -35,7 +35,7 @@ #define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE
/* serial port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* SPL */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 5434c4f7679f..1f642fbecc3c 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b9c853d7dfef..28372d41590a 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,8 +20,8 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00
#endif
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 148598fab465..b57eb52d1488 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,7 +26,7 @@
/* GPIO */
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3f2dfa640c9c..3579f9c8437b 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,7 +47,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock()
/* * I2C diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bd2f74c1262a..45665115f662 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,7 +227,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif
/* diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 8c43f652ab65..1e2db12a83f2 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock()
/* I2C */
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 06830f401a31..323feb6e3333 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,7 +145,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif
/* diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 7dd5649005b7..587f23be587f 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,7 +28,7 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* Miscellaneous configurable options */
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 2fc06c1dd2dc..6fc509af232c 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 40b4cb964d11..8a3c87c6abdb 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 5668e07d1354..2117b0811686 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,7 +45,7 @@
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 895c566fea2f..c79a50795b8c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,7 +37,7 @@ /* I2C */
/* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b90a84da8ad7..a8d8d8b09e02 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1f733d112dd7..e09e9c82eb8d 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,8 +22,8 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_COM1 0xbe000c00 +#define CFG_SYS_NS16550_CLK 50000000 +#define CFG_SYS_NS16550_COM1 0xbe000c00 #endif
/* Serial common */ diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index da16e3b21a4b..bb12ebfe4fd0 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,8 +14,8 @@
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif
/* Serial common */ diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index eaffe0bf4c95..3da7619d78d7 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,8 +12,8 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_COM1 0x11005200 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005200 +#define CFG_SYS_NS16550_CLK 26000000
/* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 347598868bb5..0f7981a56611 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,8 +12,8 @@ #include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_COM1 0x11005000 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005000 +#define CFG_SYS_NS16550_CLK 26000000
/* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 4f1067c23bbc..e870fc810cb1 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,9 +32,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 6f16e336d146..cc4784232f9b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,12 +40,12 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK
/* * select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c59e10324395..baa452156ecd 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index cce5556fe266..883cc0b99c9e 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -28,7 +28,7 @@
#include <configs/ti_omap5_common.h>
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE
/* MMC ENV related defines */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 81ca68de9bcc..2b47d4ca3768 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -91,7 +91,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 065820689caf..9fc22f0a6cbc 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,13 +319,13 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/include/configs/paz00.h b/include/configs/paz00.h index c12f4d0937d5..a945f4e9b289 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,7 +17,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index ed3201aa3c42..71807837673f 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -50,11 +50,11 @@ "\0"
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE +#define CFG_SYS_NS16550_COM1 UART0_BASE +#define CFG_SYS_NS16550_COM2 UART1_BASE +#define CFG_SYS_NS16550_COM3 UART2_BASE +#define CFG_SYS_NS16550_COM4 UART3_BASE +#define CFG_SYS_NS16550_COM5 UART4_BASE +#define CFG_SYS_NS16550_COM6 UART5_BASE
#endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 09f0ed9b9a1b..99db59c489e0 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index c7f03a1e7543..4887747968f2 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -22,7 +22,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5765f2ccb5e7..c9dd7509cb2a 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,9 +38,9 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_NS16550_COM4 0x481a6000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_COM4 0x481a6000
/* I2C Configuration */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index c29bc448eed6..6054fa42c1a2 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,8 +52,8 @@ * Serial */
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 029f898b64ff..2b2d78b8c8e0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -75,7 +75,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000
/* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1ed0a262bc61..cd2a74fb52d7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -19,16 +19,16 @@ /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 #else -#define CONFIG_SYS_NS16550_CLK 24000000 +#define CFG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE -# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif
/* CPU */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 38a43b726f03..92ee920346bb 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 166666666 +#define CFG_SYS_NS16550_CLK 166666666
/* * Even though the board houses Realtek RTL8211E PHY diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index f8e741ab6fc1..098796637010 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -14,7 +14,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/tec.h b/include/configs/tec.h index 2377b47e0541..ddf753da4a9f 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2915db7f8bf7..92df457e8189 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -26,7 +26,7 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK
#ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 60632c58c67d..9614fe686f6b 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,8 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
/* CPU */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index f2dbe3544a5d..1bd2a1874b86 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
/* allow overwriting serial config and ethaddr */
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fb017771688e..00eb329faa83 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,7 +17,7 @@ #include <asm/arch/omap.h>
/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000
/* * SPL related defines. The Public RAM memory map the ROM defines the diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index aaeea77281b6..119b4c0410c7 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,13 +34,13 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
/* UART Configuration */ -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE
#ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 #endif
/* SPI Configuration */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 80d2a011f0fe..d282c3956e0c 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -26,15 +26,15 @@
/* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200}
/* Select serial console configuration */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #endif
/* Physical Memory Map */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index eb930341c3a8..ce50e35d8d4b 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -27,9 +27,9 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE #endif
/* TWL6030 */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index a1efb57f1b09..c49c177390b3 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -29,7 +29,7 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000
/* * Environment setup diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index b14726ad234f..22d783c325b2 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_CLK 40000000
/* * Command diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b562d44a13ba..e4cbc7da843e 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 02ddc6fb6e0b..338d8af8fb36 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -12,7 +12,7 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ +#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 03aa7adcc0d3..b2dc04a975ad 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -16,7 +16,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 0bd5a1e85228..f7a507768ec1 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -15,7 +15,7 @@
/* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 84e5ba39f148..2107bec6587a 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,8 +19,8 @@ #define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */ -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00
/* RAM */
diff --git a/include/configs/x530.h b/include/configs/x530.h index 318e3680a6e1..a0162cab2190 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,9 +13,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
/* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 7090fcef6804..b93451cbe07a 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,10 +127,10 @@ /* Serial Driver Info */ /*====================*/
-#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ +#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ -#define CONFIG_SYS_NS16550_CLK get_board_sys_clk() +#define CFG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/ /* Ethernet Driver Info */
On Wed, 16 Nov 2022 at 11:13, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 +- arch/arm/include/asm/arch-bcmnsp/configs.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch2.h | 8 +-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 4 +- arch/arm/mach-davinci/da850_lowlevel.c | 6 +- arch/arm/mach-davinci/spl.c | 4 +- arch/arm/mach-keystone/init.c | 4 +- arch/arm/mach-lpc32xx/devices.c | 8 +-- arch/arm/mach-omap2/am33xx/board.c | 32 +++++----- arch/arm/mach-tegra/board.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 12 ++-- arch/powerpc/include/asm/config.h | 2 +- board/Synology/ds109/ds109.c | 10 +-- board/eets/pdu001/mux.c | 12 ++-- board/emulation/qemu-ppce500/qemu-ppce500.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/nokia/rx51/rx51.c | 4 +- drivers/serial/Kconfig | 2 +- drivers/serial/ns16550.c | 8 +-- drivers/serial/serial_mtk.c | 40 ++++++------ drivers/serial/serial_ns16550.c | 64 +++++++++---------- drivers/serial/serial_omap.c | 6 +- include/configs/MPC837XERDB.h | 6 +- include/configs/MPC8548CDS.h | 6 +- include/configs/P1010RDB.h | 6 +- include/configs/P2041RDB.h | 10 +-- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 10 +-- include/configs/T104xRDB.h | 10 +-- include/configs/T208xQDS.h | 10 +-- include/configs/T208xRDB.h | 10 +-- include/configs/T4240RDB.h | 10 +-- include/configs/am335x_evm.h | 12 ++-- include/configs/am335x_guardian.h | 12 ++-- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 12 ++-- include/configs/am335x_sl50.h | 12 ++-- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-tk1.h | 2 +- include/configs/apalis_t30.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 12 ++-- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beaver.h | 2 +- include/configs/bur_am335x_common.h | 4 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/chiliboard.h | 12 ++-- include/configs/ci20.h | 2 +- include/configs/cm_t43.h | 4 +- include/configs/colibri_t20.h | 2 +- include/configs/colibri_t30.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/dra7xx_evm.h | 6 +- .../configs/gardena-smart-gateway-mt7688.h | 4 +- include/configs/harmony.h | 4 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron_sl28.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/linkit-smart-7688.h | 4 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/mt7621.h | 4 +- include/configs/mt7628.h | 4 +- include/configs/mt8183.h | 4 +- include/configs/mt8516.h | 4 +- include/configs/mv-common.h | 4 +- include/configs/nokia_rx51.h | 4 +- include/configs/nyan-big.h | 2 +- include/configs/omap5_uevm.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/p1_p2_rdb_pc.h | 6 +- include/configs/paz00.h | 2 +- include/configs/pdu001.h | 12 ++-- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/siemens-am33x-common.h | 6 +- include/configs/sniper.h | 4 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/sunxi-common.h | 14 ++-- include/configs/tb100.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/ti814x_evm.h | 4 +- include/configs/ti816x_evm.h | 4 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +-- include/configs/ti_omap3_common.h | 8 +-- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- include/configs/vocore2.h | 4 +- include/configs/x530.h | 4 +- include/configs/xtfpga.h | 4 +- 134 files changed, 347 insertions(+), 347 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 4 +- .../include/asm/arch-fsl-layerscape/config.h | 12 +-- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/cpu/mpc85xx/fdt.c | 4 +- arch/powerpc/cpu/mpc85xx/liodn.c | 6 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 6 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 4 +- arch/powerpc/include/asm/config_mpc85xx.h | 80 +++++++++---------- arch/powerpc/include/asm/fsl_portals.h | 2 +- board/freescale/ls1043aqds/eth.c | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 4 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 4 +- board/freescale/t4rdb/eth.c | 12 +-- board/freescale/t4rdb/t4rdb.h | 8 +- cmd/i2c.c | 6 +- drivers/i2c/i2c_core.c | 6 +- drivers/misc/fsl_portals.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/net/fm/fm.h | 4 +- drivers/net/fm/init.c | 48 +++++------ include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/e500.h | 2 +- include/fm_eth.h | 6 +- include/i2c.h | 2 +- 43 files changed, 138 insertions(+), 138 deletions(-)
diff --git a/README b/README index 9086207954ea..efb1d37df9a6 100644 --- a/README +++ b/README @@ -923,7 +923,7 @@ The following options need to be configured: with a list of GPIO LEDs that have inverted polarity.
- I2C Support: - CONFIG_SYS_NUM_I2C_BUSES + CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS @@ -940,7 +940,7 @@ The following options need to be configured: hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and - CONFIG_SYS_NUM_I2C_BUSES = 9: + CFG_SYS_NUM_I2C_BUSES = 9:
CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff752c21b14d..0669222fed7f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -209,9 +209,9 @@
/* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 7 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@@ -255,9 +255,9 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index aef615873343..c11018d73294 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -160,7 +160,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif unsigned long freq_qman; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index bad18d778aa0..a4e971ebbd70 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -306,7 +306,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49a1aac42b53..b0363c9c1028 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -264,7 +264,7 @@ int checkcpu (void) #endif
#ifdef CONFIG_SYS_DPAA_FMAN - for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + for (i = 0; i < CFG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 47bea512c928..2c320b202ea2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -162,7 +162,7 @@ void disable_cpc_sram(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
- for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -232,7 +232,7 @@ void enable_cpc(void) have_hwconfig = true; }
- for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (have_hwconfig) { sprintf(cpc_subarg, "cpc%u", i + 1); cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); @@ -273,7 +273,7 @@ static void invalidate_cpc(void) int i; cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
- for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { /* skip CPC when it used as all SRAM */ if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) continue; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6dd61caf1c47..32348b4e147f 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -167,7 +167,7 @@ static inline void ft_fixup_l3cache(void *blob, int off) cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; u32 cfg0 = in_be32(&cpc->cpccfg0);
- size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC; num_ways = CPC_CFG0_NUM_WAYS(cfg0); line_size = CPC_CFG0_LINE_SZ(cfg0); num_sets = size / (line_size * num_ways); @@ -469,7 +469,7 @@ static void ft_fixup_dpaa_clks(void *blob) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET, sysinfo.freq_fman[0]);
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET, sysinfo.freq_fman[1]); #endif diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 9ad48d440f92..abc14fae4ec0 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -104,7 +104,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, fm = (void *)CFG_SYS_FSL_FM1_ADDR; break;
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) case FSL_HW_PORTAL_FMAN2: fm = (void *)CFG_SYS_FSL_FM2_ADDR; break; @@ -201,7 +201,7 @@ void set_liodns(void) setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz);
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); @@ -373,7 +373,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8a8334667824..2b790868e126 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -66,7 +66,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 2, 12), SET_FMAN_RX_1G_LIODN(1, 3, 13), SET_FMAN_RX_1G_LIODN(1, 4, 14), -#if (CONFIG_SYS_NUM_FM1_10GEC == 1) +#if (CFG_SYS_NUM_FM1_10GEC == 1) SET_FMAN_RX_10G_LIODN(1, 0, 15), #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 5b766f1d5171..ba54b0310a7b 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -62,7 +62,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index e3d163af9eb9..6f11c81aba5d 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -57,7 +57,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), #endif -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), #endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 31d048192767..e2bdc2f9f112 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -406,7 +406,7 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[0] = sys_info->freq_systembus / 2; break; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 #ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 @@ -440,7 +440,7 @@ void get_sys_info(sys_info_t *sys_info) break; } #endif -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CFG_SYS_NUM_FMAN == 2 */ #else sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; #endif @@ -491,7 +491,7 @@ void get_sys_info(sys_info_t *sys_info) } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 172dbdbe4649..8fe4e96a1140 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -122,7 +122,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), @@ -175,7 +175,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 25d1b4861746..2edf0d6f83c2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -41,8 +41,8 @@ #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -65,9 +65,9 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -75,9 +75,9 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -85,11 +85,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -98,11 +98,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 5 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 5 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
@@ -119,21 +119,21 @@ #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 2 #else -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 1 #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FMAN 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 3 @@ -146,7 +146,7 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -155,23 +155,23 @@ #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 0 #endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -186,9 +186,9 @@ #elif defined(CONFIG_ARCH_T1024) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 @@ -200,12 +200,12 @@ #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index b1fd6bd5cef6..54ef4fb62954 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -11,7 +11,7 @@ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, #ifdef CONFIG_SYS_DPAA_FMAN FSL_HW_PORTAL_FMAN1, -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) FSL_HW_PORTAL_FMAN2, #endif #endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 6783ebebb59e..645c56c73d53 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -427,7 +427,7 @@ int board_eth_init(struct bd_info *bis) break; }
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 00ff6028e69f..3cae2a08677c 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis) }
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev);
/* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 88265a399487..926bd74ddc67 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -349,7 +349,7 @@ int board_eth_init(struct bd_info *bis) /* SGMII on slot 4, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 04fa57f81b29..af70d1077344 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) }
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev);
/* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23fd619ceed3..23ec32b7f975 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -162,7 +162,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index be42efa5c764..ed6b36339f74 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -85,7 +85,7 @@ int board_eth_init(struct bd_info *bis) break; }
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) } }
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index bb6641b88a99..5ce24b40964f 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -39,7 +39,7 @@ int board_eth_init(struct bd_info *bis) /* * Program on board RGMII, SGMII PHY addresses. */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 555985b6f251..62261f50ea94 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -625,7 +625,7 @@ int board_eth_init(struct bd_info *bis) break; }
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { @@ -673,7 +673,7 @@ int board_eth_init(struct bd_info *bis) } }
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 4041b3d9ac4c..241ee5a4a253 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -81,7 +81,7 @@ int board_eth_init(struct bd_info *bis) fm_disable_port(FM1_DTSEC5); fm_disable_port(FM1_DTSEC6);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -93,7 +93,7 @@ int board_eth_init(struct bd_info *bis) } }
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis) } }
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); @@ -121,7 +121,7 @@ int board_eth_init(struct bd_info *bis)
fm_disable_port(FM2_DTSEC5); fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -133,7 +133,7 @@ int board_eth_init(struct bd_info *bis) } }
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -143,7 +143,7 @@ int board_eth_init(struct bd_info *bis) break; } } -#endif /* CONFIG_SYS_NUM_FMAN */ +#endif /* CFG_SYS_NUM_FMAN */
cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h index 06779f552fac..bb3ce216d7d7 100644 --- a/board/freescale/t4rdb/t4rdb.h +++ b/board/freescale/t4rdb/t4rdb.h @@ -6,10 +6,10 @@ #ifndef __T4RDB_H__ #define __T4RDB_H__
-#undef CONFIG_SYS_NUM_FM1_DTSEC -#undef CONFIG_SYS_NUM_FM2_DTSEC -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#undef CFG_SYS_NUM_FM1_DTSEC +#undef CFG_SYS_NUM_FM2_DTSEC +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 diff --git a/cmd/i2c.c b/cmd/i2c.c index e196a73efa69..7b84378f7cd2 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1697,7 +1697,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #else int i;
- for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) { + for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; @@ -1730,7 +1730,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, } show_bus(bus); #else - if (i >= CONFIG_SYS_NUM_I2C_BUSES) { + if (i >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", i); return -1; } @@ -1788,7 +1788,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, } else { bus_no = dectoul(argv[1], NULL); #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", bus_no); return -1; } diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 09f91e674d44..c3f6a1251f15 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -34,7 +34,7 @@ struct i2c_adapter *i2c_get_adapter(int index) }
#if !defined(CONFIG_SYS_I2C_DIRECT_BUS) -struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] = +struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = CONFIG_SYS_I2C_BUSES; #endif
@@ -173,7 +173,7 @@ static int i2c_mux_disconnect_all(void) */ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr) { - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) return;
I2C_ADAP->init(I2C_ADAP, speed, slaveaddr); @@ -238,7 +238,7 @@ int i2c_set_bus_num(unsigned int bus) return 0;
#ifndef CONFIG_SYS_I2C_DIRECT_BUS - if (bus >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus >= CFG_SYS_NUM_I2C_BUSES) return -1; #endif
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 30a9409e5ab2..9c4b4d7e46dd 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -257,7 +257,7 @@ defined(CONFIG_ARCH_LS1046A) #endif
#ifdef CONFIG_SYS_DPAA_FMAN - for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + for (j = 0; j < CFG_SYS_NUM_FMAN; j++) { char name[] = "fman@0";
name[sizeof(name) - 2] = '0' + j; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 9b6dbe2882fd..1d3b7aa05836 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -26,7 +26,7 @@ #include <asm/arch/cpu.h> #endif
-struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; +struct fm_muram muram[CFG_SYS_NUM_FMAN];
void *fm_muram_base(int fm_idx) { diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 2379b3a11cab..3d9cc5ca069d 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -15,11 +15,11 @@ #define OH_PORT_ID_BASE 0x01 #define MAX_NUM_OH_PORT 7 #define RX_PORT_1G_BASE 0x08 -#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_RX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define RX_PORT_10G_BASE 0x10 #define RX_PORT_10G_BASE2 0x08 #define TX_PORT_1G_BASE 0x28 -#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_TX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define TX_PORT_10G_BASE 0x30 #define TX_PORT_10G_BASE2 0x28 #define MIIM_TIMEOUT 0xFFFF diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 34f3816e65af..8443cbb6b65f 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -19,70 +19,70 @@
#ifndef CONFIG_DM_ETH struct fm_eth_info fm_info[] = { -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1) +#if (CFG_SYS_NUM_FM1_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2) +#if (CFG_SYS_NUM_FM1_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3) +#if (CFG_SYS_NUM_FM1_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4) +#if (CFG_SYS_NUM_FM1_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(1, 4), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) +#if (CFG_SYS_NUM_FM1_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(1, 5), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6) +#if (CFG_SYS_NUM_FM1_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(1, 6), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7) +#if (CFG_SYS_NUM_FM1_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(1, 9), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8) +#if (CFG_SYS_NUM_FM1_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(1, 10), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) +#if (CFG_SYS_NUM_FM2_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2) +#if (CFG_SYS_NUM_FM2_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(2, 2), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3) +#if (CFG_SYS_NUM_FM2_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(2, 3), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) +#if (CFG_SYS_NUM_FM2_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(2, 4), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) +#if (CFG_SYS_NUM_FM2_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(2, 5), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6) +#if (CFG_SYS_NUM_FM2_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(2, 6), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7) +#if (CFG_SYS_NUM_FM2_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(2, 9), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8) +#if (CFG_SYS_NUM_FM2_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(2, 10), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) +#if (CFG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 2) +#if (CFG_SYS_NUM_FM1_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) FM_TGEC_INFO_INITIALIZER2(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) +#if (CFG_SYS_NUM_FM1_10GEC >= 4) FM_TGEC_INFO_INITIALIZER2(1, 4), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 1) +#if (CFG_SYS_NUM_FM2_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 2) +#if (CFG_SYS_NUM_FM2_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(2, 2), #endif }; @@ -101,7 +101,7 @@ int fm_standard_init(struct bd_info *bis) fm_eth_initialize(reg, &fm_info[i]); }
-#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) reg = (void *)CFG_SYS_FSL_FM2_ADDR; if (fm_init_common(1, reg)) return 0; @@ -276,7 +276,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 132786a42368..6b83b021f77e 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -30,7 +30,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b8f3d70e5953..c4fed68273b5 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,7 +15,7 @@
/* High Level Configuration Options */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 777a64eceee0..1eec94542100 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -58,7 +58,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 710f105cfad9..42a0926329e9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -22,7 +22,7 @@
/* High Level Configuration Options */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4c60364f7e78..941efdc243f8 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,7 +17,7 @@
/* High Level Configuration Options */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ba4a989fc5f7..5969854796ec 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -39,7 +39,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index a658cbc07c20..ab0d0a721af1 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/* I2C */ -#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CFG_SYS_NUM_I2C_BUSES 4 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 57b0fc906979..ad9853ab6b3b 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -156,7 +156,7 @@
#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e6e54fba898b..7af65737ff01 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -136,7 +136,7 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 diff --git a/include/e500.h b/include/e500.h index 255f46bf1e54..9f68a834c2f0 100644 --- a/include/e500.h +++ b/include/e500.h @@ -19,7 +19,7 @@ typedef struct unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/include/fm_eth.h b/include/fm_eth.h index 7475b5150738..aeb640925ee2 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -56,7 +56,7 @@ enum fm_eth_type { #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000) #endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000) #endif @@ -102,7 +102,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -131,7 +131,7 @@ enum fm_eth_type { #endif #endif
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ diff --git a/include/i2c.h b/include/i2c.h index e0ee94e55046..c07e60b04bd0 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -637,7 +637,7 @@ void i2c_early_init_f(void); /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 #define CONFIG_SYS_I2C_MAX_HOPS 0 -#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) +#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ #undef CONFIG_SYS_I2C_DIRECT_BUS
On Wed, 16 Nov 2022 at 11:11, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
README | 4 +- .../include/asm/arch-fsl-layerscape/config.h | 12 +-- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/cpu/mpc85xx/fdt.c | 4 +- arch/powerpc/cpu/mpc85xx/liodn.c | 6 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 6 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 4 +- arch/powerpc/include/asm/config_mpc85xx.h | 80 +++++++++---------- arch/powerpc/include/asm/fsl_portals.h | 2 +- board/freescale/ls1043aqds/eth.c | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 4 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 4 +- board/freescale/t4rdb/eth.c | 12 +-- board/freescale/t4rdb/t4rdb.h | 8 +- cmd/i2c.c | 6 +- drivers/i2c/i2c_core.c | 6 +- drivers/misc/fsl_portals.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/net/fm/fm.h | 4 +- drivers/net/fm/init.c | 48 +++++------ include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/e500.h | 2 +- include/fm_eth.h | 6 +- include/i2c.h | 2 +- 43 files changed, 138 insertions(+), 138 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
These RTC drivers are currently unused and reference other unused CONFIG variables, so remove them.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 1 - drivers/rtc/Makefile | 3 - drivers/rtc/ds1556.c | 179 ------------------------------------------- drivers/rtc/ds164x.c | 171 ----------------------------------------- drivers/rtc/ds174x.c | 172 ----------------------------------------- 5 files changed, 526 deletions(-) delete mode 100644 drivers/rtc/ds1556.c delete mode 100644 drivers/rtc/ds164x.c delete mode 100644 drivers/rtc/ds174x.c
diff --git a/README b/README index efb1d37df9a6..5ab042a2defb 100644 --- a/README +++ b/README @@ -473,7 +473,6 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC - CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 009dd9d28c95..2089086551d1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -17,9 +17,6 @@ obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1388) += ds1337.o -obj-$(CONFIG_RTC_DS1556) += ds1556.o -obj-$(CONFIG_RTC_DS164x) += ds164x.o -obj-$(CONFIG_RTC_DS174x) += ds174x.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c deleted file mode 100644 index 687b32937a08..000000000000 --- a/drivers/rtc/ds1556.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * modified for DS1556: - * Frank Panno fpanno@delphintech.com, Delphin Technology AG - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS1556 RTC - */ - -/*#define RTC_DEBUG */ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -#if defined(CONFIG_CMD_DATE) - -static uchar rtc_read( unsigned int addr ); -static void rtc_write( unsigned int addr, uchar val); - -#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) - -#define RTC_YEAR ( RTC_BASE + 0xf ) -#define RTC_MONTH ( RTC_BASE + 0xe ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 0xd ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 0xc ) -#define RTC_HOURS ( RTC_BASE + 0xb ) -#define RTC_MINUTES ( RTC_BASE + 0xa ) -#define RTC_SECONDS ( RTC_BASE + 0x9 ) -#define RTC_CENTURY ( RTC_BASE + 0x8 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_BASE - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x10 -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon/cent: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, century, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year from century and year in century */ - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b, reg_c; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n" ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = *(volatile unsigned char*)(addr); -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - *(volatile unsigned char*)(addr) = val; -} - -#endif diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c deleted file mode 100644 index f8707892e71f..000000000000 --- a/drivers/rtc/ds164x.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * modified for DS164x: - * The LEOX team team@leox.org, http://www.leox.org - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS164x RTC - */ - -/* #define RTC_DEBUG */ - -#include <common.h> -#include <command.h> -#include <rtc.h> - - -static uchar rtc_read(unsigned int addr ); -static void rtc_write(unsigned int addr, uchar val); - -#define RTC_EPOCH 2000 /* century */ - -/* - * DS164x registers layout - */ -#define RTC_BASE ( CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE ) - -#define RTC_YEAR ( RTC_BASE + 0x07 ) -#define RTC_MONTH ( RTC_BASE + 0x06 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 ) -#define RTC_HOURS ( RTC_BASE + 0x03 ) -#define RTC_MINUTES ( RTC_BASE + 0x02 ) -#define RTC_SECONDS ( RTC_BASE + 0x01 ) -#define RTC_CONTROL ( RTC_BASE + 0x00 ) - -#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */ -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 -#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */ -#define RTC_CB_OSC_DISABLE 0x80 -#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */ -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year in century (2000) */ - tmp->tm_year = bcd2bin( year ) + RTC_EPOCH; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = *(volatile unsigned char*)(addr); - -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - *(volatile unsigned char*)(addr) = val; -} diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c deleted file mode 100644 index 94f943d97a5e..000000000000 --- a/drivers/rtc/ds174x.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS174x RTC - */ - -/*#define DEBUG*/ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -static uchar rtc_read( unsigned int addr ); -static void rtc_write( unsigned int addr, uchar val); - -#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) - -#define RTC_YEAR ( RTC_BASE + 7 ) -#define RTC_MONTH ( RTC_BASE + 6 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) -#define RTC_HOURS ( RTC_BASE + 3 ) -#define RTC_MINUTES ( RTC_BASE + 2 ) -#define RTC_SECONDS ( RTC_BASE + 1 ) -#define RTC_CENTURY ( RTC_BASE + 0 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_DAY_OF_WEEK - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x80 -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon_cent, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year from century and year in century */ - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b, reg_c; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n" ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = in8( addr ); -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - out8( addr, val ); -}
On Wed, 16 Nov 2022 at 11:11, Tom Rini trini@konsulko.com wrote:
These RTC drivers are currently unused and reference other unused CONFIG variables, so remove them.
Signed-off-by: Tom Rini trini@konsulko.com
README | 1 - drivers/rtc/Makefile | 3 - drivers/rtc/ds1556.c | 179 ------------------------------------------- drivers/rtc/ds164x.c | 171 ----------------------------------------- drivers/rtc/ds174x.c | 172 ----------------------------------------- 5 files changed, 526 deletions(-) delete mode 100644 drivers/rtc/ds1556.c delete mode 100644 drivers/rtc/ds164x.c delete mode 100644 drivers/rtc/ds174x.c
Reviewed-by: Simon Glass sjg@chromium.org
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
Signed-off-by: Tom Rini trini@konsulko.com --- .../asm/arch-fsl-layerscape/immap_lsch2.h | 3 -- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7790.h | 3 -- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 -- .../arm/mach-rmobile/include/mach/rcar-base.h | 9 ------ arch/powerpc/include/asm/immap_85xx.h | 8 ----- include/configs/M5282EVB.h | 6 ---- include/configs/MPC8548CDS.h | 5 ---- include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 4 --- include/configs/T104xRDB.h | 6 ---- include/configs/T208xQDS.h | 5 ---- include/configs/T208xRDB.h | 5 ---- include/configs/T4240RDB.h | 5 ---- include/configs/aristainetos2.h | 2 -- include/configs/eb_cpu5282.h | 30 ------------------- include/configs/highbank.h | 5 ---- include/configs/km/km-mpc8360.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/ls1012a2g5rdb.h | 4 --- include/configs/ls1012a_common.h | 4 --- include/configs/ls1043aqds.h | 4 --- include/configs/ls1046a_common.h | 5 ---- include/configs/p1_p2_rdb_pc.h | 6 ---- include/configs/phycore_am335x_r2.h | 6 ---- include/configs/r2dplus.h | 5 ---- include/configs/socrates.h | 8 ++--- include/configs/ti814x_evm.h | 2 -- include/configs/ti_armv7_keystone2.h | 5 ---- 31 files changed, 2 insertions(+), 157 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index c11018d73294..85ac5eb28138 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
@@ -56,9 +55,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index a4e971ebbd70..59488a04e409 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -194,8 +194,6 @@ /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index ef74d59fed44..28669e3c7717 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,9 +24,6 @@ #define MSTP11_BITS 0x00000000
/* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#define R8A7790_CUT_ES2X 2 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 681d1ea524b3..37d134c5bf29 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,8 +14,6 @@ */
/* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 31433c369300..85f59d977125 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,8 +15,6 @@ */
/* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 3baa4237c262..2bd6e469c815 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,8 +24,6 @@ #define MSTP11_BITS 0x000001C0
/* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2 diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index 4c98dffa073c..e422e9100a8b 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,15 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C
-/* RCAR-I2C */ -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 - #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c9ced5474c2c..78c0d0549655 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,18 +2662,10 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
-#define CONFIG_SYS_PCI1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) -#define CONFIG_SYS_PCI2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET) #define CONFIG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) #define CONFIG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_PCIE3_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET) -#define CONFIG_SYS_PCIE4_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
#define CONFIG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e191dc615bc2..925d26eaf10d 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -130,13 +130,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000
#define CONFIG_SYS_PEHLPAR 0xC0 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bde8fa8df4dd..c29e63c54ed8 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -256,21 +256,16 @@ */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6b83b021f77e..c83298107869 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -248,8 +248,6 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
/* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -276,9 +274,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index c4fed68273b5..e21639a6951b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -349,8 +349,6 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif #endif /* CONFIG_PCI */
@@ -391,9 +389,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 1eec94542100..a3d04882f0d6 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -325,16 +325,12 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif
/* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif #endif /* CONFIG_PCI */
@@ -364,9 +360,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 42a0926329e9..72052be78a92 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -359,13 +359,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -385,9 +382,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 941efdc243f8..c798e4487a4d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -313,13 +313,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -339,9 +336,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5969854796ec..5777df8e5076 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -121,13 +121,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
/* * Miscellaneous configurable options @@ -337,9 +334,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1f2b3b58ca69..35e8840a92a0 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -30,8 +30,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ "hab_check_addr=" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index aaa2ef039d94..80a820c913b7 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -137,13 +137,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000
#define CONFIG_SYS_PASPAR 0x0F0F #define CONFIG_SYS_PEHLPAR 0xC0 @@ -160,29 +154,5 @@ #define CONFIG_I2C_RTC_ADDR 0x68 #endif
-/*----------------------------------------------------------------------- - * VIDEO configuration - */ - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 -#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 -#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 - -#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 - -#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 - -#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE -#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE -#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e2b50bbac10..a7d21a76dba5 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,11 +14,6 @@ * Miscellaneous configurable options */
-/* Environment data setup -*/ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - #define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 92e046d02d72..fb43fb81bc07 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -72,4 +72,3 @@ * PAXE on the local bus CS3 */ #define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index ab0d0a721af1..7d36a25dc232 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -8,7 +8,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0248e646462..196e024b57e0 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -11,10 +11,6 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x40000000
-/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index b57eb52d1488..809f9ae8c8dc 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -18,10 +18,6 @@ /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000
-/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* I2C */
/* GPIO */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 3b51cb8f174a..87751f786c8b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -35,10 +35,6 @@ #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif
-/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* * IFC Definitions */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8a3c87c6abdb..3934fbbb41d1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -65,11 +65,6 @@
/* I2C */
-/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_SYS_SATA AHCI_BASE_ADDR -#endif - /* FMan ucode */ #ifndef SPL_NO_FMAN #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9fc22f0a6cbc..44e608536fe8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -279,12 +279,6 @@ #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE #endif
-#define CONFIG_SYS_VSC7385_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - /* The size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index c5817b010f8a..43a60825b575 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -97,10 +97,4 @@
#endif /* !CONFIG_MTD_RAW_NAND */
-/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - #endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ac39e11a99e1..406ee6282c5f 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -18,9 +18,4 @@ #define CONFIG_SYS_FLASH_BASE (0xA0000000) #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-/* - * SuperH Clock setting - */ -#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ - #endif /* __CONFIG_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 388a4e42efb9..9b106fc1c97e 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,12 +109,8 @@ * Memory space is mapped 1-1. */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 9614fe686f6b..fc78077014b5 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -84,8 +84,6 @@
/* Defines for SPL */
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 - /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 119b4c0410c7..65abb187d96d 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -46,11 +46,6 @@ /* SPI Configuration */ #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
-/* Network Configuration */ -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 - /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
On Wed, 16 Nov 2022 at 11:11, Tom Rini trini@konsulko.com wrote:
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
Signed-off-by: Tom Rini trini@konsulko.com
.../asm/arch-fsl-layerscape/immap_lsch2.h | 3 -- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7790.h | 3 -- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 -- .../arm/mach-rmobile/include/mach/rcar-base.h | 9 ------ arch/powerpc/include/asm/immap_85xx.h | 8 ----- include/configs/M5282EVB.h | 6 ---- include/configs/MPC8548CDS.h | 5 ---- include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 4 --- include/configs/T104xRDB.h | 6 ---- include/configs/T208xQDS.h | 5 ---- include/configs/T208xRDB.h | 5 ---- include/configs/T4240RDB.h | 5 ---- include/configs/aristainetos2.h | 2 -- include/configs/eb_cpu5282.h | 30 ------------------- include/configs/highbank.h | 5 ---- include/configs/km/km-mpc8360.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/ls1012a2g5rdb.h | 4 --- include/configs/ls1012a_common.h | 4 --- include/configs/ls1043aqds.h | 4 --- include/configs/ls1046a_common.h | 5 ---- include/configs/p1_p2_rdb_pc.h | 6 ---- include/configs/phycore_am335x_r2.h | 6 ---- include/configs/r2dplus.h | 5 ---- include/configs/socrates.h | 8 ++--- include/configs/ti814x_evm.h | 2 -- include/configs/ti_armv7_keystone2.h | 5 ---- 31 files changed, 2 insertions(+), 157 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_OMAP_ABE_SYSCK
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-omap2/omap5/Kconfig | 1 + include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 78317e474dbf..3bf972052260 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -144,6 +144,9 @@ config SYS_MPUCLK help Defines the MPU clock speed (in MHz).
+config SYS_OMAP_ABE_SYSCK + bool + config TI_SECURE_EMIF_REGION_START hex "Reserved EMIF region start address" depends on TI_SECURE_DEVICE diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 4c2f990b2878..18a66764224d 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -2,6 +2,7 @@ if OMAP54XX
config DRA7XX bool + select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s.
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c3b6a3fbda2c..84555f3b13dc 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -20,8 +20,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e1d18a778306..bb335a0a473c 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -31,8 +31,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \
On Wed, 16 Nov 2022 at 11:11, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_OMAP_ABE_SYSCK
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-omap2/omap5/Kconfig | 1 + include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++---- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++---------- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 24 +++++----- .../asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 24 +++++----- arch/m68k/include/asm/immap.h | 8 ++-- arch/powerpc/cpu/mpc83xx/pcie.c | 10 ++-- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- arch/powerpc/include/asm/fsl_pci.h | 32 ++++++------- arch/powerpc/include/asm/immap_85xx.h | 4 +- board/freescale/common/p_corenet/tlb.c | 12 ++--- board/freescale/mpc8548cds/tlb.c | 6 +-- board/freescale/p1010rdb/tlb.c | 4 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/tlb.c | 10 ++-- board/freescale/t208xrdb/tlb.c | 10 ++-- board/freescale/t4rdb/tlb.c | 12 ++--- board/keymile/kmcent2/tlb.c | 4 +- board/socrates/tlb.c | 4 +- common/fdt_support.c | 4 +- drivers/pci/pci_auto.c | 8 ++-- drivers/pci/pcie_fsl.c | 16 +++---- drivers/pci/pcie_fsl.h | 12 ++--- drivers/pci/pcie_layerscape.h | 16 +++---- drivers/pci/pcie_layerscape_ep.c | 6 +-- drivers/pci/pcie_layerscape_gen4.c | 6 +-- drivers/pci/pcie_layerscape_gen4.h | 8 ++-- include/configs/MPC837XERDB.h | 18 ++++---- include/configs/MPC8548CDS.h | 24 +++++----- include/configs/P1010RDB.h | 24 +++++----- include/configs/P2041RDB.h | 20 ++++---- include/configs/T102xRDB.h | 20 ++++---- include/configs/T104xRDB.h | 24 +++++----- include/configs/T208xQDS.h | 24 +++++----- include/configs/T208xRDB.h | 24 +++++----- include/configs/T4240RDB.h | 24 +++++----- include/configs/kmcent2.h | 8 ++-- include/configs/p1_p2_rdb_pc.h | 24 +++++----- include/configs/socrates.h | 4 +- 42 files changed, 299 insertions(+), 299 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d530e0655bc2..d09c21d5d9b2 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -168,18 +168,18 @@ static void mmu_setup(void) /* Level 1 has 512 entries */ for (i = 0; i < 512; i++) { /* Mapping for PCIe 1 */ - if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR && + va_start < (CFG_SYS_PCIE1_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + CFG_SYS_PCIE1_PHYS_BASE + va_start, MT_DEVICE_MEM); /* Mapping for PCIe 2 */ - else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR && + va_start < (CFG_SYS_PCIE2_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + CFG_SYS_PCIE2_PHYS_BASE + va_start, MT_DEVICE_MEM); else set_pgsection(level1_table, i, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c11341a1d380..ef71e2cf2bca 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -257,26 +257,26 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR, + CFG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -368,19 +368,19 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void) (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { - case CONFIG_SYS_PCIE1_PHYS_ADDR: + case CFG_SYS_PCIE1_PHYS_ADDR: final_map[i].phys = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL; final_map[i].size = 0x800000000ULL; break; - case CONFIG_SYS_PCIE2_PHYS_ADDR: + case CFG_SYS_PCIE2_PHYS_ADDR: final_map[i].phys = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - case CONFIG_SYS_PCIE3_PHYS_ADDR: +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + case CFG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - case CONFIG_SYS_PCIE4_PHYS_ADDR: +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + case CFG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4db479140ea2..20f96713871a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -35,17 +35,17 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 #ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000 #else -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CFG_SYS_PCIE3_PHYS_SIZE +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #endif -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 #endif @@ -83,9 +83,9 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 85ac5eb28138..64dc7c88b7f8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
@@ -90,9 +90,9 @@ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) #define QMAN_CQSIDR_REG 0x20a80
-#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ #ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59488a04e409..cd112402e0c8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -192,35 +192,35 @@
/* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL #elif CONFIG_ARCH_LS1088A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL #elif CONFIG_ARCH_LS1028A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL /* this is used by integrated PCI on LS1028, includes ECAM and register space */ -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL +#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL #endif
/* Device Configuration */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 033341dbfb63..62026bda9e2b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -55,22 +55,22 @@
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) - -#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL -#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL -#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL -#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + +#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ /* * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. */ -#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ - CONFIG_SYS_PCIE1_VIRT_ADDR) -#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ - CONFIG_SYS_PCIE2_VIRT_ADDR) +#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \ + CFG_SYS_PCIE1_VIRT_ADDR) +#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \ + CFG_SYS_PCIE2_VIRT_ADDR)
/* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index ead62cd03871..f2eb6fcb463b 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -337,10 +337,10 @@ #define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (0x40000000) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR0 (0x40000000) +#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index d2b6b05bdaf9..47ca74c5c356 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -24,13 +24,13 @@ static struct { u32 size; } mpc83xx_pcie_cfg_space[] = { { - .base = CONFIG_SYS_PCIE1_CFG_BASE, - .size = CONFIG_SYS_PCIE1_CFG_SIZE, + .base = CFG_SYS_PCIE1_CFG_BASE, + .size = CFG_SYS_PCIE1_CFG_SIZE, }, -#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) +#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE) { - .base = CONFIG_SYS_PCIE2_CFG_BASE, - .size = CONFIG_SYS_PCIE2_CFG_SIZE, + .base = CFG_SYS_PCIE2_CFG_BASE, + .size = CFG_SYS_PCIE2_CFG_SIZE, }, #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index abc14fae4ec0..d5df02d39d82 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -387,7 +387,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif
- ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR; int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
if (pci_ver >= 0x0204) { diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 06f9bfb8ac73..809ab1d4187e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno);
#define SET_STD_PCI_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ }
#define SET_STD_PCIE_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ }
#define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR)
#define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR)
#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 78c0d0549655..9ae698743eee 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,9 +2662,9 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
-#define CONFIG_SYS_PCIE1_ADDR \ +#define CFG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) -#define CONFIG_SYS_PCIE2_ADDR \ +#define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_SFP_ADDR \ diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index ef46353a3670..4cdef89bf0ee 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -91,23 +91,23 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 8d1e5fee9365..9c8e94860089 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 4: * PCI and PCIe MEM 1G Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 5: * PCI1 IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 6: * PCIe IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), }; diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index aa7517a74d81..5e1fa70bca55 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -52,12 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_PCI /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 85d41327aa24..4cc5e01f5789 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -45,12 +45,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_PCI /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 8fdff7576fe5..74744c8ab0ad 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -54,12 +54,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 8a3d67449c27..905e4771c91e 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -67,12 +67,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f27faf5d2437..9160674b94fd 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1),
/* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index da03aadb1733..69e58e7e9732 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1),
/* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 059449af1edf..c57af3046f91 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -52,23 +52,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1),
diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 095fc7e96146..0f6dc6063ab1 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -46,12 +46,12 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_128M, 1),
/* *I*G* - PCI1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI1 I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1),
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index de80c3c0e573..1ab403d145e6 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
diff --git a/common/fdt_support.c b/common/fdt_support.c index ebebffc78904..dbceec6f2dcc 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -739,7 +739,7 @@ int fdt_delete_disabled_nodes(void *blob) }
#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4 +#define CFG_SYS_PCI_NR_INBOUND_WIN 4
#define FDT_PCI_PREFETCH (0x40000000) #define FDT_PCI_MEM32 (0x02000000) @@ -751,7 +751,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) { int addrcell, sizecell, len, r; u32 *dma_range; /* sized based on pci addr cells, size-cells, & address-cells */ - u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN]; + u32 dma_ranges[(3 + 2 + 2) * CFG_SYS_PCI_NR_INBOUND_WIN];
addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1); sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1); diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index c7968926a17f..14fd3bbf679e 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -16,9 +16,9 @@ #include <time.h> #include "pci_internal.h"
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ -#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 +/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE +#define CFG_SYS_PCI_CACHE_LINE_SIZE 8 #endif
static void dm_pciauto_setup_device(struct udevice *dev, @@ -178,7 +178,7 @@ static void dm_pciauto_setup_device(struct udevice *dev,
dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, - CONFIG_SYS_PCI_CACHE_LINE_SIZE); + CFG_SYS_PCI_CACHE_LINE_SIZE); dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); }
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a8f8c31bef8f..4600652f2b1b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -343,8 +343,8 @@ static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) { - phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; - pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS; u64 sz = min((u64)gd->ram_size, (1ull << 32)); pci_size_t pci_sz; int idx; @@ -367,8 +367,8 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) sz = 2ull << __ilog2_u64(sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_BUS, sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI_MEMORY_BUS, sz); #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) /* * On 64-bit capable systems, set up a mapping for all of DRAM @@ -380,12 +380,12 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", - (u64)CONFIG_SYS_PCI64_MEMORY_BUS, - (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + (u64)CFG_SYS_PCI64_MEMORY_BUS, + (u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI64_MEMORY_BUS, pci_sz); #endif
return 0; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 70c5f4e4cffe..ba84a232b835 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -28,16 +28,16 @@
#define DBI_RO_WR_EN 0x8bc
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS 0 #endif
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS 0 #endif
-#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) -#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS) +#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) #endif
#define PEX_CSR0_LTSSM_MASK 0xFC diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 8cdf516d9fad..a52774179e2f 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -13,20 +13,20 @@ #include <asm/arch-fsl-layerscape/svr.h> #include <asm/arch-ls102xa/svr.h>
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE #endif
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE #endif
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G #endif
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif
#define PCIE_PHYS_SIZE 0x200000000 diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index f2813aeef67d..ff26a5cd9bee 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -72,7 +72,7 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) u32 vf_flag = 0; u64 phys = 0;
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ @@ -117,8 +117,8 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) /* ATU: OUTBOUND : map MEM */ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, (u64)pcie_ep->addr_res.start + - pf * CONFIG_SYS_PCI_MEMORY_SIZE, - 0, CONFIG_SYS_PCI_MEMORY_SIZE); + pf * CFG_SYS_PCI_MEMORY_SIZE, + 0, CFG_SYS_PCI_MEMORY_SIZE); }
/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 6ecdd6af408c..021c975869fd 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -333,7 +333,7 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1) return;
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; for (bar = 0; bar < PF_BAR_NUM; bar++) { ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys); phys += PCIE_BAR_SIZE; @@ -342,8 +342,8 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) /* OUTBOUND: map MEM */ ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM, pcie->cfg_res.start + - CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0, - CONFIG_SYS_PCI_MEMORY_SIZE); + CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0, + CFG_SYS_PCI_MEMORY_SIZE);
val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf)); val &= ~FUNC_NUM_PCIE_MASK; diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h index 483eb538b5c5..805c23a7da0c 100644 --- a/drivers/pci/pcie_layerscape_gen4.h +++ b/drivers/pci/pcie_layerscape_gen4.h @@ -11,12 +11,12 @@ #include <pci.h> #include <linux/bitops.h>
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) #endif
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif
#define PCIE_PF_NUM 2 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 059885ecb54f..0e70b2853b29 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -177,15 +177,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 - -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000 + +#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
/* * TSEC diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c29e63c54ed8..c59a37646f49 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -254,31 +254,31 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CFG_SYS_PCI1_IO_VIRT 0xe2000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CFG_SYS_PCI1_IO_PHYS 0xe2000000 #endif
#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif #endif
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 05c097759f62..f87e7597ad04 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -68,31 +68,31 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c83298107869..e996dbaa4de7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -234,20 +234,20 @@ */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e21639a6951b..6d6e334bf00f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -331,24 +331,24 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif #endif /* CONFIG_PCI */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a3d04882f0d6..423ba8161702 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -307,30 +307,30 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif
/* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #endif #endif /* CONFIG_PCI */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 72052be78a92..2efc2eb95c47 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -345,24 +345,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c798e4487a4d..ca8bfac0c69d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -299,24 +299,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5777df8e5076..091920dccfe6 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -107,24 +107,24 @@ */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
/* * Miscellaneous configurable options diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 7af65737ff01..1df90def6733 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -346,10 +346,10 @@ int get_scl(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 44e608536fe8..6e8ac1b98df5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -343,31 +343,31 @@ */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif
/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif #endif /* CONFIG_PCI */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 9b106fc1c97e..a60ac6d1a3c5 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,8 +109,8 @@ * Memory space is mapped 1-1. */
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0"
On Wed, 16 Nov 2022 at 11:12, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++---- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++---------- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 24 +++++----- .../asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 24 +++++----- arch/m68k/include/asm/immap.h | 8 ++-- arch/powerpc/cpu/mpc83xx/pcie.c | 10 ++-- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- arch/powerpc/include/asm/fsl_pci.h | 32 ++++++------- arch/powerpc/include/asm/immap_85xx.h | 4 +- board/freescale/common/p_corenet/tlb.c | 12 ++--- board/freescale/mpc8548cds/tlb.c | 6 +-- board/freescale/p1010rdb/tlb.c | 4 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/tlb.c | 10 ++-- board/freescale/t208xrdb/tlb.c | 10 ++-- board/freescale/t4rdb/tlb.c | 12 ++--- board/keymile/kmcent2/tlb.c | 4 +- board/socrates/tlb.c | 4 +- common/fdt_support.c | 4 +- drivers/pci/pci_auto.c | 8 ++-- drivers/pci/pcie_fsl.c | 16 +++---- drivers/pci/pcie_fsl.h | 12 ++--- drivers/pci/pcie_layerscape.h | 16 +++---- drivers/pci/pcie_layerscape_ep.c | 6 +-- drivers/pci/pcie_layerscape_gen4.c | 6 +-- drivers/pci/pcie_layerscape_gen4.h | 8 ++-- include/configs/MPC837XERDB.h | 18 ++++---- include/configs/MPC8548CDS.h | 24 +++++----- include/configs/P1010RDB.h | 24 +++++----- include/configs/P2041RDB.h | 20 ++++---- include/configs/T102xRDB.h | 20 ++++---- include/configs/T104xRDB.h | 24 +++++----- include/configs/T208xQDS.h | 24 +++++----- include/configs/T208xRDB.h | 24 +++++----- include/configs/T4240RDB.h | 24 +++++----- include/configs/kmcent2.h | 8 ++-- include/configs/p1_p2_rdb_pc.h | 24 +++++----- include/configs/socrates.h | 4 +- 42 files changed, 299 insertions(+), 299 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_NOBQFMAN CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN CONFIG_SYS_PMAN
Signed-off-by: Tom Rini trini@konsulko.com --- arch/Kconfig.nxp | 3 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 ++--- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 35 +++++++++++++++++++ include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 3 -- include/configs/T208xQDS.h | 6 ---- include/configs/T208xRDB.h | 6 ---- include/configs/T4240RDB.h | 6 ---- include/configs/kmcent2.h | 3 -- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - 16 files changed, 45 insertions(+), 41 deletions(-)
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 8c5a6f63a9a5..805fe934a1f5 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -251,3 +251,6 @@ config QIXIS_I2C_ACCESS config HAS_FSL_DR_USB def_bool y depends on USB_EHCI_HCD && PPC + +config SYS_DPAA_FMAN + bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ebca11d17419..2862257e1f2c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -69,6 +69,7 @@ config ARCH_LS1043A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -106,6 +107,7 @@ config ARCH_LS1046A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6440ce714fd1..f18407b6d3bb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info) /* rcw_tmp is needed to get FMAN clock, or to get cluster group A * mux 2 clock for LS1043A/LS1046A. */ -#if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_ARCH_LS1046A) || \ - defined(CONFIG_ARCH_LS1043A) - u32 rcw_tmp; -#endif + __maybe_unused u32 rcw_tmp; struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index e972603f24f8..ad20d71717b3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -41,7 +41,7 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz);
-#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 3bd993bebfbc..4880a313ea6a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index abd847b5be02..e47d3af85e07 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 24d3f1f20c25..f2361560e9ad 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -252,6 +252,8 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM select FSL_CORENET + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_L3_SIZE_256KB
endchoice @@ -618,6 +620,9 @@ config ARCH_P2041 select E500MC select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME + select SYS_DPAA_RMAN select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -762,6 +767,7 @@ config ARCH_T1024 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -792,6 +798,8 @@ config ARCH_T1040 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -822,6 +830,8 @@ config ARCH_T1042 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -851,6 +861,10 @@ config ARCH_T2080 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -871,6 +885,7 @@ config ARCH_T2080 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -886,6 +901,10 @@ config ARCH_T4240 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 @@ -907,6 +926,7 @@ config ARCH_T4240 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -947,6 +967,9 @@ config E6500 help Enable PowerPC E6500 core
+config NOBQFMAN + bool + config FSL_LAW bool help @@ -1019,6 +1042,15 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change.
+config SYS_DPAA_PME + bool + +config SYS_DPAA_DCE + bool + +config SYS_DPAA_RMAN + bool + config A003399_NOR_WORKAROUND bool help @@ -1195,6 +1227,9 @@ config FSL_PCIE_DISABLE_ASPM config FSL_PCIE_RESET bool
+config SYS_PMAN + bool + config SYS_FSL_RAID_ENGINE bool
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e996dbaa4de7..8c7b877bfb92 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -36,7 +36,6 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_SYS_DPAA_RMAN /* RMan */
#ifndef __ASSEMBLY__ #include <linux/stringify.h> @@ -281,9 +280,6 @@ #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6d6e334bf00f..154b2f174afb 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -395,8 +395,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 423ba8161702..847cf65b4092 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -366,9 +366,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2efc2eb95c47..b49c26477684 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -388,12 +388,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ca8bfac0c69d..aae41a339254 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -342,12 +342,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 091920dccfe6..9dc45e397f9b 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -340,12 +340,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 1df90def6733..c8423fdfb0ab 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -372,9 +372,6 @@ int get_scl(void); #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6fc509af232c..df6338298b48 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -103,7 +103,6 @@
/* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 3934fbbb41d1..b09588f4796d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -67,7 +67,6 @@
/* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif
On Wed, 16 Nov 2022 at 11:12, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_NOBQFMAN CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN CONFIG_SYS_PMAN
Signed-off-by: Tom Rini trini@konsulko.com
arch/Kconfig.nxp | 3 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 ++--- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 35 +++++++++++++++++++ include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 3 -- include/configs/T208xQDS.h | 6 ---- include/configs/T208xRDB.h | 6 ---- include/configs/T4240RDB.h | 6 ---- include/configs/kmcent2.h | 3 -- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - 16 files changed, 45 insertions(+), 41 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This moves SYS_SATA_FAT_BOOT_PARTITION to Kconfig and enforces the current default via Kconfig rather than C code.
Signed-off-by: Tom Rini trini@konsulko.com --- common/spl/Kconfig | 5 +++++ common/spl/spl_sata.c | 4 ---- include/configs/imx6_spl.h | 5 ----- 3 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 05181bdba3e1..512c1bc721ac 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1232,6 +1232,11 @@ config SPL_SATA expense and power consumption. This enables loading from SATA using a configured device.
+config SYS_SATA_FAT_BOOT_PARTITION + int "Partition on the SATA disk to load U-Boot from" + depends on SPL_SATA && SPL_FS_FAT + default 1 + config SPL_SATA_RAW_U_BOOT_USE_SECTOR bool "SATA raw mode: by sector" depends on SPL_SATA diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 9ae02730685a..12397f0ae17e 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -17,10 +17,6 @@ #include <fat.h> #include <image.h>
-#ifndef CONFIG_SYS_SATA_FAT_BOOT_PARTITION -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR /* Dummy value to make the compiler happy */ #define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100 diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 3afe418b67dc..f34988fdd74c 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -10,11 +10,6 @@
/* MMC support */
-/* SATA support */ -#if defined(CONFIG_SPL_SATA) -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #endif
#endif
On Wed, 16 Nov 2022 at 11:12, Tom Rini trini@konsulko.com wrote:
This moves SYS_SATA_FAT_BOOT_PARTITION to Kconfig and enforces the current default via Kconfig rather than C code.
Signed-off-by: Tom Rini trini@konsulko.com
common/spl/Kconfig | 5 +++++ common/spl/spl_sata.c | 4 ---- include/configs/imx6_spl.h | 5 ----- 3 files changed, 5 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
There are now no flags being set in these files, so remove them.
Signed-off-by: Tom Rini trini@konsulko.com --- include/configs/apalis_imx6.h | 4 ---- include/configs/brppt2.h | 5 ----- include/configs/cl-som-imx7.h | 3 --- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/dart_6ul.h | 3 --- include/configs/dh_imx6.h | 3 --- include/configs/display5.h | 2 -- include/configs/el6x_common.h | 4 ---- include/configs/embestmx6boards.h | 6 ------ include/configs/ge_b1x5v2.h | 2 -- include/configs/gw_ventana.h | 1 - include/configs/imx6-engicam.h | 5 ----- include/configs/imx6_logic.h | 4 ---- include/configs/imx6_spl.h | 15 --------------- include/configs/imx6dl-mamoj.h | 3 --- include/configs/imx6q-bosch-acc.h | 1 - include/configs/imx6ulz_smm_m2.h | 3 --- include/configs/imx7-cm.h | 3 --- include/configs/imx7_spl.h | 19 ------------------- include/configs/kontron-sl-mx6ul.h | 3 --- include/configs/kp_imx6q_tpc.h | 3 --- include/configs/liteboard.h | 3 --- include/configs/mccmon6.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6memcal.h | 1 - include/configs/mx6sabreauto.h | 4 ---- include/configs/mx6sabresd.h | 4 ---- include/configs/mx6slevk.h | 4 ---- include/configs/mx6sxsabresd.h | 4 ---- include/configs/mx6ul_14x14_evk.h | 3 --- include/configs/mys_6ulx.h | 3 --- include/configs/novena.h | 3 --- include/configs/npi_imx6ull.h | 3 --- include/configs/opos6uldev.h | 4 ---- include/configs/pcl063.h | 3 --- include/configs/pcl063_ull.h | 3 --- include/configs/pcm058.h | 4 ---- include/configs/pico-imx6.h | 8 -------- include/configs/pico-imx6ul.h | 7 ------- include/configs/pico-imx7d.h | 8 -------- include/configs/somlabs_visionsom_6ull.h | 4 ---- include/configs/tqma6.h | 7 ------- include/configs/udoo.h | 2 -- include/configs/udoo_neo.h | 2 -- include/configs/vining_2000.h | 4 ---- include/configs/wandboard.h | 2 -- include/configs/xpress.h | 3 --- 48 files changed, 196 deletions(-) delete mode 100644 include/configs/imx6_spl.h delete mode 100644 include/configs/imx7_spl.h
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 192c9cf0c30c..30d32d27e3dc 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,10 +15,6 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h>
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 0c7fe5f3abba..bdedf7ea2d78 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -86,9 +86,4 @@ BUR_COMMON_ENV \ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" - -#endif /* CONFIG_SPL */ #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cbf85341a64d..fc45e597f6d1 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -101,7 +101,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0
-/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 2cb09fa30da2..25443629e208 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -143,9 +143,6 @@
/* misc */
-/* SPL */ -#include "imx6_spl.h" - /* Display */ #define CONFIG_IMX_HDMI
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14fdf5b50e66..68d923c1ae19 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,10 +15,6 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h>
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 6079596caec0..b944d50663ce 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -10,9 +10,6 @@ #include <linux/stringify.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - /* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 54b2192b4a83..e694dd7551ae 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -21,9 +21,6 @@ * 0x12_0000-0x1f_ffff ... UNUSED */
-/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */
/* MMC Configs */ diff --git a/include/configs/display5.h b/include/configs/display5.h index eb65f17cbe48..0e5ecab9feb2 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -34,8 +34,6 @@ #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x10000
-#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART5_BASE
/* I2C Configs */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index affe20a10198..16d2648e11f3 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -12,10 +12,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 555239b8e813..a4891ddbc4ff 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -49,12 +49,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -/* RiOTboard */ - -#endif - /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 176f80bb09b7..c862f15ee2b4 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,8 +12,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a9ef35ebeb6c..645ca162a35a 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -13,7 +13,6 @@
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h"
/* Serial */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index e430efad42e3..b8eb5c82cf7e 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -142,9 +142,4 @@ # define CONFIG_IMX_VIDEO_SKIP #endif
-/* SPL */ -#ifdef CONFIG_SPL -# include "imx6_spl.h" -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 7760c8c418a1..6b822e725058 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -11,10 +11,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h"
/* MMC Configs */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h deleted file mode 100644 index f34988fdd74c..000000000000 --- a/include/configs/imx6_spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey tharvey@gateworks.com - */ -#ifndef __IMX6_SPL_CONFIG_H -#define __IMX6_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif - -#endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 909453cd66f4..f7f8f33ed898 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -59,7 +59,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* SPL */ -#include "imx6_spl.h" - #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 5025ad9d9f2e..15171d7ad67b 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -91,7 +91,6 @@
/* SPL */ #ifdef CONFIG_SPL -#include "imx6_spl.h"
#ifdef CONFIG_SPL_BUILD #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index d42eb750d01b..70b4b84215d3 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> #include <linux/stringify.h>
-/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART4_BASE
#ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index caa6a11d4077..c6db5e943eea 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -83,7 +83,4 @@
#define CONFIG_USBD_HS
-/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h deleted file mode 100644 index 362b98075f05..000000000000 --- a/include/configs/imx7_spl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL definitions for the i.MX7 SPL - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#ifndef __IMX7_SPL_CONFIG_H -#define __IMX7_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif /* CONFIG_SPL */ - -#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index d3447a80ca56..b3e1fc2a864e 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -11,9 +11,6 @@ #include <linux/sizes.h>
#include "mx6_common.h" -#ifdef CONFIG_SPL_BUILD -#include "imx6_spl.h" -#endif
/* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1823a7939882..b0e49ad6df07 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -12,9 +12,6 @@
#include "mx6_common.h"
-/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */
/* FEC ethernet */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a784002158b0..1d51b87b68b3 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 69ca7c527534..f9f0825f6f81 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,8 +9,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
/* diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index bc90b9563ade..1db4d6c01b17 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -11,8 +11,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index ad53f17d6716..a6cefab5508a 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -11,7 +11,6 @@ /* SPL */
#include "mx6_common.h" -#include "imx6_spl.h"
#ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 8176566f3f61..3fdf829e9686 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,10 +8,6 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3"
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 49cd1512dc58..0d06b6dc4671 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,10 +8,6 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0"
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 26b97bd3f2e4..ca1d077437b7 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,10 +10,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 83779f09bfc6..c655671ee1bd 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,10 +12,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE
#ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d0e3d3f02849..65f0a5c99662 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,9 +15,6 @@
#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
-/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index e18d16cc99c7..273f938554de 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index f2a04ca61854..9dc05d80ec2c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -34,9 +34,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* I2C */ #define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 2a5288508299..ea407c9f6f1a 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 3e551e13aa67..b3cdd2f1ebe3 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -10,10 +10,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index bc04c5082188..6267dc729ab6 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - /* * There is a bug in some i.MX6UL processors that results in the initial * portion of OCRAM being unavailable when booting from (at least) an SD diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 817fabfb97ce..e13b5df0fabd 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h"
-/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 2
/* Environment settings */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 01190904cf6f..14cbfde28bfe 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -6,10 +6,6 @@ #ifndef __PCM058_CONFIG_H #define __PCM058_CONFIG_H
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 687133b9bdda..f95beeb214a9 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,14 +10,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d4f58b6a7b04..85772ba6e838 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -12,13 +12,6 @@ #include <linux/sizes.h> #include "mx6_common.h" #include <asm/mach-imx/gpio.h> -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif
/* Network support */
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 159bf4c68ca5..b3a38d8a940a 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,14 +10,6 @@
#include "mx7_common.h"
-#include "imx7_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 49672dfe7c3f..dcb88a3a730a 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -13,10 +13,6 @@ #include "mx6_common.h" #include <asm/mach-imx/gpio.h>
-/* SPL options */ -#include "imx6_spl.h" - - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2c5891589525..a65ebfb4deab 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -11,13 +11,6 @@ #include <linux/kconfig.h> #include <linux/stringify.h>
-/* SPL */ -/* #if defined(CONFIG_SPL_BUILD) */ -/* common IMX6 SPL configuration */ -#include "imx6_spl.h" - -/* #endif */ - /* place code in last 4 MiB of RAM */
#include "mx6_common.h" diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 8af5151c503d..268c737e7eb7 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,8 +10,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configuration */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 093e2e8dae7c..147224806fcc 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -12,8 +12,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a4484fd3f8ca..a0846b3f7c96 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -10,10 +10,6 @@
#include "mx6_common.h"
-#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 91c1f4b3b514..b4c757fd9217 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,8 +10,6 @@
#include "mx6_common.h"
-#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index fc8ec3204b1b..7d0402feead5 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include <asm/mach-imx/gpio.h>
-/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
/* MMC Configs */
On Wed, 16 Nov 2022 at 11:12, Tom Rini trini@konsulko.com wrote:
There are now no flags being set in these files, so remove them.
Signed-off-by: Tom Rini trini@konsulko.com
include/configs/apalis_imx6.h | 4 ---- include/configs/brppt2.h | 5 ----- include/configs/cl-som-imx7.h | 3 --- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/dart_6ul.h | 3 --- include/configs/dh_imx6.h | 3 --- include/configs/display5.h | 2 -- include/configs/el6x_common.h | 4 ---- include/configs/embestmx6boards.h | 6 ------ include/configs/ge_b1x5v2.h | 2 -- include/configs/gw_ventana.h | 1 - include/configs/imx6-engicam.h | 5 ----- include/configs/imx6_logic.h | 4 ---- include/configs/imx6_spl.h | 15 --------------- include/configs/imx6dl-mamoj.h | 3 --- include/configs/imx6q-bosch-acc.h | 1 - include/configs/imx6ulz_smm_m2.h | 3 --- include/configs/imx7-cm.h | 3 --- include/configs/imx7_spl.h | 19 ------------------- include/configs/kontron-sl-mx6ul.h | 3 --- include/configs/kp_imx6q_tpc.h | 3 --- include/configs/liteboard.h | 3 --- include/configs/mccmon6.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6memcal.h | 1 - include/configs/mx6sabreauto.h | 4 ---- include/configs/mx6sabresd.h | 4 ---- include/configs/mx6slevk.h | 4 ---- include/configs/mx6sxsabresd.h | 4 ---- include/configs/mx6ul_14x14_evk.h | 3 --- include/configs/mys_6ulx.h | 3 --- include/configs/novena.h | 3 --- include/configs/npi_imx6ull.h | 3 --- include/configs/opos6uldev.h | 4 ---- include/configs/pcl063.h | 3 --- include/configs/pcl063_ull.h | 3 --- include/configs/pcm058.h | 4 ---- include/configs/pico-imx6.h | 8 -------- include/configs/pico-imx6ul.h | 7 ------- include/configs/pico-imx7d.h | 8 -------- include/configs/somlabs_visionsom_6ull.h | 4 ---- include/configs/tqma6.h | 7 ------- include/configs/udoo.h | 2 -- include/configs/udoo_neo.h | 2 -- include/configs/vining_2000.h | 4 ---- include/configs/wandboard.h | 2 -- include/configs/xpress.h | 3 --- 48 files changed, 196 deletions(-) delete mode 100644 include/configs/imx6_spl.h delete mode 100644 include/configs/imx7_spl.h
Reviewed-by: Simon Glass sjg@chromium.org
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 2 +- arch/arc/lib/cache.c | 4 +- arch/arc/lib/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +-- arch/arm/dts/rockchip-optee.dtsi | 4 +- arch/arm/include/asm/emif.h | 2 +- arch/arm/include/asm/iproc-common/configs.h | 2 +- arch/arm/mach-aspeed/ast2500/board_common.c | 2 +- arch/arm/mach-aspeed/ast2600/board_common.c | 2 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 48 +++++++++---------- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 48 +++++++++---------- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-exynos/dmc_init_ddr3.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/mx6/litesom.c | 2 +- arch/arm/mach-imx/mx6/opos6ul.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-k3/r5_mpu.c | 2 +- arch/arm/mach-keystone/ddr3.c | 2 +- arch/arm/mach-mediatek/mt7623/init.c | 4 +- arch/arm/mach-mediatek/mt7981/init.c | 2 +- arch/arm/mach-mediatek/mt7986/init.c | 2 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 6 +-- arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-mvebu/armada8k/dram.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 6 +-- arch/arm/mach-omap2/emif-common.c | 8 ++-- arch/arm/mach-omap2/sec-common.c | 4 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-rockchip/sdram.c | 16 +++---- arch/arm/mach-socfpga/board.c | 2 +- arch/arm/mach-sunxi/dram_helpers.c | 8 ++-- arch/arm/mach-sunxi/dram_suniv.c | 20 ++++---- arch/arm/mach-sunxi/dram_sunxi_dw.c | 6 +-- arch/arm/mach-tegra/board2.c | 4 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/include/asm/immap.h | 4 +- arch/m68k/lib/traps.c | 2 +- arch/mips/lib/traps.c | 2 +- arch/mips/mach-jz47xx/jz4780/jz4780.c | 2 +- arch/mips/mach-mscc/cpu.c | 8 ++-- arch/mips/mach-mscc/dram.c | 2 +- arch/mips/mach-mscc/include/mach/ddr.h | 2 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/mips/mach-octeon/dram.c | 2 +- arch/nios2/cpu/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/lib/bootm.c | 2 +- arch/sandbox/cpu/state.c | 2 +- arch/sandbox/dts/sandbox.dts | 2 +- arch/sandbox/dts/sandbox64.dts | 2 +- arch/sh/cpu/u-boot.lds | 2 +- arch/sh/lib/board.c | 4 +- arch/sh/lib/bootm.c | 2 +- arch/xtensa/cpu/cpu.c | 2 +- board/BuR/brppt1/board.c | 2 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 20 ++++---- board/CZ.NIC/turris_mox/turris_mox.c | 2 +- board/Marvell/mvebu_alleycat-5/board.c | 2 +- board/Marvell/mvebu_armada-37xx/board.c | 2 +- board/Marvell/mvebu_armada-8k/board.c | 2 +- board/Marvell/octeontx/board.c | 2 +- board/Marvell/octeontx2/board.c | 2 +- board/Marvell/octeontx2_cn913x/board.c | 2 +- board/armltd/integrator/integrator.c | 6 +-- board/armltd/vexpress/vexpress_common.c | 2 +- board/astro/mcf5373l/mcf5373l.c | 12 ++--- board/atmel/at91sam9260ek/at91sam9260ek.c | 6 +-- board/atmel/at91sam9261ek/at91sam9261ek.c | 6 +-- board/atmel/at91sam9263ek/at91sam9263ek.c | 6 +-- .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 6 +-- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +-- board/atmel/at91sam9rlek/at91sam9rlek.c | 6 +-- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 6 +-- board/atmel/sam9x60ek/sam9x60ek.c | 6 +-- .../sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 6 +-- board/atmel/sama5d2_icp/sama5d2_icp.c | 6 +-- board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 6 +-- .../atmel/sama5d3_xplained/sama5d3_xplained.c | 6 +-- board/atmel/sama5d3xek/sama5d3xek.c | 6 +-- .../atmel/sama5d4_xplained/sama5d4_xplained.c | 6 +-- board/atmel/sama5d4ek/sama5d4ek.c | 6 +-- board/atmel/sama7g5ek/sama7g5ek.c | 6 +-- board/bluewater/gurnard/gurnard.c | 6 +-- board/bosch/guardian/board.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcm_ep/board.c | 8 ++-- board/calao/usb_a9263/usb_a9263.c | 6 +-- board/cobra5272/cobra5272.c | 2 +- board/compulab/cm_t43/cm_t43.c | 2 +- board/compulab/cm_t43/spl.c | 4 +- board/cssi/MCR3000/MCR3000.c | 2 +- .../ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 4 +- board/eets/pdu001/board.c | 2 +- board/egnite/ethernut5/ethernut5.c | 6 +-- board/emulation/qemu-arm/qemu-arm.c | 2 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- board/freescale/common/mpc85xx_sleep.c | 2 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 4 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1012ardb/ls1012ardb.c | 4 +- board/freescale/ls1021aqds/ddr.c | 2 +- board/freescale/ls1021atsn/ls1021atsn.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- board/freescale/m5208evbe/m5208evbe.c | 26 +++++----- board/freescale/m5235evb/m5235evb.c | 8 ++-- board/freescale/m5249evb/m5249evb.c | 2 +- board/freescale/m5253demo/m5253demo.c | 6 +-- board/freescale/m5272c3/m5272c3.c | 2 +- board/freescale/m5275evb/m5275evb.c | 18 +++---- board/freescale/m5282evb/m5282evb.c | 8 ++-- board/freescale/m53017evb/README | 2 +- board/freescale/m53017evb/m53017evb.c | 26 +++++----- board/freescale/m5329evb/m5329evb.c | 24 +++++----- board/freescale/m5373evb/README | 2 +- board/freescale/m5373evb/m5373evb.c | 24 +++++----- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +-- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/p1_p2_rdb_pc/ddr.c | 2 +- board/friendlyarm/nanopi2/board.c | 8 ++-- board/gardena/smart-gateway-at91sam/board.c | 6 +-- board/gdsys/mpc8308/sdram.c | 6 +-- board/grinn/chiliboard/board.c | 2 +- board/imgtec/boston/ddr.c | 2 +- board/imgtec/malta/lowlevel_init.S | 4 +- board/imgtec/malta/malta.c | 2 +- board/imgtec/xilfpga/xilfpga.c | 2 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/isee/igep003x/board.c | 2 +- board/keymile/common/common.c | 4 +- board/keymile/km83xx/km83xx.c | 6 +-- board/keymile/pg-wcom-ls102xa/ddr.c | 2 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/l+g/vinco/vinco.c | 6 +-- board/mediatek/mt7622/mt7622_rfb.c | 2 +- board/mediatek/mt7623/mt7623_rfb.c | 2 +- board/mediatek/mt7629/mt7629_rfb.c | 2 +- board/mediatek/mt8518/mt8518_ap1.c | 2 +- board/mscc/jr2/jr2.c | 2 +- board/mscc/luton/luton.c | 2 +- board/mscc/ocelot/ocelot.c | 2 +- board/mscc/serval/serval.c | 2 +- board/mscc/servalt/servalt.c | 2 +- board/phytec/phycore_am335x_r2/board.c | 4 +- board/phytium/pomelo/pomelo.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/stout/stout.c | 2 +- board/ronetix/pm9g45/pm9g45.c | 10 ++-- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 4 +- board/sandbox/sandbox.c | 4 +- board/siemens/common/board.c | 2 +- board/siemens/corvus/board.c | 6 +-- board/siemens/iot2050/board.c | 2 +- board/siemens/smartweb/smartweb.c | 6 +-- board/siemens/taurus/taurus.c | 10 ++-- board/sipeed/maix/maix.c | 2 +- board/socrates/sdram.c | 4 +- board/softing/vining_fpga/socfpga.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 4 +- board/sysam/amcore/amcore.c | 6 +-- board/sysam/stmark2/stmark2.c | 2 +- board/tbs/tbs2910/tbs2910.c | 2 +- board/tcl/sl50/board.c | 2 +- board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- board/ti/am57xx/board.c | 2 +- board/ti/am65x/evm.c | 4 +- board/ti/dra7xx/evm.c | 2 +- board/ti/j721e/evm.c | 4 +- board/ti/j721s2/evm.c | 4 +- board/ti/ks2_evm/board.c | 12 ++--- board/ti/ti816x/evm.c | 2 +- board/timll/devkit3250/devkit3250.c | 6 +-- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/vscom/baltos/board.c | 2 +- board/work-microwave/work_92105/work_92105.c | 6 +-- board/xilinx/zynq/board.c | 6 +-- board/xilinx/zynqmp/zynqmp.c | 8 ++-- boot/image-board.c | 4 +- cmd/ti/ddr3.c | 18 +++---- common/board_f.c | 8 ++-- doc/arch/m68k.rst | 16 +++---- doc/arch/nios2.rst | 4 +- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/ddr/marvell/axp/ddr3_axp.h | 4 +- drivers/pci/Kconfig | 2 +- drivers/pci/pci-rcar-gen2.c | 4 +- drivers/pci/pci_sh7751.c | 6 +-- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pci/pcie_layerscape.h | 4 +- drivers/ram/aspeed/sdram_ast2500.c | 4 +- drivers/ram/aspeed/sdram_ast2600.c | 6 +-- drivers/ram/mediatek/ddr3-mt7629.c | 12 ++--- drivers/ram/octeon/octeon_ddr.c | 2 +- drivers/ram/rockchip/dmc-rk3368.c | 12 ++--- drivers/ram/rockchip/sdram_common.c | 34 ++++++------- drivers/ram/rockchip/sdram_px30.c | 2 +- drivers/ram/rockchip/sdram_rk3066.c | 14 +++--- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 14 +++--- drivers/ram/rockchip/sdram_rk322x.c | 24 +++++----- drivers/ram/rockchip/sdram_rk3288.c | 14 +++--- drivers/ram/rockchip/sdram_rk3308.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/ram/rockchip/sdram_rk3568.c | 2 +- drivers/usb/host/ehci-rmobile.c | 4 +- drivers/video/sunxi/sunxi_display.c | 4 +- include/configs/10m50_devboard.h | 4 +- include/configs/3c120_devboard.h | 4 +- include/configs/M5208EVBE.h | 22 ++++----- include/configs/M5235EVB.h | 12 ++--- include/configs/M5249EVB.h | 12 ++--- include/configs/M5253DEMO.h | 12 ++--- include/configs/M5272C3.h | 12 ++--- include/configs/M5275EVB.h | 12 ++--- include/configs/M5282EVB.h | 12 ++--- include/configs/M53017EVB.h | 22 ++++----- include/configs/M5329EVB.h | 22 ++++----- include/configs/M5373EVB.h | 22 ++++----- include/configs/MCR3000.h | 4 +- include/configs/MPC837XERDB.h | 4 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 4 +- include/configs/P2041RDB.h | 4 +- include/configs/SBx81LIFKW.h | 2 +- include/configs/SBx81LIFXCAT.h | 2 +- include/configs/T102xRDB.h | 6 +-- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 4 +- include/configs/T208xRDB.h | 4 +- include/configs/T4240RDB.h | 4 +- include/configs/am62x_evm.h | 2 +- include/configs/am64x_evm.h | 2 +- include/configs/am65x_evm.h | 2 +- include/configs/amcore.h | 4 +- include/configs/ap121.h | 2 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-imx8.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/arbel.h | 4 +- include/configs/aristainetos2.h | 2 +- include/configs/aspeed-common.h | 2 +- include/configs/astro_mcf5373l.h | 12 ++--- include/configs/at91sam9260ek.h | 4 +- include/configs/at91sam9261ek.h | 4 +- include/configs/at91sam9263ek.h | 28 +++++------ include/configs/at91sam9m10g45ek.h | 4 +- include/configs/at91sam9n12ek.h | 4 +- include/configs/at91sam9rlek.h | 4 +- include/configs/at91sam9x5ek.h | 4 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 4 +- include/configs/bcm947622.h | 2 +- include/configs/bcm94908.h | 2 +- include/configs/bcm94912.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcm963146.h | 2 +- include/configs/bcm963148.h | 2 +- include/configs/bcm963158.h | 2 +- include/configs/bcm963178.h | 2 +- include/configs/bcm96756.h | 2 +- include/configs/bcm96813.h | 2 +- include/configs/bcm96846.h | 2 +- include/configs/bcm96855.h | 2 +- include/configs/bcm96856.h | 2 +- include/configs/bcm96858.h | 2 +- include/configs/bcm96878.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/bitmain_antminer_s9.h | 4 +- include/configs/bk4r1.h | 2 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 2 +- include/configs/bmips_bcm6348.h | 2 +- include/configs/bmips_bcm6358.h | 2 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 2 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/boston.h | 4 +- include/configs/brppt2.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/cobra5272.h | 12 ++--- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri-imx8x.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/corstone1000.h | 2 +- include/configs/corvus.h | 4 +- include/configs/da850evm.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/dragonboard410c.h | 2 +- include/configs/dragonboard820c.h | 2 +- include/configs/durian.h | 2 +- include/configs/ea-lpc3250devkitv2.h | 2 +- include/configs/eb_cpu5282.h | 14 +++--- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/emsdp.h | 4 +- include/configs/espresso7420.h | 2 +- include/configs/ethernut5.h | 4 +- include/configs/exynos5-common.h | 16 +++---- include/configs/exynos5250-common.h | 2 +- include/configs/exynos7420-common.h | 16 +++---- include/configs/exynos78x0-common.h | 26 +++++----- .../configs/gardena-smart-gateway-at91sam.h | 4 +- .../configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/gazerbeam.h | 6 +-- include/configs/ge_b1x5v2.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/grpeach.h | 4 +- include/configs/gw_ventana.h | 2 +- include/configs/gxp.h | 2 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imgtec_xilfpga.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_bsh_smm_s2_common.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mp_venice.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/integrator-common.h | 2 +- include/configs/iot_devkit.h | 14 +++--- include/configs/j721e_evm.h | 2 +- include/configs/j721s2_evm.h | 2 +- include/configs/km/km-mpc83xx.h | 4 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/kp_imx53.h | 2 +- include/configs/kp_imx6q_tpc.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/librem5.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a2g5rdb.h | 2 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012aqds.h | 2 +- include/configs/ls1012ardb.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 4 +- include/configs/m53menlo.h | 2 +- include/configs/malta.h | 6 +-- include/configs/maxbcm.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/meerkat96.h | 2 +- include/configs/meesc.h | 4 +- include/configs/meson64.h | 2 +- include/configs/microchip_mpfs_icicle.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mt7620.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/mt7622.h | 2 +- include/configs/mt7623.h | 2 +- include/configs/mt7628.h | 2 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 2 +- include/configs/mt7986.h | 2 +- include/configs/mt8518.h | 4 +- include/configs/mv-common.h | 2 +- include/configs/mvebu_alleycat-5.h | 2 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 2 +- include/configs/mx23_olinuxino.h | 2 +- include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/nokia_rx51.h | 4 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/octeon_common.h | 2 +- include/configs/octeontx2_common.h | 2 +- include/configs/octeontx_common.h | 2 +- include/configs/odroid.h | 4 +- include/configs/odroid_xu3.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/openpiton-riscv64.h | 2 +- include/configs/opos6uldev.h | 2 +- include/configs/origen.h | 4 +- include/configs/owl-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 8 ++-- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/peach-pi.h | 2 +- include/configs/peach-pit.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pic32mzdask.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/pm9261.h | 26 +++++----- include/configs/pm9263.h | 26 +++++----- include/configs/pm9g45.h | 4 +- include/configs/poleg.h | 2 +- include/configs/pomelo.h | 2 +- include/configs/presidio_asic.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/qemu-arm.h | 2 +- include/configs/qemu-ppce500.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/r2dplus.h | 4 +- include/configs/rcar-gen2-common.h | 4 +- include/configs/rcar-gen3-common.h | 4 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rpi.h | 4 +- include/configs/rv1108_common.h | 2 +- include/configs/s5p4418_nanopi2.h | 4 +- include/configs/s5p_goni.h | 4 +- include/configs/s5pc210_universal.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3_xplained.h | 4 +- include/configs/sama5d3xek.h | 4 +- include/configs/sama5d4_xplained.h | 4 +- include/configs/sama5d4ek.h | 4 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 4 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/sifive-unmatched.h | 2 +- include/configs/sipeed-maix.h | 4 +- include/configs/smartweb.h | 4 +- include/configs/smdk5420.h | 2 +- include/configs/smdkc100.h | 4 +- include/configs/smdkv310.h | 10 ++-- include/configs/smegw01.h | 2 +- include/configs/snapper9g45.h | 4 +- include/configs/sniper.h | 2 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/socrates.h | 4 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stmark2.h | 14 +++--- include/configs/stv0991.h | 2 +- include/configs/sunxi-common.h | 8 ++-- include/configs/synquacer.h | 2 +- include/configs/taurus.h | 4 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/theadorable.h | 2 +- include/configs/thunderx_88xx.h | 4 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_armv7_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/trats.h | 4 +- include/configs/trats2.h | 4 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usb_a9263.h | 4 +- include/configs/usbarmory.h | 2 +- include/configs/vcoreiii.h | 8 ++-- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- include/configs/vexpress_aemv8.h | 2 +- include/configs/vexpress_common.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 2 +- include/configs/vocore2.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/work_92105.h | 4 +- include/configs/xea.h | 2 +- include/configs/xenguest_arm64.h | 2 +- include/configs/xilinx_zynqmp_mini_nand.h | 4 +- include/configs/xpress.h | 2 +- include/configs/xtfpga.h | 10 ++-- include/init.h | 4 +- include/system-constants.h | 2 +- post/drivers/memory.c | 2 +- test/dm/remoteproc.c | 6 +-- 589 files changed, 1197 insertions(+), 1197 deletions(-)
diff --git a/README b/README index 5ab042a2defb..b095937121b7 100644 --- a/README +++ b/README @@ -1441,7 +1441,7 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_SDRAM_BASE: +- CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE: diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 4c696cb53a48..d97a5787424e 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) static void arc_ioc_setup(void) { /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + unsigned int ap_base = CFG_SYS_SDRAM_BASE; /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; + long ap_size = CFG_SYS_SDRAM_SIZE;
/* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!slc_exists()) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 6b215206a272..156785796183 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -20,7 +20,7 @@ int arch_cpu_init(void) timer_init();
gd->cpu_clk = get_board_sys_clk(); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE;
cache_init();
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index b4d113dc1e08..954fa5f8b450 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -29,7 +29,7 @@ */ static void __secure ls1_save_ddr_head(void) { - const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + const char *src = (const char *)CFG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ef71e2cf2bca..bbaa91f0e108 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1441,7 +1441,7 @@ int dram_init_banksize(void) } #endif
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; @@ -1571,7 +1571,7 @@ void update_early_mmu_table(void)
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, gd->ram_size, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1579,7 +1579,7 @@ void update_early_mmu_table(void) PTE_TYPE_VALID); } else { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, CONFIG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi index 328ba9084504..d84c10cf4363 100644 --- a/arch/arm/dts/rockchip-optee.dtsi +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -32,8 +32,8 @@ arch = "arm"; os = "tee"; compression = "none"; - load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext { filename = "tee.bin"; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 35424345bf02..2141a4581c7c 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -583,7 +583,7 @@ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 4733c0793c36..c63c27dac7e1 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -12,6 +12,6 @@ #define CONFIG_IPROC
/* Memory Info */ -#define CONFIG_SYS_SDRAM_BASE 0x61000000 +#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index aca200223129..bae10271844a 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 82ff21908f26..dc6cdc35d15c 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -54,7 +54,7 @@ int board_init(void) int i = 0, rc; struct udevice *dev;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
while (1) { rc = uclass_get_device(UCLASS_MISC, i++, &dev); diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 57e51c81059b..3b91a0cba33e 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -114,38 +114,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM1 + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index c51eee2f17e8..ecfe589e4559 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -201,38 +201,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL6 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL7 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL8 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 73fdd1f24329..42078b39f8ab 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -26,14 +26,14 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; }
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f30e..cad8ccc5315f 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a4863281e360..8050406613d7 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void) int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++) - if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i;
hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 802cb0e2ba83..5d95fb89a61c 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) - if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i;
hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 699a3dc317f0..2ba3245e226c 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -172,7 +172,7 @@ static void spl_dram_init(void) * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index e9d78740a157..38ead8ace20c 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -44,7 +44,7 @@ static int setup_fec(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6b8f4115c4ea..cb9801b7a13c 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = imx_ddr_size();
return 0; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 227706e8dca0..d5e1f8e2e780 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
dram_init();
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 3d2ff6775a3f..2aec96277e6f 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = { O_I_WB_RD_WR_ALLOC, REGION_8MB},
/* U-Boot's code area marking it as WB and Write allocate */ - {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_2GB}, /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 53117c2695cf..ea7d0b903cf6 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size) }
ddr3_ecc_init_range(base); - ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */ #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 5d837e059719..988b057e5984 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -25,7 +25,7 @@ int dram_init(void) { u32 i;
- if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) && ((size_t)preloader_param % sizeof(size_t) == 0) && preloader_param->magic == BOOT_ARGUMENT_MAGIC && preloader_param->dram_rank_num <= @@ -35,7 +35,7 @@ int dram_init(void) for (i = 0; i < preloader_param->dram_rank_num; i++) gd->ram_size += preloader_param->dram_rank_size[i]; } else { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SZ_2G); }
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index a8955064e031..d8b10f035808 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0; } diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index cf89e63e80ad..fb74b2f34d7b 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0; } diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index cc7f9794c547..8204d9627515 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region ac5_mem_map[] = { { /* RAM */ - .phys = CONFIG_SYS_SDRAM_BASE, - .virt = CONFIG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .virt = CFG_SYS_SDRAM_BASE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, @@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index e3098a7ca878..2c94f899f373 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); + unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index bab375e18acc..6c801bfa1db7 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 44d5214a3df1..86755d6d9543 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -72,14 +72,14 @@ int dram_init(void)
/* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; }
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; @@ -520,7 +520,7 @@ void board_init_f(ulong dummy) sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 312f868fbc71..a6a97af37d7b 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region2 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -1340,7 +1340,7 @@ void dmm_init(u32 base)
mapped_size = 0; section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; + sys_addr = CFG_SYS_SDRAM_BASE; emif1_size = get_emif_mem_size(EMIF1_BASE); emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); @@ -1568,7 +1568,7 @@ void sdram_init(void) size_prog = log_2_n_round_down(size_prog); size_prog = (1 << size_prog);
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ if (size_detect != size_prog) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0551bc125e8f..0f9b915ea3dd 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -198,11 +198,11 @@ u32 get_sec_mem_start(void) */ if (sec_mem_start == 0) sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + ( + (CFG_SYS_SDRAM_BASE + ( #if defined(CONFIG_OMAP54XX) omap_sdram_size() #else - get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4baef2eed3e4..f0f46f2dcb74 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,7 +50,7 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 12f1d7ee5637..e086c47f3c00 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t {
int dram_init_banksize(void) { - size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE), (unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64 @@ -48,26 +48,26 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_OPTEE_IMAGE struct tos_parameter_t *tos_parameter;
- tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE + TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr - - CONFIG_SYS_SDRAM_BASE; + - CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } else { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE + gd->bd->bi_dram[0].size + 0x2000000; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } #else - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; #endif #endif @@ -207,7 +207,7 @@ int dram_init(void)
phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index b49006c6c8a6..09e09192fba2 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -46,7 +46,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 2c873192e608..cdf2750f1c52 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val) bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + writel(0, CFG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset); dsb(); /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); + return readl(CFG_SYS_SDRAM_BASE) == + readl((ulong)CFG_SYS_SDRAM_BASE + offset); } #endif diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 56c2d557ff13..3aa3ce76272c 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void) u32 k = 0;
for (k = 0; k < 32; k++) - writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k); + writel(k, CFG_SYS_SDRAM_BASE + 4 * k); for (k = 0; k < 32; k++) { - if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k) + if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k) return 0; } return 1; @@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para) dram_para_setup(para); dram_scan_readpipe(para); for (i = 0; i < 32; i++) { - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; } for (i = 0; i < 32; i++) { - val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)); + val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)); if (val1 == 0x22) count++; } @@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para) para->row_width = rowflag; dram_para_setup(para); if (colflag == 10) { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000; + addr1 = CFG_SYS_SDRAM_BASE + 0x400000; + addr2 = CFG_SYS_SDRAM_BASE + 0xc00000; } else { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000; + addr1 = CFG_SYS_SDRAM_BASE + 0x200000; + addr2 = CFG_SYS_SDRAM_BASE + 0x600000; } for (i = 0; i < 32; i++) { *((u8 *)(addr1 + i)) = 0x33; @@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para)
static void simple_dram_check(void) { - volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE; + volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE; int i;
for (i = 0; i < 0x40; i++) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df5e..4af5922f334d 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank) */ static void mctl_r40_detect_rank_count(struct dram_para *para) { - ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE + + ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]); struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; @@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para)
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); } }
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 82d3d3350284..54bbd8a776e9 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -370,7 +370,7 @@ int dram_init_banksize(void)
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI @@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
/* fall back to default usable RAM computation */
- return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ac595ee0a271..3b6518c71c90 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
-#if (CONFIG_SYS_SDRAM_BASE == 0) +#if (CFG_SYS_SDRAM_BASE == 0) /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start);
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index e2985792d96f..dac2229f72e1 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags) * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); + out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE); #endif
/* wait for DQS logic to relock */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f2eb6fcb463b..672aa0bb14ea 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -338,9 +338,9 @@
#ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) -#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) #define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */
diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 0c2c1a996552..28fe803928ea 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -62,7 +62,7 @@ static void trap_init(ulong value) {
int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE);
return 0; } diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7577fdd25d79..7a682f256a65 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -135,7 +135,7 @@ void trap_restore(void)
int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE);
return 0; } diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index cff98b0a7707..15d1eff2ba7a 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -78,7 +78,7 @@ void board_init_f(ulong dummy)
phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); + return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); }
int print_cpuinfo(void) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 5bc31006aa15..d484eb92c419 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -17,16 +17,16 @@
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#elif CFG_SYS_SDRAM_SIZE <= SZ_128M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_RW -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#elif CFG_SYS_SDRAM_SIZE <= SZ_256M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#elif CFG_SYS_SDRAM_SIZE <= SZ_512M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_RW #else diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c53a4202e0d9..f7fbd33cc4b9 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -67,6 +67,6 @@ int print_cpuinfo(void)
int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d52eabbd2b1f..75fb3ca00d2c 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -13,7 +13,7 @@ #include <mach/common.h>
#define MIPS_VCOREIII_MEMORY_DDR3 -#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE +#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 3cad3567e72a..6b9f253952a1 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -18,7 +18,7 @@ #include "dram.h"
#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) #endif
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 9c5789b1c8eb..85cb084c13ff 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -81,7 +81,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ - return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, + return CFG_SYS_SDRAM_BASE + min(gd->ram_size, UBOOT_RAM_SIZE_MAX); } else { return gd->ram_top; diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 4dd9c10faa5a..85544503a5ee 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -73,7 +73,7 @@ static int nios_cpu_setup(void *ctx, struct event *event) if (ret) return ret;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #ifndef CONFIG_ROM_STUBS copy_exception_trampoline(); #endif diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e12043b26093..6d1c6b055c6b 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -288,7 +288,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b0363c9c1028..6acd31d28479 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -424,7 +424,7 @@ int dram_init(void) defined(CONFIG_ARCH_QEMU_E500) gd->ram_size = fsl_ddr_sdram_size(); #else - gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024; #endif
return 0; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index f109ecb9ff76..44f8ed8a19a3 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -195,7 +195,7 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? CONFIG_MAX_MEM_MAPPED : gd->ram_size) + - CONFIG_SYS_SDRAM_BASE - 4096; + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096;
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index d917e9dfb62f..71496ab294d2 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -16,7 +16,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) int j;
tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8ae8d8a3e7d6..1df0822e9d73 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb)
#ifdef DEBUG if (((u64)bootmap_base + bootm_size) > - (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a681e472ab65..dd7978cfced3 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -448,7 +448,7 @@ int state_init(void) { state = &main_state;
- state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_size = CFG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); if (!state->ram_buf) { printf("Out of memory\n"); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2051207f0ba9..88b57bfb7e5f 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -25,7 +25,7 @@ };
memory { - reg = <0 CONFIG_SYS_SDRAM_SIZE>; + reg = <0 CFG_SYS_SDRAM_SIZE>; };
reserved-memory { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 3eb045708914..a9cd7908f83e 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -21,7 +21,7 @@ };
memory { - reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; + reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>; };
reserved-memory { diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 85ee547b4aae..d360eea7eba3 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -18,7 +18,7 @@ OUTPUT_ARCH(sh)
MEMORY { - ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE + ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE }
ENTRY(_start) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3fa093a02ea3..b31fa6d70311 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index a5fad6c46c7e..b205e5e3db1b 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -88,7 +88,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200); set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001); set_sh_linux_param((unsigned long)param + INITRD_START, - GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE)); + GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE)); set_sh_linux_param((unsigned long)param + INITRD_SIZE, images->rd_end - images->rd_start); } diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index a09e103fc1d6..98d9753b7e34 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -45,7 +45,7 @@ int print_cpuinfo(void)
int arch_cpu_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; }
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index c8dc186cddf2..36945bbdccf5 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -150,7 +150,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 2b08930af6f6..f9a37e7215c9 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -40,8 +40,8 @@ int dram_init(void) MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); asm (" nop"); -#ifdef CONFIG_SYS_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)| +#ifdef CFG_SYS_SDRAM_BASE0 + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32; asm (" nop"); @@ -54,7 +54,7 @@ int dram_init(void) for (i = 0; i < 10; i++) asm (" nop");
- *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; asm (" nop"); @@ -65,12 +65,12 @@ int dram_init(void) MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; asm (" nop"); /* write SDRAM mode register */ - *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; asm (" nop"); - size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024; + size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024; #endif -#ifdef CONFIG_SYS_SDRAM_BASE1xx - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) +#ifdef CFG_SYS_SDRAM_BASE1xx + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -79,15 +79,15 @@ int dram_init(void)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
- *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5; + *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++) asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024; + *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif gd->ram_size = size;
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index ff1c4cb17073..a52a032e4d5d 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -139,7 +139,7 @@ int board_fix_fdt(void *blob) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c index 619cd6c6cd35..0c4f8e03b859 100644 --- a/board/Marvell/mvebu_alleycat-5/board.c +++ b/board/Marvell/mvebu_alleycat-5/board.c @@ -7,7 +7,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index c6ecc323bb99..45fe3e5f0bdf 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index 77c7dd7ab0e8..a8899af6e5af 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -150,7 +150,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c index 059ebf8f1727..224653519b95 100644 --- a/board/Marvell/octeontx/board.c +++ b/board/Marvell/octeontx/board.c @@ -63,7 +63,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE; mem_map_fill();
return 0; diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 63aa2d613496..e7899f49f0c2 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -105,7 +105,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c index 953e9db9c8e8..3d20cfb2fabe 100644 --- a/board/Marvell/octeontx2_cn913x/board.c +++ b/board/Marvell/octeontx2_cn913x/board.c @@ -34,7 +34,7 @@ int board_early_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 4959a7fd6dcf..ad02cf16da5e 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void)
int dram_init (void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -160,12 +160,12 @@ extern void dram_query(void); * */ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, 0x01000000 << sdram_shift); } #else - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 1c8301926531..763131c217e5 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -73,7 +73,7 @@ static void flash__init(void) int dram_init(void) { gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; }
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index 3e2f79a1cf4c..43563c412793 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -39,12 +39,12 @@ int dram_init(void) * GPIO configuration for bus should be set correctly from reset, * so we do not care! First, set up address space: at this point, * we should be running from internal SRAM; - * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, * and do not care where it is */ - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, &sdp->cs0); - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, &sdp->cs1); /* * I am not sure from the data sheet, but it seems burst length @@ -72,7 +72,7 @@ int dram_init(void) */ __raw_writel(0x71462C00, &sdp->ctrl); /* Dummy write to start SDRAM */ - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); #endif
/* @@ -82,8 +82,8 @@ int dram_init(void) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - 0x80000000 - CONFIG_SYS_SDRAM_BASE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + 0x80000000 - CFG_SYS_SDRAM_BASE);
return 0; } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index d2c6ada66838..b8e02f459031 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -81,7 +81,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(); @@ -92,8 +92,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 2992353199fe..eab3a1308195 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -156,7 +156,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); @@ -176,8 +176,8 @@ int board_eth_init(struct bd_info *bis)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index b2b709308050..15f20b62f672 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -95,7 +95,7 @@ int board_init(void) /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); @@ -108,8 +108,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 2f3a772b81fa..f53c1cf612d5 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -168,7 +168,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
/* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); @@ -181,8 +181,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 546851953a11..a3e294c88fc8 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -99,7 +99,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL at91sam9n12ek_nand_hw_init(); @@ -114,8 +114,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index bca7c8d9af52..11725f778b7d 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -93,7 +93,7 @@ int board_init(void) /* arch number of AT91SAM9RLEK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9rlek_nand_hw_init(); @@ -104,7 +104,7 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 817aa2fef707..ab666b6be34f 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -115,7 +115,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
/* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND at91sam9x5ek_nand_hw_init(); @@ -129,8 +129,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 786de18f8c64..a3e35f306663 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -120,7 +120,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND sam9x60ek_nand_hw_init(); @@ -130,7 +130,7 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 6524867708af..6e41017af17c 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -84,8 +84,8 @@ int misc_init_r(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 020777002823..fabe492715ab 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -54,7 +54,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -63,8 +63,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 16e9183f5414..854715ea2269 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -115,7 +115,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -130,8 +130,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index a778f2694df1..ce73a801e501 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -94,7 +94,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL sama5d3_xplained_nand_hw_init(); @@ -110,8 +110,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 008f1db6b0e2..660a6b9d5835 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -147,7 +147,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL sama5d3xek_nand_hw_init(); @@ -166,8 +166,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 4058594e4dec..780aba15ab1d 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -121,7 +121,7 @@ int misc_init_r(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL sama5d4_xplained_nand_hw_init(); @@ -135,8 +135,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index ef5a8a0d5cc6..2226906a3b3d 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -107,7 +107,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL sama5d4ek_nand_hw_init(); @@ -121,8 +121,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index 7d83e76f9ac0..295fd079dcf7 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -67,7 +67,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
board_leds_init();
@@ -76,7 +76,7 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 35c74ba9dd28..9b42299b080f 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -307,7 +307,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND ret = gurnard_nand_hw_init(); @@ -407,8 +407,8 @@ int board_eth_init(struct bd_info *bis)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index bdf8d06add8a..c31e2c86a2d5 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -182,7 +182,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND gpmc_init(); diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index a7a9775fdf4e..e3a9c00e8098 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -449,7 +449,7 @@ int board_init(void) if (read_eeprom() < 0) puts("EEPROM Content Invalid.\n");
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c index 6064eb43db11..e91fa40e640c 100644 --- a/board/broadcom/bcm_ep/board.c +++ b/board/broadcom/bcm_ep/board.c @@ -26,7 +26,7 @@ int board_init(void) * Address of boot parameters passed to kernel * Use default offset 0x100 */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } @@ -36,14 +36,14 @@ int board_init(void) */ int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index c89ad0bfe3d4..3d31776d4841 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -95,7 +95,7 @@ static void usb_a9263_macb_hw_init(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND usb_a9263_nand_hw_init(); @@ -111,8 +111,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 3e2418866c73..69a9df942311 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -28,7 +28,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *) 0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0; }; diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index bcfe1bfaf670..5df378a62e3c 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -45,7 +45,7 @@ int power_init_board(void)
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); set_i2c_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index e67bf81ee3a8..a6223a477fef 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -119,7 +119,7 @@ void sdram_init(void) unsigned long ram_size;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || ram_size == 0x40000000 || ram_size == 0x20000000) @@ -127,7 +127,7 @@ void sdram_init(void)
ddr3_emif_regs.sdram_config = 0x638453B2; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x08000000) return;
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c index c20e87149493..e95e04a30a6b 100644 --- a/board/cssi/MCR3000/MCR3000.c +++ b/board/cssi/MCR3000/MCR3000.c @@ -114,7 +114,7 @@ int dram_init(void) out_be32(&memctl->memc_mcr, 0x80002038); udelay(200);
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
return 0; diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 72cf46c749ff..2b03e4891d92 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -29,13 +29,13 @@ board_early_init_f(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000; return 0; }
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M); return 0; } diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 1054837d434d..648d77fd21e3 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -286,7 +286,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; }
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index a5d79d8e3e1a..913c2ea16640 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -85,8 +85,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
@@ -135,7 +135,7 @@ int board_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Set adress of boot parameters. */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Initialize UARTs and power management. */ ethernut5_power_init(); #ifdef CONFIG_CMD_NAND diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 16237e29e467..3df3e41c0b2c 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -126,7 +126,7 @@ void *board_fdt_blob_setup(int *err) { *err = 0; /* QEMU loads a generated DTB for us at the start of RAM. */ - return (void *)CONFIG_SYS_SDRAM_BASE; + return (void *)CFG_SYS_SDRAM_BASE; }
void enable_caches(void) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 98043b020c52..2304e9e8ec3d 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -264,7 +264,7 @@ int board_init(void) meesc_ethercat_hw_init();
/* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index f5bed6c35bb3..46ffd817b44b 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -61,7 +61,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */ src = (u64 *)in_le32(&scfg->sparecr[2]); - dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + dst = (u64 *)CFG_SYS_SDRAM_BASE;
for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst++ = *src++; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index 71922aab4ef4..d3323b9ec1e5 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -50,7 +50,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); - dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); + dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst-- = *src--; diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index bc37c553a5b4..f2b8750a3f38 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -102,7 +102,7 @@ int dram_init(void) else gd->ram_size = SYS_SDRAM_SIZE_512; #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif } return 0; @@ -139,7 +139,7 @@ int dram_init(void) gd->ram_size = SYS_SDRAM_SIZE_512; } #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif mmdc_init(&mparam);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 3f70fbc35659..f17a6c186d3b 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -66,7 +66,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0; } @@ -90,7 +90,7 @@ int dram_init(void) };
mmdc_init(&mparam); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 456609d99324..62c935e4d3ec 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -113,7 +113,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0; } @@ -140,7 +140,7 @@ int dram_init(void) mmdc_init(&mparam); #endif
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 66fe1519cc6d..4e70acc5a0cc 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -192,7 +192,7 @@ int fsl_initdram(void)
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index 4325439be95c..d144f25c623c 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -47,7 +47,7 @@ static void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 33027ad05750..8b74d458237d 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -162,7 +162,7 @@ void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */ diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 7bfb4557dd5b..6125c9e13aa3 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop");
/* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop");
/* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop");
out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); asm("nop");
udelay(100); diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index e7c7a94036b5..44161a0b0a1c 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -44,7 +44,7 @@ int dram_init(void) GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3));
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -61,7 +61,7 @@ int dram_init(void)
/* Initialize DACR0 */ out_be32(&sdram->dacr0, - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32); asm("nop"); @@ -80,7 +80,7 @@ int dram_init(void) }
/* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); @@ -95,7 +95,7 @@ int dram_init(void) asm("nop");
/* Write to the SDRAM Mode Register */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; }
gd->ram_size = dramsize; diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index 48c00791114d..efff05514096 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -86,7 +86,7 @@ int dram_init(void) mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0; }; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 85f5f0c03409..179a2a242a8d 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -47,7 +47,7 @@ int dram_init(void) __asm__("nop");
/* Initialize DMR0 */ - dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); + dramsize = (CFG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); @@ -57,7 +57,7 @@ int dram_init(void) __asm__("nop");
/* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5; mb(); __asm__("nop");
@@ -74,7 +74,7 @@ int dram_init(void) mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop");
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; mb(); }
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 9580cf2a0390..3c20a23385c5 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -30,7 +30,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0; }; diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 1c4fb7232afb..00fa35ca5f71 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -35,7 +35,7 @@ int dram_init(void) out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */ - out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE); out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */ @@ -49,34 +49,34 @@ int dram_init(void) setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */ - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */ setbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | MCF_SDRAMC_SDMR_CMD); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */ out_be32(&sdp->sdmr, 0x058d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); @@ -91,7 +91,7 @@ int dram_init(void) | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) | MCF_SDRAMC_SDCR_DQS_OE(0x3));
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0; }; diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index e1ea9b3a58f8..53e0f202101c 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -21,7 +21,7 @@ int dram_init(void) { u32 dramsize, i, dramclk;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -40,7 +40,7 @@ int dram_init(void)
/* Initialize DACR0 */ MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) + | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) | MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32); @@ -62,7 +62,7 @@ int dram_init(void) }
/* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; asm("nop");
/* Set RE (bit 15) in DACR */ @@ -79,7 +79,7 @@ int dram_init(void) asm("nop");
/* Write to the SDRAM Mode Register */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } gd->ram_size = dramsize;
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 8a7d8cadf02e..0de36a7f747b 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -106,7 +106,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index c9f89353ce4b..76ebc0ab8dcd 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop");
/* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop");
/* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop");
out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); asm("nop");
udelay(100); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 7a75b04dd0d2..b278dbfb4852 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bba54202155b..bfbcd5dc81db 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -105,7 +105,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index cfa5ca4a477c..0e9eec316c2f 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 2650d300e384..85d43cccd1a0 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -97,10 +97,10 @@ int dram_init(void) int fixed_sdram(void) { immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -127,7 +127,7 @@ int fixed_sdram(void)
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CONFIG_SYS_SDRAM_SIZE >> 20; + return CFG_SYS_SDRAM_SIZE >> 20; } #endif /*!CONFIG_SYS_SPD_EEPROM */
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 46095acedfdd..86364acf8ca0 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 038e6736acec..f896fd7ccce5 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -244,7 +244,7 @@ phys_size_t fixed_sdram(void) printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, sysinfo.freq_ddrbus));
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index 70e4dfcfa456..954197282e6b 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -507,7 +507,7 @@ int splash_screen_prepare(void) /* u-boot dram initialize */ int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; }
@@ -518,10 +518,10 @@ int dram_init_banksize(void) unsigned int reg_val = readl(SCR_USER_SIG6_READ);
/* set global data memory */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c index c6eb11e93263..d9dfb256b32a 100644 --- a/board/gardena/smart-gateway-at91sam/board.c +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -45,15 +45,15 @@ int board_early_init_f(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; }
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 47b880435210..4889a6a4f3b9 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,11 +34,11 @@ DECLARE_GLOBAL_DATA_PTR; static long fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & 0xfffff000); + CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -66,7 +66,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); + return get_ram_size(CFG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 6423c1efb24b..b472ca5b94a6 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -95,7 +95,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init();
return 0; diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 5b245cb44734..8532225dc0db 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -27,7 +27,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { DECLARE_GLOBAL_DATA_PTR;
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) { + if (gd->ram_top < CFG_SYS_SDRAM_BASE) { /* 2GB wrapped around to 0 */ return CKSEG0ADDR(256 << 20); } diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index bed24972f7a8..aa910bf1ce1b 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -118,7 +118,7 @@ _msc01: /* setup basic address decode */ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 - li t2, -CONFIG_SYS_SDRAM_SIZE + li t2, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) sw t2, MSC01_BIU_MCMSK1L_OFS(t0) sw t1, MSC01_BIU_MCBAS2L_OFS(t0) @@ -168,7 +168,7 @@ _msc01: sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */ - li t1, -CONFIG_SYS_SDRAM_SIZE + li t1, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 9853a0ba82f6..4a72ab5cecad 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void)
int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0; } diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index 6a836370e36d..712269272114 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -19,7 +19,7 @@ int dram_init(void) { /* MIG IP block is smart and doesn't need SW * to do any init */ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ + gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
return 0; } diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index 7dbb3a914324..f3a0de3967bb 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -412,7 +412,7 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30); return 0; }
diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 02ae7df04db9..5462a3dea228 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -185,7 +185,7 @@ int spl_start_uboot(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index c8138dcf3058..0252ada93ff5 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -52,7 +52,7 @@ int set_km_env(void) char envval[16]; char *p;
- pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -65,7 +65,7 @@ int set_km_env(void) CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram);
- varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 6a7b84816145..ddd8f7a13e1a 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -142,10 +142,10 @@ static int fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); + msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); enable_addr_trans(); msize /= (1024 * 1024); - if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) { + if (CFG_SYS_SDRAM_SIZE >> 20 != msize) { for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) @@ -169,7 +169,7 @@ int dram_init(void) return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); + CFG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 4ec60f168543..556d39d4d4e3 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,7 +84,7 @@ int fsl_initdram(void)
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
return 0; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 3719bcf7317e..1a7fa3fc1e48 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -184,7 +184,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { /* Define only 1MiB range for mem_regions at the middle of the RAM */ /* For 1GiB range mem_regions takes approx. 4min */ - *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); + *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1); *size = 1 << 20; return 0; } diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index d47c7b5f1eb1..b3c176dd59a0 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -164,7 +164,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if !CONFIG_IS_ENABLED(DM_SPI) vinco_spi0_hw_init(); @@ -188,8 +188,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 0504d6177fd5..ff233e920a03 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; }
diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c index 755e879085c2..ec10f77c51e4 100644 --- a/board/mediatek/mt7623/mt7623_rfb.c +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c index d1bca6d62ef8..55f7696c5107 100644 --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c index fce5de6767cd..2490b15ec78f 100644 --- a/board/mediatek/mt8518/mt8518_ap1.c +++ b/board/mediatek/mt8518/mt8518_ap1.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
debug("gd->fdt_blob is %p\n", gd->fdt_blob); return 0; diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 6abf08bd24cc..84b95be648d7 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -28,7 +28,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0; } diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 76e3f2ebbce7..48170b3aa12d 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -29,7 +29,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0; } diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 2a75ec281cb1..f261346b358d 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -77,7 +77,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0; } diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 87e79076574f..99d5f5be657e 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0; } diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index bd8c7e8b7003..49993168c237 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0; } diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index d97ebd015120..e84dd251c254 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -166,7 +166,7 @@ void sdram_init(void) 0);
/* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE);
/* Reconfigure memory for actual detected size */ @@ -269,7 +269,7 @@ void set_mux_conf_regs(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; }
diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 4fbe1e583584..75d2636bf453 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -24,7 +24,7 @@ int dram_init(void) ddr_init();
gd->mem_clk = 0; - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
sec_init(); debug("PBF relocate done\n"); diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 3b60afc59c36..85fbaf0b28b6 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -70,7 +70,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index a36526986cab..ea090575fb20 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -312,7 +312,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 6197e549c2e5..2d1435acff6c 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 199ec4a31098..f609e4f07289 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0; } diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 87607df20d5e..c3ebcd3e39fe 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 8e24ac013c05..1437875cfa7b 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -89,7 +89,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 1a3a4c11a172..db1fb4b035f0 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 4558070af883..6ecebfe814df 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -71,7 +71,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index 56bdb34329a7..f069eccde974 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -88,7 +88,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
cpld_init();
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 23b55e3e0302..c56582a19485 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -126,7 +126,7 @@ int board_init(void) /* arch number of AT91SAM9M10G45EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND pm9g45_nand_hw_init(); @@ -141,15 +141,15 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 5320c1f2e0ad..a992dc684291 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -46,7 +46,7 @@ int dram_init(void) u32 addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -64,7 +64,7 @@ int dram_init_banksize(void) u32 addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 943b498293b9..16ce5cb89253 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -122,7 +122,7 @@ int dram_init(void) unsigned long addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -134,7 +134,7 @@ int dram_init_banksize(void) unsigned long addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr; diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 4d89f9be1cd9..6672ae7fcc87 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -102,7 +102,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; }
@@ -160,7 +160,7 @@ int board_late_init(void) int init_addr_map(void) { if (IS_ENABLED(CONFIG_ADDR_MAP)) - addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0); + addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0);
return 0; } diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 85025f20efae..2efede62aa5d 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -85,7 +85,7 @@ int board_init(void) #ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index d87628097d0d..569b86db00ac 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -262,7 +262,7 @@ void at91_udp_hw_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* we have to request the gpios again after relocation */ corvus_request_gpio(); @@ -287,8 +287,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index b965ae9fa497..8f4b0eae4951 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -146,7 +146,7 @@ int dram_init_banksize(void) dram_init();
/* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size;
/* Bank 1 declares the memory available in the DDR high region */ diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index ce6c877959ad..3d0f7341a371 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -167,7 +167,7 @@ int board_init(void) #endif
/* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
smartweb_nand_hw_init(); smartweb_macb_hw_init(); @@ -177,8 +177,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 47d3f6aef22e..1eee972d49e1 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -185,8 +185,8 @@ void mem_init(void) sdramc_configure(AT91_SDRAMC_NC_10);
/* Do memtest for 128MB */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
/* * If 32MB or 16MB should be supported check also for @@ -306,7 +306,7 @@ struct at91_udc_data board_udc_data = { int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
taurus_request_gpio(); #ifdef CONFIG_CMD_NAND @@ -326,8 +326,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index a218278cb34e..79e492f0a8ec 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -11,7 +11,7 @@
phys_size_t get_effective_memsize(void) { - return CONFIG_SYS_SDRAM_SIZE; + return CFG_SYS_SDRAM_SIZE; }
static int sram_init(void) diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 04527cf79ab2..ad49999dc28e 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -51,11 +51,11 @@ phys_size_t fixed_sdram(void) asm ("sync; isync; msync"); udelay(1000);
- if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { + if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) { /* * OK, size detected -> all done */ - return CONFIG_SYS_SDRAM_SIZE<<20; + return CFG_SYS_SDRAM_SIZE<<20; }
return 0; /* nothing found ! */ diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 229922739118..b3f9550742ec 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -30,7 +30,7 @@ int board_late_init(void) status_led_set(2, CONFIG_LED_STATUS_ON);
/* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); if (!ret) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8e80ca6e17e0..7c44379ec4af 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -107,7 +107,7 @@ int dram_init(void) { u32 max_size = imx_ddr_size();
- gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE, (u32)max_size);
return 0; @@ -288,7 +288,7 @@ int board_init(void) int ret = 0;
/* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3 ret = setup_display(); diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index beab4e9d1884..5426fc4ffd84 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -88,7 +88,7 @@ int dram_init(void) */ out_be32(&dc->dacr0, 0x00003304);
- dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; + dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; out_be32(&dc->dmr0, dramsize|1);
/* issue a PRECHARGE ALL */ @@ -102,8 +102,8 @@ int dram_init(void) out_be32(&dc->dacr0, 0x0000b344); out_be32((u32 *)0x00000c00, 0xbeaddeed);
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index d48da48b69d6..475e3edfa62e 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -35,7 +35,7 @@ int dram_init(void) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
gd->ram_size = dramsize;
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index 3a447ca8a93c..8d9eedb7523c 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -144,7 +144,7 @@ static const struct boot_mode board_boot_modes[] = { int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3 setup_display(); diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index b7ddc3ba78f4..839a692ce85d 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -238,7 +238,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; }
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b97fedddd5e2..9e5828161157 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -704,7 +704,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 529129ecc76e..d0b7a14e0e99 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -639,7 +639,7 @@ int board_init(void) u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, modena_init0_bw_integer, modena_init0_watermark_0;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init();
/* diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index cfc825e52a36..652c40f55c4c 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -661,7 +661,7 @@ bool am571x_idk_needs_lcd(void) int board_init(void) { gpmc_init(); - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0; } diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 34ec3915f3d7..b266ccb4b82e 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -75,13 +75,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index a854d615c1d7..1c00e253ffc8 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -644,7 +644,7 @@ int dram_init_banksize(void)
ram_size = board_ti_get_emif_size();
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); if (ram_size > CONFIG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index d6e431ead0ef..d4e672a7acd5 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -71,13 +71,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index e09adc8ad34e..4d28582311be 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -60,13 +60,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x7fffffff; gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x37fffffff; gd->ram_size = 0x400000000; #endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 51e8de4b8912..34818736a4f5 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -46,7 +46,7 @@ int dram_init(void)
ddr3_size = ddr3_init();
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) if (!(board_is_k2g_ice() || board_is_k2g_i1())) @@ -71,7 +71,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; }
@@ -120,7 +120,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
/* adjust memory start address for LPAE */ if (lpae) { - start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] -= CFG_SYS_SDRAM_BASE; start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; }
@@ -174,11 +174,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) "linux,initrd-end", NULL); if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); - initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start -= CFG_SYS_SDRAM_BASE; initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); - initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end -= CFG_SYS_SDRAM_BASE; initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end);
@@ -221,7 +221,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) *reserve_start = __cpu_to_be64(*reserve_start); size = __cpu_to_be64(*(reserve_start + 1)); if (size) { - *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += CONFIG_SYS_LPAE_SDRAM_BASE; *reserve_start = diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 2d42af6b809d..8c708355d4ca 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 9d4ffb0f979b..efef855b3d06 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -56,7 +56,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_SYS_FLASH_CFI /* Use 16-bit memory interface for NOR Flash */ @@ -76,8 +76,8 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 96d0185329d2..3c7cfa309c13 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -79,7 +79,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size());
return 0; diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 475250d8013a..65e0e9a156ab 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -73,7 +73,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size());
return 0; diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 07fe45447186..f335d5b4f4aa 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -266,7 +266,7 @@ int board_init(void) hw_watchdog_init(); #endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index 5d12f84cfeaa..c8e791a4da8a 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -67,15 +67,15 @@ int board_init(void) { reset_periph(); /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0; }
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 17ee541bd840..df4c45767238 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -105,7 +105,7 @@ int board_late_init(void) return board_late_init_xilinx(); }
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); @@ -123,8 +123,8 @@ int dram_init(void) #else int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
zynq_ddrc_init();
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 5fe0873fe221..f88c7f8fc902 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -236,7 +236,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, return ret; }
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { int ret; @@ -261,7 +261,7 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize();
mem_map_fill(); @@ -271,8 +271,8 @@ int dram_init_banksize(void)
int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE);
return 0; } diff --git a/boot/image-board.c b/boot/image-board.c index 34d1e5f18bef..8813be544be1 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -116,8 +116,8 @@ ulong env_get_bootm_low(void) return tmp; }
-#if defined(CONFIG_SYS_SDRAM_BASE) - return CONFIG_SYS_SDRAM_BASE; +#if defined(CFG_SYS_SDRAM_BASE) + return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) return gd->bd->bi_dram[0].start; #else diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index aaaedfe9735e..bbd406fc66ec 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ARCH_KEYSTONE #include <asm/arch/ddr3.h> -#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE +#define DDR_MIN_ADDR CFG_SYS_SDRAM_BASE #define STACKSIZE (512 << 10) /* 512 KiB */
#define DDR_REMAP_ADDR 0x80000000 @@ -247,9 +247,9 @@ static int is_addr_valid(u32 addr) /* Check in ecc address range 1 */ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 1 */ return 1; @@ -259,9 +259,9 @@ static int is_addr_valid(u32 addr) if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { range = readl(&emif->emif_ecc_address_range_2); start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 2 */ return 1; @@ -309,11 +309,11 @@ static int do_ddr_test(struct cmd_tbl *cmdtp, start_addr = hextoul(argv[2], NULL); end_addr = hextoul(argv[3], NULL);
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) || - (start_addr > (CONFIG_SYS_SDRAM_BASE + + if ((start_addr < CFG_SYS_SDRAM_BASE) || + (start_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || - (end_addr < CONFIG_SYS_SDRAM_BASE) || - (end_addr > (CONFIG_SYS_SDRAM_BASE + + (end_addr < CFG_SYS_SDRAM_BASE) || + (end_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { puts("Invalid start or end address!\n"); return cmd_usage(cmdtp); diff --git a/common/board_f.c b/common/board_f.c index e6117a7ba5e1..aab1130763e3 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -329,12 +329,12 @@ __weak int mach_cpu_init(void) /* Get the top of usable RAM */ __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size) { -#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0 +#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 /* * Detect whether we have so much RAM that it goes past the end of our * 32-bit address space. If so, clip the usable RAM so it doesn't. */ - if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) + if (gd->ram_top < CFG_SYS_SDRAM_BASE) /* * Will wrap back to top of 32-bit space when reservations * are made. @@ -369,8 +369,8 @@ static int setup_dest_addr(void) */ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif -#ifdef CONFIG_SYS_SDRAM_BASE - gd->ram_base = CONFIG_SYS_SDRAM_BASE; +#ifdef CFG_SYS_SDRAM_BASE + gd->ram_base = CFG_SYS_SDRAM_BASE; #endif gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->mon_len); diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 15806dfaee15..584503eb12e4 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -142,21 +142,21 @@ CONFIG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config -CONFIG_SYS_SDRAM_BASE: +CFG_SYS_SDRAM_BASE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_SIZE: +CFG_SYS_SDRAM_SIZE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_BASEX: +CFG_SYS_SDRAM_BASEX: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG1: +CFG_SYS_SDRAM_CFG1: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG2: +CFG_SYS_SDRAM_CFG2: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CTRL: +CFG_SYS_SDRAM_CTRL: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_MODE: +CFG_SYS_SDRAM_MODE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_EMOD: +CFG_SYS_SDRAM_EMOD: SDRAM config for SDRAM controller-specific registers, please see arch/m68k/cpu/<specific_cpu>/start.S files to see how these options are used. diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 35defb0af0b1..34a75e7fb007 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -96,8 +96,8 @@ to 0xDxxx_xxxx.
.. code-block:: c
- #define CONFIG_SYS_SDRAM_BASE 0xc8000000 - #define CONFIG_SYS_SDRAM_SIZE 0x08000000 + #define CFG_SYS_SDRAM_BASE 0xc8000000 + #define CFG_SYS_SDRAM_SIZE 0x08000000
You will need to change the environment variables location and setting, too. You may change other configs to fit your board. diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 5e8fb7a89c21..9dada5e11756 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -130,7 +130,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3c1f7a189120..f8d1468a26f1 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -230,7 +230,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fcff223b4f0d..4975dbb821e1 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -30,7 +30,7 @@ */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 0f2dc243cb82..1c4a1cae4df4 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -162,7 +162,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */ diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index a14c766dda71..c40cd768abf5 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60
-#ifndef CONFIG_SYS_SDRAM_SIZE +#ifndef CFG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) +#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 22f4995453ed..a3b662fb13da 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,7 +60,7 @@ config PCI_MAP_SYSTEM_MEMORY instead of a physical address (e.g. on MIPS). The PCI core will then remap the virtual memory base address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. - This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still + This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address.
config PCI_SRIOV diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index dc114027814d..b81eb3536896 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -191,7 +191,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev)
/* AHB-PCI Bridge Communication Registers */ writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); @@ -204,7 +204,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* PCI Configuration Registers for AHBPCI */ devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0); writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); writel(0xf0000000, devad + PCI_BASE_ADDRESS_2); writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index d514c040344c..c1be56ce7a08 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -158,9 +158,9 @@ static int sh7751_pci_probe(struct udevice *dev)
/* Set up target memory mappings (for external DMA access) */ /* Map both P0 and P2 range to Area 3 RAM for ease of use */ - p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); + p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); + p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); + p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
p4_out(0, SH7751_PCILSR1); p4_out(0, SH7751_PCILAR1); diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 99891dce61d5..a0b82c78321c 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -459,9 +459,9 @@ static void pcie_dw_set_host_bars(const void *regs_base) }
/* Set the BAR base and size towards DDR */ - bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; + bar0 = CFG_SYS_SDRAM_BASE & ~0xf; bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; - writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); + writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
reg = ((size >> 20) - 1) << 12; writel(size, regs_base + RESIZABLE_BAR_CTL0); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index a52774179e2f..b7f692f64507 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -14,11 +14,11 @@ #include <asm/arch-ls102xa/svr.h>
#ifndef CFG_SYS_PCI_MEMORY_BUS -#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE #endif
#ifndef CFG_SYS_PCI_MEMORY_PHYS -#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE #endif
#ifndef CFG_SYS_PCI_MEMORY_SIZE diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index 141b19b57ac0..dc466a88e712 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -203,7 +203,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_1024M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -231,7 +231,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 9ad398d24155..dd4285020d76 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -724,7 +724,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_2048M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -752,7 +752,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, @@ -893,7 +893,7 @@ static void ast2600_sdrammc_update_size(struct dram_info *info) break; }
- info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
if (0 == (conf & SDRAM_CONF_ECC_SETUP)) diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index d12a3b4f436e..1737fdac9707 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -243,17 +243,17 @@ static int mtk_ddr3_rank_size_detect(struct udevice *dev) * and it has maximum addressing region */
- writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); + writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
- if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN) + if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN) return -EINVAL;
for (step = 0; step < 5; step++) { - writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + + writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
- start = readl(CONFIG_SYS_SDRAM_BASE); - test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step)); + start = readl(CFG_SYS_SDRAM_BASE); + test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step)); if ((test != ~WALKING_PATTERN) || test == start) break; } @@ -727,7 +727,7 @@ static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info) struct mtk_ddr3_priv *priv = dev_get_priv(dev); u32 val = readl(priv->emi + EMI_CONA);
- info->base = CONFIG_SYS_SDRAM_BASE; + info->base = CFG_SYS_SDRAM_BASE;
switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) { case 0: diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 42daf0686686..bb21078df140 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -2687,7 +2687,7 @@ static int octeon_ddr_probe(struct udevice *dev) if (!mem_mbytes) return -ENODEV;
- priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = MB(mem_mbytes);
/* diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 69c454a4ba86..6929a7e494ee 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -617,12 +617,12 @@ static int sdram_col_row_detect(struct udevice *dev)
/* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + params->chan.bw - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; }
@@ -637,11 +637,11 @@ static int sdram_col_row_detect(struct udevice *dev)
/* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; }
diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index b3e7421d0854..ec46ba54575e 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -220,12 +220,12 @@ int sdram_detect_col(struct sdram_cap_info *cap_info, u32 bw = cap_info->bw;
for (col = coltmp; col >= 9; col -= 1) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (col + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -245,12 +245,12 @@ int sdram_detect_bank(struct sdram_cap_info *cap_info, u32 bk; u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bktmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) bk = 3; else bk = 2; @@ -268,12 +268,12 @@ int sdram_detect_bg(struct sdram_cap_info *cap_info, u32 dbw; u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bw + 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) dbw = 0; else dbw = 1; @@ -337,12 +337,12 @@ int sdram_detect_row(struct sdram_cap_info *cap_info, void __iomem *test_addr;
for (row = rowtmp; row > 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (row + bktmp + coltmp + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -363,8 +363,8 @@ int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, u32 row = cap_info->cs0_row; void __iomem *test_addr, *test_addr1;
- test_addr = CONFIG_SYS_SDRAM_BASE; - test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = CFG_SYS_SDRAM_BASE; + test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE + (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
writel(0, test_addr); @@ -421,15 +421,15 @@ int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type)
/* detect cs1 row */ for (row = cap_info->cs0_row; row > 12; row--) { - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + cs0_cap + (1ul << (row + bktmp + coltmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap); + writel(0, CFG_SYS_SDRAM_BASE + cs0_cap); writel(PATTERN, test_addr);
if (((readl(test_addr) & byte_mask) == (PATTERN & byte_mask)) && - ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) & + ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) & byte_mask) == 0)) { break; } diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index c024a0cd6337..98b2593ac49f 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -726,7 +726,7 @@ static int px30_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index 832154ee3af1..a2425f22e2ca 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -616,12 +616,12 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in
/* Detect col. */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -638,11 +638,11 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in rk3066_dmc_move_to_access_state(chan); /* Detect row, max 15, min13 for rk3066 */ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -854,7 +854,7 @@ static int rk3066_dmc_probe(struct udevice *dev) if (ret) return ret; } else { - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); }
diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 16cfbf947bde..ded65393806e 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -23,7 +23,7 @@ static int rk3128_dmc_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[1]);
diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index be8ba4464d45..272b1b2dce1f 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -638,12 +638,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
/* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -660,11 +660,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row, max 15,min13 in rk3188*/ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -919,7 +919,7 @@ static int rk3188_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index cd4234f389eb..1b204fb56e66 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -636,12 +636,12 @@ static int dram_cap_detect(struct dram_info *dram, writel(3, &axi_bus->ddrconf); move_to_access_state(dram->chan[0].pctl); for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -656,11 +656,11 @@ static int dram_cap_detect(struct dram_info *dram,
/* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -672,11 +672,11 @@ static int dram_cap_detect(struct dram_info *dram, sdram_params->ch[0].cs0_row = row; } /* cs detect */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); - writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); - if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + writel(0, CFG_SYS_SDRAM_BASE); + writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30)); + writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4); + if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && + (readl(CFG_SYS_SDRAM_BASE) == 0)) sdram_params->ch[0].rank = 2; else sdram_params->ch[0].rank = 1; @@ -813,7 +813,7 @@ static int rk322x_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 227a3cc6a88d..83778ad1c2c1 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -684,12 +684,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
/* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -705,11 +705,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -1087,7 +1087,7 @@ static int rk3288_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 44d7d8a0d9be..10828e80822a 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -21,7 +21,7 @@ static int rk3308_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
return 0; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 9c6798f816ac..b511c6bf6fe5 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -580,7 +580,7 @@ static int rk3328_dmc_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index cbf502bd0e96..136e4ede7122 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3151,7 +3151,7 @@ static int rk3399_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); #endif diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c index 0ac4b54eef3e..f661615c1b91 100644 --- a/drivers/ram/rockchip/sdram_rk3568.c +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -21,7 +21,7 @@ static int rk3568_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index 130b73dfe49d..60525f228679 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -90,7 +90,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* AHB-PCI Bridge Communication Registers */ writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win1_ctr); writel(0xf0000000 | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win2_ctr); @@ -103,7 +103,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, &ahbcom_pci->ahbpci_win1_ctr); writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); writel(0xf0000000, &ahbconf_pci->win2_basead); writel(SERREN | PERREN | MASTEREN | MEMEN, &ahbconf_pci->cmnd_sts); diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 2ee6212c58dc..9110a4848211 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -385,7 +385,7 @@ static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS); - writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); + writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); writel(mode->xres * 4, &de_fe->ch0_stride); writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt); writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt); @@ -1222,7 +1222,7 @@ static int sunxi_de_probe(struct udevice *dev) EFI_RESERVED_MEMORY_TYPE); #endif
- fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE; + fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE; if (overscan_offset) { fb_dma_addr += 0x1000 - (overscan_offset & 0xfff); sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000); diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 719caf7b0c3b..3a4fbc6eab83 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -30,8 +30,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xc8000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xc8000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ad7bd133200f..ab889180eede 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -26,8 +26,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xD0000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 25c3f22bea13..6dfa3dd0f02a 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -60,22 +60,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1002000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index f200d706a92a..e28662c6e59a 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -70,10 +70,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* * For booting Linux, the board info and command line data @@ -81,7 +81,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -109,8 +109,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 9ff66d751c66..f1da278d5159 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -52,10 +52,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */ @@ -67,7 +67,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -90,8 +90,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f7bfe598a80a..bd3c57d1438c 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -77,17 +77,17 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) @@ -117,8 +117,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index dcd83650f22e..7c3bc032bfee 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -71,10 +71,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE 0xffe00000
/* @@ -82,7 +82,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* * FLASH organization @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 9012794501a8..4eb4abea7251 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -73,10 +73,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/* @@ -84,7 +84,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -101,8 +101,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 925d26eaf10d..eda394467e93 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -72,10 +72,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 @@ -85,7 +85,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -105,8 +105,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 79a4e6171d23..159993a46bc5 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -74,22 +74,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -118,8 +118,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index fc21af56ec7b..d7ece6393498 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -68,22 +68,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f7c09a2333cb..b2fc6923e0d9 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -70,22 +70,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index a5518d3d50f2..2e7140cd86a1 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -62,8 +62,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) #define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
-/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ +#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */ #define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 0e70b2853b29..d9627e393d9c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -69,7 +69,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c59a37646f49..6a51149a9494 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -40,7 +40,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f87e7597ad04..21491b9f97ca 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -110,9 +110,9 @@ #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8c7b877bfb92..d7e06d23ec45 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -69,10 +69,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/* * Local Bus Definitions diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 824190a41234..417b9ae7b241 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFKW_H
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
/* * NS16550 Configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index e67da1fe1dc2..87b68227a0d9 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFXCAT_H
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
/* * NS16550 Configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 154b2f174afb..616387f48769 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -116,12 +116,12 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CFG_SYS_SDRAM_SIZE 2048 #endif
/* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 847cf65b4092..37dfe32e21bf 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -88,11 +88,11 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/* * IFC Definitions diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b49c26477684..8f56de40ce8f 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -86,8 +86,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index aae41a339254..e9db4a224f90 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -81,8 +81,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9dc45e397f9b..cc86c9d4a51b 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -62,7 +62,7 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* * IFC Definitions @@ -154,7 +154,7 @@ #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/* * IFC Definitions diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 78201adc07f5..57f3f37908df 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -13,7 +13,7 @@ #include <environment/ti/mmc.h>
/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 140940730d0e..25c71f00a20f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -16,7 +16,7 @@ #include <environment/ti/k3_dfu.h>
/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0345160787ef..0307426e4aba 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -15,7 +15,7 @@ #include <environment/ti/k3_dfu.h>
/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 2bda66fe033b..eba78d3894c8 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -33,8 +33,8 @@ /* size of internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 650140bb724c..63c7dfc1feba 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 3114cf0c4fba..865aad2a3f90 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/ap152.h b/include/configs/ap152.h index f0674456fd0c..0464a69e8236 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index e2e491bdb0aa..cf23837863be 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -63,7 +63,7 @@ /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 30d32d27e3dc..356d4c35ee2b 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/arbel.h b/include/configs/arbel.h index f7deba4f5666..ed32e772f8e2 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -6,9 +6,9 @@ #ifndef __CONFIG_ARBEL_H #define __CONFIG_ARBEL_H
-#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 35e8840a92a0..90cf4705f4f4 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -406,7 +406,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 5c9005805e1f..cbd0d6cea011 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -14,7 +14,7 @@
/* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE +#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ #define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 58635df149b7..b142ea3c3350 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,7 @@
#define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/* * Define baudrate for UART1 (console output, tftp, ...) @@ -158,7 +158,7 @@ * (Set up by the startup code) * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* * Chipselect bank definitions @@ -195,8 +195,8 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
@@ -213,8 +213,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 574bfe37e9ad..0d76f419db5b 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -31,8 +31,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 2c785ad4264d..dcc1cca4791b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -17,8 +17,8 @@ #include <asm/hardware.h>
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index bba8574b1c86..aefa9fc60c40 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -23,8 +23,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 @@ -100,22 +100,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 3ce264a4a90b..08cfee1a4e18 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 5e3ded241fa9..76f87c16192e 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -14,8 +14,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000
/* DataFlash */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b79c8ba5bf86..e1111b6dd38e 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 40ea4ed49e8a..eb1d1ad60d1a 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -20,8 +20,8 @@ */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* DataFlash */
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index e3b6956eb5a2..83ac87b10a58 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -28,7 +28,7 @@ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
/* * Serial console configuration diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 1932713f453a..6d82712186d4 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -20,8 +20,8 @@ */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_512M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_512M
/* * UART configuration diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h index d0c46a2c823b..b02ed1bfe0e0 100644 --- a/include/configs/bcm947622.h +++ b/include/configs/bcm947622.h @@ -6,7 +6,7 @@ #ifndef __BCM947622_H #define __BCM947622_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#define COUNTER_FREQUENCY 50000000 #endif diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h index 1346ace4bf6c..246feb66b295 100644 --- a/include/configs/bcm94908.h +++ b/include/configs/bcm94908.h @@ -6,6 +6,6 @@ #ifndef __BCM94908_H #define __BCM94908_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h index f3d17ddaacfb..c428b1ab5785 100644 --- a/include/configs/bcm94912.h +++ b/include/configs/bcm94912.h @@ -6,6 +6,6 @@ #ifndef __BCM94912_H #define __BCM94912_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index 361569a8c5f0..f1b68ba67338 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -6,7 +6,7 @@ #ifndef __BCM963138_H #define __BCM963138_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_HZ_CLOCK 500000000
#endif diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h index edbdfc3c51ad..90dfa98311d2 100644 --- a/include/configs/bcm963146.h +++ b/include/configs/bcm963146.h @@ -6,6 +6,6 @@ #ifndef __BCM963146_H #define __BCM963146_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h index 5a24cccba108..54f6750c7433 100644 --- a/include/configs/bcm963148.h +++ b/include/configs/bcm963148.h @@ -6,6 +6,6 @@ #ifndef __BCM963148_H #define __BCM963148_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h index b15c4111c967..2fdd22d1b0d1 100644 --- a/include/configs/bcm963158.h +++ b/include/configs/bcm963158.h @@ -6,6 +6,6 @@ #ifndef __BCM963158_H #define __BCM963158_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h index b25f6a12819a..32fc4a5e390f 100644 --- a/include/configs/bcm963178.h +++ b/include/configs/bcm963178.h @@ -6,6 +6,6 @@ #ifndef __BCM963178_H #define __BCM963178_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h index c8f32672b7d8..c69d177da2ea 100644 --- a/include/configs/bcm96756.h +++ b/include/configs/bcm96756.h @@ -6,6 +6,6 @@ #ifndef __BCM96756_H #define __BCM96756_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h index 5d9e87b693a0..37d2d91d96f0 100644 --- a/include/configs/bcm96813.h +++ b/include/configs/bcm96813.h @@ -6,6 +6,6 @@ #ifndef __BCM96813_H #define __BCM96813_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h index 1d6d5d616691..581fd559856e 100644 --- a/include/configs/bcm96846.h +++ b/include/configs/bcm96846.h @@ -6,6 +6,6 @@ #ifndef __BCM96846_H #define __BCM96846_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h index 6e420f2c66fb..3fb1ab9230c8 100644 --- a/include/configs/bcm96855.h +++ b/include/configs/bcm96855.h @@ -6,6 +6,6 @@ #ifndef __BCM96855_H #define __BCM96855_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h index a7ae71eeaafe..5f5af321897a 100644 --- a/include/configs/bcm96856.h +++ b/include/configs/bcm96856.h @@ -6,6 +6,6 @@ #ifndef __BCM96856_H #define __BCM96856_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h index 4e584b41fb37..9a0d89a7519f 100644 --- a/include/configs/bcm96858.h +++ b/include/configs/bcm96858.h @@ -6,6 +6,6 @@ #ifndef __BCM96858_H #define __BCM96858_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h index 3e23e94ac4bd..7702d1f56828 100644 --- a/include/configs/bcm96878.h +++ b/include/configs/bcm96878.h @@ -6,6 +6,6 @@ #ifndef __BCM96878_H #define __BCM96878_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 76189a4d31f7..b5469880fe2f 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -15,7 +15,7 @@ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* * Initial SP before reloaction is placed at end of first DRAM bank, diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9f51b9ca59d2..9769a7140926 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -81,7 +81,7 @@ extern phys_addr_t prior_stage_fdt_address; * MiB. However, BOLT can be configured to allow loading larger * initramfs images, in which case this limitation is eliminated. */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
/* diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 829e816ad664..556bfa08ebba 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_BITMAIN_ANTMINER_S9_H #define __CONFIG_BITMAIN_ANTMINER_S9_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index ca2bc1907e39..a075a5b2f326 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -199,7 +199,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index c328f4142015..e40f110cac6e 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index d16d50e5ec2f..508317f231ee 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index f69c46b11c4b..c5bda16d2bcd 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index acd021ecadcc..32397c26e8ab 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index fa9e5f02a085..18c99727a042 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index bcf5c874d322..f8d7148d497e 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index e31b8bc719e6..d564a32ee526 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6e707d341b7f..f982a4363db6 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index bb72c8cb533b..11d623c28b21 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index a1c992b7a6e6..30965c85bfaa 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/boston.h b/include/configs/boston.h index a09e831c540e..0033a7fb0223 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -22,9 +22,9 @@ * Memory map */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index bdedf7ea2d78..78b2000aa2ed 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -76,7 +76,7 @@ BUR_COMMON_ENV \
/* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 1bf6baf75c23..f1734aaca7f5 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -45,7 +45,7 @@ * always, even when we have more. We always start at 0x80000000, * and we place the initial stack pointer in our SRAM. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c4110f84c0bc..474ad69d996c 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -92,7 +92,7 @@
/* On CCP board, USDHC1 is for eMMC */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 /* DDR3 board total DDR is 1 GB */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index c395384c8d38..6f2b8245b986 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -111,7 +111,7 @@
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index b7511adc09ad..f268dfd0943d 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -11,7 +11,7 @@
/* Memory configuration */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index fc45e597f6d1..eb899c455782 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 25443629e208..47c4aacc436b 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,7 +21,7 @@ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 52000b58b73f..65b9074cd9cb 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -30,7 +30,7 @@ */
#define CONFIG_SYS_CLK 66000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -152,9 +152,9 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
/* *------------------------------------------------------------------------- @@ -162,7 +162,7 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */
-/* #define CONFIG_SYS_SDRAM_SIZE 16 */ +/* #define CFG_SYS_SDRAM_SIZE 16 */
/* *----------------------------------------------------------------------- @@ -186,8 +186,8 @@ enter a valid image address in flash */ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index afe8badd6502..ca8445a3d05a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -116,7 +116,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index d641fbf47e75..6002d8d5c9f0 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -96,7 +96,7 @@ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CFG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 68d923c1ae19..14278e9ca4f7 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -100,7 +100,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index f9bf849ae980..c08095561d83 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -160,7 +160,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0f6f99d244f9..11283071397f 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -85,7 +85,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (256 * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8e0230c135e3..8aec52d508e2 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM_1 (V2M_BASE) #define PHYS_SDRAM_1_SIZE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 9d44e6723e2a..c7a3e47437bc 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -32,8 +32,8 @@ #define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 4f0188dd19ed..e2e1cfedbde1 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -166,7 +166,7 @@ /* Load U-Boot Image From MMC */
/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b944d50663ce..b16f3d48e386 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -42,7 +42,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5244b9cf5cc8..c473f3d86ebf 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -15,8 +15,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_64M
/* * DMA diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index e694dd7551ae..ddc436d50190 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -72,7 +72,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/display5.h b/include/configs/display5.h index 0e5ecab9feb2..0a7428b02caf 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -283,7 +283,7 @@
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index c37b4c635b27..daf7ecd7975b 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -17,7 +17,7 @@ #define PHYS_SDRAM_1 0x80000000 /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1fa5d05e7b47..31cd8536de4b 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0x5ea4ffff
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#include <config_distro_bootcmd.h>
diff --git a/include/configs/durian.h b/include/configs/durian.h index 8f0e8be43307..001596c00a45 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -11,7 +11,7 @@ /* Sdram Bank #1 Address */ #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE 0x7B000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* BOOT */
diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 1d655292d7ef..fc1c2aed7780 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,7 +13,7 @@ /* * RAM */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
/* * cmd diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80a820c913b7..80de73d15d50 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -66,13 +66,13 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE0 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE0 0x00000000 +#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 +#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0 +#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0
/* * For booting Linux, the board info and command line data @@ -103,8 +103,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 16d2648e11f3..d24bc56f34ab 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -50,7 +50,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index a4891ddbc4ff..e39bb94314f3 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 60fab0419f5d..c2b921e7cb8b 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -8,8 +8,8 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_16M +#define CFG_SYS_SDRAM_BASE 0x10000000 +#define CFG_SYS_SDRAM_SIZE SZ_16M
/* * Environment diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 2f067a442482..b4f14a9a589d 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,7 +10,7 @@
#include <configs/exynos7420-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index f19e12d90904..97a8ffb4f61e 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -26,8 +26,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 44f5cb1e83f4..dd322c2b3a79 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -29,21 +29,21 @@
#define CONFIG_RD_LVL
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* SPI */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 8e2f135f934c..cc0cf5ecbfbd 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index a8bef860c2f7..cff910c1bd5b 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -23,21 +23,21 @@
/* select serial console configuration */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* Configuration of ENV Blocks */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index b05846d0b920..68c36dc2fd95 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -21,32 +21,32 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
#ifndef MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index ba098316e083..f5353ec79a1a 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -18,8 +18,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a1400eba1ada..a7557144402b 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -7,7 +7,7 @@ #define __CONFIG_GARDENA_SMART_GATEWAY_H
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index fa6f0e63ac50..6cdfe8c4c3c0 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -12,9 +12,9 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/* * Memory test diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index c862f15ee2b4..85ceaf8ccb1a 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -37,7 +37,7 @@ /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d519384d026e..1dba2e92fb9d 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -94,7 +94,7 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index d2138c220f0a..dd6b22de7bac 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,8 +13,8 @@ /* Miscellaneous */
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
/* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 645ca162a35a..fe00272a1bd0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -53,7 +53,7 @@
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/gxp.h b/include/configs/gxp.h index e3c97b20d51e..2b0b04891cc2 100644 --- a/include/configs/gxp.h +++ b/include/configs/gxp.h @@ -10,6 +10,6 @@ #ifndef _GXP_H_ #define _GXP_H_
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#endif diff --git a/include/configs/highbank.h b/include/configs/highbank.h index a7d21a76dba5..0d281a3379aa 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,7 +14,7 @@ * Miscellaneous configurable options */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 18c1e83aeb4a..775f166f1d35 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -24,7 +24,7 @@ /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ #define PHYS_SDRAM_1_SIZE 0x3EFFFFFF
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 973df8e4abce..914c3ad9ef04 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -16,7 +16,7 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_SIZE 0xC0000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 1d7b171da75a..fcb2dec54ec1 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -22,8 +22,8 @@ */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G
/* * UART configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 9e092e16ea04..0ae935208ca5 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -21,8 +21,8 @@ */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G
/* * UART configuration diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index 1fc45f9060bb..f1ca28b7ca32 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -21,8 +21,8 @@ */
/* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
/*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 974dff8f6f44..594aa4f75e77 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -130,5 +130,5 @@ "upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index b8eb5c82cf7e..d4e2583ee8a4 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -109,7 +109,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 6b822e725058..1b08c5e9a7e6 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -105,7 +105,7 @@
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index f7f8f33ed898..a074df5829b4 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -55,7 +55,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 15171d7ad67b..855af29ec96d 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -85,7 +85,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 70b4b84215d3..0a688afe6cdb 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -63,7 +63,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index c6db5e943eea..e5118f11580e 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -69,7 +69,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 917d567d2eca..e62f9c5462b2 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 8e0889945805..143da0011046 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -74,7 +74,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index dd9f93f35c29..c7669305f592 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index f1d1c1c9c3d1..9937071874fd 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 9cdba70493b2..cd47d842ffc7 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 065356341fca..58e165c35a7b 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 0ae3da12ad38..f532c1052f5d 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -78,7 +78,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index d6959ac95a13..415248eadfc5 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000
#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 9c75e3eec152..8857bc7c598b 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index a484d9136492..628bb5813ff1 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -46,7 +46,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d5252abb2180..a169be35a492 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index bf8782513644..62bcef5eecdb 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1b533e2c142e..d394762e3bb2 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -55,7 +55,7 @@
/* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000
diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 7986d20eed1a..3e995c972172 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 8f2b474817d9..1943a24b79db 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -136,7 +136,7 @@
/* Totally 6GB or 4G DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G) #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index b1c213cc89b6..7d360583c416 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4b2107e40574..271376cb9fc8 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 2d4c8d78c676..672a9fa7a342 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 1905e538c5be..dd354b0265de 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -88,7 +88,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7f6d59db3aa2..f1f907f3e5a4 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -103,7 +103,7 @@
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 67f19bc19220..fe27ac36a3b1 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -108,7 +108,7 @@ */ #define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 567351fcad64..19f1dba04706 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -103,7 +103,7 @@
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 7bf0ce784c5e..592df2795b13 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -54,7 +54,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index b28146640863..077a4d843dcd 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 512e0e61aa78..8d0458d1d63f 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -30,7 +30,7 @@ */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* * FLASH and environment organization diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index a2e50c3b8df2..5a769e078717 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -32,12 +32,12 @@ * : : * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : - * Specified explicitly by CONFIG_SYS_SDRAM_BASE + * Specified explicitly by CFG_SYS_SDRAM_BASE * * NOTES: * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, - * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing - * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on + * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing + * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage * leading to unexpected behavior, typically but not limited to: * - "Returning" back to bogus caller function @@ -50,16 +50,16 @@ #define DCCM_BASE 0x80000000 #define DCCM_SIZE SZ_128K
-#define CONFIG_SYS_SDRAM_BASE DCCM_BASE -#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE +#define CFG_SYS_SDRAM_BASE DCCM_BASE +#define CFG_SYS_SDRAM_SIZE DCCM_SIZE
#define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K
#define RAM_DATA_BASE SYS_INIT_SP_ADDR -#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ +#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \ (SYS_INIT_SP_ADDR - \ - CONFIG_SYS_SDRAM_BASE) - \ + CFG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 9f54f259994a..2a0b0c7163a7 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -16,7 +16,7 @@ #include <environment/ti/k3_dfu.h>
/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ #define CONFIG_SYS_FLASH_BASE 0x000000000
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 932d7d3c8cb5..e690ef959060 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -17,7 +17,7 @@ #include <environment/ti/k3_dfu.h>
/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7d36a25dc232..db1daee13633 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -7,7 +7,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -17,7 +17,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
/* * The reserved memory diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index ad9853ab6b3b..b5913ed70003 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index c8423fdfb0ab..dbf038cefa03 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -163,10 +163,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/****************************************************************************** * (PRAM usage) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index b3e1fc2a864e..e2808ec02dc1 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -14,7 +14,7 @@
/* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index a2aedefcec21..73b595176219 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -17,7 +17,7 @@ /* RAM */ #define PHYS_SDRAM DDR_CSD1_BASE_ADDR #define PHYS_SDRAM_SIZE (SZ_4G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 6acd2f792534..9b452818c1e1 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 7ed1f153c232..bbf0761814b4 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -21,7 +21,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c401fd32169d..967de66f3c9d 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -67,7 +67,7 @@ #define PHYS_SDRAM_1_SIZE (512 * SZ_1M) #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index b0e49ad6df07..de1fc0bfa4c6 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -86,7 +86,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 1f642fbecc3c..bee064c6f385 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -85,7 +85,7 @@ "bootscript=source ${bootscraddr}\0"
/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/librem5.h b/include/configs/librem5.h index dbd7d107dae9..3a2c508ffacf 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -82,7 +82,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 28372d41590a..b9134508853b 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -7,7 +7,7 @@ #define __CONFIG_LINKIT_SMART_7688_H
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 1d51b87b68b3..d1ebd99ae144 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -87,7 +87,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 196e024b57e0..f0a9e9ab3155 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -9,7 +9,7 @@ #include "ls1012a_common.h"
/* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000
#undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 809f9ae8c8dc..07124370775b 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -12,7 +12,7 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 674bcbeb7584..c19ed2f43ecf 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h"
/* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
#undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 9ad3a1201183..54555b34dd47 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h"
/* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000
/* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 4f77acdaedec..d74936d1281d 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h"
/* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000
/* * I2C IO expander diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3579f9c8437b..49a77fd6b6bb 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -42,7 +42,7 @@ #define SDRAM_CFG_BI 0x00000001
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* * Serial Port diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 45665115f662..1f5a80ff085a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -20,7 +20,7 @@ #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 1e2db12a83f2..495460661150 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -57,7 +57,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 323feb6e3333..d77224934c01 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* * IFC Definitions diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 587f23be587f..064c4f069cbd 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -15,7 +15,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index df6338298b48..e940dff99889 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b09588f4796d..ce254d8b3f12 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 2117b0811686..f8eaee881d06 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -32,7 +32,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c79a50795b8c..21c097ecbbdf 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -19,7 +19,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/* diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 8b2b7479c11b..ad85e2de6eda 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 0x200000000UL +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1734f323f929..cbdb2fa1357e 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/malta.h b/include/configs/malta.h index 2dd34ea7313c..c9aee00cd357 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -22,11 +22,11 @@ */
#ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index db84302231a6..5ad945b55896 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,6 +47,6 @@ */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_SIZE SZ_1G
#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index f9f0825f6f81..8aa3b0cd808c 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -214,7 +214,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index c6ce8837474e..2422cbf9f0b6 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -17,7 +17,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/meesc.h b/include/configs/meesc.h index cd3910ee4ba6..2e07886c194b 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -44,8 +44,8 @@ #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 0c41df2a9574..f06fe73485fb 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -29,7 +29,7 @@ #define STDIN_CFG "serial" #endif
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0
/* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 4c7cfac8af75..3def93d61e8a 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -9,7 +9,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index bd35378800b7..ac5ff9289a52 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ #define PHYS_SDRAM_2 0xc0000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index c76e1fcaed9e..65cd6f5bc4c2 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7620_H #define __CONFIG_MT7620_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index e09e9c82eb8d..1211bb474880 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7621_H #define __CONFIG_MT7621_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index fd8e30acf592..e5d60e1cd2b1 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -15,7 +15,7 @@ /* SPL -> Uboot */ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 73093f94d2b6..39a7ba76633b 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -21,7 +21,7 @@ #define MMC_SUPPORTS_TUNING
/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* This is needed for kernel booting */ #define FDT_HIGH "0xac000000" diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index bb12ebfe4fd0..9c5034f5f086 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7628_H #define __CONFIG_MT7628_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 668dc3c4f741..d330adbc01b9 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -25,7 +25,7 @@ /* UBoot -> Kernel */
/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 9f26b0ba7bba..249f0b9662d0 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#endif diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 4fbd57a573db..990e411a6406 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#endif diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 7cabbef92889..8a8bc85ca70e 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -10,8 +10,8 @@ #define __MT8518_H
/* DRAM definition */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
/* Uboot definition */
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e870fc810cb1..e45bfd76b6e1 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -27,7 +27,7 @@ */
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
/* * NS16550 Configuration diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 41bdfae6c31c..9c4038be8b04 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -9,7 +9,7 @@ #include <asm/arch/soc.h>
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x200000000 +#define CFG_SYS_SDRAM_BASE 0x200000000
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 6d3cb99b2dfe..7641b5622194 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -13,7 +13,7 @@ */
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 5debd9117c6e..358e06fd2079 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index dd303a17d61c..aa3d7a1a3fc8 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -10,7 +10,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Status LED */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 4c0531212edd..f597cdb30563 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 140f5e98c521..bc8c89337043 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* UBI and NAND partitioning */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 95afb350ec34..2229980db370 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -112,7 +112,7 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 778356397202..e84bac67ef72 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 3c9b2ad58ee4..9e837a388337 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -95,7 +95,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b26613a2ea83..52ff7b00b436 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -96,7 +96,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 1db4d6c01b17..3c4ba095e4e7 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -85,7 +85,7 @@ #include <config_distro_bootcmd.h>
/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index a6cefab5508a..9c160c41ece6 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index bc9fab12909a..711b5a334aad 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -139,7 +139,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ca1d077437b7..3c2621d8c91a 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 44a5eeff1984..a3a12aeb3900 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -82,7 +82,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_2G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index a41e428eb8ad..f0e239fdb6eb 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -78,7 +78,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index c655671ee1bd..a0f9c537e5dd 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 65f0a5c99662..8199b4b8319e 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -108,7 +108,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 604923ec2b77..827385c65e2a 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -102,7 +102,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index af176583814f..c39b3572b84b 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -81,7 +81,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 62e8e6299118..362de482f575 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -26,7 +26,7 @@ /* Physical Memory Map */
#define PHYS_SDRAM 0x60000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index e93824928b32..9ef1eea5e61d 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -26,7 +26,7 @@
#define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 273f938554de..cdd12866ac0a 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index ec5339d930a3..9d0981131647 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -90,7 +90,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index cc4784232f9b..9732039ef126 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -160,7 +160,7 @@ * FLASH and environment organization */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
@@ -169,7 +169,7 @@ */
#define SDRAM_SIZE 0x10000000 /* 256 MB */ -#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) +#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE)
#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ #define KERNEL_OFFSET 0x40000 /* 256 kB */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 9dc05d80ec2c..8d39d75a42bc 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ea407c9f6f1a..080c659b6ecb 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nsim.h b/include/configs/nsim.h index d469ef83c240..b930a538640d 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -13,8 +13,8 @@ */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_256M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_256M
/* * Console configuration diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 00f7d871271d..5ac951a370a4 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -7,7 +7,7 @@ #include "mx6_common.h"
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 0fa7490e7de6..b475354bbc6d 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -14,6 +14,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 #endif
-#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index ab1eb787e70f..03d1a8e7b5fc 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -10,7 +10,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 38f99ab21674..58275ccffa01 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -36,7 +36,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h index babd3ca9631c..ce8ea583fa10 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -17,9 +17,9 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#include <linux/sizes.h>
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 15646297423e..d2d7fca54450 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -10,7 +10,7 @@ #include <configs/exynos5420-common.h> #include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#define TZPC_BASE_OFFSET 0x10000
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 2b47d4ca3768..5b0d87a33679 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -154,7 +154,7 @@ /* defines for SPL */
/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 3ff8187b5df7..5b097e9fef29 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -14,7 +14,7 @@ #include <linux/sizes.h>
/* Environment options */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index b3cdd2f1ebe3..53889d699b26 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -14,7 +14,7 @@ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/origen.h b/include/configs/origen.h index 36aaa7c14fb3..6633d541a31b 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -11,8 +11,8 @@ #include <configs/exynos4-common.h>
/* ORIGEN has 4 bank of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Power Down Modes */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index b0233b96b06d..8d0311cfb3b4 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -11,7 +11,7 @@ #define _OWL_COMMON_CONFIG_H_
/* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0
/* Some commands use this as the default load address */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6e8ac1b98df5..14d702e1efeb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -125,13 +125,13 @@ #define SPD_EEPROM_ADDRESS 0x52
#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #else -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 6267dc729ab6..85cedde09884 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -34,7 +34,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index e13b5df0fabd..f7e36f22ce87 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -36,7 +36,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a04a03a7e181..586cddf41848 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -118,7 +118,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 14cbfde28bfe..cf705dcb1972 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -15,7 +15,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 7a8d3c63d445..bfc0011fbf96 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -20,7 +20,7 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_POWER_TPS65090_EC
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 2c749ac2143d..09c6b4f8dd51 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -20,7 +20,7 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index c98393b7c757..ac68c933a06e 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 49cd9d4b3c69..aedaf806e5e7 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -63,7 +63,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 4ea16d6115ab..d9abbbc28b37 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -23,7 +23,7 @@ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CFG_SYS_SDRAM_BASE 0x88000000
/* Memory Test */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index f95beeb214a9..fc2cab960c67 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 85772ba6e838..22b4976d722f 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index b3a38d8a940a..f5b9eed2bcd9 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -93,7 +93,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 17af19d49dc1..91baff963862 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -67,7 +67,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index adb2f43ea4d1..3fbddd903a3f 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -78,22 +78,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -160,6 +160,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ ""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 4352a242de33..c1f6334d6a1a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -90,22 +90,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -184,6 +184,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ ""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index a7deaa321371..4a0a16818ed0 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -20,8 +20,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 05253d59efdc..365fdd30c08c 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -11,7 +11,7 @@ #endif
#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 2e206542f8db..1c11685f49e4 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -9,7 +9,7 @@ #define __POMELO_CONFIG_H__
/* SDRAM Bank #1 start address */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* SIZE of malloc pool */
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index f9decb2a4c2c..bee1ef649488 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -36,7 +36,7 @@ #define DDR_BASE 0x00000000 #define PHYS_SDRAM_1 DDR_BASE #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Console I/O Buffer Size */
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 8b151ef18836..99376155b491 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -14,7 +14,7 @@ #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30)
diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 535762ecb240..a67af73fd56f 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -10,7 +10,7 @@
/* Physical memory map */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 9fc51fdfd763..e7c810957d6d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -31,7 +31,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d81e5d6c8620..72f35cc05420 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,7 +8,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 406ee6282c5f..f6ee7201eba1 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -6,8 +6,8 @@ /* SCIF */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x8C000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x8C000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 3a38e0656de1..61b9447ea5f5 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -17,8 +17,8 @@ /* console */ #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
-#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */ #define CONFIG_TMU_TIMER diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 7432cffb5a56..585307259780 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -26,8 +26,8 @@ /* MEMORY */
#define DRAM_RSV_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) -#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6616396777a0..b4c19727478e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,7 @@
#define CONFIG_SYS_HZ_CLOCK 24000000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 9297184bded8..99c86edeaa40 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -11,7 +11,7 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 12d4bc65d7e4..fac27a7d27c6 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -14,7 +14,7 @@
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000
/* usb mass storage */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 6fe1b2d9a2e0..334fb3affa5e 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -13,7 +13,7 @@
/* spl size 32kb sram - 2kb bootrom */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 4fb86b69a8e9..6889ba591b3d 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -12,7 +12,7 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 81f16edbad64..4aa7e0449dbc 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -15,7 +15,7 @@
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 263d1bd180c5..4b510b139910 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -10,7 +10,7 @@
#define CONFIG_IRAM_BASE 0xfff80000
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 1e214e4ebe15..132b7d0fe9bc 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0xff090000
/* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000
#define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 37e0c1d936c3..92cdc1a51fbd 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -11,7 +11,7 @@ #include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee58197b..78f624d31ca2 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -21,7 +21,7 @@ /* RAW SD card / eMMC locations. */
/* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000
#ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 15e815234020..d43dc2580e46 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -10,7 +10,7 @@
#define CONFIG_IRAM_BASE 0xfdcc0000
-#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000
#define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index cd8fe8b518b5..2c24944d9c3d 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -23,7 +23,7 @@ #endif
/* Memory layout */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares @@ -31,7 +31,7 @@ * smaller amount of RAM is present in order to avoid stomping on the area * the VC uses. */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_SIZE SZ_128M
/* Devices */ /* LCD */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 83c3167f38dc..76836add3027 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000
/* rockchip ohci host driver */
diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index ae94f0ecc56a..e071d4da5e86 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,7 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x71000000 +#define CFG_SYS_SDRAM_BASE 0x71000000
/* * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in @@ -55,7 +55,7 @@ * Starting kernel ... * ... */ -#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE)
#define BMP_LOAD_ADDR 0x78000000
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index de4510aa4348..ed891ab22a98 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -14,7 +14,7 @@ #include <asm/arch/cpu.h> /* get chip and board defs */
/* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
@@ -114,7 +114,7 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0"
/* Goni has 3 banks of DRAM, but swap the bank */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 668b52600e85..614d04fda072 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -14,8 +14,8 @@ /* Keep L2 Cache Disabled */
/* Universal has 2 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index afb1e3d0f105..75302bf5c05d 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -17,7 +17,7 @@ #define CONFIG_USART_ID 0 /* ignored in arm */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
#endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 7c5bfdb2e6d3..22813d4c5448 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -23,8 +23,8 @@ */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index de6c92ed7d43..f826eab9ff2a 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000
/* SPL */
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index ebdb39273ef5..01ed1a3c8e7d 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 09cc4dddb2ad..2e3c1ea40063 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND Flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 1c9af9b6759a..4b13a101170f 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -24,8 +24,8 @@ #define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index afb9b9a2fbf6..3f58928565ff 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -31,8 +31,8 @@ #endif
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
/* SerialFlash */
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 0daadec5536b..084cb4def667 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h"
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index d59899f0baa0..cbc1c0f46517 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h"
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 3f905bf2d77d..68fa31fe76fd 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000
#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5168e2fa3531..a3b2a7926fd8 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -26,8 +26,8 @@ /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y #define SB_TO_UL(s) SB_CONCAT(s, UL) -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE \ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index c9dd7509cb2a..31552f4619d7 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -33,7 +33,7 @@ /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 2e5592cf94d5..5ad2124bddab 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,7 +11,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 85fab927195f..f4b1a16019ec 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,7 +11,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 7159fc35d52b..974531ea0d82 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,8 +8,8 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_8M
#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 7c8f1676be26..d2bc73a400e5 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -45,8 +45,8 @@ * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M)
/* * Perform a SDRAM Memtest from the start of SDRAM diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 12c2e1f6159a..0392530c0adf 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -14,7 +14,7 @@
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ba562b237803..64963eebe5ce 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -16,7 +16,7 @@ /* input clock of PLL: SMDKC100 has 12MHz input clock */
/* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
@@ -77,7 +77,7 @@ */
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
/*----------------------------------------------------------------------- diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0b1f0c5f54ca..af0c8200fc23 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -11,7 +11,7 @@ #include "exynos4-common.h"
/* High Level Configuration Options */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,13 +23,13 @@
/* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index faa13c65216f..44b9109d442f 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -38,7 +38,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 7c35c912e597..9b1cb372ece7 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -21,8 +21,8 @@ /* CPU */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 6054fa42c1a2..95516800793a 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -32,7 +32,7 @@ * Memory */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* * I2C diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 70a24ed267ef..2656c9776730 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -38,7 +38,7 @@ * in U-Boot pre-reloc is higher than in SPL. */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* * U-Boot general configurations diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 2b2d78b8c8e0..9403e2f4306d 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -70,7 +70,7 @@ */ #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0
/* * Serial / UART configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index a60ac6d1a3c5..c628860eac74 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -55,7 +55,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */ @@ -73,7 +73,7 @@ #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ +#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/* * Flash on the LocalBus diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index dcb88a3a730a..008aa5001072 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -53,7 +53,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 1e966a23227c..806323e375df 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -11,7 +11,7 @@
/* ram memory-related information */ #define PHYS_SDRAM_1 0x40000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000
#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 07a5bfc8a86e..d71114931427 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index b809f9322ad2..f78ce41ed854 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ba49075ce068..234327e017bc 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -56,10 +56,10 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_DRAM_TEST
@@ -75,8 +75,8 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -89,8 +89,8 @@ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 567aa1ffe433..b2dcb6058b10 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -10,7 +10,7 @@
/* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000
/* user interface */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cd2a74fb52d7..e1a66f53ff56 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -42,13 +42,13 @@ */ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #else #define SDRAM_OFFSET(x) 0x4##x -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ #endif
@@ -66,7 +66,7 @@ /* FIXME: this may be larger on some SoCs */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
/* mmc config */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 63d897d090af..daa9bbec88a7 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -11,7 +11,7 @@ /* * SDRAM (for initialize) */ -#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index dd1fe0af7cd2..1aba986e1e6a 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,8 +41,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
/* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 92ee920346bb..cd1309b3b889 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -13,8 +13,8 @@ */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M
/* * UART configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7f197851d0a7..2d8bde1cee86 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -13,7 +13,7 @@ /* General configuration */
/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 92df457e8189..7e764b0000b0 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -40,7 +40,7 @@ #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 655fcb0011b0..76b496303f3e 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -68,6 +68,6 @@ /* Defines for SPL */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_SDRAM_SIZE SZ_2G
#endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index cf2efdbe230b..1f60b9b49790 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -13,7 +13,7 @@ /* Link Definitions */
/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0)
/* PL011 Serial Configuration */
@@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index fc78077014b5..e5b23d2a54ca 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -69,7 +69,7 @@ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/** * Platform/Board specific defs diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 1bd2a1874b86..4a7c3d5b4495 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -20,7 +20,7 @@ #define V_SCLK (V_OSCK >> 1)
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/** * Platform/Board specific defs diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index b289b9e26a00..d54c208ef66f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -64,7 +64,7 @@ * initial stack pointer in our SRAM. Otherwise, we can define * CONFIG_NR_DRAM_BANKS before including this file. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
/* If DM_I2C, enable non-DM I2C support */
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index ab6cd0633215..a609aa3a2aa9 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -23,7 +23,7 @@ /* Top 48MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x03000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 22d783c325b2..137898199177 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CFG_SYS_SDRAM_BASE 0xa0000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a65ebfb4deab..f8e3a2d017a3 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -268,7 +268,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/trats.h b/include/configs/trats.h index ca3186877839..23dcf20c1f4e 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -16,8 +16,8 @@ #endif
/* TRATS has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index f324ea7ebeb5..9c6433ccfd87 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -17,8 +17,8 @@ #endif
/* TRATS2 has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index f549f9f7ad06..4ca8eafc9143 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,7 +8,7 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 268c737e7eb7..c1e80b44c854 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -49,7 +49,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 147224806fcc..f73092661a1d 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -57,7 +57,7 @@
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 2cdc3fbf737f..d2fd23e1d91d 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -25,8 +25,8 @@ */
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index c381934f31a9..e944e78603e7 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM CSD0_BASE_ADDR #define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 338d8af8fb36..d9e5dfaceaf8 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -14,13 +14,13 @@
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) -#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M) #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) -#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M) #else #error Unknown DDR size - please add! #endif diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index f513dade6aa6..b209d97e5ecb 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -60,7 +60,7 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index fea4329d23cc..1b9f2ca26f69 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -69,7 +69,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) #define PHYS_SDRAM_2 0x100000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0c11b6b3331e..9a46d50c6f39 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -96,7 +96,7 @@ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define PHYS_SDRAM_2 (0x880000000) diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 5d773060d826..ef136c75a83c 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -135,7 +135,7 @@ #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
/* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 215149af2e0b..7b526f725af6 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -123,7 +123,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vinco.h b/include/configs/vinco.h index a15729676184..df0e269b5d20 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x4000000
/* MMC */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a0846b3f7c96..7555d97c8148 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 2107bec6587a..38b940d35ea8 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,7 +7,7 @@ #define __VOCORE2_CONFIG_H__
/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b4c757fd9217..3acef2213273 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -89,7 +89,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a4b12dc55ed0..cba215c379fd 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -84,7 +84,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 054eb89d49ca..32555c9b6af1 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -16,8 +16,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M
#define CONFIG_RTC_DS1374
diff --git a/include/configs/xea.h b/include/configs/xea.h index 19ccf633c404..87f628d4ab8e 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -23,7 +23,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 364dae0cd934..612436aeb48f 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -11,7 +11,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_SDRAM_BASE +#undef CFG_SYS_SDRAM_BASE
#undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index d2c0e91b32e0..1b6e26ee3966 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -12,7 +12,7 @@
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x0
#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 7d0402feead5..613ed9595532 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -21,7 +21,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE (128 << 20)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index b93451cbe07a..8739bb24841e 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -42,12 +42,12 @@ */
#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE #else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 #endif
-#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
@@ -70,12 +70,12 @@ #endif
#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE + CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) #endif
/*==============================*/ diff --git a/include/init.h b/include/init.h index d40d11f33d22..699dc2482c08 100644 --- a/include/init.h +++ b/include/init.h @@ -90,8 +90,8 @@ int dram_init(void); * * If this is not provided, a default implementation will try to set up a * single bank. It will do this if CONFIG_NR_DRAM_BANKS and - * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of - * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CFG_SYS_SDRAM_BASE and the size will be determined by a call to * get_effective_memsize(). * * Return: 0 if OK, -ve on error diff --git a/include/system-constants.h b/include/system-constants.h index 83b41b384f39..07c3505e8f58 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,7 +12,7 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d249942af068..8deac75ebb05 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -467,7 +467,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { struct bd_info *bd = gd->bd;
- *vstart = CONFIG_SYS_SDRAM_BASE; + *vstart = CFG_SYS_SDRAM_BASE; *size = (gd->ram_size >= 256 << 20 ? 256 << 20 : gd->ram_size) - (1 << 20);
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index 1cc07bc80832..b5e9f9ddc98c 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -208,7 +208,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) * at SDRAM_BASE *device* address (p_paddr field). * Its size is defined by the p_filesz field. */ - phdr->p_paddr = CONFIG_SYS_SDRAM_BASE; + phdr->p_paddr = CFG_SYS_SDRAM_BASE; loaded_firmware_size = phdr->p_filesz;
/* @@ -231,7 +231,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Resource table */ - shdr->sh_addr = CONFIG_SYS_SDRAM_BASE; + shdr->sh_addr = CFG_SYS_SDRAM_BASE; rsc_table_size = shdr->sh_size;
loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET; @@ -243,7 +243,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) /* Load and verify */ ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size, &rsc_addr, &rsc_size)); - ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE); + ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE); ut_asserteq(rsc_size, rsc_table_size); ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset, shdr->sh_size);
On Wed, 16 Nov 2022 at 11:14, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
README | 2 +- arch/arc/lib/cache.c | 4 +- arch/arc/lib/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +-- arch/arm/dts/rockchip-optee.dtsi | 4 +- arch/arm/include/asm/emif.h | 2 +- arch/arm/include/asm/iproc-common/configs.h | 2 +- arch/arm/mach-aspeed/ast2500/board_common.c | 2 +- arch/arm/mach-aspeed/ast2600/board_common.c | 2 +-
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_TIMER_COUNTS_DOWN
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-kirkwood/include/mach/config.h | 1 - arch/sh/include/asm/config.h | 1 - configs/alt_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/blanche_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/porter_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/silk_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stout_defconfig | 1 + configs/syzygy_hub_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + include/configs/rcar-gen2-common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/vexpress_common.h | 1 - include/configs/zynq-common.h | 1 - lib/Kconfig | 3 +++ 40 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index ae1f6fee531e..5186f6e4f9ad 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,7 +52,6 @@
/* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK #endif diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 09a15da4859d..99d8797a549f 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,6 @@ #include <asm/processor.h>
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
diff --git a/configs/alt_defconfig b/configs/alt_defconfig index e4d6fc2d2cf3..d28cdf4b366b 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index cbcbc9b18db9..02257176e3e2 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -93,4 +93,5 @@ CONFIG_ZYNQ_SERIAL=y # CONFIG_WATCHDOG is not set CONFIG_WDT=y CONFIG_WDT_CDNS=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index bed737080742..630a13f9297b 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -81,3 +81,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 55222ebe01f7..b918b131d383 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index b4e6baef486c..24eff4648edf 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 472d8dafc436..56057e272dfa 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 83cc54aef908..ca56008cb50d 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index cee9a1ff5c55..4217175345da 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -57,4 +57,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 9ff9e23ef987..5005e1677fd6 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 2951574464bd..67c6e74eb846 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 9c3c0f66b2ea..ce1a3492992e 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b3ba9ff21e2e..01c29a25e34f 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -82,3 +82,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 5f5706fbdb22..905afb7d0461 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -75,3 +75,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 1f835bea9275..f2a53ba24711 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 412b0da0dbd1..dbf979ee476f 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 68a36892fb3d..613bf4426204 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -60,4 +60,5 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 3a21bc77a2e3..32d7b745207e 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 8be8b85c0c25..4d16ec32b61f 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -73,3 +73,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index debe22f30ac2..7a805df5a342 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -112,4 +112,5 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 31cc03a5fd89..b3de6701f931 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 72a70375360c..80a98712f67e 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -80,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 44e9ba6c8844..cbe37d22feb7 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -76,3 +76,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 96c0ebbc0cd1..cdad36bbfd8c 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -116,3 +116,4 @@ CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 231e22a2a0b8..53dce6a16129 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -104,3 +104,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index acce95ec026c..9bc03f2a904d 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -80,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index e3ed0b27327b..96aa62a7ec12 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index cb156562ba48..41ba8a7487d1 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 03d1887cdac4..763bd8cccdd3 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 234686eb7b0c..70ce13ecccf7 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -54,3 +54,4 @@ CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_BAUDRATE=38400 CONFIG_CONS_INDEX=0 +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1db3a2c63524..a4c555dac5c5 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -146,6 +146,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_SPL_GZIP=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 7ca74837aecb..74c35f3a4d80 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -78,5 +78,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 28e9c459817c..f1c648a8f9a6 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -80,5 +80,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 215d5ed5ebff..c623caf56489 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -90,5 +90,6 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 61b9447ea5f5..606a0a7ecde1 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -22,7 +22,6 @@
/* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2656c9776730..7ef7c5da8289 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -55,7 +55,6 @@ */ #ifndef CONFIG_TIMER #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) #ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index ef136c75a83c..de571f63ee12 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -114,7 +114,6 @@
#define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN
/* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 6574cf92e26e..2d6522af81b8 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -16,7 +16,6 @@
#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 #define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
/* GUIDs for capsule updatable firmware images */ diff --git a/lib/Kconfig b/lib/Kconfig index 6abe1d0a863b..c39fc5232147 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -15,6 +15,9 @@ config SYS_NUM_ADDR_MAP help Sets the number of entries in the virtual-physical mapping table.
+config SYS_TIMER_COUNTS_DOWN + bool "System timer counts down rathe than up" + config PHYSMEM bool "Access to physical memory region (> 4G)" help
On Wed, 16 Nov 2022 at 11:12, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_TIMER_COUNTS_DOWN
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-kirkwood/include/mach/config.h | 1 - arch/sh/include/asm/config.h | 1 - configs/alt_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/blanche_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/porter_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/silk_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stout_defconfig | 1 + configs/syzygy_hub_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + include/configs/rcar-gen2-common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/vexpress_common.h | 1 - include/configs/zynq-common.h | 1 - lib/Kconfig | 3 +++ 40 files changed, 36 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_MASTER CONFIG_SYS_SRIO
Signed-off-by: Tom Rini trini@konsulko.com --- README | 12 ------------ arch/powerpc/Kconfig | 15 +++++++++++++++ configs/MPC8548CDS_36BIT_defconfig | 2 ++ configs/MPC8548CDS_defconfig | 2 ++ configs/MPC8548CDS_legacy_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ configs/T2080QDS_NAND_defconfig | 4 ++++ configs/T2080QDS_SDCARD_defconfig | 4 ++++ configs/T2080QDS_SECURE_BOOT_defconfig | 4 ++++ configs/T2080QDS_SPIFLASH_defconfig | 4 ++++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 ++++ configs/T2080QDS_defconfig | 4 ++++ include/configs/MPC8548CDS.h | 3 --- include/configs/P2041RDB.h | 5 ----- include/configs/T102xRDB.h | 2 -- include/configs/T208xQDS.h | 6 ------ include/configs/T208xRDB.h | 1 - 20 files changed, 61 insertions(+), 29 deletions(-)
diff --git a/README b/README index b095937121b7..bb35a895b755 100644 --- a/README +++ b/README @@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing
-- CONFIG_SYS_SRIO: - Chip has SRIO or not - -- CONFIG_SRIO1: - Board has SRIO 1 port available - -- CONFIG_SRIO2: - Board has SRIO 2 port available - -- CONFIG_SRIO_PCIE_BOOT_MASTER - Board can support master function for Boot from SRIO and PCIE - - CONFIG_SYS_SRIOn_MEM_VIRT: Virtual Address of SRIO port 'n' memory region
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c355a954537d..cf93a7b1dad0 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" depends on MPC83xx || MPC85xx
+config SYS_SRIO + bool "Serial RapidIO support" + +config SRIO1 + bool "Board has SRIO 1 port available" + depends on SYS_SRIO + +config SRIO2 + bool "Board has SRIO 2 port available" + depends on SYS_SRIO + +config SRIO_PCIE_BOOT_MASTER + bool "Board can support master function for Boot from SRIO and PCIE" + depends on SYS_SRIO + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index e5c45a1bffab..98a2c4f85fc5 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 85ec76a59714..b47dbb533cee 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 852ac9a6eeb3..af2c6a25eb9c 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 2ba566644627..aa80f79fd7f7 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 9a2796fc7fce..bd223c18988d 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 8cb00d5d316b..dbd5845789cc 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index c0bd16bd61f8..c17318c7cc15 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index beb0259488de..9263174db8a1 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 7ee5fb4f476b..3ea1c30a32c0 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c050e310c8fb..05f631f7e777 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 0ff651ae6880..2bf2d377820c 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 98065da77d6d..31ef6035d50e 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xFFE20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 88e943d4d0d2..27bf2496e02e 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6a51149a9494..eb75f8b37d5f 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,9 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index d7e06d23ec45..be8d09f6dd75 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -32,11 +32,6 @@
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER - #ifndef __ASSEMBLY__ #include <linux/stringify.h> #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 616387f48769..f9f9318448b2 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -49,8 +49,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif
-/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8f56de40ce8f..acaad1bfc827 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,11 +14,6 @@ #include <linux/stringify.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#endif
/* High Level Configuration Options */
@@ -52,7 +47,6 @@
#endif /* CONFIG_RAMBOOT_PBL */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e9db4a224f90..7315afa39f81 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -47,7 +47,6 @@
#endif /* CONFIG_RAMBOOT_PBL */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
On Wed, 16 Nov 2022 at 11:13, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_MASTER CONFIG_SYS_SRIO
Signed-off-by: Tom Rini trini@konsulko.com
README | 12 ------------ arch/powerpc/Kconfig | 15 +++++++++++++++ configs/MPC8548CDS_36BIT_defconfig | 2 ++ configs/MPC8548CDS_defconfig | 2 ++ configs/MPC8548CDS_legacy_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ configs/T2080QDS_NAND_defconfig | 4 ++++ configs/T2080QDS_SDCARD_defconfig | 4 ++++ configs/T2080QDS_SECURE_BOOT_defconfig | 4 ++++ configs/T2080QDS_SPIFLASH_defconfig | 4 ++++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 ++++ configs/T2080QDS_defconfig | 4 ++++ include/configs/MPC8548CDS.h | 3 --- include/configs/P2041RDB.h | 5 ----- include/configs/T102xRDB.h | 2 -- include/configs/T208xQDS.h | 6 ------ include/configs/T208xRDB.h | 1 - 20 files changed, 61 insertions(+), 29 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
The rest of the unmigrated CONFIG symbols in the SRIO namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc8xxx/law.c | 20 +++---- arch/powerpc/cpu/mpc8xxx/srio.c | 72 +++++++++++++------------- board/freescale/common/p_corenet/tlb.c | 8 +-- board/freescale/t208xqds/tlb.c | 8 +-- board/freescale/t208xrdb/tlb.c | 8 +-- include/configs/MPC8548CDS.h | 8 +-- include/configs/P2041RDB.h | 46 ++++++++-------- include/configs/T102xRDB.h | 38 +++++++------- include/configs/T208xQDS.h | 42 +++++++-------- include/configs/T208xRDB.h | 42 +++++++-------- 10 files changed, 146 insertions(+), 146 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index dd274166c01a..35409dc8824c 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -309,42 +309,42 @@ void init_laws(void) */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c815d19384bd..dc1bc0db4237 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -240,8 +240,8 @@ void srio_init(void) devdisr = &gur->devdisr; #endif if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + set_next_law(CFG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -256,8 +256,8 @@ void srio_init(void)
#ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + set_next_law(CFG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -301,44 +301,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's ucode and ENV */ debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); }
void srio_boot_master_release_slave(int port) @@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + CFG_SYS_SRIO2_MEM_PHYS >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + CFG_SYS_SRIO1_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowar, SRIO_OB_ATMU_AR_MAINT @@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO2_MEM_PHYS + (CFG_SYS_SRIO2_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO1_MEM_PHYS + (CFG_SYS_SRIO1_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowar, @@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port) * by the maint-outbound window */ if (port - 1) { - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } else { - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } debug("SRIOBOOT - MASTER: " "Release slave successfully! Now the slave should start up!\n"); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 4cdef89bf0ee..7302b7606628 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -69,8 +69,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -150,8 +150,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 9160674b94fd..f2448e86c0d2 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 69e58e7e9732..45c27c081205 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eb75f8b37d5f..25b4fe0c7d4d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -282,13 +282,13 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index be8d09f6dd75..c3ef21633354 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,9 +18,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
@@ -173,49 +173,49 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif
/* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f9f9318448b2..b567b63980e9 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -53,40 +53,40 @@ * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #endif /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* PCIe Boot - Slave */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index acaad1bfc827..798822e5031f 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
@@ -295,39 +295,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif
/* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 7315afa39f81..ea366b671c02 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
@@ -254,39 +254,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif
/*
On Wed, 16 Nov 2022 at 11:13, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the SRIO namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
arch/powerpc/cpu/mpc8xxx/law.c | 20 +++---- arch/powerpc/cpu/mpc8xxx/srio.c | 72 +++++++++++++------------- board/freescale/common/p_corenet/tlb.c | 8 +-- board/freescale/t208xqds/tlb.c | 8 +-- board/freescale/t208xrdb/tlb.c | 8 +-- include/configs/MPC8548CDS.h | 8 +-- include/configs/P2041RDB.h | 46 ++++++++-------- include/configs/T102xRDB.h | 38 +++++++------- include/configs/T208xQDS.h | 42 +++++++-------- include/configs/T208xRDB.h | 42 +++++++-------- 10 files changed, 146 insertions(+), 146 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- .checkpatch.conf | 2 +- Kconfig | 6 +- Makefile | 16 +- README | 66 +-- arch/arm/cpu/arm1176/start.S | 2 +- arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/armv7/arch_timer.c | 6 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 4 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 4 +- arch/arm/cpu/armv7/stv0991/timer.c | 4 +- arch/arm/cpu/armv7m/systick-timer.c | 8 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 54 +-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3 | 4 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- arch/arm/cpu/armv8/sec_firmware.c | 4 +- .../include/asm/arch-fsl-layerscape/config.h | 36 +- .../asm/arch-fsl-layerscape/fsl_icid.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch2.h | 80 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 22 +- .../include/asm/arch-ls102xa/immap_ls102xa.h | 18 +- .../asm/arch-ls102xa/ls102xa_stream_id.h | 4 +- arch/arm/include/asm/arch-mx31/imx-regs.h | 4 +- .../include/asm/arch-stv0991/stv0991_gpt.h | 2 +- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/include/asm/global_data.h | 2 +- arch/arm/lib/bdinfo.c | 2 +- arch/arm/lib/cache-pl310.c | 2 +- arch/arm/lib/cache.c | 2 +- arch/arm/lib/vectors.S | 4 +- arch/arm/mach-at91/arm920t/clock.c | 6 +- arch/arm/mach-at91/arm920t/cpu.c | 6 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 18 +- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/clock.c | 6 +- arch/arm/mach-at91/arm926ejs/cpu.c | 6 +- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 54 +-- arch/arm/mach-at91/armv7/clock.c | 8 +- arch/arm/mach-at91/armv7/cpu.c | 6 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- arch/arm/mach-at91/include/mach/sam9x60.h | 2 +- arch/arm/mach-at91/include/mach/sama5d2.h | 2 +- arch/arm/mach-at91/include/mach/sama5d3.h | 2 +- arch/arm/mach-at91/include/mach/sama5d4.h | 2 +- arch/arm/mach-at91/spl_at91.c | 12 +- arch/arm/mach-at91/spl_atmel.c | 2 +- arch/arm/mach-davinci/cpu.c | 2 +- arch/arm/mach-davinci/da850_lowlevel.c | 24 +- arch/arm/mach-davinci/timer.c | 4 +- arch/arm/mach-exynos/spl_boot.c | 2 +- arch/arm/mach-imx/image-container.c | 8 +- arch/arm/mach-imx/mx5/lowlevel_init.S | 10 +- arch/arm/mach-k3/config_secure.mk | 2 +- arch/arm/mach-keystone/cmd_mon.c | 2 +- .../arm/mach-keystone/include/mach/hardware.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 4 +- .../mach-kirkwood/include/mach/kw88f6192.h | 2 +- .../mach-kirkwood/include/mach/kw88f6281.h | 2 +- arch/arm/mach-mvebu/cpu.c | 4 +- arch/arm/mach-mvebu/include/mach/soc.h | 10 +- arch/arm/mach-mvebu/lowlevel.S | 4 +- arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c | 2 +- arch/arm/mach-omap2/config_secure.mk | 2 +- arch/arm/mach-omap2/mem-common.c | 12 +- arch/arm/mach-omap2/timer.c | 2 +- .../arm/mach-orion5x/include/mach/mv88f5182.h | 2 +- arch/arm/mach-orion5x/timer.c | 6 +- arch/arm/mach-rmobile/include/mach/r8a7790.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7792.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 +- arch/arm/mach-rmobile/timer.c | 8 +- arch/arm/mach-socfpga/misc.c | 2 +- arch/arm/mach-socfpga/misc_arria10.c | 4 +- arch/arm/mach-socfpga/misc_gen5.c | 2 +- arch/arm/mach-socfpga/spl_a10.c | 2 +- arch/arm/mach-socfpga/timer.c | 2 +- arch/arm/mach-u8500/cache.c | 2 +- arch/arm/mach-uniphier/arm32/timer.c | 2 +- arch/arm/mach-versatile/timer.c | 8 +- arch/m68k/cpu/mcf523x/cpu.c | 2 +- arch/m68k/cpu/mcf523x/cpu_init.c | 38 +- arch/m68k/cpu/mcf523x/speed.c | 2 +- arch/m68k/cpu/mcf523x/start.S | 6 +- arch/m68k/cpu/mcf52x2/cpu.c | 10 +- arch/m68k/cpu/mcf52x2/cpu_init.c | 110 ++--- arch/m68k/cpu/mcf52x2/speed.c | 14 +- arch/m68k/cpu/mcf52x2/start.S | 48 +- arch/m68k/cpu/mcf530x/cpu.c | 2 +- arch/m68k/cpu/mcf530x/cpu_init.c | 48 +- arch/m68k/cpu/mcf530x/speed.c | 4 +- arch/m68k/cpu/mcf530x/start.S | 10 +- arch/m68k/cpu/mcf532x/cpu.c | 2 +- arch/m68k/cpu/mcf532x/cpu_init.c | 86 ++-- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/cpu/mcf532x/start.S | 6 +- arch/m68k/cpu/mcf5445x/cpu_init.c | 38 +- arch/m68k/cpu/mcf5445x/start.S | 46 +- arch/m68k/include/asm/cache.h | 24 +- arch/m68k/include/asm/immap.h | 32 +- arch/m68k/include/asm/immap_520x.h | 52 +-- arch/m68k/include/asm/immap_5235.h | 72 +-- arch/m68k/include/asm/immap_5249.h | 14 +- arch/m68k/include/asm/immap_5253.h | 26 +- arch/m68k/include/asm/immap_5271.h | 72 +-- arch/m68k/include/asm/immap_5272.h | 36 +- arch/m68k/include/asm/immap_5275.h | 76 +-- arch/m68k/include/asm/immap_5282.h | 72 +-- arch/m68k/include/asm/immap_5301x.h | 80 ++-- arch/m68k/include/asm/immap_5307.h | 18 +- arch/m68k/include/asm/m5249.h | 16 +- arch/m68k/include/asm/m5271.h | 12 +- arch/m68k/include/asm/m5282.h | 388 ++++++++-------- arch/m68k/lib/bdinfo.c | 4 +- arch/m68k/lib/cache.c | 24 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 46 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 14 +- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 +- arch/powerpc/cpu/mpc83xx/start.S | 48 +- arch/powerpc/cpu/mpc83xx/sysio/sysio.h | 8 +- arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +- arch/powerpc/cpu/mpc85xx/cpu.c | 18 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 52 +-- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 22 +- arch/powerpc/cpu/mpc85xx/fdt.c | 32 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 14 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/release.S | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 42 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +- arch/powerpc/cpu/mpc85xx/start.S | 130 +++--- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t1040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 8 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 +- arch/powerpc/cpu/mpc8xx/start.S | 4 +- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 8 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 8 +- arch/powerpc/include/asm/config_mpc85xx.h | 42 +- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/fsl_liodn.h | 18 +- arch/powerpc/include/asm/fsl_secure_boot.h | 20 +- arch/powerpc/include/asm/immap_83xx.h | 10 +- arch/powerpc/include/asm/immap_85xx.h | 44 +- arch/powerpc/lib/spl.c | 2 +- arch/sh/include/asm/config.h | 4 +- arch/x86/lib/physmem.c | 2 +- arch/xtensa/include/asm/addrspace.h | 4 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 6 +- board/LaCie/net2big_v2/net2big_v2.c | 12 +- board/Synology/common/legacy.c | 4 +- board/armltd/integrator/timer.c | 14 +- board/armltd/vexpress64/vexpress64.c | 4 +- board/cadence/xtfpga/xtfpga.c | 10 +- board/cavium/thunderx/atf.c | 2 +- board/cavium/thunderx/thunderx.c | 4 +- board/cobra5272/flash.c | 10 +- board/cortina/presidio-asic/lowlevel_init.S | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/davinci/da8xxevm/da850evm.c | 16 +- board/egnite/ethernut5/ethernut5.c | 2 +- board/emulation/qemu-ppce500/qemu-ppce500.c | 6 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 14 +- board/freescale/common/p_corenet/law.c | 14 +- board/freescale/common/p_corenet/tlb.c | 48 +- board/freescale/common/qixis.c | 10 +- board/freescale/common/qixis.h | 6 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1021aqds/ls1021aqds.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 12 +- board/freescale/ls1043aqds/ls1043aqds.c | 48 +- board/freescale/ls1043ardb/cpld.c | 4 +- board/freescale/ls1043ardb/ls1043ardb.c | 32 +- board/freescale/ls1046aqds/ls1046aqds.c | 48 +- board/freescale/ls1046ardb/cpld.c | 4 +- board/freescale/ls1088a/ls1088a.c | 30 +- board/freescale/ls2080aqds/README | 4 +- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/lx2160a/lx2160a.c | 6 +- board/freescale/m5249evb/m5249evb.c | 6 +- board/freescale/m5253demo/flash.c | 18 +- board/freescale/m5253demo/m5253demo.c | 4 +- board/freescale/m53017evb/README | 6 +- board/freescale/m5329evb/nand.c | 2 +- board/freescale/m5373evb/README | 6 +- board/freescale/m5373evb/nand.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 28 +- board/freescale/mpc8548cds/law.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 12 +- board/freescale/mpc8548cds/tlb.c | 16 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/p1010rdb/law.c | 4 +- board/freescale/p1010rdb/p1010rdb.c | 14 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/tlb.c | 30 +- board/freescale/p1_p2_rdb_pc/ddr.c | 56 +-- board/freescale/p1_p2_rdb_pc/law.c | 6 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 22 +- board/freescale/p1_p2_rdb_pc/tlb.c | 38 +- board/freescale/p2041rdb/eth.c | 24 +- board/freescale/p2041rdb/p2041rdb.c | 4 +- board/freescale/t102xrdb/cpld.c | 4 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/law.c | 18 +- board/freescale/t102xrdb/t102xrdb.c | 6 +- board/freescale/t102xrdb/tlb.c | 54 +-- board/freescale/t104xrdb/cpld.c | 6 +- board/freescale/t104xrdb/ddr.c | 2 +- board/freescale/t104xrdb/eth.c | 18 +- board/freescale/t104xrdb/law.c | 18 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 6 +- board/freescale/t104xrdb/tlb.c | 58 +-- board/freescale/t208xqds/law.c | 14 +- board/freescale/t208xqds/t208xqds.c | 4 +- board/freescale/t208xqds/tlb.c | 46 +- board/freescale/t208xrdb/cpld.c | 4 +- board/freescale/t208xrdb/law.c | 18 +- board/freescale/t208xrdb/t208xrdb.c | 4 +- board/freescale/t208xrdb/tlb.c | 50 +- board/freescale/t4rdb/cpld.c | 6 +- board/freescale/t4rdb/law.c | 18 +- board/freescale/t4rdb/t4240rdb.c | 4 +- board/freescale/t4rdb/tlb.c | 50 +- board/gdsys/mpc8308/sdram.c | 24 +- board/isee/igep00x0/igep00x0.c | 2 +- board/keymile/common/qrio.c | 36 +- board/keymile/km83xx/km83xx.c | 30 +- board/keymile/kmcent2/kmcent2.c | 6 +- board/keymile/kmcent2/law.c | 10 +- board/keymile/kmcent2/tlb.c | 40 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/nokia/rx51/rx51.c | 2 +- board/samsung/goni/onenand.c | 2 +- board/samsung/universal_c210/onenand.c | 2 +- board/siemens/smartweb/smartweb.c | 2 +- board/siemens/taurus/taurus.c | 2 +- board/socrates/law.c | 10 +- board/socrates/sdram.c | 22 +- board/socrates/socrates.c | 10 +- board/socrates/tlb.c | 22 +- board/sysam/amcore/amcore.c | 2 +- board/ti/ks2_evm/board.c | 8 +- board/ti/omap5_uevm/evm.c | 2 +- board/xes/common/fsl_8xxx_misc.c | 4 +- boot/Kconfig | 2 +- boot/image-board.c | 4 +- cmd/date.c | 4 +- cmd/i2c.c | 16 +- common/board_f.c | 4 +- common/board_r.c | 8 +- common/spl/Kconfig.nxp | 4 +- common/spl/spl.c | 6 +- common/spl/spl_fit.c | 2 +- common/spl/spl_nor.c | 2 +- common/spl/spl_spi.c | 8 +- common/spl/spl_ubi.c | 2 +- common/spl/spl_xip.c | 2 +- doc/README.atmel_mci | 4 +- doc/README.cfi | 4 +- doc/README.davinci | 2 +- doc/README.generic_usb_ohci | 2 +- doc/README.mpc85xx | 16 +- doc/README.nand | 2 +- doc/README.serial_multi | 2 +- doc/arch/m68k.rst | 18 +- doc/develop/driver-model/migration.rst | 2 +- doc/device-tree-bindings/video/exynos-dp.txt | 4 +- doc/device-tree-bindings/video/exynos-fb.txt | 10 +- doc/imx/common/imx5.txt | 2 +- doc/usage/environment.rst | 6 +- drivers/bootcount/Kconfig | 2 +- drivers/bootcount/bootcount_i2c.c | 4 +- drivers/clk/at91/compat.c | 2 +- drivers/core/Kconfig | 6 +- drivers/ddr/fsl/main.c | 4 +- drivers/fpga/ACEX1K.c | 6 +- drivers/fpga/cyclon2.c | 6 +- drivers/fpga/spartan2.c | 16 +- drivers/fpga/spartan3.c | 16 +- drivers/fpga/virtex2.c | 28 +- drivers/fpga/zynqpl.c | 14 +- drivers/gpio/pca953x.c | 10 +- drivers/gpio/tca642x.c | 6 +- drivers/i2c/davinci_i2c.c | 2 +- drivers/i2c/fsl_i2c.c | 2 +- drivers/i2c/i2c_core.c | 6 +- drivers/i2c/kona_i2c.c | 2 +- drivers/i2c/mvtwsi.c | 6 +- drivers/i2c/mxc_i2c.c | 4 +- drivers/misc/fsl_ifc.c | 438 +++++++++--------- drivers/misc/fsl_portals.c | 28 +- drivers/misc/fsl_sec_mon.c | 6 +- drivers/mmc/fsl_esdhc_spl.c | 18 +- drivers/mmc/gen_atmel_mci.c | 8 +- drivers/mmc/sh_sdhi.c | 2 +- drivers/mtd/cfi_flash.c | 32 +- drivers/mtd/nand/raw/fsl_ifc_nand.c | 4 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 8 +- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 6 +- drivers/mtd/onenand/onenand_spl.c | 6 +- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/spi/fsl_espi_spl.c | 12 +- drivers/mtd/stm32_flash.c | 2 +- drivers/net/fm/eth.c | 2 +- drivers/net/fm/fm.c | 4 +- drivers/net/fm/init.c | 4 +- drivers/net/fsl-mc/dpio/qbman_sys.h | 4 +- drivers/net/fsl-mc/mc.c | 48 +- drivers/net/fsl_mcdmafec.c | 26 +- drivers/net/mcffec.c | 8 +- drivers/net/qe/uec.h | 14 +- drivers/net/tsec.c | 4 +- drivers/net/vsc7385.c | 12 +- drivers/power/power_dialog.c | 2 +- drivers/qe/uec.h | 14 +- drivers/qe/uec_phy.c | 10 +- drivers/rtc/ds1307.c | 8 +- drivers/rtc/ds1337.c | 4 +- drivers/rtc/ds1374.c | 16 +- drivers/rtc/ds3231.c | 4 +- drivers/rtc/m41t62.c | 10 +- drivers/rtc/max6900.c | 8 +- drivers/rtc/pcf8563.c | 4 +- drivers/rtc/pt7c4338.c | 4 +- drivers/rtc/rs5c372.c | 12 +- drivers/rtc/rx8010sj.c | 12 +- drivers/rtc/x1205.c | 4 +- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 4 +- drivers/spi/davinci_spi.c | 4 +- drivers/spi/kirkwood_spi.c | 4 +- drivers/sysreset/sysreset_xtfpga.c | 4 +- drivers/timer/arm_global_timer.c | 2 +- drivers/timer/imx-gpt-timer.c | 10 +- drivers/timer/orion-timer.c | 4 +- drivers/timer/stm32_timer.c | 4 +- drivers/usb/host/ohci-hcd.c | 2 +- drivers/video/imx/ipu_common.c | 6 +- env/Kconfig | 2 +- env/embedded.c | 2 +- include/config_fallbacks.h | 4 +- include/configs/M5208EVBE.h | 42 +- include/configs/M5235EVB.h | 52 +-- include/configs/M5249EVB.h | 66 +-- include/configs/M5253DEMO.h | 86 ++-- include/configs/M5272C3.h | 48 +- include/configs/M5275EVB.h | 48 +- include/configs/M5282EVB.h | 68 +-- include/configs/M53017EVB.h | 54 +-- include/configs/M5329EVB.h | 56 +-- include/configs/M5373EVB.h | 56 +-- include/configs/MCR3000.h | 8 +- include/configs/MPC837XERDB.h | 60 +-- include/configs/MPC8548CDS.h | 58 +-- include/configs/P1010RDB.h | 146 +++--- include/configs/P2041RDB.h | 132 +++--- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 209 ++++----- include/configs/T104xRDB.h | 228 ++++----- include/configs/T208xQDS.h | 226 ++++----- include/configs/T208xRDB.h | 192 ++++---- include/configs/T4240RDB.h | 206 ++++---- include/configs/am335x_evm.h | 4 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/amcore.h | 44 +- include/configs/ap121.h | 4 +- include/configs/ap143.h | 4 +- include/configs/ap152.h | 4 +- include/configs/apalis_imx6.h | 4 +- include/configs/arbel.h | 6 +- include/configs/aristainetos2.h | 6 +- include/configs/aspeed-common.h | 8 +- include/configs/astro_mcf5373l.h | 68 +-- include/configs/at91-sama5_common.h | 4 +- include/configs/at91sam9260ek.h | 12 +- include/configs/at91sam9261ek.h | 10 +- include/configs/at91sam9263ek.h | 56 +-- include/configs/at91sam9m10g45ek.h | 12 +- include/configs/at91sam9n12ek.h | 12 +- include/configs/at91sam9rlek.h | 8 +- include/configs/at91sam9x5ek.h | 12 +- include/configs/ax25-ae350.h | 8 +- include/configs/axs10x.h | 4 +- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcmstb.h | 4 +- include/configs/bk4r1.h | 4 +- include/configs/blanche.h | 8 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 4 +- include/configs/bmips_bcm6348.h | 4 +- include/configs/bmips_bcm6358.h | 4 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 4 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/bmips_common.h | 2 +- include/configs/boston.h | 2 +- include/configs/brppt2.h | 6 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 8 +- include/configs/cm_fx6.h | 6 +- include/configs/cm_t43.h | 4 +- include/configs/cobra5272.h | 48 +- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri_imx6.h | 4 +- include/configs/colibri_imx7.h | 4 +- include/configs/colibri_vf.h | 4 +- include/configs/corvus.h | 12 +- include/configs/da850evm.h | 36 +- include/configs/dart_6ul.h | 4 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 4 +- include/configs/display5.h | 10 +- include/configs/dra7xx_evm.h | 10 +- include/configs/draak.h | 4 +- include/configs/dragonboard845c.h | 2 +- include/configs/eb_cpu5282.h | 86 ++-- include/configs/ebisu.h | 4 +- include/configs/edison.h | 2 +- include/configs/el6x_common.h | 4 +- include/configs/embestmx6boards.h | 4 +- include/configs/etamin.h | 2 +- include/configs/ethernut5.h | 16 +- include/configs/evb_ast2500.h | 2 +- include/configs/evb_ast2600.h | 2 +- include/configs/exynos5-dt-common.h | 2 +- include/configs/exynos78x0-common.h | 2 +- .../configs/gardena-smart-gateway-at91sam.h | 12 +- .../configs/gardena-smart-gateway-mt7688.h | 8 +- include/configs/gazerbeam.h | 14 +- include/configs/ge_b1x5v2.h | 4 +- include/configs/ge_bx50v3.h | 6 +- include/configs/gw_ventana.h | 4 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 4 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6dl-mamoj.h | 4 +- include/configs/imx6q-bosch-acc.h | 4 +- include/configs/imx6ulz_smm_m2.h | 4 +- include/configs/imx7-cm.h | 4 +- include/configs/imx8mm-cl-iot-gate.h | 6 +- include/configs/imx8mm_beacon.h | 6 +- include/configs/imx8mm_data_modul_edm_sbc.h | 4 +- include/configs/imx8mm_evk.h | 8 +- include/configs/imx8mm_icore_mx8mm.h | 6 +- include/configs/imx8mm_venice.h | 6 +- include/configs/imx8mn_beacon.h | 6 +- include/configs/imx8mn_bsh_smm_s2_common.h | 6 +- include/configs/imx8mn_evk.h | 6 +- include/configs/imx8mn_var_som.h | 6 +- include/configs/imx8mn_venice.h | 6 +- include/configs/imx8mp_dhcom_pdk2.h | 4 +- include/configs/imx8mp_evk.h | 6 +- include/configs/imx8mp_icore_mx8mp.h | 6 +- include/configs/imx8mp_rsb3720.h | 6 +- include/configs/imx8mp_venice.h | 6 +- include/configs/imx8mq_cm.h | 4 +- include/configs/imx8mq_evk.h | 4 +- include/configs/imx8mq_phanbell.h | 4 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8ulp_evk.h | 6 +- include/configs/imx93_evk.h | 6 +- include/configs/imxrt1020-evk.h | 2 +- include/configs/imxrt1050-evk.h | 2 +- include/configs/imxrt1170-evk.h | 2 +- include/configs/integrator-common.h | 4 +- include/configs/integratorap.h | 4 +- include/configs/integratorcp.h | 2 +- include/configs/j721e_evm.h | 6 +- include/configs/j721s2_evm.h | 4 +- include/configs/km/keymile-common.h | 2 +- include/configs/km/km-mpc832x.h | 32 +- include/configs/km/km-mpc8360.h | 32 +- include/configs/km/km-mpc83xx.h | 20 +- include/configs/km/pg-wcom-ls102xa.h | 86 ++-- include/configs/kmcent2.h | 204 ++++---- include/configs/kmcoge5ne.h | 6 +- include/configs/kmeter1.h | 2 +- include/configs/kontron-sl-mx6ul.h | 6 +- include/configs/kontron-sl-mx8mm.h | 4 +- include/configs/kontron_pitx_imx8m.h | 4 +- include/configs/kontron_sl28.h | 8 +- include/configs/kp_imx53.h | 4 +- include/configs/kp_imx6q_tpc.h | 4 +- include/configs/lacie_kw.h | 2 +- include/configs/legoev3.h | 10 +- include/configs/librem5.h | 4 +- include/configs/linkit-smart-7688.h | 8 +- include/configs/liteboard.h | 4 +- include/configs/ls1012a_common.h | 6 +- include/configs/ls1012aqds.h | 4 +- include/configs/ls1021aiot.h | 10 +- include/configs/ls1021aqds.h | 174 +++---- include/configs/ls1021atsn.h | 10 +- include/configs/ls1021atwr.h | 74 +-- include/configs/ls1028a_common.h | 6 +- include/configs/ls1028aqds.h | 12 +- include/configs/ls1028ardb.h | 10 +- include/configs/ls1043a_common.h | 20 +- include/configs/ls1043aqds.h | 224 ++++----- include/configs/ls1043ardb.h | 146 +++--- include/configs/ls1046a_common.h | 8 +- include/configs/ls1046afrwy.h | 22 +- include/configs/ls1046aqds.h | 236 +++++----- include/configs/ls1046ardb.h | 56 +-- include/configs/ls1088a_common.h | 36 +- include/configs/ls1088aqds.h | 216 ++++----- include/configs/ls1088ardb.h | 80 ++-- include/configs/ls2080a_common.h | 36 +- include/configs/ls2080aqds.h | 158 +++---- include/configs/ls2080ardb.h | 110 ++--- include/configs/lx2160a_common.h | 40 +- include/configs/lx2160aqds.h | 2 +- include/configs/lx2160ardb.h | 2 +- include/configs/lx2162aqds.h | 2 +- include/configs/m53menlo.h | 10 +- include/configs/malta.h | 6 +- include/configs/mccmon6.h | 14 +- include/configs/meerkat96.h | 4 +- include/configs/meesc.h | 8 +- include/configs/microblaze-generic.h | 4 +- include/configs/msc_sm2s_imx8mp.h | 6 +- include/configs/mt7620.h | 6 +- include/configs/mt7621.h | 6 +- include/configs/mt7622.h | 4 +- include/configs/mt7628.h | 8 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 4 +- include/configs/mt7986.h | 4 +- include/configs/mt8512.h | 2 +- include/configs/mv-common.h | 6 +- include/configs/mvebu_alleycat-5.h | 4 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 4 +- include/configs/mx51evk.h | 10 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 6 +- include/configs/mx53ppd.h | 6 +- include/configs/mx6_common.h | 2 +- include/configs/mx6cuboxi.h | 4 +- include/configs/mx6memcal.h | 4 +- include/configs/mx6sabre_common.h | 4 +- include/configs/mx6sabreauto.h | 4 +- include/configs/mx6slevk.h | 4 +- include/configs/mx6sllevk.h | 4 +- include/configs/mx6sxsabreauto.h | 4 +- include/configs/mx6sxsabresd.h | 4 +- include/configs/mx6ul_14x14_evk.h | 4 +- include/configs/mx6ullevk.h | 4 +- include/configs/mx7dsabresd.h | 4 +- include/configs/mx7ulp_com.h | 6 +- include/configs/mx7ulp_evk.h | 6 +- include/configs/mxs.h | 6 +- include/configs/mys_6ulx.h | 4 +- include/configs/nitrogen6x.h | 4 +- include/configs/nokia_rx51.h | 10 +- include/configs/novena.h | 4 +- include/configs/npi_imx6ull.h | 4 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 4 +- include/configs/octeon_common.h | 4 +- include/configs/odroid.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_igep00x0.h | 4 +- include/configs/omap3_logic.h | 4 +- include/configs/omap5_uevm.h | 4 +- include/configs/omapl138_lcdk.h | 32 +- include/configs/opos6uldev.h | 4 +- include/configs/p1_p2_bootsrc.h | 6 +- include/configs/p1_p2_rdb_pc.h | 164 +++---- include/configs/pcl063.h | 4 +- include/configs/pcl063_ull.h | 4 +- include/configs/pcm052.h | 4 +- include/configs/pcm058.h | 4 +- include/configs/pg-wcom-expu1.h | 16 +- include/configs/pg-wcom-seli8.h | 16 +- include/configs/phycore_imx8mm.h | 6 +- include/configs/phycore_imx8mp.h | 6 +- include/configs/pic32mzdask.h | 6 +- include/configs/pico-imx6.h | 4 +- include/configs/pico-imx6ul.h | 4 +- include/configs/pico-imx7d.h | 4 +- include/configs/pico-imx8mq.h | 4 +- include/configs/pm9261.h | 52 +-- include/configs/pm9263.h | 56 +-- include/configs/pm9g45.h | 12 +- include/configs/poleg.h | 4 +- include/configs/presidio_asic.h | 16 +- include/configs/qcs404-evb.h | 2 +- include/configs/qemu-ppce500.h | 34 +- include/configs/r2dplus.h | 6 +- include/configs/rcar-gen2-common.h | 6 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rpi.h | 6 +- include/configs/rv1108_common.h | 6 +- include/configs/s5p_goni.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/salvator-x.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_som1_ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3xek.h | 2 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 2 +- include/configs/sdm845.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/smartweb.h | 18 +- include/configs/smdkc100.h | 2 +- include/configs/smegw01.h | 4 +- include/configs/snapper9g45.h | 8 +- include/configs/sniper.h | 4 +- include/configs/socfpga_arria10_socdk.h | 2 +- include/configs/socfpga_arria5_secu1.h | 4 +- include/configs/socfpga_chameleonv3.h | 2 +- include/configs/socfpga_common.h | 24 +- include/configs/socfpga_soc64_common.h | 4 +- include/configs/socrates.h | 66 +-- include/configs/somlabs_visionsom_6ull.h | 4 +- include/configs/stemmy.h | 2 +- include/configs/stih410-b2260.h | 4 +- include/configs/stm32f429-discovery.h | 4 +- include/configs/stm32f429-evaluation.h | 6 +- include/configs/stm32f469-discovery.h | 6 +- include/configs/stm32f746-disco.h | 8 +- include/configs/stm32h743-disco.h | 6 +- include/configs/stm32h743-eval.h | 6 +- include/configs/stm32h750-art-pi.h | 6 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp13_st_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stm32mp15_st_common.h | 2 +- include/configs/stmark2.h | 42 +- include/configs/stv0991.h | 6 +- include/configs/sunxi-common.h | 4 +- include/configs/synquacer.h | 8 +- include/configs/taurus.h | 18 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 6 +- include/configs/tegra-common.h | 10 +- include/configs/ten64.h | 2 +- include/configs/thunderx_88xx.h | 6 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +- include/configs/ti_omap3_common.h | 4 +- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 4 +- include/configs/tqma6.h | 4 +- include/configs/tqma6_wru4.h | 4 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 4 +- include/configs/udoo_neo.h | 4 +- include/configs/ulcb.h | 4 +- include/configs/uniphier.h | 6 +- include/configs/usb_a9263.h | 8 +- include/configs/usbarmory.h | 4 +- include/configs/vcoreiii.h | 2 +- include/configs/verdin-imx8mm.h | 6 +- include/configs/verdin-imx8mp.h | 6 +- include/configs/vexpress_aemv8.h | 4 +- include/configs/vexpress_common.h | 18 +- include/configs/vf610twr.h | 4 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 4 +- include/configs/vocore2.h | 6 +- include/configs/wandboard.h | 4 +- include/configs/warp7.h | 4 +- include/configs/work_92105.h | 2 +- include/configs/x530.h | 2 +- include/configs/x86-common.h | 2 +- include/configs/xea.h | 6 +- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_versal_net.h | 2 +- include/configs/xilinx_zynqmp.h | 8 +- include/configs/xilinx_zynqmp_r5.h | 6 +- include/configs/xpress.h | 4 +- include/configs/xtfpga.h | 40 +- include/configs/zynq-common.h | 20 +- include/configs/zynq_cse.h | 8 +- include/fsl-mc/fsl_mc.h | 2 +- include/fsl_ifc.h | 2 +- include/i2c.h | 16 +- include/mpc85xx.h | 34 +- include/mpc86xx.h | 6 +- include/mtd/cfi_flash.h | 4 +- include/mvebu_mmc.h | 2 +- include/post.h | 4 +- include/spl.h | 2 +- include/system-constants.h | 4 +- include/tca642x.h | 8 +- include/tsec.h | 4 +- lib/time.c | 14 +- post/drivers/memory.c | 4 +- post/tests.c | 8 +- tools/envcrc.c | 6 +- 744 files changed, 5931 insertions(+), 5930 deletions(-)
diff --git a/.checkpatch.conf b/.checkpatch.conf index 9e40ea060be1..c368d4147260 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -4,7 +4,7 @@ # Temporary for false positive in checkpatch --ignore COMPLEX_MACRO
-# For CONFIG_SYS_I2C_NOPROBES +# For CFG_SYS_I2C_NOPROBES --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
# For simple_strtoul diff --git a/Kconfig b/Kconfig index 67f46467b17e..297281e4746f 100644 --- a/Kconfig +++ b/Kconfig @@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR default y if TFABOOT help Typically, we use an initial stack pointer address that is calculated - by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the - statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the + by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the + statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different but statica calculation is performed. However, some platforms will take a different approach. Say Y here to define the address statically @@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN particular needs this to operate, so that it can allocate the initial serial device and any others that are needed.
- It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new + It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F_LEN diff --git a/Makefile b/Makefile index d6699a54dbb8..2f3c2fea8423 100644 --- a/Makefile +++ b/Makefile @@ -1141,10 +1141,10 @@ endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) - @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which + @# CFG_SYS_TIMER_RATE has brackets in it for some boards which @# confuses this rule. Use if() to send just a single character which @# is enable to tell 'deprecated' that one of these symbols exists - $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x)) + $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) @# Check that this build does not use CONFIG options that we do not @@ -1364,8 +1364,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE # U-Boot entry point, needed for booting of full-blown U-Boot # from the SPL U-Boot version. # -ifndef CONFIG_SYS_UBOOT_START -CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) +ifndef CFG_SYS_UBOOT_START +CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) endif
# Boards with more complex image requirements can provide an .its source file @@ -1390,7 +1390,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ @@ -1398,10 +1398,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) else MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log endif @@ -1432,7 +1432,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE diff --git a/README b/README index bb35a895b755..0a7635d1a24d 100644 --- a/README +++ b/README @@ -341,7 +341,7 @@ The following options need to be configured:
CFG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the - same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs.
- MIPS CPU options: @@ -352,7 +352,7 @@ The following options need to be configured: be swapped if a flash programmer is used.
- ARM options: - CONFIG_SYS_EXCEPTION_VECTORS_HIGH + CFG_SYS_EXCEPTION_VECTORS_HIGH
Select high exception vectors of the ARM core, e.g., do not clear the V bit of the c1 register of CP15. @@ -415,7 +415,7 @@ The following options need to be configured: the defaults discussed just above.
- Cache Configuration for ARM: - CONFIG_SYS_PL310_BASE - Physical base address of PL310 + CFG_SYS_PL310_BASE - Physical base address of PL310 controller register space
- Serial Ports: @@ -485,7 +485,7 @@ The following options need to be configured: - GPIO Support: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
- The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of + The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip.
@@ -927,21 +927,21 @@ The following options need to be configured:
CONFIG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. - if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can + if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can omit this define.
- CONFIG_SYS_I2C_MAX_HOPS + CFG_SYS_I2C_MAX_HOPS define how many muxes are maximal consecutively connected on one i2c bus. If you not use i2c muxes, omit this define.
- CONFIG_SYS_I2C_BUSES + CFG_SYS_I2C_BUSES hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example - a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and + a board with CFG_SYS_I2C_MAX_HOPS = 1 and CFG_SYS_NUM_I2C_BUSES = 9:
- CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ + CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \ @@ -1044,7 +1044,7 @@ The following options need to be configured: active. To switch to a different bus, use the 'i2c dev' command. Note that bus numbering is zero-based.
- CONFIG_SYS_I2C_NOPROBES + CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS @@ -1053,16 +1053,16 @@ The following options need to be configured:
e.g. #undef CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68} + #define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
- CONFIG_SYS_RTC_BUS_NUM + CFG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC. If not defined, then U-Boot assumes that RTC is on I2C bus 0. @@ -1120,19 +1120,19 @@ The following options need to be configured: configuration if the INIT_B line goes low (which indicated a CRC error).
- CONFIG_SYS_FPGA_WAIT_INIT + CFG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to de-assert after PROB_B has been de-asserted during a Virtex II FPGA configuration sequence. The default time is 500 ms.
- CONFIG_SYS_FPGA_WAIT_BUSY + CFG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to de-assert during Virtex II FPGA configuration. The default is 5 ms.
- CONFIG_SYS_FPGA_WAIT_CONFIG + CFG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is 200 ms. @@ -1429,12 +1429,12 @@ Configuration Settings: - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input.
-- CONFIG_SYS_BAUDRATE_TABLE: +- CFG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board.
-- CONFIG_SYS_MEM_RESERVE_SECURE +- CFG_SYS_MEM_RESERVE_SECURE Only implemented for ARMv8 for now. - If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory + If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory is substracted from total RAM and won't be reported to OS. This memory can be used as secure memory. A variable gd->arch.secure_ram is used to track the location. In systems @@ -1444,7 +1444,7 @@ Configuration Settings: - CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here.
-- CONFIG_SYS_FLASH_BASE: +- CFG_SYS_FLASH_BASE: Physical start address of Flash memory.
- CONFIG_SYS_MALLOC_LEN: @@ -1468,16 +1468,16 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_BOOTMAPSZ: +- CFG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" environment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" - and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment + and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment variable "bootm_mapsize" will override the value of - CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, + CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE: @@ -1638,11 +1638,11 @@ Low Level (hardware related) configuration options: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs.
-- CONFIG_SYS_CCSRBAR: +- CFG_SYS_CCSRBAR: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
-- CONFIG_SYS_CCSRBAR_PHYS: +- CFG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should be set to that address. Otherwise, it should be set to the @@ -1650,17 +1650,17 @@ Low Level (hardware related) configuration options: is typically relocated on 36-bit builds. It is recommended that this macro be defined via the _HIGH and _LOW macros:
- #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH - * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH: - Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically +- CFG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically either 0 (32-bit build) or 0xF (36-bit build). This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSRBAR_PHYS_LOW: - Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is +- CFG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL").
@@ -1668,7 +1668,7 @@ Low Level (hardware related) configuration options: DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx systems only]
-- CONFIG_SYS_INIT_RAM_ADDR: +- CFG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for initial data and stack; please note that this must be @@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc. cause you grief during the initial boot! It is frequently not used.
- CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere + CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere with your processor/board/system design. The default value you will find in any recent u-boot distribution in walnut.h should work for you. I'd set it to a value larger diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 5a1536539dc9..9e76a4a9e0e1 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -18,7 +18,7 @@ #include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE -#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE +#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE #endif
/* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index aca7793c5798..c882bd39eab0 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ -#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index d96406f7626f..17bd53dae847 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_HZ_CLOCK +#ifndef CFG_SYS_HZ_CLOCK static inline u32 read_cntfrq(void) { u32 frq; @@ -29,8 +29,8 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0;
-#ifdef CONFIG_SYS_HZ_CLOCK - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#ifdef CFG_SYS_HZ_CLOCK + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = read_cntfrq(); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d09c21d5d9b2..25e4b49c70e5 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis)
int arch_cpu_init(void) { - void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = - (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; u32 state;
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 0e7d5fa06dc6..599b7e18ef31 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, - CONFIG_SYS_IFC_ADDR); + CFG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 954fa5f8b450..dbb0766a9c64 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
static void __secure ls1_fsm_setup(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); @@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
static void __secure ls1_start_fsm(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 67764ccf66a6..f7cc45772f91 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff;
rndoff = (usec % 10) ? 1 : 0; diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index 556eaf8c74ad..c30af4ff7a28 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -18,7 +18,7 @@ * The number of reference clock ticks that correspond to 10ms is normally * defined in the SysTick Calibration register's TENMS field. However, on some * devices this is wrong, so this driver allows the clock rate to be defined - * using CONFIG_SYS_HZ_CLOCK. + * using CFG_SYS_HZ_CLOCK. */
#include <common.h> @@ -76,10 +76,10 @@ int timer_init(void)
/* * If the TENMS field is inexact or wrong, specify the clock rate using - * CONFIG_SYS_HZ_CLOCK. + * CFG_SYS_HZ_CLOCK. */ -#if defined(CONFIG_SYS_HZ_CLOCK) - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#if defined(CFG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bbaa91f0e108..99413ef52e22 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -114,7 +114,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -130,9 +130,9 @@ static struct mm_region early_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif @@ -391,7 +391,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE {}, /* space holder for secure mem */ #endif {}, @@ -445,7 +445,7 @@ static inline void early_mmu_setup(void) if (el == 3) gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE; else - gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; + gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
@@ -568,7 +568,7 @@ static inline void final_mmu_setup(void) } }
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) { /* @@ -580,7 +580,7 @@ static inline void final_mmu_setup(void) gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; final_map[index].virt = gd->arch.secure_ram & ~0x3; final_map[index].phys = final_map[index].virt; - final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; + final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE; final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; tlb_addr_save = gd->arch.tlb_addr; @@ -1323,10 +1323,10 @@ phys_size_t get_effective_memsize(void) ea_size = gd->ram_size; }
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* Check if we have enough space for secure memory */ - if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) - ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + if (ea_size > CFG_SYS_MEM_RESERVE_SECURE) + ea_size -= CFG_SYS_MEM_RESERVE_SECURE; else printf("Error: No enough space for secure memory.\n"); #endif @@ -1433,7 +1433,7 @@ int dram_init_banksize(void) * gd->arch.secure_ram should be done to avoid running it repeatedly. */
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { debug("No need to run again, skip %s\n", __func__);
@@ -1442,11 +1442,11 @@ int dram_init_banksize(void) #endif
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; + CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; @@ -1458,17 +1458,17 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[0].size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->bd->bi_dram[0].size > - CONFIG_SYS_MEM_RESERVE_SECURE) { + CFG_SYS_MEM_RESERVE_SECURE) { gd->bd->bi_dram[0].size -= - CONFIG_SYS_MEM_RESERVE_SECURE; + CFG_SYS_MEM_RESERVE_SECURE; gd->arch.secure_ram = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } -#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ +#endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ @@ -1520,7 +1520,7 @@ int dram_init_banksize(void) } #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE debug("%s is called. gd->ram_size is reduced to %lu\n", __func__, (ulong)gd->ram_size); #endif @@ -1580,7 +1580,7 @@ void update_early_mmu_table(void) } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | @@ -1589,10 +1589,10 @@ void update_early_mmu_table(void) #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" #endif - if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE > CONFIG_SYS_DDR_BLOCK2_SIZE) { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1601,7 +1601,7 @@ void update_early_mmu_table(void) mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE - + CFG_SYS_DDR_BLOCK1_SIZE - CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1611,9 +1611,9 @@ void update_early_mmu_table(void) #endif { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 9119d60ffb31..6f3fe7ca6e08 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -116,10 +116,10 @@ Flash Layout Environment Variables ===================== mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value - CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment from the location where it is stored(NOR, NAND, SD, SATA, USB)during diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 4880a313ea6a..e3c3fc6bfb55 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -10,7 +10,7 @@ #include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index e47d3af85e07..333d7e2fa21a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -9,7 +9,7 @@ #include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 89a6262c1282..359cbc043097 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -531,7 +531,7 @@ static void erratum_a010539(void)
porsr1 = in_be32(&gur->porsr1); porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; - out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif @@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void) out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS | SCFG_RD_QOS1_PFE2_QOS));
- ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); - out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, ecccr2 | (unsigned int)DISABLE_PFE_ECC); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 3a4b665f244f..61fced451eb5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA -#ifndef CONFIG_SYS_MEM_RESERVE_SECURE +#ifndef CFG_SYS_MEM_RESERVE_SECURE #error Need secure RAM for PPA #endif /* diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 540436ba0280..c0e8726346f5 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, goto out; }
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * The SEC Firmware must be stored in secure memory. * Append SEC Firmware to secure mmu table. @@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + gd->arch.tlb_size; #else -#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" +#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" #endif
/* Align SEC Firmware base address to 4K */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0669222fed7f..c9c72e327172 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -20,13 +20,13 @@ * Reserve secure memory * To be aligned with MMU block size */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ +#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -37,8 +37,8 @@ #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -96,7 +96,7 @@
#elif defined(CONFIG_ARCH_LS1088A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4 #define SRDS_BITS_PER_LANE 4 @@ -122,8 +122,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -141,15 +141,15 @@ #endif #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
-#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -192,8 +192,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
@@ -212,8 +212,8 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -251,15 +251,15 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 9cddb41a89c8..d5f63f4a7ed7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob);
#define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \ SET_SCFG_ICID(compat, streamid, sata_icid,\ @@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz;
#define SET_USB_ICID(usb_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 64dc7c88b7f8..9794db044996 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,11 +11,11 @@ #include <linux/bitops.h> #endif
-#define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CFG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) @@ -30,37 +30,37 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) - -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 -#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_BMAN_MEM_BASE) -#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0x508000000 +#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CFG_SYS_BMAN_MEM_BASE) +#define CFG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0x500000000 +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
@@ -134,20 +134,20 @@ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ #define TP_INIT_PER_CLUSTER 4
-#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR 0x01000000 +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0x01000000 #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000 #endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd112402e0c8..ca5e33379ba9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,7 +33,7 @@ #define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -67,8 +67,8 @@ #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -105,7 +105,7 @@ #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */ -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */ #define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull @@ -173,7 +173,7 @@ #endif
/* Security Monitor */ -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
/* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 6de431f6bbbc..3ad78cb1e645 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -23,7 +23,7 @@ #define CFG_SYS_NS16550_CLK 13000000 #endif
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
/* NAND */ @@ -49,7 +49,7 @@
/* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE #endif
#endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 62026bda9e2b..6413a307d273 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,36 +11,36 @@ #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000
-#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) -#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 +#define CFG_SYS_TSEC1_OFFSET 0x01d10000 +#define CFG_SYS_MDIO1_OFFSET 0x01d24000
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0acf677984b..a0c3da7f46d9 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -42,24 +42,24 @@
#define DCFG_DCSR_PORCR1 0
-#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR #endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index fb5ded890783..acd8c69f694d 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -12,14 +12,14 @@ { .compat = name, \ .id = { idA }, .num_ids = 1, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ }
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ }
/* diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index d5c0ed8e6c2b..a0ab3a0e665c 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -899,9 +899,9 @@ struct esdc_regs { * Generic timer support */ #ifdef CONFIG_MX31_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 #else -#define CONFIG_SYS_TIMER_RATE 32768 +#define CFG_SYS_TIMER_RATE 32768 #endif
#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index 5b12d90d5859..eb1ddca60028 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,6 +36,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) +#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 3525f22e7df7..241b44928a95 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -18,6 +18,6 @@ #endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 +#define CFG_SYS_TCLK 24000000
#endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index cd6112dfcda5..9e746e380a21 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -54,7 +54,7 @@ struct arch_global_data { unsigned long tlb_emerg; #endif #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE #define MEM_RESERVE_SECURE_SECURED 0x1 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 826e09e72c09..5e6eaad968d6 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -29,7 +29,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd;
bdinfo_print_num_l("arch_number", bd->bi_arch_number); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { bdinfo_print_num_ll("Secure ram", gd->arch.secure_ram & diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index bbaaaa4157a5..d05314ee57fc 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -11,7 +11,7 @@ #include <config.h> #include <common.h>
-struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
static void pl310_cache_sync(void) { diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index a2bf2e57b941..1a589c7e2a0d 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -152,7 +152,7 @@ __weak int arm_reserve_mmu(void) debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * Record allocated tlb_addr in case gd->tlb_addr to be overwritten * with location within secure ram. diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index a54c84b062b1..7cf7d1636f54 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -83,8 +83,8 @@ */
_start: -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG - .word CONFIG_SYS_DV_NOR_BOOT_CFG +#ifdef CFG_SYS_DV_NOR_BOOT_CFG + .word CFG_SYS_DV_NOR_BOOT_CFG #endif ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index c7440278d8f8..09ac66d619d2 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -107,7 +107,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -120,7 +120,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 44c079c0fdd9..9bf03fd68ecc 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -16,11 +16,11 @@ #include <asm/arch/hardware.h> #include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif
int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 3b91a0cba33e..6b7d3cbc7107 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -94,11 +94,11 @@ SMRDATA: .word AT91_ASM_MC_SMC_CSR0 .word CONFIG_SYS_SMC_CSR0_VAL .word AT91_ASM_PMC_PLLAR - .word CONFIG_SYS_PLLAR_VAL + .word CFG_SYS_PLLAR_VAL .word AT91_ASM_PMC_PLLBR .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR - .word CONFIG_SYS_MCKR_VAL + .word CFG_SYS_MCKR_VAL SMRDATAE: /* here there's a delay */ SMRDATA1: @@ -107,17 +107,17 @@ SMRDATA1: .word AT91_ASM_PIOC_BSR .word CONFIG_SYS_PIOC_BSR_VAL .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL + .word CFG_SYS_PIOC_PDR_VAL .word AT91_ASM_MC_EBI_CSA .word CONFIG_SYS_EBI_CSA_VAL .word AT91_ASM_MC_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL + .word CFG_SYS_SDRC_MR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word CFG_SYS_SDRAM @@ -135,15 +135,15 @@ SMRDATA1: .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM1 .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL + .word CFG_SYS_SDRC_TR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL SMRDATA1E: diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index c400e8781356..8ef5764e3153 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) +#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
int timer_init(void) { @@ -92,7 +92,7 @@ void __udelay(unsigned long usec) u32 endtime; signed long diff;
- tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo = CFG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= 1000;
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c68e0c0c3c44..013daf43b742 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -115,7 +115,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -128,7 +128,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 761edb6df589..5e84b0a40e13 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -15,13 +15,13 @@ #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif
int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); }
void arch_preboot_os(void) diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index ecfe589e4559..e159a74eeac3 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -21,8 +21,8 @@ #ifdef CONFIG_ATMEL_LEGACY #include <asm/arch/at91sam9_matrix.h> #endif -#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL -#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#ifndef CFG_SYS_MATRIX_EBICSA_VAL +#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL #endif
.globl lowlevel_init @@ -67,7 +67,7 @@ POS1: ldr r1, =(AT91_ASM_PMC_MOR) ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ - ldr r0, =CONFIG_SYS_MOR_VAL + ldr r0, =CFG_SYS_MOR_VAL str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */ @@ -85,7 +85,7 @@ MOSCS_Loop: * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_ASM_PMC_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL + ldr r0, =CFG_SYS_PLLAR_VAL str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */ @@ -105,7 +105,7 @@ MOSCS_Loop1: ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL + ldr r0, =CFG_SYS_MCKR1_VAL str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */ @@ -116,7 +116,7 @@ MCKRDY_Loop: cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop
- ldr r0, =CONFIG_SYS_MCKR2_VAL + ldr r0, =CFG_SYS_MCKR2_VAL str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */ @@ -158,53 +158,53 @@ SDRAM_setup_end:
SMRDATA: .word AT91_ASM_WDT_MR - .word CONFIG_SYS_WDTC_WDMR_VAL + .word CFG_SYS_WDTC_WDMR_VAL /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) .word AT91_ASM_PIOD_PDR - .word CONFIG_SYS_PIOD_PDR_VAL1 + .word CFG_SYS_PIOD_PDR_VAL1 .word AT91_ASM_PIOD_PUDR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL .word AT91_ASM_PIOD_ASR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL1 + .word CFG_SYS_PIOC_PDR_VAL1 .word AT91_ASM_PIOC_PUDR - .word CONFIG_SYS_PIOC_PPUDR_VAL + .word CFG_SYS_PIOC_PPUDR_VAL #endif .word AT91_ASM_MATRIX_CSA0 - .word CONFIG_SYS_MATRIX_EBICSA_VAL + .word CFG_SYS_MATRIX_EBICSA_VAL
/* flash */ .word AT91_ASM_SMC_MODE0 - .word CONFIG_SYS_SMC0_MODE0_VAL + .word CFG_SYS_SMC0_MODE0_VAL
.word AT91_ASM_SMC_CYCLE0 - .word CONFIG_SYS_SMC0_CYCLE0_VAL + .word CFG_SYS_SMC0_CYCLE0_VAL
.word AT91_ASM_SMC_PULSE0 - .word CONFIG_SYS_SMC0_PULSE0_VAL + .word CFG_SYS_SMC0_PULSE0_VAL
.word AT91_ASM_SMC_SETUP0 - .word CONFIG_SYS_SMC0_SETUP0_VAL + .word CFG_SYS_SMC0_SETUP0_VAL
SMRDATA1: .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL1 + .word CFG_SYS_SDRC_TR_VAL1 .word AT91_ASM_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_SDRAMC_MDR - .word CONFIG_SYS_SDRC_MDR_VAL + .word CFG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL2 .word CFG_SYS_SDRAM_BASE @@ -222,20 +222,20 @@ SMRDATA1: .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL4 + .word CFG_SYS_SDRC_MR_VAL4 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL5 + .word CFG_SYS_SDRC_MR_VAL5 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL2 + .word CFG_SYS_SDRC_TR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR - .word CONFIG_SYS_RSTC_RMR_VAL + .word CFG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ .word AT91_ASM_MATRIX_MCFG diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index aa6bb6bf31e0..6bfa02d1d0a3 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -28,7 +28,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -58,7 +58,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -71,7 +71,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; @@ -271,7 +271,7 @@ u32 at91_get_periph_generated_clk(u32 id) clk_source = regval & AT91_PMC_PCR_GCKCSS; switch (clk_source) { case AT91_PMC_PCR_GCKCSS_SLOW_CLK: - freq = CONFIG_SYS_AT91_SLOW_CLOCK; + freq = CFG_SYS_AT91_SLOW_CLOCK; break; case AT91_PMC_PCR_GCKCSS_MAIN_CLK: freq = gd->arch.main_clk_rate_hz; diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 9b3753491eb2..616621a1f9de 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -18,8 +18,8 @@ #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif
int arch_cpu_init(void) @@ -27,7 +27,7 @@ int arch_cpu_init(void) #if defined(CONFIG_CLK_CCF) return 0; #else - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); #endif }
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 2daeb4fef8f8..103db2695335 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -128,7 +128,7 @@ #define ATMEL_BASE_CS7 0x80000000
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index d5de8d555107..2b252f1e1eda 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS7 0x80000000
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index c9fff934da42..0aa1862567c4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -127,7 +127,7 @@ #define ATMEL_BASE_CS7 0x80000000
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 588032582b2a..22116f375b8f 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -132,7 +132,7 @@ #define ATMEL_BASE_CS7 0x80000000
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 8f9155c9ea68..b2c074e93ec6 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index e3c494c5d5d4..0efb4a9f6d61 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -162,7 +162,7 @@ #endif
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h index c08d19c6917b..47c7c7209e37 100644 --- a/arch/arm/mach-at91/include/mach/sam9x60.h +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -140,7 +140,7 @@ #define ATMEL_CPU_NAME get_cpu_name()
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c +#define CFG_SYS_TIMER_COUNTER 0xfffffe4c
/* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 5ff20e957328..567cdd3cbacf 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -238,7 +238,7 @@ #define cpu_is_sama5d2 _cpu_is_sama5d2
/* PIT Timer(PIT_PIIR) */ -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c +#define CFG_SYS_TIMER_COUNTER 0xf804803c
#ifndef __ASSEMBLY__ unsigned int get_chip_id(void); diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 83f18a8148f7..9efcf5f4fab5 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -185,7 +185,7 @@ #define CPU_HAS_PCR
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/* * PMECC table in ROM diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index e2edb6a51b11..9c80286adecc 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -217,7 +217,7 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D44))
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/* * No PMECC Galois table in ROM diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index ea19ec322e81..dfba9f730c12 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -101,17 +101,17 @@ void board_init_f(ulong dummy) at91_pllicpr_init(0x00);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); + at91_plla_init(CFG_SYS_AT91_PLLA);
/* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); + at91_mck_init(CFG_SYS_MCKR);
/* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); + at91_mck_init(CFG_SYS_MCKR_CSS);
-#if defined(CONFIG_SYS_AT91_PLLB) +#if defined(CFG_SYS_AT91_PLLB) /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); + at91_pllb_init(CFG_SYS_AT91_PLLB); #endif
/* Enable External Reset */ @@ -120,7 +120,7 @@ void board_init_f(ulong dummy) /* Initialize matrix */ matrix_init();
- gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 217ed12e31ef..a30c4f6c075f 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -124,7 +124,7 @@ void board_init_f(ulong dummy) /* PMC configuration */ at91_pmc_init();
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
matrix_init();
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index 0f68f9fe59e5..dae60262f5b7 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -42,7 +42,7 @@ int clk_get(enum davinci_clk_ids id) int pll_out; unsigned int pll_base;
- pll_out = CONFIG_SYS_OSCIN_FREQ; + pll_out = CFG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID) goto out; diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 2319ac6d5631..08c8f5925243 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -185,9 +185,9 @@ static int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); } setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); - writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { /* DDR2 */ clrbits_le32(&davinci_syscfg1_regs->ddr_slew, (1 << DDR_SLEW_DDR_PDENA_BIT) | @@ -211,19 +211,19 @@ static int da850_ddr_setup(void) * At the same time, set the TIMUNLOCK bit to allow changing * the timing registers */ - tmp = CONFIG_SYS_DA850_DDR2_SDBCR; + tmp = CFG_SYS_DA850_DDR2_SDBCR; tmp &= ~DV_DDR_BOOTUNLOCK; tmp |= DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */ - if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { /* MOBILE DDR only*/ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + writel(CFG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); } - writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* clear the TIMUNLOCK bit and write the value of the CL field */ tmp &= ~DV_DDR_TIMUNLOCK; @@ -233,7 +233,7 @@ static int da850_ddr_setup(void) * LPMODEN and MCLKSTOPEN must be set! * Without this bits set, PSC don;t switch states !! */ - writel(CONFIG_SYS_DA850_DDR2_SDRCR | + writel(CFG_SYS_DA850_DDR2_SDRCR | (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), &dv_ddr2_regs_ctrl->sdrcr); @@ -246,7 +246,7 @@ static int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); - writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0; } @@ -265,7 +265,7 @@ int arch_cpu_init(void) writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc, - CONFIG_SYS_DA850_SYSCFG_SUSPSRC); + CFG_SYS_DA850_SYSCFG_SUSPSRC);
/* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) @@ -273,8 +273,8 @@ int arch_cpu_init(void)
#if defined(CONFIG_SYS_DA850_PLL_INIT) /* PLL setup */ - da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); - da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); + da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM); + da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM); #endif /* setup CSn config */ #if defined(CONFIG_SYS_DA850_CS2CFG) diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 43e0574901ee..83c190b620e7 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct davinci_timer * const timer = - (struct davinci_timer *)CONFIG_SYS_TIMERBASE; + (struct davinci_timer *)CFG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL 0xffffffff
@@ -47,7 +47,7 @@ int timer_init(void) writel(0x0, &timer->tim34); writel(TIMER_LOAD_VAL, &timer->prd34); writel(2 << 22, &timer->tcr); - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV; + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV; gd->arch.timer_reset_value = 0;
return(0); diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index f5185390571b..553dac75b61d 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -141,7 +141,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) { int upto, todo; int i, timeout = 100; - struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE; + struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* set the spi1 GPIO */ diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 0e7678648221..06ee608c4a46 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -248,13 +248,13 @@ unsigned long spl_nor_get_uboot_base(void) int end;
/* Calculate the image set end, - * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), - * we use CONFIG_SYS_UBOOT_BASE + * if it is less than CFG_SYS_UBOOT_BASE(0x8281000), + * we use CFG_SYS_UBOOT_BASE * Otherwise, use the calculated address */ end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); - if (end <= CONFIG_SYS_UBOOT_BASE) - end = CONFIG_SYS_UBOOT_BASE; + if (end <= CFG_SYS_UBOOT_BASE) + end = CFG_SYS_UBOOT_BASE; else end = ROUND(end, SZ_1K);
diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S index b42cc3e9e43a..6ec38dcfa4ea 100644 --- a/arch/arm/mach-imx/mx5/lowlevel_init.S +++ b/arch/arm/mach-imx/mx5/lowlevel_init.S @@ -205,7 +205,7 @@ setup_pll_func:
/* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -215,7 +215,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3_BASE_ADDR, 216 @@ -240,10 +240,10 @@ setup_pll_func:
/* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =CONFIG_SYS_CLKTL_CBCDR + ldr r1, =CFG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */ @@ -378,7 +378,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_SYS_MAIN_PWR_ON) +#if defined(CFG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk index 9cc1f9eb24fa..7bc8af813a6b 100644 --- a/arch/arm/mach-k3/config_secure.mk +++ b/arch/arm/mach-k3/config_secure.mk @@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$( $(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index 4734e4c7143b..dc97bac85501 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -23,7 +23,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE;
- freq = CONFIG_SYS_HZ_CLOCK; + freq = CFG_SYS_HZ_CLOCK;
addr = hextoul(argv[1], NULL);
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 98a8f058df4a..424c32a4bee3 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -263,7 +263,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) -#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ +#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \ KS2_MSMC_SEG_SIZE_SHIFT)
/* Device speed */ diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 5186f6e4f9ad..a2781e25a23b 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,8 +52,8 @@
/* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK +#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK #endif
#endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index c44eacfc1b9f..d3a3a8365764 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -15,6 +15,6 @@ #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index f86cd0bb6013..7f8e156a6bdc 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */ -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000)
#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1f8cdf8744e6..67ad5e5907be 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -659,7 +659,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
@@ -691,7 +691,7 @@ void v7_outer_cache_enable(void) void v7_outer_cache_disable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3b9618852c6d..e6383d4a86e2 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -54,7 +54,7 @@
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) -#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE +#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) @@ -146,7 +146,7 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ @@ -169,7 +169,7 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ @@ -188,7 +188,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) @@ -209,7 +209,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif
#endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 60c2072c354b..6c9783aa63fb 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -35,10 +35,10 @@ ENTRY(arch_very_early_init) * Disable L2 cache * * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG - * but CONFIG_SYS_PL310_BASE is already calculated from base + * but CFG_SYS_PL310_BASE is already calculated from base * address SOC_REGS_PHY_BASE. */ - ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) ldr r0, [r1, #L2X0_CTRL_OFF] bic r0, #L2X0_CTRL_EN str r0, [r1, #L2X0_CTRL_OFF] diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index cba2e342dc23..ed4b1ca5c983 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -11,7 +11,7 @@ void l2_pl310_init(void);
void set_pl310_ctrl(u32 enable) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
writel(enable, &pl310->pl310_ctrl); } diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index f76262bb0ce8..24ddcdb9614e 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 803dc7fb71d6..19197482aa42 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -124,11 +124,11 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_NOR) case MTD_DEV_TYPE_NOR: gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + base = CFG_SYS_FLASH_BASE; + size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : GPMC_SIZE_16M))); break; #endif @@ -142,7 +142,7 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_CMD_ONENAND) case MTD_DEV_TYPE_ONENAND: gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; + base = CFG_SYS_ONENAND_BASE; size = GPMC_SIZE_128M; break; #endif diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 00d91c10136d..71fdf5bf487c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE; static ulong get_timer_masked(void);
/* diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h index 0e9fe0dc51af..ee0aa94bf2c2 100644 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h @@ -18,6 +18,6 @@ #define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index d7ea2e3943fc..b373e59e6fe3 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -74,7 +74,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = static inline ulong read_timer(void) { return readl(CNTMR_VAL_REG(UBOOT_CNTR)) - / (CONFIG_SYS_TCLK / 1000); + / (CFG_SYS_TCLK / 1000); }
DECLARE_GLOBAL_DATA_PTR; @@ -92,7 +92,7 @@ static ulong get_timer_masked(void) } else { /* we have an overflow ... */ timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now; } lastdec = now;
@@ -115,7 +115,7 @@ void __udelay(unsigned long usec) ulong delayticks;
current = uboot_cntr_val(); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + delayticks = (usec * (CFG_SYS_TCLK / 1000000));
if (current < delayticks) { delayticks -= current; diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index 28669e3c7717..485ea7e28d11 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x00000000
/* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
#define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 37d134c5bf29..2006ad58a52d 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,7 +14,7 @@ */
/* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 06db64af6cfc..cc1b00db33f5 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -24,6 +24,6 @@ #define MSTP11_BITS 0x00000008
/* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 85f59d977125..02f4286ef1ac 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,7 +15,7 @@ */
/* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 2bd6e469c815..a2a949d4d61c 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x000001C0
/* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2 #define IS_R8A7794_ES2() \ diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c index ba06535e4c2a..293c23b5e254 100644 --- a/arch/arm/mach-rmobile/timer.c +++ b/arch/arm/mach-rmobile/timer.c @@ -40,8 +40,8 @@ static u64 get_time_us(void) { u64 timer = get_cpu_global_timer();
- timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); + timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); + do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); return timer; }
@@ -65,7 +65,7 @@ void __udelay(unsigned long usec) u64 wait;
start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); + wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); do { current = get_cpu_global_timer(); } while ((current - start) < wait); @@ -83,5 +83,5 @@ unsigned long long get_ticks(void)
ulong get_tbclk(void) { - return (ulong)(CONFIG_SYS_CPU_CLK >> 2); + return (ulong)(CFG_SYS_CPU_CLK >> 2); } diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de71b..5b5a81a255d5 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data");
#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; #endif
struct bsel bsel_str[] = { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7ce888d19797..93c9e8b0fb40 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -60,7 +60,7 @@ static Altera_desc altera_fpga[] = {
#if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
@@ -256,7 +256,7 @@ void dram_bank_mmu_setup(int bank) /* If we're still in OCRAM, don't set the XN bit on it */ if (!(gd->flags & GD_FLG_RELOC)) { set_section_dcache( - CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, DCACHE_WRITETHROUGH); }
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 4edf4f9b5c16..e7500c16f720 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 2c567edd502e..9edbbf4a29c3 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ -#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \ SOCFPGA_PHYS_OCRAM_SIZE - \ BOOTROM_SHARED_MEM_SIZE) #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index a58f1cf9d3a1..d9e8c84bfcfe 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -10,7 +10,7 @@
#define TIMER_LOAD_VAL 0xFFFFFFFF
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
/* * Timer initialization diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index f9fd4fe7d337..05a91346a897 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -22,7 +22,7 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_disable(void) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
/* * Linux expects the L2 cache to be turned off by the bootloader. diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c index a40bdf17055e..58247c2738aa 100644 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ b/arch/arm/mach-uniphier/arm32/timer.c @@ -10,7 +10,7 @@ #include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) +#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void) { diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index 739cb2997ad7..b471412186d1 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -36,9 +36,9 @@ int timer_init (void) ulong tmr_ctrl_val;
/* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/* * The Timer Control Register has one Undefined/Shouldn't Use Bit @@ -52,11 +52,11 @@ int timer_init (void) * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
return 0; } diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index e44656db5f23..6d87908965d2 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0;
/* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module);
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 87effa71dc37..10be73822fa5 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -47,36 +47,36 @@ void cpu_init_f(void) out_be16(&wdog->cr, 0); #endif
- out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */ out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -108,8 +108,8 @@ void cpu_init_f(void) #endif
#ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif
icache_enable(); diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index f41f977d7f5f..6b08a12af0b6 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -29,7 +29,7 @@ int get_clocks(void) while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) ;
- gd->bus_clk = CONFIG_SYS_CLK; + gd->bus_clk = CFG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 4c9c96d7831e..d2a21c3279b9 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -91,10 +91,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1
/* invalidate and disable cache */ @@ -116,7 +116,7 @@ _start: move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 8f72ef567feb..d21d82fef758 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -132,11 +132,11 @@ int print_cpuinfo(void)
if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); + cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CONFIG_SYS_CLK)); + pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0; } @@ -284,7 +284,7 @@ int print_cpuinfo(void) char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -370,7 +370,7 @@ int print_cpuinfo(void) char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -394,7 +394,7 @@ int print_cpuinfo(void)
unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 9d4a10f028d1..99eb61f16758 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -36,31 +36,31 @@ void init_fbcs(void) { fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) @@ -214,9 +214,9 @@ void cpu_init_f(void) init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG = - CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG = + CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #ifdef CONFIG_SYS_I2C2_OFFSET CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; @@ -335,21 +335,21 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR); gpio_t *gpio = (gpio_t *) (MMAP_GPIO); csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); - out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); + out_be16(&sysctrl->sc_scr, CFG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */ - out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); - out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); - out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); - out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); - out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); - out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); - out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); + out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CFG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); @@ -472,8 +472,8 @@ void cpu_init_f(void) #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif
/* enable instruction cache now */ @@ -560,8 +560,8 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | - MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); + MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) | + MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD); while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0; @@ -573,17 +573,17 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PFPAR MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; #endif -#ifdef CONFIG_SYS_PJPAR - MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; +#ifdef CFG_SYS_PJPAR + MCFGPIO_PJPAR = CFG_SYS_PJPAR; #endif #ifdef CONFIG_SYS_PSDPAR MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; #endif -#ifdef CONFIG_SYS_PASPAR - MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; +#ifdef CFG_SYS_PASPAR + MCFGPIO_PASPAR = CFG_SYS_PASPAR; #endif -#ifdef CONFIG_SYS_PEHLPAR - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; +#ifdef CFG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; #endif #ifdef CONFIG_SYS_PQSPAR MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; @@ -600,15 +600,15 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif -#ifdef CONFIG_SYS_PUAPAR - MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; +#ifdef CFG_SYS_PUAPAR + MCFGPIO_PUAPAR = CFG_SYS_PUAPAR; #endif
#if defined(CONFIG_SYS_DDRD) MCFGPIO_DDRD = CONFIG_SYS_DDRD; #endif -#ifdef CONFIG_SYS_DDRUA - MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; +#ifdef CFG_SYS_DDRUA + MCFGPIO_DDRUA = CFG_SYS_DDRUA; #endif
/* FlexBus Chipselect */ @@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; } else { MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR; } return 0; } @@ -678,12 +678,12 @@ void cpu_init_f(void) * which is their primary function. * ~Jeremy */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); + mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/* * dBug Compliance: diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index 045908a13d40..6c7628252b59 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -23,19 +23,19 @@ int get_clocks(void) #if defined(CONFIG_M5208) pll_t *pll = (pll_t *) MMAP_PLL;
- out_8(&pll->odr, CONFIG_SYS_PLL_ODR); - out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); + out_8(&pll->odr, CFG_SYS_PLL_ODR); + out_8(&pll->fdr, CFG_SYS_PLL_FDR); #endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr;
-#ifndef CONFIG_SYS_PLL_BYPASS +#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ @@ -43,7 +43,7 @@ int get_clocks(void) #endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253 - pllcr = CONFIG_SYS_PLLCR; + pllcr = CFG_SYS_PLLCR; #endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ @@ -52,7 +52,7 @@ int get_clocks(void) pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ +#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -68,7 +68,7 @@ int get_clocks(void) ; #endif
- gd->cpu_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CLK; #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 6dddbe76f3a2..d48d0192eea2 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -35,7 +35,7 @@ */ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -81,9 +81,9 @@ _vectors:
.text
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ +#if defined(CFG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ .long 0xFFFFFFFF /* all sectors protected */ .long 0x00000000 /* supervisor/User restriction */ @@ -100,53 +100,53 @@ _start:
#if defined(CONFIG_M5208) /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/ -#ifdef CONFIG_SYS_MBAR2 +#ifdef CFG_SYS_MBAR2 /* Get MBAR2 address */ - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 + move.l #(CFG_SYS_MBAR2 + 1), %d0 /* Set MBAR2 */ movec %d0, #0xc0e #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1
#if defined(CONFIG_M5282) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) /* * Setup code in SRAM to initialize FLASHBAR, * if start from internal Flash */ - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 + move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1 + move.l #(CFG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR + jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -154,9 +154,9 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR -#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ +#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif #endif @@ -165,22 +165,22 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) + move.l #CFG_SYS_INT_FLASH_BASE, %d0 #else - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 #endif movec %d0, %VBR #endif
#ifdef CONFIG_M5275 /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #endif
@@ -195,7 +195,7 @@ _after_flashbar_copy: move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 0659bf655811..53a25d8362cd 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -33,7 +33,7 @@ int print_cpuinfo(void) char buf[32];
printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CPU_CLK)); + strmhz(buf, CFG_SYS_CPU_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 83529408eb3e..dad47d87ab31 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -40,35 +40,35 @@ void init_csm(void) { csm_t *csm = (csm_t *)(MMAP_CSM);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ - defined(CONFIG_SYS_CS0_CTRL)) - out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); - out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \ + defined(CFG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CFG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CFG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ - defined(CONFIG_SYS_CS1_CTRL)) - out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); - out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \ + defined(CFG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CFG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CFG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ - defined(CONFIG_SYS_CS2_CTRL)) - out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); - out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \ + defined(CFG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CFG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CFG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ - defined(CONFIG_SYS_CS3_CTRL)) - out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); - out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \ + defined(CFG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CFG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CFG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ defined(CONFIG_SYS_CS4_CTRL)) diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index 03d9abeb182b..c8d079016f2e 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -16,8 +16,8 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #if defined(CONFIG_M5307) - gd->bus_clk = CONFIG_SYS_CLK; - gd->cpu_clk = CONFIG_SYS_CPU_CLK; + gd->bus_clk = CFG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CPU_CLK; #endif
return 0; diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 644c372bdd25..dbe2b54e4101 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -39,7 +39,7 @@ _vectors: /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 #if defined(CONFIG_M5307) && \ - (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -92,10 +92,10 @@ _start: move.w #0x2700,%sr
/* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 move.c %d0, %RAMBAR
/* DS 4.8.2 (Cache Organization) invalidate and disable cache */ @@ -110,7 +110,7 @@ _start: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif
@@ -125,7 +125,7 @@ _start: move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 1dadffd4ca36..8a48d73475c8 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0;
/* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 1311f3967c9a..844d2cd7600f 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -37,34 +37,34 @@ void cpu_init_f(void) out_be32(&scm1->pacrf, 0); out_be32(&scm1->pacrg, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -102,8 +102,8 @@ int cpu_init_r(void) rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
- out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); - out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); + out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
#endif #ifdef CONFIG_MCFFEC @@ -236,36 +236,36 @@ void cpu_init_f(void) /* Port configuration */ out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ setbits_8(&gpio->par_cs, GPIO_PAR_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -327,7 +327,7 @@ void uart_port_conf(int port) clrbits_8(&gpio->par_feci2c, 0x00ff); setbits_8(&gpio->par_feci2c, GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); -#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) +#elif defined(CFG_SYS_UART2_ALT3_GPIO) clrbits_be16(&gpio->par_ssi, 0x0f00); setbits_be16(&gpio->par_ssi, GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index dac2229f72e1..32ffac08135d 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -252,7 +252,7 @@ int clock_pll(int fsys, int flags) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { - gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; + gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 26728919160e..72a2f99b7dd2 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -98,11 +98,11 @@ _start:
#if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1
/* invalidate and disable cache */ @@ -131,7 +131,7 @@ _start: move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9b3f9f0fe133..1ce244872f14 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -29,30 +29,30 @@ void init_fbcs(void) fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_SERIAL_BOOT) -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -208,14 +208,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs();
-#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* * now the flash base address is no longer at 0 (Newer ColdFire family * boot at address 0 instead of 0xFFnn_nnnn). The vector table must * also move to the new location. */ - if (CONFIG_SYS_CS0_BASE != 0) - setvbr(CONFIG_SYS_CS0_BASE); + if (CFG_SYS_CS0_BASE != 0) + setvbr(CFG_SYS_CS0_BASE); #endif
icache_enable(); diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index aea8f3090fef..a083c3d45d27 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -27,10 +27,10 @@
#if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #endif
.text @@ -123,18 +123,18 @@ asm_dram_init:
#ifdef CONFIG_SYS_NAND_BOOT /* for assembly stack */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- #endif
#ifdef CONFIG_CF_SBF - move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + move.l #CFG_SYS_INIT_RAM_ADDR, %d0 movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1
/* initialize general use internal ram */ @@ -145,7 +145,7 @@ asm_dram_init: move.l %d0, (%a2)
/* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -153,17 +153,17 @@ asm_dram_init: movec %d0, %ACR2 movec %d0, %ACR3
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@-
-#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif #endif /* CONFIG_CF_SBF */
@@ -216,8 +216,8 @@ asm_dspi_init: move.l (%a1)+, %d5 move.l (%a1), %a4
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
@@ -334,14 +334,14 @@ asm_nand_init: movec %d0, %ACR2 movec %d0, %ACR3
-#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif
/* NAND port configuration */ @@ -442,10 +442,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1
/* initialize general use internal ram */ @@ -456,7 +456,7 @@ _start: move.l %d0, (%a2)
/* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -464,7 +464,7 @@ _start: movec %d0, %ACR2 movec %d0, %ACR3 #else - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif
@@ -472,7 +472,7 @@ _start: move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index ceb462f438f2..c05356fc930c 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -135,28 +135,28 @@ #endif /* CONFIG_CF_V4 */
-#ifndef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_ICACR 0 +#ifndef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_ICACR 0 #endif
-#ifndef CONFIG_SYS_CACHE_DCACR -#ifdef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#ifndef CFG_SYS_CACHE_DCACR +#ifdef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR #else -#define CONFIG_SYS_CACHE_DCACR 0 +#define CFG_SYS_CACHE_DCACR 0 #endif #endif
-#ifndef CONFIG_SYS_CACHE_ACR0 -#define CONFIG_SYS_CACHE_ACR0 0 +#ifndef CFG_SYS_CACHE_ACR0 +#define CFG_SYS_CACHE_ACR0 0 #endif
-#ifndef CONFIG_SYS_CACHE_ACR1 -#define CONFIG_SYS_CACHE_ACR1 0 +#ifndef CFG_SYS_CACHE_ACR1 +#define CFG_SYS_CACHE_ACR1 0 #endif
-#ifndef CONFIG_SYS_CACHE_ACR2 -#define CONFIG_SYS_CACHE_ACR2 0 +#ifndef CFG_SYS_CACHE_ACR2 +#define CFG_SYS_CACHE_ACR2 0 #endif
#ifndef CONFIG_SYS_CACHE_ACR3 diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 672aa0bb14ea..dab8b26a7037 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -14,7 +14,7 @@ #include <asm/m520x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ #ifdef CONFIG_MCFTMR @@ -37,7 +37,7 @@ #include <asm/m5235.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */ #ifdef CONFIG_MCFTMR @@ -59,7 +59,7 @@ #include <asm/immap_5249.h> #include <asm/m5249.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -82,7 +82,7 @@ #include <asm/m5249.h> #include <asm/m5253.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -105,7 +105,7 @@ #include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */ #ifdef CONFIG_MCFTMR @@ -128,7 +128,7 @@ #include <asm/m5272.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -152,7 +152,7 @@
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (192) @@ -175,7 +175,7 @@ #include <asm/m5282.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) @@ -198,7 +198,7 @@ #include <asm/m5307.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x40)) + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64)
@@ -223,7 +223,7 @@
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ #ifdef CONFIG_MCFTMR @@ -246,7 +246,7 @@ #include <asm/m5329.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ #ifdef CONFIG_MCFTMR @@ -271,12 +271,12 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#if (CONFIG_SYS_UART_PORT < 4) +#if (CFG_SYS_UART_PORT < 4) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x4000)) + (CFG_SYS_UART_PORT * 0x4000)) #else #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ - ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) + ((CFG_SYS_UART_PORT - 4) * 0x4000)) #endif
#define MMAP_DSPI MMAP_DSPI0 @@ -320,7 +320,7 @@ #define FEC1_TX_INIT 31 #endif
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) @@ -339,7 +339,7 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) -#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR) #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h index bb1237453ff1..7c7443b96885 100644 --- a/arch/m68k/include/asm/immap_520x.h +++ b/arch/m68k/include/asm/immap_520x.h @@ -9,32 +9,32 @@ #ifndef __IMMAP_520X__ #define __IMMAP_520X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000)
#include <asm/coldfire/crossbar.h> #include <asm/coldfire/edma.h> diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h index 27d905ef9419..a1825c2a944f 100644 --- a/arch/m68k/include/asm/immap_5235.h +++ b/arch/m68k/include/asm/immap_5235.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5235__ #define __IMMAP_5235__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h index b599ca6e81c4..aa4c3ef42fad 100644 --- a/arch/m68k/include/asm/immap_5249.h +++ b/arch/m68k/include/asm/immap_5249.h @@ -8,13 +8,13 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h> #include <asm/coldfire/qspi.h> diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h index 883782aa97ce..1ab7243dfd8a 100644 --- a/arch/m68k/include/asm/immap_5253.h +++ b/arch/m68k/include/asm/immap_5253.h @@ -9,20 +9,20 @@ #ifndef __IMMAP_5253__ #define __IMMAP_5253__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000)
-#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) +#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C) +#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h index 27d786139938..a5bf18c4b848 100644 --- a/arch/m68k/include/asm/immap_5271.h +++ b/arch/m68k/include/asm/immap_5271.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h index cd7b67256cfb..c5c3cc751258 100644 --- a/arch/m68k/include/asm/immap_5272.h +++ b/arch/m68k/include/asm/immap_5272.h @@ -8,24 +8,24 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__
-#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) -#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840) +#define MMAP_USB (CFG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index 8b1a08b4f24f..9b8d71d30d44 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -10,44 +10,44 @@ #ifndef __IMMAP_5275__ #define __IMMAP_5275__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800) +#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index d7c68f5749a2..f810a4dd5cb5 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -8,42 +8,42 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index 29e60863bfde..e1f7858b1007 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -9,46 +9,46 @@ #ifndef __IMMAP_5301X__ #define __IMMAP_5301X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) -#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) -#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000) +#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000) +#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000) +#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000) +#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000) +#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000) +#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000)
#include <asm/coldfire/crossbar.h> #include <asm/coldfire/dspi.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index 930e0899e8ca..d6442d95b4ba 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -7,15 +7,15 @@ #ifndef __IMMAP_5307__ #define __IMMAP_5307__
-#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) +#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244)
typedef struct sim { u8 rsr; diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h index 9303629e4b2a..afafb4e547dc 100644 --- a/arch/m68k/include/asm/m5249.h +++ b/arch/m68k/include/asm/m5249.h @@ -14,14 +14,14 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
/* * Size of internal RAM diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index 7ebeddbb683b..e63b42c00de3 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -11,12 +11,12 @@ #ifndef _MCF5271_H_ #define _MCF5271_H_
-#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) +#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
#define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h index 0c91cf491e24..180f20386fc7 100644 --- a/arch/m68k/include/asm/m5282.h +++ b/arch/m68k/include/asm/m5282.h @@ -108,112 +108,112 @@
/* General Purpose I/O Module GPIO */
-#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) +#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C))
/* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -310,25 +310,25 @@
/* System Conrol Module SCM */
-#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) - -#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013)) + +#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -337,8 +337,8 @@
/* Reset Controller Module RCM */
-#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -360,9 +360,9 @@
/* Chip Configuration Module CCM */
-#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A))
/* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -377,18 +377,18 @@
/* Clock Module */
-#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08
-#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -418,60 +418,60 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001)
-#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) +#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006))
/********************************************************************* * General Purpose Timer (GPT) Module *********************************************************************/
-#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) - -#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E)) + +#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E))
/* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -556,7 +556,7 @@
/* Coldfire Flash Module CFM */
-#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -564,23 +564,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020)
-#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002))
-#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000)
-#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04
-#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 7eca6725a658..0b4629f1c8a7 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -16,7 +16,7 @@ int arch_setup_bdinfo(void) { struct bd_info *bd = gd->bd;
- bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ + bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ @@ -38,7 +38,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd;
bdinfo_print_mhz("busfreq", bd->bi_busfreq); -#if defined(CONFIG_SYS_MBAR) +#if defined(CFG_SYS_MBAR) bdinfo_print_num_l("mbar", bd->bi_mbar_base); #endif bdinfo_print_mhz("cpufreq", bd->bi_intfreq); diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index aa2b93e0e0fb..4ddda69f5a38 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -34,18 +34,18 @@ void icache_enable(void) *cf_icache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2)); __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); #endif #else - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR)); }
void icache_disable(void) @@ -72,9 +72,9 @@ void icache_invalid(void) { u32 temp;
- temp = CONFIG_SYS_ICACHE_INV; + temp = CFG_SYS_ICACHE_INV; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); } @@ -89,15 +89,15 @@ void dcache_enable(void) *cf_dcache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); #endif #endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR)); }
void dcache_disable(void) @@ -124,11 +124,11 @@ void dcache_invalid(void) #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) u32 temp;
- temp = CONFIG_SYS_DCACHE_INV; + temp = CFG_SYS_DCACHE_INV; if (*cf_dcache_status) - temp |= CONFIG_SYS_CACHE_DCACR; + temp |= CFG_SYS_CACHE_DCACR; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); #endif diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 6b9f253952a1..7063f32610b7 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -19,7 +19,7 @@
#ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) + CFG_SYS_INIT_SP_OFFSET) #endif
#define SP_ADDR_TEMP 0xbe10dff0 diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 33835eeec2a8..63c2729411c7 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -77,10 +77,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ SCCR_TSEC1CM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ SCCR_TSEC2CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ @@ -92,10 +92,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ SCCR_USBMPHCM | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ SCCR_USBDRCM | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ SCCR_SATACM | #endif 0; @@ -115,11 +115,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | @@ -130,11 +130,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | #endif 0;
@@ -175,26 +175,26 @@ void cpu_init_f (volatile immap_t * im) setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/* System General Purpose Register */ -#ifdef CONFIG_SYS_SICRH +#ifdef CFG_SYS_SICRH #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, &im->sysconf.sicrh); #else - __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); + __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif -#ifdef CONFIG_SYS_SICRL - __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); +#ifdef CFG_SYS_SICRL + __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); #endif -#ifdef CONFIG_SYS_GPR1 - __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); +#ifdef CFG_SYS_GPR1 + __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); #endif -#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ - __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); +#ifdef CFG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif -#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ - __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); +#ifdef CFG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); #endif
#if !defined(CONFIG_PINCTRL) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 6d1c6b055c6b..4f982b8303ae 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -59,9 +59,9 @@ void board_add_ram_info(int use_default)
printf(", %s MHz)", strmhz(buf, gd->mem_clk));
-#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) +#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE) puts("\nSDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); + print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); #endif }
@@ -204,12 +204,12 @@ long int spd_sdram() return 0; }
-#ifdef CONFIG_SYS_DDRCDR_VALUE +#ifdef CFG_SYS_DDRCDR_VALUE /* * Adjust DDR II IO voltage biasing. It just makes it work. */ if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; } udelay(50000); #endif @@ -693,7 +693,7 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ -#ifdef CONFIG_SYS_DDR_MODE_WEAK +#ifdef CFG_SYS_DDR_MODE_WEAK | (1 << (16 + 1)) /* weak driver (~60%) */ #endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ @@ -767,8 +767,8 @@ long int spd_sdram() debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); }
-#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; +#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 8fcf20854ed9..7cc0383afbfc 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -54,12 +54,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CFG_SYS_DDRCDR + im->sysconf.ddrcdr = CFG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CFG_SYS_OBIR + im->sysconf.obir = CFG_SYS_OBIR; #endif
/* diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 8a351b927c05..52326f0ec155 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -246,7 +246,7 @@ in_flash:
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif
@@ -486,7 +486,7 @@ init_e300_core: /* time t 10 */ #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ - lis r4, CONFIG_SYS_WATCHDOG_VALUE + lis r4, CFG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3)
@@ -1048,10 +1048,10 @@ trap_init: lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -1070,10 +1070,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 dcbi r0, r3 @@ -1122,14 +1122,14 @@ map_flash_by_law1: * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1150,24 +1150,24 @@ remap_flash_by_law0: lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 - lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l + lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3) - lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) + lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1) or r4, r4, r5 stw r4, OR0(r3)
- lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h index f8c2f104c1b9..b2f98074fc06 100644 --- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -1,7 +1,7 @@ #ifdef CONFIG_ARCH_MPC8308
-#ifndef CONFIG_SYS_SICRL -#define CONFIG_SYS_SICRL (\ +#ifndef CFG_SYS_SICRL +#define CFG_SYS_SICRL (\ CONFIG_SICRL_SPI |\ CONFIG_SICRL_UART |\ CONFIG_SICRL_IRQ |\ @@ -10,8 +10,8 @@ ) #endif
-#ifndef CONFIG_SYS_SICRH -#define CONFIG_SYS_SICRH (\ +#ifndef CFG_SYS_SICRH +#define CFG_SYS_SICRH (\ CONFIG_SICRH_ESDHC_A |\ CONFIG_SICRH_ESDHC_B |\ CONFIG_SICRH_ESDHC_C |\ diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 3dccc0e1068e..013a171ed87b 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ed890114ec48..c7d473d4a1b4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -23,7 +23,7 @@ */ static void check_erratum_a4849(uint32_t svr) { - void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000; unsigned int i;
#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) @@ -120,7 +120,7 @@ static void check_erratum_a4580(uint32_t svr) */ static void check_erratum_a007212(void) { - u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
if (in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6acd31d28479..74ad7483dc10 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -417,7 +417,7 @@ void print_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ - !defined(CONFIG_SYS_INIT_L2_ADDR) + !defined(CFG_SYS_INIT_L2_ADDR) int dram_init(void) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, @@ -591,7 +591,7 @@ static void dump_spd_ddr_reg(void) /* invalid the TLBs for DDR and setup new ones to cover p_addr */ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; int ddr_esel; @@ -624,8 +624,8 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) test_cap = p_size; #else test_cap = gd->ram_size; @@ -635,7 +635,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; printf("Testing 0x%08llx - 0x%08llx\n", (u64)(*vstart) + (*phys_offset), @@ -651,13 +651,13 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
- *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { puts("Cannot test more than "); print_size(CONFIG_MAX_MEM_MAPPED, diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c320b202ea2..f07e8ab388e8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -165,7 +165,7 @@ void disable_cpc_sram(void) for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ - struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
if (law.index == -1) { printf("\nFatal error happened\n"); @@ -315,15 +315,15 @@ void fsl_erratum_a007212_workaround(void) { ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; - u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); - u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); - u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); + u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) - u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); - u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); + u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) - u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); - u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); + u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68); #endif #endif /* @@ -378,7 +378,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) @@ -403,7 +403,7 @@ ulong cpu_init_f(void)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ - law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + law = find_law(CFG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index);
@@ -430,7 +430,7 @@ ulong cpu_init_f(void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc();
- #ifdef CONFIG_SYS_DCSRBAR_PHYS + #ifdef CFG_SYS_DCSRBAR_PHYS /* set DCSRCR so that DCSR space is 1G */ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); in_be32(&gur->dcsrcr); @@ -533,7 +533,7 @@ int l2cache_init(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl;
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) if (cache_ctl & MPC85xx_L2CTL_L2E) { /* Clear L2 SRAM memory-mapped base address */ out_be32(&l2cache->l2srbar0, 0x0); @@ -590,15 +590,15 @@ int l2cache_init(void)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); -#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) +#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE - && l2srbar >= CONFIG_SYS_FLASH_BASE) { - l2srbar = CONFIG_SYS_INIT_L2_ADDR; + && l2srbar >= CFG_SYS_FLASH_BASE) { + l2srbar = CFG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR); } -#endif /* CONFIG_SYS_INIT_L2_ADDR */ +#endif /* CFG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -625,9 +625,9 @@ int l2cache_init(void) #endif
/* enable the cache */ - mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
- if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { + if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); @@ -656,7 +656,7 @@ skip_l2: int cpu_init_r(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -763,13 +763,13 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; - __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; + __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
for (i = 0; i < 12; i++) { p += i + (i > 5 ? 11 : 0); out_be32(p, 0x2); } - p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; + p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108; out_be32(p, 0x34); } #endif @@ -799,18 +799,18 @@ int cpu_init_r(void) { if (SVR_MAJ(svr) < 3) { void *p; - p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + p = (void *)CFG_SYS_DCSRBAR + 0x20520; setbits_be32(p, 1 << (31 - 14)); } } #endif
-#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing * speed for NOR flash. */ - clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -850,7 +850,7 @@ int cpu_init_r(void) */ if (IS_SVR_REV(get_svr(), 1, 0)) { struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) - (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET); setbits_be32(&dcfg->ecccr1, (DCSR_DCFG_ECC_DISABLE_USB1 | DCSR_DCFG_ECC_DISABLE_USB2)); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 18bfa2aed14e..a67f37e3af96 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -17,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_A003399_NOR_WORKAROUND void setup_ifc(void) { - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; u32 _mas0, _mas1, _mas2, _mas3, _mas7; - phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; + phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
/* * Adjust the TLB we were running out of to match the phys addr of the * chip select we are adjusting and will return to. */ - flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | @@ -52,7 +52,7 @@ void setup_ifc(void) * * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * bacause flash's physical address is going to change as - * CONFIG_SYS_FLASH_BASE_PHYS. + * CFG_SYS_FLASH_BASE_PHYS. */ _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); @@ -72,9 +72,9 @@ void setup_ifc(void) #endif
/* Change flash's physical address */ - ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0); + ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0); + ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
return; } @@ -101,7 +101,7 @@ void cpu_init_early_f(void *fdt)
#ifdef CONFIG_ARCH_QEMU_E500 /* - * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; @@ -109,9 +109,9 @@ void cpu_init_early_f(void *fdt)
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
write_tlb(mas0, mas1, mas2, mas3, mas7);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 32348b4e147f..a7e1df104d73 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -144,14 +144,14 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_SPL_MMC_BOOT - off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, - CONFIG_SYS_MMC_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START, + CFG_SYS_MMC_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SD deep sleep: %s\n", fdt_strerror(off)); #elif defined(CONFIG_SPL_SPI_BOOT) - off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, - CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START, + CFG_SYS_SPI_FLASH_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SPI deep sleep: %s\n", fdt_strerror(off)); @@ -448,7 +448,7 @@ void fdt_add_enet_stashing(void *fdt) static void ft_fixup_clks(void *blob, const char *compat, u32 offset, unsigned long freq) { - phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS; int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) { @@ -679,17 +679,17 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
ft_fixup_dpaa_clks(blob);
-#if defined(CONFIG_SYS_BMAN_MEM_PHYS) +#if defined(CFG_SYS_BMAN_MEM_PHYS) fdt_portal(blob, "fsl,bman-portal", "bman-portals", - (u64)CONFIG_SYS_BMAN_MEM_PHYS, - CONFIG_SYS_BMAN_MEM_SIZE); + (u64)CFG_SYS_BMAN_MEM_PHYS, + CFG_SYS_BMAN_MEM_SIZE); fdt_fixup_bportals(blob); #endif
-#if defined(CONFIG_SYS_QMAN_MEM_PHYS) +#if defined(CFG_SYS_QMAN_MEM_PHYS) fdt_portal(blob, "fsl,qman-portal", "qman-portals", - (u64)CONFIG_SYS_QMAN_MEM_PHYS, - CONFIG_SYS_QMAN_MEM_SIZE); + (u64)CFG_SYS_QMAN_MEM_PHYS, + CFG_SYS_QMAN_MEM_SIZE);
fdt_fixup_qportals(blob); #endif @@ -737,7 +737,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) * beginning of CCSR. */ #define CCSR_VIRT_TO_PHYS(x) \ - (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
static void msg(const char *name, uint64_t uaddr, uint64_t daddr) { @@ -783,8 +783,8 @@ int ft_verify_fdt(void *fdt) return 0; }
- if (addr != CONFIG_SYS_CCSRBAR_PHYS) { - msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); + if (addr != CFG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } @@ -818,12 +818,12 @@ int ft_verify_fdt(void *fdt) * the 'reg' property to be wrong, so check it here. For now, we * only check for "fsl,elbc" nodes. */ -#ifdef CONFIG_SYS_LBC_ADDR +#ifdef CFG_SYS_LBC_ADDR off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); if (off > 0) { const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); if (reg) { - uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
addr = fdt_translate_address(fdt, off, reg); if (uaddr != addr) { diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 3a6ce32f7e6c..9b6577e547e5 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -203,7 +203,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = - (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); + (struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR); u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; u32 bc_status, fc_status, dc_status, pll_sr2; serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 437ecde61559..7c2de02c4c56 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -264,9 +264,9 @@ void serdes_reset_rx(enum srds_prtcl device) } #endif
-#ifndef CONFIG_SYS_DCSRBAR_PHYS -#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ -#define CONFIG_SYS_DCSRBAR 0x80000000 +#ifndef CFG_SYS_DCSRBAR_PHYS +#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CFG_SYS_DCSRBAR 0x80000000 #define __DCSR_NOT_DEFINED_BY_CONFIG #endif
@@ -315,16 +315,16 @@ static void enable_bank(ccsr_gur_t *gur, int bank) */ { #ifdef __DCSR_NOT_DEFINED_BY_CONFIG - struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS); int law_index; if (law.index == -1) - law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); else - set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); #endif - u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114; out_be32(p, rcw5); #ifdef __DCSR_NOT_DEFINED_BY_CONFIG if (law.index == -1) diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 2b790868e126..540a6e6e191f 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7db05d9672b8..8f645258a5fc 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index ba54b0310a7b..db411162022b 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), SET_QP_INFO( 3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 6f11c81aba5d..bd05eae2551d 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index d37e1ccf1e7f..391751ce1e71 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -276,8 +276,8 @@ __secondary_start_page: mtspr SPRN_L2CSR1,r3 #endif
- lis r3,CONFIG_SYS_INIT_L2CSR0@h - ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + lis r3,CFG_SYS_INIT_L2CSR0@h + ori r3,r3,CFG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 isync 2: diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e2bdc2f9f112..a6e352ceabb1 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -218,22 +218,22 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -243,7 +243,7 @@ void get_sys_info(sys_info_t *sys_info)
} #else - sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
#endif #endif @@ -380,25 +380,25 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -407,31 +407,31 @@ void get_sys_info(sys_info_t *sys_info) break; } #if (CFG_SYS_NUM_FMAN) == 2 -#ifdef CONFIG_SYS_FM2_CLK +#ifdef CFG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4; break; case 5: sys_info->freq_fman[1] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -442,7 +442,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif /* CFG_SYS_NUM_FMAN == 2 */ #else - sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; + sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK; #endif #endif
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 47df3c2ce19f..ce2b9c216677 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -14,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR;
ulong cpu_init_f(void) { -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
- out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
/* set MBECCDIS=1, SBECCDIS=1 */ out_be32(&l2cache->l2errdis, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 534175697435..562b6993b9da 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -128,7 +128,7 @@ bootsect: .Lconf_pair_start:
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ - .long CONFIG_SYS_INIT_L2_ADDR + .long CFG_SYS_INIT_L2_ADDR
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC @@ -428,12 +428,12 @@ l2_disabled: mtspr SPRN_BUCSR,r0 #endif
-#if defined(CONFIG_SYS_INIT_DBCR) +#if defined(CFG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CONFIG_SYS_INIT_DBCR@l + lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CFG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif
@@ -573,34 +573,34 @@ nexti: mflr r1 /* R1 = our PC */ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for * long-term TLBs, so we use TLB0 here. */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS)
-#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) -#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW) +#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined." #endif
create_ccsr_new_tlb: /* * Create a TLB for the new location of CCSR. Register R8 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR). */ - lis r8, CONFIG_SYS_CCSRBAR@h - ori r8, r8, CONFIG_SYS_CCSRBAR@l - lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h - ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + lis r8, CFG_SYS_CCSRBAR@h + ori r8, r8, CFG_SYS_CCSRBAR@l + lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 /* * Create a TLB for the current location of CCSR. Register R9 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: create_tlb0_entry 1, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 0, r3 /* The default CCSR address is always a 32-bit number */
@@ -634,7 +634,7 @@ infinite_debug_loop:
#ifdef CONFIG_FSL_CORENET
-#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ @@ -644,10 +644,10 @@ create_temp_law: * On CoreNet systems, we create the temporary LAW using a special LAW * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. */ - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRBAR_LAWAR@h ori r2, r2, CCSRBAR_LAWAR@l
@@ -683,10 +683,10 @@ read_old_ccsrbar: * instruction. */ write_new_ccsrbar: - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRAR_C@h ori r2, r2, CCSRAR_C@l
@@ -723,9 +723,9 @@ write_new_ccsrbar: lwz r0, 0(r9) isync
-/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ -#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ - (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) +/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CFG_SYS_CCSRBAR_PHYS_LOW >> 12))
/* Write the new value to CCSRBAR. */ lis r0, CCSRBAR_PHYS_RS12@h @@ -752,10 +752,10 @@ write_new_ccsrbar:
/* Delete the temporary TLBs */ delete_temp_tlbs: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 - delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
-#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: @@ -765,14 +765,14 @@ create_ccsr_l2_tlb: */ create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3
enable_l2_cluster_l2: /* enable L2 cache */ - lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h - ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l li r4, 33 /* stash id */ stw r4, 4(r3) lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -813,7 +813,7 @@ enable_l2_cluster_l2: beq 1b
delete_ccsr_l2_tlb: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif
/* @@ -863,7 +863,7 @@ delete_ccsr_l2_tlb: andi. r1,r3,L1CSR0_DCE@l beq 2b #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 -#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_1M 0x13 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
@@ -884,13 +884,13 @@ delete_ccsr_l2_tlb: rlwimi r0, r8, 16, MAS0_ESEL_MSK lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l - lis r7, CONFIG_SYS_CCSRBAR@h - ori r7, r7, CONFIG_SYS_CCSRBAR@l + lis r7, CFG_SYS_CCSRBAR@h + ori r7, r7, CFG_SYS_CCSRBAR@l ori r2, r7, MAS2_I|MAS2_G - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l - lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 @@ -1132,7 +1132,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6
/* @@ -1148,7 +1148,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6
#else @@ -1164,19 +1164,19 @@ create_init_ram_area: #endif
/* create a temp mapping in AS=1 to the stack */ -#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ - defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) +#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH) create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
#else create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif
@@ -1194,8 +1194,8 @@ switch_as:
/* Allocate Initial RAM in data cache. */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -1230,11 +1230,11 @@ switch_as: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + lis r3,(CFG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
#if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif
@@ -1243,8 +1243,8 @@ _start_cont: #endif
/* End of RAM */ - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + lis r4,(CFG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l
li r0,0
@@ -1826,8 +1826,8 @@ trap_init: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) @@ -1844,8 +1844,8 @@ unlock_ram_in_cache: sync
/* Invalidate the TLB entries for the cache */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index d2744bb9f82b..bab076b2b180 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 99b52bacdad6..59f4f9c6692c 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 17521dc3a4a8..390bb1153758 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 8fe4e96a1140..37ea7788ccfc 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 81e60722f9fc..5d21bef58781 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -302,7 +302,7 @@ uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; u64 size;
@@ -324,13 +324,13 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { return - setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); }
/* Invalidate the DDR TLBs for the requested size */ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; phys_addr_t rpn = 0; @@ -351,7 +351,7 @@ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
void clear_ddr_tlbs(unsigned int memsize_in_meg) { - clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); }
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index f28826c5d1a2..d918b4395bf4 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -64,7 +64,7 @@ SECTIONS _end = .;
#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif @@ -101,7 +101,7 @@ SECTIONS .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 0ebb7b33a8bc..1f1107e61d5f 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -141,8 +141,8 @@ in_flash: mtspr DER, r2
/* set up the stack on top of internal DPRAM */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l stw r0, -4(r3) stw r0, -8(r3) addi r1, r3, -8 diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 1101b9138f14..1c051d18980f 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -230,7 +230,7 @@ static int pamu_config_spaace(uint32_t liodn,
int pamu_init(void) { - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; u32 i = 0; u64 ppaact_phys, ppaact_lim, ppaact_size; @@ -292,7 +292,7 @@ int pamu_init(void) void pamu_enable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); @@ -304,7 +304,7 @@ void pamu_enable(void) void pamu_reset(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs;
for (i = 0; i < CONFIG_NUM_PAMU; i++) { @@ -328,7 +328,7 @@ void pamu_reset(void) void pamu_disable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CONFIG_NUM_PAMU; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 71496ab294d2..caad6670cc90 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -21,17 +21,17 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++; -#ifdef CONFIG_SYS_FLASH_BASE_PHYS +#ifdef CFG_SYS_FLASH_BASE_PHYS tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS); tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2edf0d6f83c2..d9e5a7d62170 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -43,9 +43,9 @@ #elif defined(CONFIG_ARCH_P1023) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CFG_SYS_QMAN_NUM_PORTALS 3 +#define CFG_SYS_BMAN_NUM_PORTALS 3 +#define CFG_SYS_FM_MURAM_SIZE 0x10000
/* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -68,7 +68,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -78,7 +78,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -90,7 +90,7 @@ #define CFG_SYS_NUM_FM2_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -103,7 +103,7 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_DTSEC 5 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131) @@ -134,11 +134,11 @@ #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 #define CFG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_PME_CLK 0 +#define CFG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 3 -#define CONFIG_SYS_FM2_CLK 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM1_CLK 3 +#define CFG_SYS_FM2_CLK 3 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -147,9 +147,9 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 @@ -173,11 +173,11 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_FM_PLAT_CLK_DIV 1 -#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -191,9 +191,9 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -212,10 +212,10 @@ #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5038cb9f590a..a03f091c3059 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -469,7 +469,7 @@ extern void print_lbc_regs(void); extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size);
-#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR) #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index de85bcfdcf96..0af3d8902ace 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ }
#define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ }
#define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -70,22 +70,22 @@ extern void fdt_fixup_liodn(void *blob); { .compat[0] = name1, \ .compat[1] = name2, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ }
#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ }
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ }
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3e707600f28f..e8b26802062b 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,11 +9,11 @@
#ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#define CFG_SYS_PBI_FLASH_BASE 0xc0000000 #else -#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#define CFG_SYS_PBI_FLASH_BASE 0xce000000 #endif -#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000
#if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ @@ -21,18 +21,18 @@ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#undef CFG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif
#if defined(CONFIG_RAMBOOT_PBL) -#undef CONFIG_SYS_INIT_L3_ADDR -#ifdef CONFIG_SYS_INIT_L3_VADDR -#define CONFIG_SYS_INIT_L3_ADDR \ - (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ +#undef CFG_SYS_INIT_L3_ADDR +#ifdef CFG_SYS_INIT_L3_VADDR +#define CFG_SYS_INIT_L3_ADDR \ + (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 0xbff00000 #else -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8e1820267088..19774f3053b3 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -871,11 +871,11 @@ struct ccsr_gpio { #define CFG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
-#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) +#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9ae698743eee..283fdf3b458a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2445,10 +2445,10 @@ struct ccsr_pman { #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ -#define CONFIG_SYS_OSPR_OFFSET 0x200 -#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#define CFG_SYS_OSPR_OFFSET 0x200 +#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET) #else -#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#define CFG_SYS_SFP_OFFSET 0xE8000 #endif #define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 @@ -2489,7 +2489,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 -#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 +#define CFG_SYS_SEC_MON_OFFSET 0x314000 #define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CFG_SYS_FSL_QMAN_OFFSET 0x318000 #define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2542,13 +2542,13 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#define CFG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) -#define CONFIG_SYS_TSEC1_OFFSET 0x10000 +#define CFG_SYS_TSEC1_OFFSET 0x10000 #else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 @@ -2559,8 +2559,8 @@ struct ccsr_pman { #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 -#define CONFIG_SYS_SFP_OFFSET 0xE7000 +#define CFG_SYS_SEC_MON_OFFSET 0xE6000 +#define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 #define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CFG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2574,9 +2574,9 @@ struct ccsr_pman { #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CFG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) #define CFG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) #define CFG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) #define CFG_SYS_FSL_BMAN_ADDR \ @@ -2603,9 +2603,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) -#define CONFIG_SYS_LBC_ADDR \ +#define CFG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_IFC_ADDR \ +#define CFG_SYS_IFC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) #define CFG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) @@ -2659,7 +2659,7 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) #define CFG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) -#define CONFIG_SYS_PAMU_ADDR \ +#define CFG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CFG_SYS_PCIE1_ADDR \ @@ -2667,14 +2667,14 @@ struct ccsr_pman { #define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
-#define CONFIG_SYS_SFP_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CFG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET)
-#define CONFIG_SYS_SEC_MON_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) +#define CFG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { @@ -2735,7 +2735,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
-#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index d4a6057527c2..b638ea7be611 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -23,7 +23,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point;
- image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, + image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ, 0, 0); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 99d8797a549f..03c196fec3b1 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,7 @@ #include <asm/processor.h>
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
#endif diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index c11101b44ece..1eb97ac5bb17 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -144,7 +144,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c,
/* Make sure the window is below U-Boot. */ assert(window + LARGE_PAGE_SIZE < - gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE); + gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE); /* Map the page into the window and then memset the appropriate part. */ x86_phys_map_page(window, map_addr, 1); memset((void *)(window + offset), c, size); diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h index 3b27f9308a06..920b5fd26b20 100644 --- a/arch/xtensa/include/asm/addrspace.h +++ b/arch/xtensa/include/asm/addrspace.h @@ -22,8 +22,8 @@ * The actual location of memory and IO is the board property. */
-#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) -#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) +#define IOADDR(x) (CFG_SYS_IO_BASE + (x)) +#define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x)) #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ XCHAL_VECBASE_RESET_PADDR)
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index f9a37e7215c9..ea49c7a99c0b 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n"); -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) puts(" Boot from Internal FLASH\n"); #endif return 0; @@ -38,7 +38,7 @@ int dram_init(void)
size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | - MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); + MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4); asm (" nop"); #ifdef CFG_SYS_SDRAM_BASE0 MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| @@ -94,7 +94,7 @@ int dram_init(void) return 0; }
-#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 695d6f6ed470..917091340009 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -88,7 +88,7 @@ int board_init(void)
#if defined(CONFIG_MISC_INIT_R)
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR) +#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR) /* * Start I2C fan (GMT G762 controller) */ @@ -100,11 +100,11 @@ static void init_fan(void)
/* Enable open-loop and PWM modes */ data = 0x20; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_FAN_CMD1, 1, &data, 1) != 0) goto err; data = 0; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_CNT, 1, &data, 1) != 0) goto err; /* @@ -124,18 +124,18 @@ static void init_fan(void) * Start fan at low speed (2800 RPM): */ data = 0x08; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_OUT, 1, &data, 1) != 0) goto err;
return; err: printf("Error: failed to start I2C fan @%02x\n", - CONFIG_SYS_I2C_G762_ADDR); + CFG_SYS_I2C_G762_ADDR); } #else static void init_fan(void) {} -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */ +#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */
#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO) /* diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index 06f964f53a3b..a0bace7b46c2 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -56,8 +56,8 @@ void setup_board_tags(struct tag **in_params) t = (struct tag_mv_uboot *)¶ms->u;
t->uboot_version = VER_NUM | syno_board_id(); - t->tclk = CONFIG_SYS_TCLK; - t->sysclk = CONFIG_SYS_TCLK * 2; + t->tclk = CFG_SYS_TCLK; + t->sysclk = CFG_SYS_TCLK * 2; t->isusbhost = usb_port_modes();
for (i = 0; i < ETHADDR_MAX; i++) { diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index d220b877d661..9db5135a8ffa 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -41,10 +41,10 @@ static unsigned long long div_clock = DIV_CLOCK_INIT; static unsigned long long div_timer = 1; /* Divisor to convert timer reading * change to U-Boot ticks */ -/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ +/* CONFIG_SYS_HZ = CFG_SYS_HZ_CLOCK/(div_clock * div_timer) */ static ulong timestamp; /* U-Boot ticks since startup */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) +#define READ_TIMER (*(volatile ulong *)(CFG_SYS_TIMERBASE+4))
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec * - unless otherwise stated @@ -55,7 +55,7 @@ static ulong timestamp; /* U-Boot ticks since startup */ int timer_init (void) { /* Load timer with initial value */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; #ifdef CONFIG_ARCH_CINTEGRATOR /* Set timer to be * enabled 1 @@ -66,7 +66,7 @@ int timer_init (void) * 32 bit 1 * wrapping 0 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x000000C2; #else /* Set timer to be * enabled 1 @@ -75,7 +75,7 @@ int timer_init (void) * divider 256 10 * XX 00 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x00000088; #endif
/* init the timestamp */ @@ -85,7 +85,7 @@ int timer_init (void) /* start "advancing" time stamp from 0 */ timestamp = 0L;
- div_timer = CONFIG_SYS_HZ_CLOCK; + div_timer = CFG_SYS_HZ_CLOCK; do_div(div_timer, CONFIG_SYS_HZ); do_div(div_timer, div_clock);
@@ -156,7 +156,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - unsigned long long tmp = CONFIG_SYS_HZ_CLOCK; + unsigned long long tmp = CFG_SYS_HZ_CLOCK;
do_div(tmp, div_clock);
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index af326dc6f453..4ca544f1017d 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -108,7 +108,7 @@ unsigned long __section(".data") prior_stage_fdt_address[2]; #define JUNO_FLASH_SEC_SIZE (256 * 1024) static phys_addr_t find_dtb_in_nor_flash(const char *partname) { - phys_addr_t sector = CONFIG_SYS_FLASH_BASE; + phys_addr_t sector = CFG_SYS_FLASH_BASE; int i;
for (i = 0; @@ -140,7 +140,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; reg = readl(imginfo + 0x54);
- return CONFIG_SYS_FLASH_BASE + + return CFG_SYS_FLASH_BASE + reg * JUNO_FLASH_SEC_SIZE; } } diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index ade7f9d120ae..f38f5564a06c 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -58,8 +58,8 @@ unsigned long get_board_sys_clk(void) * else non-zero (hang). */
-#ifdef CONFIG_SYS_FPGAREG_FREQ - return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#ifdef CFG_SYS_FPGAREG_FREQ + return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ); #else /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ return 50000000; @@ -90,7 +90,7 @@ int misc_init_r(void) if (s == 0) { unsigned int x; char s[] = __stringify(CONFIG_ETHBASE); - x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW) & FPGAREG_MAC_MASK; sprintf(&s[15], "%02x", x); env_set("ethaddr", s); @@ -106,9 +106,9 @@ U_BOOT_DRVINFO(sysreset) = {
static struct ethoc_eth_pdata ethoc_pdata = { .eth_pdata = { - .iobase = CONFIG_SYS_ETHOC_BASE, + .iobase = CFG_SYS_ETHOC_BASE, }, - .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, + .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR, };
U_BOOT_DRVINFO(ethoc) = { diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index 1a039c53c142..37340fe97003 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -187,7 +187,7 @@ static void atf_print_part_table(void) int ret; char *ptype;
- struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + struct storage_partition *part = (void *)CFG_SYS_LOWMEM_BASE;
pcount = atf_get_pcount();
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index a8f8c7855844..ab20825ed36f 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -20,7 +20,7 @@ #include <dm/platform_data/serial_pl01x.h>
static const struct pl01x_serial_plat serial0 = { - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, .type = TYPE_PL011, .clock = 0, .skip_init = true, @@ -32,7 +32,7 @@ U_BOOT_DRVINFO(thunderx_serial0) = { };
static const struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, .clock = 0, .skip_init = true, diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 5d15ed4e691d..8416af163ad1 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -12,7 +12,7 @@ #include <uuid.h> #include <linux/delay.h>
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; @@ -102,8 +102,8 @@ unsigned long flash_init(void) }
flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); + CFG_SYS_FLASH_BASE, + CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
return size; } @@ -117,8 +117,8 @@ unsigned long flash_init(void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S index cbf8134346d5..8d8842ebedfa 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/board/cortina/presidio-asic/lowlevel_init.S @@ -27,7 +27,7 @@ skip_smp_setup:
#if defined(CONFIG_SOC_CA8277B) /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE + ldr x0, =CFG_SYS_TIMER_BASE mov x1, #1 str w1, [x0] #endif diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index f344622b0243..aae0a5dac066 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -84,7 +84,7 @@ int board_init(void) unsigned int reg_data, jtag_id;
/* Enable timer */ - writel(1, CONFIG_SYS_TIMER_BASE); + writel(1, CFG_SYS_TIMER_BASE);
/* Enable snoop in CCI400 slave port#4 */ writel(3, 0xF5595000); diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 2436aab71ccf..e3a0f266a4c5 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -371,20 +371,20 @@ int rmii_hw_init(void) /* Set polarity to non-inverted */ buf[0] = 0x0; buf[1] = 0x0; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); return ret; }
/* Configure P07-P05 as outputs */ buf[0] = 0x1f; buf[1] = 0xff; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); }
/* For Ethernet RMII selection @@ -392,16 +392,16 @@ int rmii_hw_init(void) * P06(SelB)=1 * P05(SelC)=1 */ - if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x read FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); }
buf[0] &= 0x1f; buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); - if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); }
/* Set the output as high */ diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 913c2ea16640..ceb0d2cf0aa3 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -193,6 +193,6 @@ int board_mmc_init(struct bd_info *bd)
int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN); } #endif diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index a4254250bbf3..a39bcb4fa0c7 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -41,7 +41,7 @@ static void *get_fdt_virt(void) if (gd->flags & GD_FLG_RELOC) return (void *)gd->fdt_blob; else - return (void *)CONFIG_SYS_TMPVIRT; + return (void *)CFG_SYS_TMPVIRT; }
static uint64_t get_fdt_phys(void) @@ -163,7 +163,7 @@ int misc_init_r(void) * U-Boot is relocated to RAM already, let's delete the temporary FDT * virtual-physical mapping that was used in the pre-relocation phase. */ - disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1)); + disable_tlb(find_tlb_idx((void *)CFG_SYS_TMPVIRT, 1));
/* * Detect the presence of the platform bus node, and @@ -248,7 +248,7 @@ void init_tlbs(void) init_used_tlb_cams();
/* Create a dynamic AS=0 CCSRBAR mapping */ - assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + assert(!tlb_map_range(CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, 1024 * 1024, TLB_MAP_IO));
/* Create a RAM map that spans all accessible RAM */ diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 2304e9e8ec3d..21f4ba98b531 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -240,7 +240,7 @@ int misc_init_r(void) if (str && (strcmp(str, "4") == 0)) { writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | AT91SAM9_PMC_MDIV_4, &pmc->mckr); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index d31ad026568b..9ca350ed4689 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -43,7 +43,7 @@ int fsl_check_boot_mode_secure(void) { uint32_t val; - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 3424d49208fe..285ed9afcc9a 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -85,7 +85,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); + u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); u32 flash_addr, addr; int found = 0; int i = 0; @@ -160,7 +160,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + @@ -170,7 +170,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) *ie_addr = (uintptr_t)((sg_tbl->src_addr & - ~(CONFIG_SYS_PBI_FLASH_BASE)) + + ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else *ie_addr = (uintptr_t)sg_tbl->src_addr; @@ -203,7 +203,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img) /* This function returns ospr's key_revoc values.*/ static u32 get_key_revoc(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> OSPR_KEY_REVOC_SHIFT; } @@ -342,7 +342,7 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
/* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; @@ -367,7 +367,7 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
@@ -871,7 +871,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr) int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, uintptr_t *img_addr_ptr) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; struct fsl_secboot_img_priv *img; diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 8951fae32d3b..1a1e9343d23b 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -11,12 +11,12 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), #endif #ifdef PIXIS_BASE_PHYS SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), @@ -24,9 +24,9 @@ struct law_entry law_table[] = { #ifdef CPLD_BASE_PHYS SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 7302b7606628..1a2d9cbfc0ce 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -11,20 +11,20 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), #ifdef CPLD_BASE @@ -41,25 +41,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
#if !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot - * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR, * and virtual address is CONFIG_SYS_MONITOR_BASE */
SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #endif @@ -80,13 +80,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -112,26 +112,26 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000, + CFG_SYS_BMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000, + CFG_SYS_QMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 2bb838cea6c4..da2c1de078b7 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -29,15 +29,15 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #endif
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { #if !CONFIG_IS_ENABLED(DM_I2C) - return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg); #else struct udevice *dev;
- if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) return 0xff;
return dm_i2c_reg_read(dev, reg); @@ -48,11 +48,11 @@ void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; #if !CONFIG_IS_ENABLED(DM_I2C) - i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val); #else struct udevice *dev;
- if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) dm_i2c_reg_write(dev, reg, val); #endif
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index af76327e4d2f..784046ac4e07 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,12 +100,12 @@ u16 qixis_read_minor(void); char *qixis_read_time(char *result); char *qixis_read_tag(char *buf); const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif
-#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR) #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) @@ -114,7 +114,7 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) #endif
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index f17a6c186d3b..194b5d27295b 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -117,7 +117,7 @@ int misc_init_r(void) struct udevice *dev; int ret;
- ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -128,7 +128,7 @@ int misc_init_r(void) #else i2c_set_bus_num(bus_num);
- i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); #endif
return 0; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d0674d014ac5..d5cb7312095a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -196,7 +196,7 @@ void board_init_f(ulong dummy) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); - out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8b74d458237d..4f5834347db4 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -98,7 +98,7 @@ struct cpld_data { #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void cpld_show(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", in_8(&cpld_data->cpld_ver) & VERSION_MASK, @@ -248,7 +248,7 @@ int board_eth_init(struct bd_info *bis) static void convert_serdes_mux(int type, int need_reset) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
current_serdes = cpld_data->serdes_mux;
@@ -322,7 +322,7 @@ int config_serdes_mux(void) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_board_mux(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); int conflict_flag;
conflict_flag = 0; @@ -610,7 +610,7 @@ u16 flash_read16(void *addr) && !defined(CONFIG_SPL_BUILD) static void convert_flash_bank(char bank) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
printf("Now switch to boot from flash bank %d.\n", bank); cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; @@ -644,7 +644,7 @@ U_BOOT_CMD( static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
if (argc > 2) return CMD_RET_USAGE; @@ -671,7 +671,7 @@ U_BOOT_CMD( static void print_serdes_mux(void) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
current_serdes = cpld_data->serdes_mux;
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 5fe40c4bdb25..841d8b59bb4c 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -57,8 +57,8 @@ enum { struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -71,8 +71,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -126,8 +126,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -139,8 +139,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -152,15 +152,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 232035638b38..9db3aa586059 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -12,14 +12,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index a8a7263a6538..741a4d64ea9e 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -60,15 +60,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; @@ -102,15 +102,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 97d71dbf2adb..3d0881643cd9 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -55,8 +55,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -81,15 +81,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -110,8 +110,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -123,8 +123,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -136,15 +136,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 548601a5ae16..ee19d4ff8aab 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -12,14 +12,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index ff3abc830229..0d3f22ce2bb3 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -52,13 +52,13 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR, 0, }, { "nor1", - CONFIG_SYS_NOR1_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR1_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK_EARLY, CFG_SYS_NOR_CSOR, { @@ -68,7 +68,7 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR, CFG_SYS_NOR_AMASK, }, { @@ -86,10 +86,10 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -121,10 +121,10 @@ struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -746,12 +746,12 @@ int set_serdes_volt(int svdd)
/* Read the BRDCFG54 via CLPD */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else struct udevice *dev;
- ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (!ret) ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, (void *)&brdcfg4, 1); @@ -766,7 +766,7 @@ int set_serdes_volt(int svdd)
/* Write to the BRDCFG4 */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 971633c9c8b2..a4cb1a6cac4e 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -118,10 +118,10 @@ Kernel.itb 0x01000000 0x08000 Environment Variables --------------------- - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
- mcmemsize: MC DRAM block size. If this variable is not defined - the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) ------------------------------------------------------------------- diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 5df85722d1df..91db618227d0 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -217,7 +217,7 @@ int board_init(void)
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT #if CONFIG_IS_ENABLED(DM_I2C) - rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); + rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); #else rtc_enable_32khz_output(); #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 437675517ebd..cf5b1ee46e00 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -57,9 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pl01x_serial_plat serial0 = { #if CONFIG_CONS_INDEX == 0 - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, #elif CONFIG_CONS_INDEX == 1 - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, #else #error "Unsupported console index value." #endif @@ -72,7 +72,7 @@ U_BOOT_DRVINFO(nxp_serial0) = { };
static struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, };
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index efff05514096..d67db24d5883 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -26,7 +26,7 @@ int checkboard (void) { /* * Set LED on */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0; @@ -42,13 +42,13 @@ int dram_init(void) * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 */
-#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK /* * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 */ mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CONFIG_SYS_PLL_BYPASS +#elif CFG_SYS_PLL_BYPASS /* * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index bff1ac5fb113..fbd483541608 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -42,7 +42,7 @@ ulong flash_init(void) ulong size = 0; ulong fbase = 0;
- fbase = (ulong) CONFIG_SYS_FLASH_BASE; + fbase = (ulong) CFG_SYS_FLASH_BASE; flash_get_size((FPWV *) fbase, &flash_info[0]); flash_get_offsets((ulong) fbase, &flash_info[0]); fbase += flash_info[0].size; @@ -64,9 +64,9 @@ int flash_get_offsets(ulong base, flash_info_t * info)
info->start[0] = base; info->protect[0] = 0; - for (i = 1; i < CONFIG_SYS_SST_SECT; i++) { + for (i = 1; i < CFG_SYS_SST_SECT; i++) { info->start[i] = info->start[i - 1] - + CONFIG_SYS_SST_SECTSZ; + + CFG_SYS_SST_SECTSZ; info->protect[i] = 0; } } @@ -162,8 +162,8 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info)
info->sector_count = 0; info->size = 0; - info->sector_count = CONFIG_SYS_SST_SECT; - info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ; + info->sector_count = CFG_SYS_SST_SECT; + info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ;
/* reset ID mode */ *addr = (FPWV) 0x00F000F0; @@ -222,7 +222,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
start = get_timer(0);
- if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { + if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) { if (prot == 0) { addr = (FPWV *) info->start[0];
@@ -259,7 +259,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) enable_interrupts();
return 0; - } else if (prot == CONFIG_SYS_SST_SECT) { + } else if (prot == CFG_SYS_SST_SECT) { return 1; } } @@ -282,7 +282,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
flag = disable_interrupts();
- base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */ + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */
base[FLASH_CYCLE1] = 0x00AA; /* unlock */ base[FLASH_CYCLE2] = 0x0055; /* unlock */ @@ -411,7 +411,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) return (2); }
- base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + base = (FPWV *) (CFG_SYS_FLASH_BASE);
/* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 179a2a242a8d..c1cff52fb3db 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -36,7 +36,7 @@ int dram_init(void) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp;
- RC = (CONFIG_SYS_CLK / 1000000) >> 1; + RC = (CFG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */ @@ -113,7 +113,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ + period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */ out_8(&ata->t1, CALC_TIMING(piotms[2][0])); diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 0de36a7f747b..34f05f3fdc72 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -68,7 +68,7 @@ CONFIG_M53015 -- define for MCF53015 CPUs CONFIG_M53017EVB -- define for M53017EVB board
CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver @@ -96,11 +96,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset
-CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index a10c365ec378..d921eef8b675 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bfbcd5dc81db..7240648796b5 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -67,7 +67,7 @@ CONFIG_M5373 -- define for all Freescale MCF5373 CPUs CONFIG_M5373EVB -- define for M5373EVB board
CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver @@ -95,11 +95,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset
-CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index fdf3e0ac1b1b..6d825a66e33f 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 85d43cccd1a0..4a1455402650 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -22,7 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { @@ -103,25 +103,25 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; udelay(50000);
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000);
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; udelay(1000);
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; sync(); udelay(1000);
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index d19438899152..7b6ef5b11c92 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -12,7 +12,7 @@
struct law_entry law_table[] = { /* LBC window - maps 256M */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index e4c951feb5ac..73e024eaa011 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -103,11 +103,11 @@ void lbc_sdram_init(void)
uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE; uint lsdmr_common;
puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/* @@ -115,17 +115,17 @@ void lbc_sdram_init(void) */ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->lbcr = CFG_SYS_LBC_LBCR; asm("msync");
- lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CFG_SYS_LBC_LSRT; + lbc->mrtpr = CFG_SYS_LBC_MRTPR; asm("msync");
/* * MPC8548 uses "new" 15-16 style addressing. */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516;
/* diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 9c8e94860089..994a32dd92ad 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -11,16 +11,16 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
@@ -29,7 +29,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 0: * FLASH(cover boot page) 16M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1),
@@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 1: * CCSRBAR 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1),
@@ -45,8 +45,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 2: * LBC SDRAM 64M Cacheable, non-guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, - CONFIG_SYS_LBC_SDRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, + CFG_SYS_LBC_SDRAM_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 2, BOOKE_PAGESZ_64M, 1),
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 4f27d3e8ecce..d447ad840adb 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ u32 get_board_rev(void)
int rev = readl(&fuse->gp[6]);
- if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) rev = 0;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; @@ -81,7 +81,7 @@ static int power_init(void) int ret; struct pmic *p;
- if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) { ret = pmic_dialog_init(I2C_PMIC); if (ret) return ret; diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 2dcee79b3aee..13fc2fa2e38c 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -8,8 +8,8 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), };
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ab3b2e3e69b5..0f014823c935 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -83,7 +83,7 @@ struct cpld_data { int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); /* @@ -97,7 +97,7 @@ int board_early_init_f(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -118,12 +118,12 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1);
set_tlb(1, flashbase + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); return 0; @@ -138,7 +138,7 @@ int config_board_mux(int ctrl_type) struct udevice *dev; int ret; #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR1, 1, &dev); @@ -254,7 +254,7 @@ int config_board_mux(int ctrl_type) #endif #else #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
switch (ctrl_type) { case MUX_TYPE_IFC: @@ -404,7 +404,7 @@ int i2c_pca9557_read(int type) int checkboard(void) { struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 val;
cpu = gd->arch.cpu; diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 9bf948cb5c96..e450f626e0ad 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -29,7 +29,7 @@ void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
console_init_f();
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 5e1fa70bca55..265cde81a3c2 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -8,19 +8,19 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
@@ -36,17 +36,17 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1),
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1),
@@ -73,14 +73,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif
-#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index f896fd7ccce5..5f16779abaad 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -201,7 +201,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */
-#ifdef CONFIG_SYS_DDR_CS0_BNDS +#ifdef CFG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -209,35 +209,35 @@ phys_size_t fixed_sdram(void) char buf[32]; size_t ddr_size; fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS, + .cs[0].config = CFG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2, #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, + .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS, + .cs[1].config = CFG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2, #endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CFG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CFG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL, .ddr_data_init = 0xdeadbeef, /* Poison value */ - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CFG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CFG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2 };
get_sys_info(&sysinfo); @@ -248,7 +248,7 @@ phys_size_t fixed_sdram(void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 8f3f4840e604..6085984eab43 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -8,11 +8,11 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 2999c85d0aed..ab7972442970 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -90,20 +90,20 @@ void board_reset_prepare(void) * This ensures that external watchdog does not trigger * another reset or possible infinite reset loop. */ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); in_8(&cpld_data->wd_cfg); /* Read back to sync write */ }
void board_reset_last(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->system_rst, 1); }
void board_cpld_init(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); @@ -226,7 +226,7 @@ int board_early_init_f(void)
int checkboard(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, invert, io_config, val; int bus_num = CONFIG_SYS_SPD_BUS_NUM; @@ -246,7 +246,7 @@ int checkboard(void) struct udevice *dev; int ret;
- ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -264,10 +264,10 @@ int checkboard(void) #else /* Non DM I2C support - will be removed */ i2c_set_bus_num(bus_num);
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { + if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } @@ -319,7 +319,7 @@ int checkboard(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); #ifdef CONFIG_VSC7385_ENET unsigned int vscfw_addr; @@ -344,7 +344,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 4cc5e01f5789..94773969e9d8 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -8,20 +8,20 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
@@ -32,14 +32,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1),
@@ -57,13 +57,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_VSC7385_ENET /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif #endif /* not SPL */
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1),
@@ -76,27 +76,27 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020RDB_PD) /* **M** - 2G DDR on P1020MBG, map the second 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */
-#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* ***G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000, + CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 12, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23ec32b7f975..3e12c816abc4 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -35,10 +35,10 @@ static u8 lane_to_slot[] = { };
static int riser_phy_addr[] = { - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, };
/* @@ -101,12 +101,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, slot = lane_to_slot[lane]; if (slot) { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } else { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + CFG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } @@ -158,9 +158,9 @@ int board_eth_init(struct bd_info *bis) * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; @@ -180,8 +180,8 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + CFG_SYS_FM1_DTSEC5_PHY_ADDR : + CFG_SYS_FM1_DTSEC4_PHY_ADDR); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", @@ -198,7 +198,7 @@ int board_eth_init(struct bd_info *bis) slot = lane_to_slot[lane]; if (slot) fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + CFG_SYS_FM1_10GEC1_PHY_ADDR); }
fm_info_set_mdio(FM1_10GEC1, diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1b1263091e50..575259b19c03 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -119,7 +119,7 @@ void board_config_lanes_mux(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -140,7 +140,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1);
diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index 47c3b1627e34..17a6226cafc7 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -14,14 +14,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 818c20cf1b5e..1b4173989925 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -222,7 +222,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 850ece0110ef..d636bef325f0 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -9,19 +9,19 @@
struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f777f5a2fe7f..baa59615b3ee 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -130,8 +130,8 @@ int board_early_init_f(void)
int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -150,7 +150,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 74744c8ab0ad..2519a9e4dbee 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -8,31 +8,31 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -42,13 +42,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -64,27 +64,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -93,18 +93,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index ac34095f3b66..9ac57bbd8300 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -7,7 +7,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map */
#include <common.h> @@ -18,14 +18,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 539a36d2a9ba..02ddb6614158 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -115,7 +115,7 @@ found: #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 5ce24b40964f..fe51d68c7bb6 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis) * DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042RDB @@ -59,7 +59,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, 0); /* T1042RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042D4RDB @@ -68,11 +68,11 @@ int board_eth_init(struct bd_info *bis) * & DTSEC3 */ if (FM1_DTSEC1 == i) - phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + phy_addr = CFG_SYS_SGMII1_PHY_ADDR; if (FM1_DTSEC2 == i) - phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + phy_addr = CFG_SYS_SGMII2_PHY_ADDR; if (FM1_DTSEC3 == i) - phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + phy_addr = CFG_SYS_SGMII3_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; #endif @@ -81,9 +81,9 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) - phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + phy_addr = CFG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) - phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + phy_addr = CFG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { for (i = 0; i < 4; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus); @@ -124,7 +124,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { for (i = 4; i < 8; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus); diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index 2f00d8010698..a0d6eb5b2707 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -9,19 +9,19 @@
struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 66a142b3ad03..dd8283f3c60a 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong bootflag) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000), pinctl); } #endif diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 7d3fd291a019..45ebdd30004c 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -62,8 +62,8 @@ int board_early_init_f(void)
int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -84,7 +84,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 905e4771c91e..10be580b8136 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -8,32 +8,32 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \ !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1),
@@ -44,8 +44,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * and virtual address is 0xfffc0000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, - CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR, + CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -55,13 +55,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -77,27 +77,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -111,18 +111,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index f97467e84455..3cdd4937684e 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -11,19 +11,19 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif #ifdef QIXIS_BASE_PHYS SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 82710cf897b2..8be55e52e5f6 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -282,7 +282,7 @@ static void esdhc_adapter_card_ident(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -303,7 +303,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1);
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f2448e86c0d2..3d220afc16e6 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -11,31 +11,31 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -143,7 +143,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index b9ba62adffcd..933fa0decc31 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -11,14 +11,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index 3ff4c773d599..53a13694506f 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -11,19 +11,19 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1c8017b593aa..04cb313e8c4c 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -77,7 +77,7 @@ int checkboard(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -96,7 +96,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1);
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 45c27c081205..688a208c621f 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -11,31 +11,31 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -126,8 +126,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index d484509bc20a..8b1012086ec7 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -9,7 +9,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CFG_SYS_CPLD_BASE - The virtual address of the base of the * CPLD register map * */ @@ -22,14 +22,14 @@
u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg); }
void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value); } diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 438589604f19..43eeb884e2ff 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -8,19 +8,19 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 20ce7523e57a..0bd0ba939628 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -54,7 +54,7 @@ int checkboard(void)
int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -75,7 +75,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1);
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index c57af3046f91..f5af893c2d9d 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -8,29 +8,29 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 512K SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_512K, 1), #else @@ -40,13 +40,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -73,28 +73,28 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -108,13 +108,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 18, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 4889a6a4f3b9..4fac146353da 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -40,26 +40,26 @@ static long fixed_sdram(void) out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE);
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
/* Currently we use only one CS, so disable the other bank. */ out_be32(&im->ddr.cs_config[1], 0);
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); sync();
/* enable DDR controller */ diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 6c5e6fbbcb0d..f1599306e618 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -82,7 +82,7 @@ int onenand_board_init(struct mtd_info *mtd) { if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; return 0; } return 1; diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 5401bddf06a9..b433f69675ab 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -20,7 +20,7 @@
void show_qrio(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
printf("QRIO: id = %u, revision = %u\n", @@ -33,7 +33,7 @@ bool qrio_get_selftest_pin(void) { u8 slftest;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
slftest = in_8(qrio_base + SLFTEST_OFF);
@@ -46,7 +46,7 @@ bool qrio_get_pgy_pres_pin(void) { u8 pgy_pres;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
pgy_pres = in_8(qrio_base + BPRTH_OFF);
@@ -57,7 +57,7 @@ int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
gprt = in_be32(qrio_base + port_off + GPRT_OFF);
@@ -68,7 +68,7 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) { u32 gprt, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
@@ -85,7 +85,7 @@ void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) { u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
@@ -100,7 +100,7 @@ void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) { u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
@@ -113,7 +113,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) { u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
@@ -133,7 +133,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) void qrio_wdmask(u8 bit, bool wden) { u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
wdmask = in_be16(qrio_base + WDMASK_OFF);
@@ -150,7 +150,7 @@ void qrio_wdmask(u8 bit, bool wden) void qrio_prst(u8 bit, bool en, bool wden) { u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
qrio_wdmask(bit, wden);
@@ -170,7 +170,7 @@ void qrio_prstcfg(u8 bit, u8 mode) { unsigned long prstcfg; u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
@@ -191,7 +191,7 @@ void qrio_prstcfg(u8 bit, u8 mode) void qrio_set_leds(void) { u8 ctrlh; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
/* set UNIT LED to RED and BOOT LED to ON */ ctrlh = in_8(qrio_base + CTRLH_OFF); @@ -205,7 +205,7 @@ void qrio_set_leds(void) void qrio_enable_app_buffer(void) { u8 ctrll; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
/* enable application buffer */ ctrll = in_8(qrio_base + CTRLL_OFF); @@ -219,7 +219,7 @@ void qrio_enable_app_buffer(void) void qrio_cpuwd_flag(bool flag) { u8 reason1; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
reason1 = in_8(qrio_base + REASON1_OFF); if (flag) @@ -246,7 +246,7 @@ void qrio_cpuwd_flag(bool flag) bool qrio_reason_unitrst(void) { u16 reason; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
reason = in_be16(qrio_base + REASON1_OFF);
@@ -258,7 +258,7 @@ bool qrio_reason_unitrst(void) void qrio_uprstreq(u8 mode) { u32 rstcfg; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
rstcfg = in_8(qrio_base + RSTCFG_OFF);
@@ -277,7 +277,7 @@ void qrio_uprstreq(u8 mode)
ulong early_bootcount_load(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; @@ -295,7 +295,7 @@ ulong early_bootcount_load(void)
void early_bootcount_store(ulong ebootcount) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ddd8f7a13e1a..88afc76bbbf6 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -40,7 +40,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; static int piggy_present(void) { struct km_bec_fpga __iomem *base = - (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
return in_8(&base->bprth) & PIGGY_PRESENT; } @@ -53,7 +53,7 @@ int ethernet_present(void) int board_early_init_r(void) { struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
#if defined(CONFIG_ARCH_MPC8360) unsigned short svid; @@ -126,18 +126,18 @@ static int fixed_sdram(void) u32 ddr_size_log2;
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); - out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); udelay(200); setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
@@ -215,7 +215,7 @@ int post_hotkeys_pressed(void) { int testpin = 0; struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 6a1711092b62..9f68c215f38c 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -44,7 +44,7 @@ int checkboard(void)
int board_early_init_f(void) { - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false;
@@ -141,7 +141,7 @@ int board_early_init_r(void) { int ret = 0;
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1);
/* @@ -162,7 +162,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); }
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1);
diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c index b04a8e20dce9..ec3bb8fe8061 100644 --- a/board/keymile/kmcent2/law.c +++ b/board/keymile/kmcent2/law.c @@ -10,12 +10,12 @@ #include <asm/fsl_law.h>
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), /* other application LAW are not used in u-boot */ }; diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 0f6dc6063ab1..41b24e39433d 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -11,20 +11,20 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
@@ -35,13 +35,13 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, 0, 2, BOOKE_PAGESZ_128M, 1),
@@ -56,22 +56,22 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1),
@@ -80,11 +80,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), /* QRIO */ - SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 11, BOOKE_PAGESZ_64K, 1), /* MRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 12, BOOKE_PAGESZ_128M, 1), /* BFTIC */ @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * in cpu_init_f, so do not use them here!!. */ /* PAXE */ - SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 16, BOOKE_PAGESZ_128M, 1) }; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 1a7fa3fc1e48..e005ece469bb 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -52,7 +52,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */ setbits_be32(&gur->ddrclkdr, 2); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index fa95886fa3b6..238b9637badd 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -232,7 +232,7 @@ int board_init(void) gpmc_init(); #if defined(CONFIG_CMD_ONENAND) enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], - CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); + CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M); #endif /* Enable the clks & power */ per_clocks_enable(); diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index 9f21795437a6..c67c107b16c2 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -14,7 +14,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc110_chip_probe;
diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 37e911c430a9..265a2cde4b48 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -13,7 +13,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc210_chip_probe;
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 3d0f7341a371..15044c7d0edf 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -246,7 +246,7 @@ void mem_init(void)
setting.cr = SDRAM_BASE_CONF; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
/* * I write here directly in this register, because this diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 1eee972d49e1..ad44a7c0d28b 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -168,7 +168,7 @@ void sdramc_configure(unsigned int mask) at91_sdram_hw_init(); setting.cr = SDRAM_BASE_CONF | mask; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, diff --git a/board/socrates/law.c b/board/socrates/law.c index 840941b63e50..e4427ecff1bc 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -30,12 +30,12 @@ */
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#if defined(CFG_SYS_FPGA_BASE) + SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ad49999dc28e..61402a554b78 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -34,20 +34,20 @@ phys_size_t fixed_sdram(void) ddr->cs0_config = 0; ddr->sdram_cfg = 0;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; + ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CFG_SYS_DDR_MODE; + ddr->sdram_interval = CFG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL;
asm ("sync;isync;msync"); udelay(1000);
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; + ddr->sdram_cfg = CFG_SYS_DDR_CONFIG; asm ("sync; isync; msync"); udelay(1000);
@@ -62,7 +62,7 @@ phys_size_t fixed_sdram(void) } #endif
-#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index eaba87542e76..9c4dd186fca7 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -83,7 +83,7 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) { set_lbc_or(0, gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); set_lbc_br(0, gd->bd->bi_flashstart | @@ -98,7 +98,7 @@ int misc_init_r (void) /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) { set_lbc_or(1, 0); set_lbc_br(1, 0);
@@ -143,7 +143,7 @@ void local_bus_init (void) sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; - uint lcrr = CONFIG_SYS_LBC_LCRR; + uint lcrr = CFG_SYS_LBC_LCRR;
get_sys_info (&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -204,8 +204,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_FPGA_BASE; - val[i++] = CONFIG_SYS_FPGA_SIZE; + val[i++] = CFG_SYS_FPGA_BASE; + val[i++] = CFG_SYS_FPGA_SIZE;
rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index 1ab403d145e6..631f6c340755 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -14,16 +14,16 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
@@ -33,7 +33,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1),
@@ -53,12 +53,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
-#if defined(CONFIG_SYS_FPGA_BASE) +#if defined(CFG_SYS_FPGA_BASE) /* * TLB 4: 1M Non-cacheable, guarded * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), #endif @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * (0xcbfc0000 256K LIME GDC MMIO) * MMIO is relocatable and could be at 0xcbfc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, + SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1),
@@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1),
@@ -91,11 +91,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index 5426fc4ffd84..429f886771b7 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -77,7 +77,7 @@ int dram_init(void) * DCR * set proper RC as per specification */ - RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; + RC = (CFG_SYS_CPU_CLK / 1000000) >> 1; RC = (RC * 15) >> 4;
/* 0x8000 is the faster option */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 34818736a4f5..1683f780a33b 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -121,7 +121,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* adjust memory start address for LPAE */ if (lpae) { start[0] -= CFG_SYS_SDRAM_BASE; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + start[0] += CFG_SYS_LPAE_SDRAM_BASE; }
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { @@ -175,11 +175,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); initrd_start -= CFG_SYS_SDRAM_BASE; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start += CFG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); initrd_end -= CFG_SYS_SDRAM_BASE; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end += CFG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end);
err = fdt_delprop(blob, nodeoffset, @@ -223,7 +223,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (size) { *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; + CFG_SYS_LPAE_SDRAM_BASE; *reserve_start = __cpu_to_be64(*reserve_start); } else { diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 929668ebaa87..09cbd6bf7198 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -146,7 +146,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
- tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); + tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init);
return 0; } diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index 9d921032eaff..bc7e5c5764f8 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -13,7 +13,7 @@ */ int board_flash_wp_on(void) { - if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) & CONFIG_SYS_PCA953X_NVM_WP) return 1;
@@ -30,7 +30,7 @@ uint get_board_derivative(void) #if defined(CONFIG_MPC85xx) volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; #elif defined(CONFIG_MPC86xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; + volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; #endif
diff --git a/boot/Kconfig b/boot/Kconfig index d5c582ebe8c8..88cdc8aff5a8 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -654,7 +654,7 @@ config SYS_MONITOR_BASE default TEXT_BASE help The physical start address of boot monitor code (which is the same as - CONFIG_TEXT_BASE when linking) and the same as CONFIG_SYS_FLASH_BASE + CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE when booting from flash.
config SPL_SYS_MONITOR_BASE diff --git a/boot/image-board.c b/boot/image-board.c index 8813be544be1..0fd63291d3fc 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -161,8 +161,8 @@ phys_size_t env_get_bootm_mapsize(void) return tmp; }
-#if defined(CONFIG_SYS_BOOTMAPSZ) - return CONFIG_SYS_BOOTMAPSZ; +#if defined(CFG_SYS_BOOTMAPSZ) + return CFG_SYS_BOOTMAPSZ; #else return env_get_bootm_size(); #endif diff --git a/cmd/date.c b/cmd/date.c index 0e2dfbc4fc28..58505e6e1d3e 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -51,10 +51,10 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, } #elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) old_bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); + i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM); #else old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM); + I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM); #endif
switch (argc) { diff --git a/cmd/i2c.c b/cmd/i2c.c index 7b84378f7cd2..da8b4c255555 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -97,19 +97,19 @@ static uint i2c_mm_last_alen; * When multiple buses are present, the list is an array of bus-address * pairs. The following macros take care of this */
-#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) static struct { uchar bus; uchar addr; -} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +} i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM i2c_get_bus_num() #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr #else /* single bus */ -static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +static uchar i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM 0 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) @@ -912,7 +912,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, int j; int addr = -1; int found = 0; -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) int k, skip; unsigned int bus = GET_BUS_NUM; #endif /* NOPROBES */ @@ -932,7 +932,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, if ((0 <= addr) && (j != addr)) continue;
-#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) skip = 0; for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { @@ -955,7 +955,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, } putc ('\n');
-#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) puts ("Excluded chip addresses:"); for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus,k)) @@ -1702,7 +1702,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j;
- for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", @@ -1737,7 +1737,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; - for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", diff --git a/common/board_f.c b/common/board_f.c index aab1130763e3..e027248db56d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -900,9 +900,9 @@ static const init_fnc_t init_sequence_f[] = { post_init_f, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ +#endif /* CFG_SYS_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_POST diff --git a/common/board_r.c b/common/board_r.c index f7fb7df54a03..347bb7f7c02d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -346,7 +346,7 @@ static int initr_flash(void) * NOTE: Maybe we should add some schedule()? XXX */ if (env_get_yesno("flashchecksum") == 1) { - const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE; + const uchar *flash_base = (const uchar *)CFG_SYS_FLASH_BASE;
printf(" CRC: %08X", crc32(0, flash_base, @@ -356,8 +356,8 @@ static int initr_flash(void) putc('\n');
/* update start of FLASH memory */ -#ifdef CONFIG_SYS_FLASH_BASE - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + bd->bi_flashstart = CFG_SYS_FLASH_BASE; #endif /* size of FLASH memory (final value) */ bd->bi_flashsize = flash_size; @@ -370,7 +370,7 @@ static int initr_flash(void) #if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = CONFIG_TEXT_BASE + flash_size; -#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE +#elif CONFIG_SYS_MONITOR_BASE == CFG_SYS_FLASH_BASE bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ #endif return 0; diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp index 8da85539afd1..fc696cf0cee2 100644 --- a/common/spl/Kconfig.nxp +++ b/common/spl/Kconfig.nxp @@ -26,7 +26,7 @@ config SPL_SYS_CCSR_DO_NOT_RELOCATE bool "Ensures that CCSR is not relocated" depends on PPC help - If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a + If this is defined, then CFG_SYS_CCSRBAR_PHYS will be forced to a value that ensures that CCSR is not relocated.
config TPL_SYS_CCSR_DO_NOT_RELOCATE @@ -59,7 +59,7 @@ config SPL_RELOC_TEXT_BASE config SPL_RELOC_STACK hex "Address of the start of the stack SPL will use after relocation." help - If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting + If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START. Starting address of the malloc pool used in SPL. When this option is set the full malloc is used in SPL and it is set up by spl_init() and before that, the simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined. diff --git a/common/spl/spl.c b/common/spl/spl.c index 22d2a0621e1e..1d2e8fda7284 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -43,8 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; DECLARE_BINMAN_MAGIC_SYM;
-#ifndef CONFIG_SYS_UBOOT_START -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#ifndef CFG_SYS_UBOOT_START +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #endif
u32 *boot_params_ptr = NULL; @@ -250,7 +250,7 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->entry_point = u_boot_pos; spl_image->load_addr = u_boot_pos; } else { - spl_image->entry_point = CONFIG_SYS_UBOOT_START; + spl_image->entry_point = CFG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; } spl_image->os = IH_OS_U_BOOT; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c1ed31e367c7..08da7fed88ea 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -828,7 +828,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, }
/* - * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's + * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's * Makefile will set it to 0 and it will end up as the entry point * here. What it actually means is: use the load address. */ diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index eaa95fb9b590..1ef5e4126242 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -20,7 +20,7 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
unsigned long __weak spl_nor_get_uboot_base(void) { - return CONFIG_SYS_UBOOT_BASE; + return CFG_SYS_UBOOT_BASE; }
static int spl_nor_load_image(struct spl_image_info *spl_image, diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index da6742416ed9..2aff025f76ee 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -31,7 +31,7 @@ static int spi_load_image_os(struct spl_image_info *spl_image, int err;
/* Read for a header, parse or error out. */ - spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header), (void *)header);
if (image_get_magic(header) != IH_MAGIC) @@ -41,12 +41,12 @@ static int spi_load_image_os(struct spl_image_info *spl_image, if (err) return err;
- spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, spl_image->size, (void *)spl_image->load_addr);
/* Read device tree. */ - spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, - CONFIG_SYS_SPI_ARGS_SIZE, + spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS, + CFG_SYS_SPI_ARGS_SIZE, (void *)CONFIG_SYS_SPL_ARGS_ADDR);
return 0; diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index fb804f020892..bcac25cd021c 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -31,7 +31,7 @@ int spl_ubi_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_ONENAND_SUPPORT case BOOT_DEVICE_ONENAND: info.read = onenand_spl_read_block; - info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE; + info.peb_size = CFG_SYS_ONENAND_BLOCK_SIZE; break; #endif default: diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 1258d85e63da..77c23ba05978 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -25,6 +25,6 @@ static int spl_xip(struct spl_image_info *spl_image, } #endif return(spl_parse_image_header(spl_image, bootdev, - (const struct legacy_img_hdr *)CONFIG_SYS_UBOOT_BASE)); + (const struct legacy_img_hdr *)CFG_SYS_UBOOT_BASE)); } SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip); diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index 00e64ba0c7d5..0b6d2c53db74 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd) /* this is a weak define that we are overriding */ int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN); }
#endif @@ -70,5 +70,5 @@ and the board definition files needs: /* SD/MMC card */ #define CONFIG_GENERIC_ATMEL_MCI 1 #define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */ -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 +#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9 #define CONFIG_CMD_MMC 1 diff --git a/doc/README.cfi b/doc/README.cfi index ad52850818ff..381857470286 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly: void flash_cmd_reset(flash_info_t *info) { /* - * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and + * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and * needs the Spansion type reset commands. The other flash chip * is located behind a FPGA (Xilinx DS617) and needs the Intel type * reset command. */ - if (info->start[0] == CONFIG_SYS_FLASH_BASE) + if (info->start[0] == CFG_SYS_FLASH_BASE) flash_write_cmd(info, 0, 0, AMD_CMD_RESET); else flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); diff --git a/doc/README.davinci b/doc/README.davinci index 607531af2a8a..326efa0a2d6d 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138 Davinci special defines =======================
-CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode +CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode need a "NOR Boot Configuration Word" stored in the NOR Flash. This define adds this. More Info about this, see: diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 82fea6201d60..767614cbc6d3 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,7 +11,7 @@ Configuration options
CONFIG_USB_OHCI_NEW: enable the new OHCI driver
- CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI + CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers
CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 3c6ebbdb0e6e..bafffe6dc51f 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G
5) Invalidate unproctected TLB Entries @@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 8) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT
@@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "create_init_ram_area" TLB Entry : 15 #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 12) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT diff --git a/doc/README.nand b/doc/README.nand index a3c3ab4b9501..37657512533d 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -134,7 +134,7 @@ Configuration Options: chip.IO_ADDR_R = ...; chip.IO_ADDR_W = ...;
- if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) + if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL)) error out
/* diff --git a/doc/README.serial_multi b/doc/README.serial_multi index c9049fd01d66..0446fe95937a 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -35,7 +35,7 @@ just after switching the console: setenv sout serial_scc; setenv baudrate 38400
After that press 'enter' at the SCC console. Note that baudrates <38400 -are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in +are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in include/configs/lwmon.h).
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 584503eb12e4..770327fea21a 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -112,16 +112,16 @@ CONFIG_M5272: Other options, generally set inside include/configs/<boardname>.h, they may apply to one or more cpu for the ColdFire family:
-CONFIG_SYS_MBAR: +CFG_SYS_MBAR: defines the base address of the MCF5272 configuration registers -CONFIG_SYS_SCR: +CFG_SYS_SCR: defines the contents of the System Configuration Register -CONFIG_SYS_SPR: +CFG_SYS_SPR: defines the contents of the System Protection Register -CONFIG_SYS_MFD: +CFG_SYS_MFD: defines the PLL Multiplication Factor Divider (see table 9-4 of MCF user manual) -CONFIG_SYS_RFD: +CFG_SYS_RFD: defines the PLL Reduce Frequency Devider (see table 9-4 of MCF user manual) CONFIG_SYS_CSx_BASE: @@ -136,9 +136,9 @@ CONFIG_SYS_CSx_RO: if set to 0 chip select x is read/write else chip select is read only CONFIG_SYS_CSx_WS: defines the number of wait states of chip select x -CONFIG_SYS_CACHE_ICACR: +CFG_SYS_CACHE_ICACR: cache-related registers config -CONFIG_SYS_CACHE_DCACR: +CFG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config @@ -162,7 +162,7 @@ CFG_SYS_SDRAM_EMOD: these options are used. CONFIG_MCFUART: defines enabling of ColdFire UART driver -CONFIG_SYS_UART_PORT: +CFG_SYS_UART_PORT: defines the UART port to be used (only a single UART can be actually enabled) -CONFIG_SYS_SBFHDR_SIZE: +CFG_SYS_SBFHDR_SIZE: size of the prepended SBF header, if any diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst index 43665de64f5b..fe1ae210def0 100644 --- a/doc/develop/driver-model/migration.rst +++ b/doc/develop/driver-model/migration.rst @@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015. Maintainers should submit patches switching over to using CONFIG_DM_I2C and other base driver model options in time for inclusion in the 2021.10 release.
-CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER +CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER -------------------------------------------------- Deadline: 2023.01
diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt index 464a85302ecf..273d8fc79688 100644 --- a/doc/device-tree-bindings/video/exynos-dp.txt +++ b/doc/device-tree-bindings/video/exynos-dp.txt @@ -30,9 +30,9 @@ Optional properties: 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), 10(MOBILE_WHITEBAR_64) samsung,h-sync-polarity: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,v-sync-polarity: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,interlaced: Progressive if 0, else Interlaced samsung,color-space: input video data format COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index b022f6163f1a..bff0cecfcfbc 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -23,15 +23,15 @@ Board(panel specific): samsung,vl-height: Height of display area in mm
samsung,vl-clkp: Clock polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-oep: Output Enable polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-hsp: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-vsp: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-dp: Data polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-cmd-allow-len: Wait end of frame samsung,winid: Window number on which data is to be displayed diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt index ea0e144cedcf..6c8c2e594fb7 100644 --- a/doc/imx/common/imx5.txt +++ b/doc/imx/common/imx5.txt @@ -16,7 +16,7 @@ i.MX5x SoCs. of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure.
-1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. +1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. This option should be enabled for boards having a SYS_ON_OFF_CTL signal connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the reference designs. diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 15897f63dd9a..83f210d2d058 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -162,7 +162,7 @@ bootm_low for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and + kernel -- see the description of CFG_SYS_BOOTMAPSZ and bootm_mapsize.
bootm_mapsize @@ -170,7 +170,7 @@ bootm_mapsize This variable is given as a hexadecimal number and it defines the size of the memory region starting at base address bootm_low that is accessible by the Linux kernel - during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used + during early boot. If unset, CFG_SYS_BOOTMAPSZ is used as the default value if it is defined, and bootm_size is used otherwise.
@@ -228,7 +228,7 @@ initrd_high is usually what you want since it allows for maximum initrd size. If for some reason you want to make sure that the initrd image is loaded below the - CONFIG_SYS_BOOTMAPSZ limit, you can set this environment + CFG_SYS_BOOTMAPSZ limit, you can set this environment variable to a value of "no" or "off" or "0". Alternatively, you can set it to a maximum upper address to use (U-Boot will still check that it diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 8d6424c9da10..570252d186a4 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -83,7 +83,7 @@ config BOOTCOUNT_I2C bool "Boot counter on I2C device" help Enable support for the bootcounter on an i2c (like RTC) device. - CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CFG_SYS_I2C_RTC_ADDR = i2c chip address CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for the bootcounter.
diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c index 496741d63f78..b3ac67ea35dd 100644 --- a/drivers/bootcount/bootcount_i2c.c +++ b/drivers/bootcount/bootcount_i2c.c @@ -17,7 +17,7 @@ void bootcount_store(ulong a)
buf[0] = BC_MAGIC; buf[1] = (a & 0xff); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) puts("Error writing bootcount\n"); @@ -28,7 +28,7 @@ ulong bootcount_load(void) unsigned char buf[3]; int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) { puts("Error loading bootcount\n"); diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index b2bfb529cc80..2fdc2fbd5547 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -150,7 +150,7 @@ static int at91_slow_clk_enable(struct clk *clk)
static ulong at91_slow_clk_get_rate(struct clk *clk) { - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; }
static struct clk_ops at91_slow_clk_ops = { diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index b79e99b63de8..8fde77c23ee0 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -14,7 +14,7 @@ config SPL_DM help Enable driver model in SPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -27,7 +27,7 @@ config TPL_DM help Enable driver model in TPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -42,7 +42,7 @@ config VPL_DM help Enable driver model in VPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
config DM_WARN diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 4975dbb821e1..cd332718b640 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -22,7 +22,7 @@
/* * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view - * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff @@ -32,7 +32,7 @@ #ifdef CONFIG_MPC83xx #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE #endif #endif
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index a1ff47035be3..ca49ee40a71d 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -24,8 +24,8 @@ #define CONFIG_FPGA_DELAY() #endif
-#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif
static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -138,7 +138,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index f264ff8c0ecd..3eed461e1e5c 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -22,8 +22,8 @@ #define CONFIG_FPGA_DELAY() #endif
-#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -130,7 +130,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer(0); /* get current time */ do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index f72dfdec94ea..57a4532f736e 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -21,8 +21,8 @@ #define CONFIG_FPGA_DELAY() #endif
-#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif
static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -149,7 +149,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -182,7 +182,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -214,7 +214,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -333,7 +333,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); return FPGA_FAIL; } @@ -347,7 +347,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); return FPGA_FAIL; } @@ -404,7 +404,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index b7a063a95fc8..fdec89bb815f 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -26,8 +26,8 @@ #define CONFIG_FPGA_DELAY() #endif
-#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif
static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -154,7 +154,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -187,7 +187,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -221,7 +221,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -340,7 +340,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -356,7 +356,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -423,7 +423,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 0d536f0d0446..8871deaea6f6 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -49,8 +49,8 @@ * which yields 11.44 mS. So let's make it bigger in order to handle * an XC2V1000, if anyone can ever get ahold of one. */ -#ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ +#ifndef CFG_SYS_FPGA_WAIT_INIT +#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif
/* @@ -58,15 +58,15 @@ * This is normally not necessary since for most reasonable configuration * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ -#ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ +#ifndef CFG_SYS_FPGA_WAIT_BUSY +#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif
/* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ -#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ +#ifndef CFG_SYS_FPGA_WAIT_CONFIG +#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) udelay(10); ts = get_timer(0); do { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) ts = get_timer(0); do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, break; }
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) { printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG); (*fn->abort)(cookie); ret_val = FPGA_FAIL; break; @@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer(0); while ((*fn->busy)(cookie)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) { printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", __func__, __LINE__, - CONFIG_SYS_FPGA_WAIT_BUSY); + CFG_SYS_FPGA_WAIT_BUSY); (*fn->abort)(cookie); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0c83df46da41..53dd780a6ca2 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,8 +36,8 @@ #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
-#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME @@ -232,7 +232,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to clear\n", __func__); return FPGA_FAIL; @@ -246,7 +246,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) ts = get_timer(0); while (!(readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to set\n", __func__); return FPGA_FAIL; @@ -400,7 +400,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -484,7 +484,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -561,7 +561,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 2fd2996798ce..b5ed35256ee7 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -14,8 +14,8 @@ #include <pca953x.h>
/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_PCA953X_ADDR -#define CONFIG_SYS_I2C_PCA953X_ADDR (~0) +#ifndef CFG_SYS_I2C_PCA953X_ADDR +#define CFG_SYS_I2C_PCA953X_ADDR (~0) #endif
enum { @@ -26,14 +26,14 @@ enum { PCA953X_CMD_INVERT, };
-#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH +#ifdef CFG_SYS_I2C_PCA953X_WIDTH struct pca953x_chip_ngpio { uint8_t chip; uint8_t ngpio; };
static struct pca953x_chip_ngpio pca953x_chip_ngpios[] = - CONFIG_SYS_I2C_PCA953X_WIDTH; + CFG_SYS_I2C_PCA953X_WIDTH;
/* * Determine the number of GPIO pins supported. If we don't know we assume @@ -204,7 +204,7 @@ static struct cmd_tbl cmd_pca953x[] = { static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; + static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR; int ret = CMD_RET_USAGE, val; ulong ul_arg2 = 0; ulong ul_arg3 = 0; diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 7f67f96b0ec0..b07496e6e49c 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -52,7 +52,7 @@ static int tca642x_reg_write(uchar chip, uint8_t addr, int ret;
org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { printf("Could not read before writing\n"); @@ -76,7 +76,7 @@ static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) int ret = 0;
org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { ret = -1; goto error; @@ -242,7 +242,7 @@ static struct cmd_tbl cmd_tca642x[] = { static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; + static uchar chip = CFG_SYS_I2C_TCA642X_ADDR; int ret = CMD_RET_USAGE, val; int gpio_bank = 0; uint8_t bank_shift; diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index ae177227dea3..25ef937dc0b3 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -91,7 +91,7 @@ static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
psc = 2; /* SCLL + SCLH */ - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index edbcd83b6469..187db92b75f6 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M68K -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CFG_SYS_MBAR #endif
#if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index c3f6a1251f15..7f65db23205a 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -35,7 +35,7 @@ struct i2c_adapter *i2c_get_adapter(int index)
#if !defined(CONFIG_SYS_I2C_DIRECT_BUS) struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = - CONFIG_SYS_I2C_BUSES; + CFG_SYS_I2C_BUSES; #endif
DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +114,7 @@ static int i2c_mux_set_all(void) /* Connect requested bus if behind muxes */ if (i2c_bus_tmp->next_hop[0].chip != 0) { /* Set all muxes along the path to that bus */ - for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) { + for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) { int ret;
if (i2c_bus_tmp->next_hop[i].chip == 0) @@ -143,7 +143,7 @@ static int i2c_mux_disconnect_all(void) /* Disconnect current bus (turn off muxes if any) */ if ((i2c_bus_tmp->next_hop[0].chip != 0) && (I2C_ADAP->init_done != 0)) { - i = CONFIG_SYS_I2C_MAX_HOPS; + i = CFG_SYS_I2C_MAX_HOPS; do { uint8_t chip; int ret; diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c index 4edcba29110e..b9b0ff1c39e2 100644 --- a/drivers/i2c/kona_i2c.c +++ b/drivers/i2c/kona_i2c.c @@ -129,7 +129,7 @@ struct bcm_kona_i2c_dev { #define DEF_DEVICE(num) \ {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
-static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { #ifdef CONFIG_SYS_I2C_BASE0 DEF_DEVICE(0), #endif diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index f48a4f25aae6..a9c7d6e1bc26 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* CONFIG_DM_I2C */
/* - * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to + * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to * always have it. */ #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI) @@ -427,9 +427,9 @@ static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) static uint twsi_calc_freq(const int n, const int m) { #ifdef CONFIG_ARCH_SUNXI - return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n)); #else - return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n)); #endif }
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f80ff5383bc3..9a1599dcd91e 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -39,8 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define VF610_I2C_REGSHIFT 0
#define I2C_EARLY_INIT_INDEX 0 -#ifdef CONFIG_SYS_I2C_IFDR_DIV -#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV +#ifdef CFG_SYS_I2C_IFDR_DIV +#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV #else #define I2C_IFDR_DIV_CONSERVATIVE 0x7e #endif diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 8fdaacd5e04c..58b00587363d 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -12,37 +12,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "cs0", -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - CONFIG_SYS_CSPR0, -#ifdef CONFIG_SYS_CSPR0_EXT - CONFIG_SYS_CSPR0_EXT, +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + CFG_SYS_CSPR0, +#ifdef CFG_SYS_CSPR0_EXT + CFG_SYS_CSPR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0 - CONFIG_SYS_AMASK0, +#ifdef CFG_SYS_AMASK0 + CFG_SYS_AMASK0, #else 0, #endif - CONFIG_SYS_CSOR0, + CFG_SYS_CSOR0, { - CONFIG_SYS_CS0_FTIM0, - CONFIG_SYS_CS0_FTIM1, - CONFIG_SYS_CS0_FTIM2, - CONFIG_SYS_CS0_FTIM3, + CFG_SYS_CS0_FTIM0, + CFG_SYS_CS0_FTIM1, + CFG_SYS_CS0_FTIM2, + CFG_SYS_CS0_FTIM3, }, -#ifdef CONFIG_SYS_CSOR0_EXT - CONFIG_SYS_CSOR0_EXT, +#ifdef CFG_SYS_CSOR0_EXT + CFG_SYS_CSOR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR0_FINAL - CONFIG_SYS_CSPR0_FINAL, +#ifdef CFG_SYS_CSPR0_FINAL + CFG_SYS_CSPR0_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - CONFIG_SYS_AMASK0_FINAL, +#ifdef CFG_SYS_AMASK0_FINAL + CFG_SYS_AMASK0_FINAL, #else 0, #endif @@ -52,37 +52,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 { "cs1", -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - CONFIG_SYS_CSPR1, -#ifdef CONFIG_SYS_CSPR1_EXT - CONFIG_SYS_CSPR1_EXT, +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + CFG_SYS_CSPR1, +#ifdef CFG_SYS_CSPR1_EXT + CFG_SYS_CSPR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1 - CONFIG_SYS_AMASK1, +#ifdef CFG_SYS_AMASK1 + CFG_SYS_AMASK1, #else 0, #endif - CONFIG_SYS_CSOR1, + CFG_SYS_CSOR1, { - CONFIG_SYS_CS1_FTIM0, - CONFIG_SYS_CS1_FTIM1, - CONFIG_SYS_CS1_FTIM2, - CONFIG_SYS_CS1_FTIM3, + CFG_SYS_CS1_FTIM0, + CFG_SYS_CS1_FTIM1, + CFG_SYS_CS1_FTIM2, + CFG_SYS_CS1_FTIM3, }, -#ifdef CONFIG_SYS_CSOR1_EXT - CONFIG_SYS_CSOR1_EXT, +#ifdef CFG_SYS_CSOR1_EXT + CFG_SYS_CSOR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - CONFIG_SYS_CSPR1_FINAL, +#ifdef CFG_SYS_CSPR1_FINAL + CFG_SYS_CSPR1_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - CONFIG_SYS_AMASK1_FINAL, +#ifdef CFG_SYS_AMASK1_FINAL + CFG_SYS_AMASK1_FINAL, #else 0, #endif @@ -93,37 +93,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 { "cs2", -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - CONFIG_SYS_CSPR2, -#ifdef CONFIG_SYS_CSPR2_EXT - CONFIG_SYS_CSPR2_EXT, +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + CFG_SYS_CSPR2, +#ifdef CFG_SYS_CSPR2_EXT + CFG_SYS_CSPR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2 - CONFIG_SYS_AMASK2, +#ifdef CFG_SYS_AMASK2 + CFG_SYS_AMASK2, #else 0, #endif - CONFIG_SYS_CSOR2, + CFG_SYS_CSOR2, { - CONFIG_SYS_CS2_FTIM0, - CONFIG_SYS_CS2_FTIM1, - CONFIG_SYS_CS2_FTIM2, - CONFIG_SYS_CS2_FTIM3, + CFG_SYS_CS2_FTIM0, + CFG_SYS_CS2_FTIM1, + CFG_SYS_CS2_FTIM2, + CFG_SYS_CS2_FTIM3, }, -#ifdef CONFIG_SYS_CSOR2_EXT - CONFIG_SYS_CSOR2_EXT, +#ifdef CFG_SYS_CSOR2_EXT + CFG_SYS_CSOR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - CONFIG_SYS_CSPR2_FINAL, +#ifdef CFG_SYS_CSPR2_FINAL + CFG_SYS_CSPR2_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - CONFIG_SYS_AMASK2_FINAL, +#ifdef CFG_SYS_AMASK2_FINAL + CFG_SYS_AMASK2_FINAL, #else 0, #endif @@ -134,37 +134,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 { "cs3", -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - CONFIG_SYS_CSPR3, -#ifdef CONFIG_SYS_CSPR3_EXT - CONFIG_SYS_CSPR3_EXT, +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + CFG_SYS_CSPR3, +#ifdef CFG_SYS_CSPR3_EXT + CFG_SYS_CSPR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3 - CONFIG_SYS_AMASK3, +#ifdef CFG_SYS_AMASK3 + CFG_SYS_AMASK3, #else 0, #endif - CONFIG_SYS_CSOR3, + CFG_SYS_CSOR3, { - CONFIG_SYS_CS3_FTIM0, - CONFIG_SYS_CS3_FTIM1, - CONFIG_SYS_CS3_FTIM2, - CONFIG_SYS_CS3_FTIM3, + CFG_SYS_CS3_FTIM0, + CFG_SYS_CS3_FTIM1, + CFG_SYS_CS3_FTIM2, + CFG_SYS_CS3_FTIM3, }, -#ifdef CONFIG_SYS_CSOR3_EXT - CONFIG_SYS_CSOR3_EXT, +#ifdef CFG_SYS_CSOR3_EXT + CFG_SYS_CSOR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - CONFIG_SYS_CSPR3_FINAL, +#ifdef CFG_SYS_CSPR3_FINAL + CFG_SYS_CSPR3_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - CONFIG_SYS_AMASK3_FINAL, +#ifdef CFG_SYS_AMASK3_FINAL + CFG_SYS_AMASK3_FINAL, #else 0, #endif @@ -175,37 +175,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 { "cs4", -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - CONFIG_SYS_CSPR4, -#ifdef CONFIG_SYS_CSPR4_EXT - CONFIG_SYS_CSPR4_EXT, +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + CFG_SYS_CSPR4, +#ifdef CFG_SYS_CSPR4_EXT + CFG_SYS_CSPR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4 - CONFIG_SYS_AMASK4, +#ifdef CFG_SYS_AMASK4 + CFG_SYS_AMASK4, #else 0, #endif - CONFIG_SYS_CSOR4, + CFG_SYS_CSOR4, { - CONFIG_SYS_CS4_FTIM0, - CONFIG_SYS_CS4_FTIM1, - CONFIG_SYS_CS4_FTIM2, - CONFIG_SYS_CS4_FTIM3, + CFG_SYS_CS4_FTIM0, + CFG_SYS_CS4_FTIM1, + CFG_SYS_CS4_FTIM2, + CFG_SYS_CS4_FTIM3, }, -#ifdef CONFIG_SYS_CSOR4_EXT - CONFIG_SYS_CSOR4_EXT, +#ifdef CFG_SYS_CSOR4_EXT + CFG_SYS_CSOR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR4_FINAL - CONFIG_SYS_CSPR4_FINAL, +#ifdef CFG_SYS_CSPR4_FINAL + CFG_SYS_CSPR4_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4_FINAL - CONFIG_SYS_AMASK4_FINAL, +#ifdef CFG_SYS_AMASK4_FINAL + CFG_SYS_AMASK4_FINAL, #else 0, #endif @@ -257,37 +257,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 { "cs6", -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - CONFIG_SYS_CSPR6, -#ifdef CONFIG_SYS_CSPR6_EXT - CONFIG_SYS_CSPR6_EXT, +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + CFG_SYS_CSPR6, +#ifdef CFG_SYS_CSPR6_EXT + CFG_SYS_CSPR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6 - CONFIG_SYS_AMASK6, +#ifdef CFG_SYS_AMASK6 + CFG_SYS_AMASK6, #else 0, #endif - CONFIG_SYS_CSOR6, + CFG_SYS_CSOR6, { - CONFIG_SYS_CS6_FTIM0, - CONFIG_SYS_CS6_FTIM1, - CONFIG_SYS_CS6_FTIM2, - CONFIG_SYS_CS6_FTIM3, + CFG_SYS_CS6_FTIM0, + CFG_SYS_CS6_FTIM1, + CFG_SYS_CS6_FTIM2, + CFG_SYS_CS6_FTIM3, }, -#ifdef CONFIG_SYS_CSOR6_EXT - CONFIG_SYS_CSOR6_EXT, +#ifdef CFG_SYS_CSOR6_EXT + CFG_SYS_CSOR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR6_FINAL - CONFIG_SYS_CSPR6_FINAL, +#ifdef CFG_SYS_CSPR6_FINAL + CFG_SYS_CSPR6_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6_FINAL - CONFIG_SYS_AMASK6_FINAL, +#ifdef CFG_SYS_AMASK6_FINAL + CFG_SYS_AMASK6_FINAL, #else 0, #endif @@ -298,37 +298,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 { "cs7", -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - CONFIG_SYS_CSPR7, -#ifdef CONFIG_SYS_CSPR7_EXT - CONFIG_SYS_CSPR7_EXT, +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + CFG_SYS_CSPR7, +#ifdef CFG_SYS_CSPR7_EXT + CFG_SYS_CSPR7_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7 - CONFIG_SYS_AMASK7, +#ifdef CFG_SYS_AMASK7 + CFG_SYS_AMASK7, #else 0, #endif - CONFIG_SYS_CSOR7, -#ifdef CONFIG_SYS_CSOR7_EXT - CONFIG_SYS_CSOR7_EXT, + CFG_SYS_CSOR7, +#ifdef CFG_SYS_CSOR7_EXT + CFG_SYS_CSOR7_EXT, #else 0, #endif { - CONFIG_SYS_CS7_FTIM0, - CONFIG_SYS_CS7_FTIM1, - CONFIG_SYS_CS7_FTIM2, - CONFIG_SYS_CS7_FTIM3, + CFG_SYS_CS7_FTIM0, + CFG_SYS_CS7_FTIM1, + CFG_SYS_CS7_FTIM2, + CFG_SYS_CS7_FTIM3, }, -#ifdef CONFIG_SYS_CSPR7_FINAL - CONFIG_SYS_CSPR7_FINAL, +#ifdef CFG_SYS_CSPR7_FINAL + CFG_SYS_CSPR7_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7_FINAL - CONFIG_SYS_AMASK7_FINAL, +#ifdef CFG_SYS_AMASK7_FINAL + CFG_SYS_AMASK7_FINAL, #else 0, #endif @@ -412,91 +412,91 @@ void init_final_memctl_regs(void) #else void init_early_memctl_regs(void) { -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3);
#ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#ifdef CFG_SYS_CSPR0_EXT + set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT); #endif -#ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#ifdef CFG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT); #endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0); #endif #endif
-#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); +#ifdef CFG_SYS_CSPR1_EXT + set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT); #endif -#ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#ifdef CFG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT); #endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3);
- set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); + set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1); #endif
-#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); +#ifdef CFG_SYS_CSPR2_EXT + set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT); #endif -#ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#ifdef CFG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT); #endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3);
- set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); + set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2); #endif
-#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); +#ifdef CFG_SYS_CSPR3_EXT + set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT); #endif -#ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#ifdef CFG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT); #endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3);
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3); #endif
-#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); +#ifdef CFG_SYS_CSPR4_EXT + set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT); #endif -#ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#ifdef CFG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT); #endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0); + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1); + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2); + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3);
- set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); + set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4); + set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4); + set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4); #endif
#ifdef CONFIG_SYS_CSPR5_EXT @@ -516,66 +516,66 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); #endif
-#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); +#ifdef CFG_SYS_CSPR6_EXT + set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT); #endif -#ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#ifdef CFG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT); #endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0); + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1); + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2); + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3);
- set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); + set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6); + set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6); + set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6); #endif
-#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); +#ifdef CFG_SYS_CSPR7_EXT + set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT); #endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#ifdef CFG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT); #endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0); + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1); + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2); + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3);
- set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); + set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7); + set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7); + set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7); #endif }
void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#ifdef CFG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL); #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); +#ifdef CFG_SYS_AMASK0_FINAL + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); +#ifdef CFG_SYS_CSPR1_FINAL + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL); #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); +#ifdef CFG_SYS_AMASK1_FINAL + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL); #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); +#ifdef CFG_SYS_CSPR2_FINAL + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL); #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); +#ifdef CFG_SYS_AMASK2_FINAL + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); +#ifdef CFG_SYS_CSPR3_FINAL + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL); #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); +#ifdef CFG_SYS_AMASK3_FINAL + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); #endif } #endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 9c4b4d7e46dd..6b831281e96f 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -20,25 +20,25 @@ #endif #include <fsl_qbman.h>
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) -#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) +#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE) +#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE) void setup_qbman_portals(void) { - void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + - CONFIG_SYS_BMAN_SWP_ISDR_REG; - void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + - CONFIG_SYS_QMAN_SWP_ISDR_REG; + void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE + + CFG_SYS_BMAN_SWP_ISDR_REG; + void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE + + CFG_SYS_QMAN_SWP_ISDR_REG; struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ #ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); + out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32)); #endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS); #ifdef CONFIG_FSL_CORENET int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; u16 dliodn = qp_info[i].dliodn; @@ -53,7 +53,7 @@ void setup_qbman_portals(void) #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 ficid = qp_info[i].ficid; u16 dicid = qp_info[i].dicid; @@ -68,10 +68,10 @@ void setup_qbman_portals(void) #endif
/* Change default state of BMan ISDR portals to all 1s */ - inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, - CONFIG_SYS_BMAN_SP_CINH_SIZE); - inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, - CONFIG_SYS_QMAN_SP_CINH_SIZE); + inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, + CFG_SYS_BMAN_SP_CINH_SIZE); + inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, + CFG_SYS_QMAN_SP_CINH_SIZE); }
void inhibit_portals(void __iomem *addr, int max_portals, diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index 321bd27fd325..3597ee22242c 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -10,7 +10,7 @@ static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; }
@@ -19,7 +19,7 @@ static int set_sec_mon_state_non_sec(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR);
sts = get_sec_mon_state();
@@ -120,7 +120,7 @@ static int set_sec_mon_state_soft_fail(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR);
printf("SEC_MON state transitioning to Soft Fail.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index aa00d7e2014d..6d7c0cff22a5 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -9,7 +9,7 @@ #include <mmc.h> #include <malloc.h>
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS extern uchar mmc_u_boot_offs[]; #endif
@@ -97,7 +97,7 @@ void __noreturn mmc_boot(void) }
#ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + offset = CFG_SYS_MMC_U_BOOT_OFFS; #else sector = 0; again: @@ -153,16 +153,16 @@ again: val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE; #else - offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + offset += CFG_SYS_MMC_U_BOOT_OFFS; #endif #endif /* * Load U-Boot image from mmc into RAM */ - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; + code_len = CFG_SYS_MMC_U_BOOT_SIZE; blk_start = offset / mmc->read_bl_len; blk_off = offset % mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; @@ -176,7 +176,7 @@ again: blk_start++; } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (uchar *)CFG_SYS_MMC_U_BOOT_DST + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); @@ -189,18 +189,18 @@ again: * after SDHC DMA transfer. */ if (blk_off) - memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST, tmp_buf + blk_off, mmc->read_bl_len - blk_off);
/* * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE);
/* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + uboot = (void *)CFG_SYS_MMC_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 607a22368cba..d91819acfd7f 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -24,8 +24,8 @@ #include <asm/arch/hardware.h> #include "atmel_mci.h"
-#ifndef CONFIG_SYS_MMC_CLK_OD -# define CONFIG_SYS_MMC_CLK_OD 150000 +#ifndef CFG_SYS_MMC_CLK_OD +# define CFG_SYS_MMC_CLK_OD 150000 #endif
#define MMC_DEFAULT_BLKLEN 512 @@ -448,9 +448,9 @@ static int mci_init(struct mmc *mmc)
/* Set default clocks and blocklen */ #ifdef CONFIG_DM_MMC - mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #else - mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #endif
return 0; diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index b2d0fac96368..3ce7cbf71f80 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -761,7 +761,7 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) struct mmc *mmc; struct sh_sdhi_host *host = NULL;
- if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL) + if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL) return -ENODEV;
host = malloc(sizeof(struct sh_sdhi_host)); diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index d34d8ee97671..c1cdd2cbc3e2 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -53,7 +53,7 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between * reading and writing ... (yes there is such a Hardware). */
@@ -119,14 +119,14 @@ phys_addr_t cfi_flash_bank_addr(int i) #else __weak phys_addr_t cfi_flash_bank_addr(int i) { - return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; + return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i]; } #endif
__weak unsigned long cfi_flash_bank_size(int i) { -#ifdef CONFIG_SYS_FLASH_BANKS_SIZES - return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; +#ifdef CFG_SYS_FLASH_BANKS_SIZES + return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i]; #else return 0; #endif @@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr) */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ (defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)) + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE)) static flash_info_t *flash_get_info(ulong base) { int i; @@ -227,7 +227,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) int i; int cword_offset; int cp_offset; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) u32 cmd_le = cpu_to_le32(cmd); #endif uchar val; @@ -235,7 +235,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
for (i = info->portwidth; i > 0; i--) { cword_offset = (info->portwidth - i) % info->chipwidth; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) cp_offset = info->portwidth - i; val = *((uchar *)&cmd_le + cword_offset); #else @@ -292,7 +292,7 @@ static inline uchar flash_read_uchar(flash_info_t *info, uint offset) uchar retval;
cp = flash_map(info, 0, offset); -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = flash_read8(cp); #else retval = flash_read8(cp + info->portwidth - 1); @@ -335,7 +335,7 @@ static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, for (x = 0; x < 4 * info->portwidth; x++) debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); #endif -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = ((flash_read8(addr) << 16) | (flash_read8(addr + info->portwidth) << 24) | (flash_read8(addr + 2 * info->portwidth)) | @@ -580,7 +580,7 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector, #endif
/* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -673,7 +673,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, #endif
/* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -713,7 +713,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, */ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) { -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -724,7 +724,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) cword->w8 = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w16 = (cword->w16 >> 8) | w; @@ -733,7 +733,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->w32 = (cword->w32 >> 8) | l; @@ -742,7 +742,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->w64 = (cword->w64 >> 8) | ll; @@ -2359,7 +2359,7 @@ static void flash_protect_default(void)
/* Monitor protection ON by default */ #if defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \ (!defined(CONFIG_MONITOR_IS_IN_RAM)) flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 59de3256405b..18abd7544184 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -780,10 +780,10 @@ static void fsl_ifc_ctrl_init(void) ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
/* clear event registers */ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U); diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 7d4b77dd11d4..3b464ce10ce9 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -54,14 +54,14 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat,
static inline struct fsl_ifc_runtime *runtime_regs_address(void) { - struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL}; + struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL}; int ver = 0;
ver = ifc_in32(®s.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
return regs.rregs; } @@ -108,7 +108,7 @@ static inline int bad_block(uchar *marker, int port_size)
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { - struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR; struct fsl_ifc_runtime *ifc = NULL; uchar *buf = (uchar *)CFG_SYS_NAND_BASE; int page_size; diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 5bc5301d6349..a884c65d18b8 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -84,8 +84,8 @@ struct lpc32xx_nand_mlc_registers { static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
-#if !defined(CONFIG_SYS_MAX_NAND_CHIPS) -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#if !defined(CFG_SYS_MAX_NAND_CHIPS) +#define CFG_SYS_MAX_NAND_CHIPS 1 #endif
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) @@ -586,7 +586,7 @@ void board_nand_init(void) lpc32xx_nand_init();
/* identify chip */ - ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL); + ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL); if (ret) { pr_err("nand_scan_ident returned %i", ret); return; diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index ab6f1a8be3ee..2699958a5de2 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -49,12 +49,12 @@ static inline int onenand_bufferram_address(int block)
static inline uint16_t onenand_readw(uint32_t addr) { - return readw(CONFIG_SYS_ONENAND_BASE + addr); + return readw(CFG_SYS_ONENAND_BASE + addr); }
static inline void onenand_writew(uint16_t value, uint32_t addr) { - writew(value, CONFIG_SYS_ONENAND_BASE + addr); + writew(value, CFG_SYS_ONENAND_BASE + addr); }
static enum onenand_spl_pagesize onenand_spl_get_geometry(void) @@ -82,7 +82,7 @@ static enum onenand_spl_pagesize onenand_spl_get_geometry(void) static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf, enum onenand_spl_pagesize pagesize) { - const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM; + const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM; uint32_t offset;
onenand_writew(onenand_block_address(block), diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 3a8c7b867eba..04791df69bb0 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -35,7 +35,7 @@ void onenand_init(void) /* It's used for some board init required */ err = onenand_board_init(&onenand_mtd); #else - onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; + onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE; #endif
if (!err && !(onenand_scan(&onenand_mtd, 1))) { diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 5c41d7558c24..dfc35d6eabf0 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -49,8 +49,8 @@ void fsl_spi_boot(void) }
#ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; - code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; + offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE; #else /* * Load U-Boot image from SPI flash into RAM @@ -66,7 +66,7 @@ void fsl_spi_boot(void) flash->page_size, (void *)buf); offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); /* Skip spl code */ - offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS; /* Get the code size from offset 0x48 */ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ @@ -76,7 +76,7 @@ void fsl_spi_boot(void) printf("Loading second stage boot loader "); while (copy_len <= code_len) { spi_flash_read(flash, offset + copy_len, 0x2000, - (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST + copy_len)); copy_len = copy_len + 0x2000; putc('.'); @@ -85,7 +85,7 @@ void fsl_spi_boot(void) /* * Jump to U-Boot image */ - flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len); - uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START; + flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len); + uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index 95afa2d6bc72..4523344ba6b0 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -39,7 +39,7 @@ unsigned long flash_init(void) for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_STM32; flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20); + flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20); flash_info[i].size = sect_sz_kb[0]; for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) { flash_info[i].start[j] = flash_info[i].start[j - 1] diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index c23e0c07702f..c8381cc7133c 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -128,7 +128,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */ - out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + out_be32(®s->tbipa, CFG_SYS_TBIPA_VALUE); #endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 1d3b7aa05836..c476cb31200a 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -67,9 +67,9 @@ static void fm_init_muram(int fm_idx, void *reg) void *base = reg;
muram[fm_idx].base = base; - muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE; muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE; - muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE; }
/* diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 8443cbb6b65f..618c1bccbe3f 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -244,9 +244,9 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off; uint32_t ph; - phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; + phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset; #ifndef CONFIG_SYS_FMAN_V3 - u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + + u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS + CFG_SYS_FSL_FM1_DTSEC1_OFFSET; #endif
diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index 8be38e11a843..ff998d49dc4c 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -256,12 +256,12 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; - s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE); + s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE); if (!s->cena) { printf("Could not allocate page for cena shadow\n"); return -1; } - memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE); + memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE);
#ifdef QBMAN_CHECKING /* We should never be asked to initialise for a portal that isn't in diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 68833f9ddd92..69da465eaabc 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -54,7 +54,7 @@ static int mc_memset_resv_ram; static struct mc_version mc_ver_info; static int mc_boot_status = -1; static int mc_dpl_applied = -1; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET static int mc_aiop_applied = -1; #endif struct fsl_mc_io *root_mc_io = NULL; @@ -500,13 +500,13 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) int dpc_size; #endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
- mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; + mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" #endif
/* @@ -531,7 +531,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) }
dpc_size = fdt_totalsize(dpc_fdt_hdr); - if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { + if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", dpc_size); return -EINVAL; @@ -576,13 +576,13 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) int dpl_size; #endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
- mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; + mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" #endif
/* @@ -603,7 +603,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) }
dpl_size = fdt_totalsize(dpl_fdt_hdr); - if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", dpl_size); return -EINVAL; @@ -624,7 +624,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) */ static unsigned long get_mc_boot_timeout_ms(void) { - unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
@@ -636,14 +636,14 @@ static unsigned long get_mc_boot_timeout_ms(void) "' environment variable: %lu\n", timeout_ms);
- timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS; } }
return timeout_ms; }
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
__weak bool soc_has_aiop(void) { @@ -666,12 +666,12 @@ static int load_mc_aiop_img(u64 aiop_fw_addr)
#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + - CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #else aiop_img = (void *)aiop_fw_addr; mc_copy_image("MC AIOP image", - (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, - mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, + mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #endif mc_aiop_applied = 0;
@@ -896,7 +896,7 @@ int get_mc_boot_status(void) return mc_boot_status; }
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void) { return mc_aiop_applied; @@ -938,14 +938,14 @@ u64 mc_get_dram_addr(void) */ unsigned long mc_get_dram_block_size(void) { - unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
if (dram_block_size_env_var) { dram_block_size = hextoul(dram_block_size_env_var, NULL);
- if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { + if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { printf("fsl-mc: WARNING: Invalid value for '" MC_MEM_SIZE_ENV_VAR "' environment variable: %lu\n", @@ -1838,7 +1838,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, case 's': { char sub_cmd; u64 mc_fw_addr, mc_dpc_addr; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET u64 aiop_fw_addr; #endif if (argc < 3) @@ -1864,7 +1864,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, err = mc_init_object(); break;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET case 'a': if (argc < 4) goto usage; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 6825f9e27c06..cc61a1074038 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -43,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; static void init_eth_info(struct fec_info_dma *info) { /* setup Receive and Transmit buffer descriptor */ -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp;
if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH;
@@ -59,7 +59,7 @@ static void init_eth_info(struct fec_info_dma *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -67,7 +67,7 @@ static void init_eth_info(struct fec_info_dma *info) (PKTBUFSRX * sizeof(cbd_t))); info->txbd = (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); info->txbuf = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif @@ -283,15 +283,15 @@ static int fec_init(struct udevice *dev)
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) * Settings: Last, Tx CRC */ - for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { + for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) { info->txbd[i].cbd_sc = 0; info->txbd[i].cbd_datlen = 0; info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); } - info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
info->used_tbd_idx = 0; - info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER; + info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */ fecp->rfcr = 0x0c000000; @@ -352,7 +352,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
/* process all the consumed TBDs */ - while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) { + while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) { p_used_tbd = &info->txbd[info->used_tbd_idx]; if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { #ifdef ET_DEBUG @@ -363,7 +363,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) }
/* clean this buffer descriptor */ - if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) + if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1)) p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; else p_used_tbd->cbd_sc = 0; @@ -371,7 +371,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) /* update some indeces for a correct handling of TBD ring */ info->clean_tbd_num++; info->used_tbd_idx = (info->used_tbd_idx + 1) - % CONFIG_SYS_TX_ETH_BUFFER; + % CFG_SYS_TX_ETH_BUFFER; }
/* Check for valid length of data. */ @@ -389,7 +389,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) p_tbd->cbd_datlen = length; p_tbd->cbd_bufaddr = (u32)packet; p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER; + info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
/* Enable DMA transmit task */ MCD_continDma(info->tx_task); @@ -524,8 +524,8 @@ static int mcdmafec_probe(struct udevice *dev) if (val) info->tx_init = fdt32_to_cpu(*val);
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#ifdef CFG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; #endif init_eth_info(info);
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 4dd848932b96..ec1fae9688bd 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -39,11 +39,11 @@ DECLARE_GLOBAL_DATA_PTR;
static void init_eth_info(struct fec_info_s *info) { -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp;
if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH;
@@ -56,7 +56,7 @@ static void init_eth_info(struct fec_info_s *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -387,7 +387,7 @@ static int mcffec_send(struct udevice *dev, void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifndef CFG_SYS_FEC_BUF_USE_SRAM /* * FEC unable to initial transmit data packet. * A nop will ensure the descriptor polling active completed. diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h index 32b7d3e56130..551d7061ccc3 100644 --- a/drivers/net/qe/uec.h +++ b/drivers/net/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ }
struct uec_inf { diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d69a9ff47736..8b6f034ea165 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -764,7 +764,7 @@ static int tsec_initialize(struct bd_info *bis, priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr; - priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; + priv->tbiaddr = CFG_SYS_TBIPA_VALUE; priv->flags = tsec_info->flags;
strcpy(dev->name, tsec_info->devname); @@ -832,7 +832,7 @@ int tsec_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_plat(dev); struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; - u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + u32 tbiaddr = CFG_SYS_TBIPA_VALUE; struct tsec_data *data; ofnode parent, child; fdt_addr_t reg; diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index af8d99cefbef..09883f06be28 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -39,13 +39,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size) u8 *fw = firmware; unsigned int i;
- u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050); - u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040); - u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044); - u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048); - u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070); + u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070); #ifdef DEBUG - u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060); + u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060); #endif
out_be32(gloreset, 3); diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c index e286dd108f31..ad7aaf35a9a0 100644 --- a/drivers/power/power_dialog.c +++ b/drivers/power/power_dialog.c @@ -24,7 +24,7 @@ int pmic_dialog_init(unsigned char bus) p->number_of_regs = DIALOG_NUM_OF_REGS;
p->interface = PMIC_I2C; - p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; + p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 83461c024c77..63371e71bf74 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ }
struct uec_inf { diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9d429c832f49..fcf06d103283 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -52,7 +52,7 @@ * * Some boards do not have a PHY for each ethernet port. These ports are known * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate - * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) + * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network * speed and duplex should be for the port. @@ -61,10 +61,10 @@ * #define CONFIG_FIXED_PHY 0xFFFFFFFF * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) * - * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 - * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 + * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC2_PHY_ADDR 0x02 + * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC4_PHY_ADDR 0x04 * * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ * {name, speed, duplex}, diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 40ca66bdceee..0e9d3d24dd89 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -80,8 +80,8 @@ enum ds_type { #endif /*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif
#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) @@ -212,13 +212,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); }
#endif /* !CONFIG_DM_RTC */ diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 486c01f9ba20..2c780ab8edfa 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -184,13 +184,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static uchar rtc_read(struct udevice *dev, uchar reg) diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 9f2647d707e5..89442f9386ba 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -29,8 +29,8 @@ #endif /*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif
#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000) @@ -194,21 +194,21 @@ void rtc_reset (void){ */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write(uchar reg, uchar val, bool set) { if (set == true) { - val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } else { - val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val; + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } }
static void rtc_write_raw (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index 5b72e86768a1..bd32ed2dbf91 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -164,13 +164,13 @@ void rtc_enable_32khz_output(void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 8be532c3e318..66a0faa0ecff 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -319,7 +319,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_update_rtc_time(tm, buf);
return 0; @@ -329,10 +329,10 @@ int rtc_set(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_set_rtc_buf(tm, buf);
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, + if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; @@ -349,8 +349,8 @@ void rtc_reset(void) * M41T82: Make sure HT (Halt Update) bit is cleared. * This bit is 0 in M41T62 so its save to clear it always. */ - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); val &= ~M41T80_ALHOUR_HT; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif /* CONFIG_DM_RTC */ diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index 11928839dcfc..e03a87f94da9 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -16,20 +16,20 @@ #include <i2c.h> #include <linux/delay.h>
-#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x50 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x50 #endif
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); udelay(2500); }
diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 19faefba7c8f..91a412440b85 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -111,12 +111,12 @@ void rtc_reset (void)
static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); }
static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index c987494b669d..e0a7bd3662fb 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -53,12 +53,12 @@ /****** Helper functions ****************************************/ static u8 rtc_read(u8 reg) { - return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg); }
static void rtc_write(u8 reg, u8 val) { - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val); } /****************************************************************/
diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 97ec001aef56..6b1c23ca5db6 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -39,8 +39,8 @@ static unsigned int rtc_debug = DEBUG; #define rtc_debug 0 /* gcc will remove all the debug code for us */ #endif
-#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x32 #endif
#define RS5C372_RAM_SIZE 0x10 @@ -63,7 +63,7 @@ rs5c372_readram(unsigned char *buf, int len) { int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); if (ret != 0) { printf("%s: failed to read\n", __FUNCTION__); return ret; @@ -103,7 +103,7 @@ rs5c372_enable(void) buf[14] = 0; /* reg. 13 */ buf[15] = 0; /* reg. 14 */ buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); if (ret != 0) { printf("%s: failed\n", __FUNCTION__); return; @@ -204,7 +204,7 @@ int rtc_set (struct rtc_time *tmp) memset(buf, 0, sizeof(buf));
/* only read register 15 */ - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
if (ret == 0) { /* need to save register 15 */ @@ -233,7 +233,7 @@ int rtc_set (struct rtc_time *tmp) printf("WARNING: year should be between 1970 and 2069!\n"); buf[7] = bin2bcd(tmp->tm_year % 100);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); if (ret != 0) { printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); return -1; diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index d513561b8202..bf93b557748b 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -33,8 +33,8 @@ #endif /*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x32 #endif
/* @@ -313,7 +313,7 @@ static int rx8010sj_rtc_reset(DEV_TYPE *dev) int rtc_get(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, };
return rx8010sj_rtc_get(&dev, tm); @@ -322,7 +322,7 @@ int rtc_get(struct rtc_time *tm) int rtc_set(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, };
return rx8010sj_rtc_set(&dev, tm); @@ -331,7 +331,7 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, };
rx8010sj_rtc_reset(&dev); @@ -340,7 +340,7 @@ void rtc_reset(void) void rtc_init(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, };
rx8010sj_rtc_init(&dev); diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index ce23427b1744..4a8d1c5903f3 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -77,7 +77,7 @@
static void rtc_write(int reg, u8 val) { - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); }
/* @@ -89,7 +89,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[8];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 83cda1f20409..8a489a2e3f95 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
#if CONFIG_IS_ENABLED(SERIAL_PRESENT) static int serial_check_stdout(const void *blob, struct udevice **devp) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 6cdbb89841c1..4d5496509481 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -22,7 +22,7 @@ static struct serial_device *serial_current; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
/** * serial_null() - Void registration routine of a serial driver @@ -459,7 +459,7 @@ void default_serial_puts(const char *s) }
#if CONFIG_POST & CONFIG_SYS_POST_UART -static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; +static const int bauds[] = CFG_SYS_BAUDRATE_TABLE;
/** * uart_post_test() - Test the currently selected serial port using POST diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ee6171108a8..9ebc4ed48f0a 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -225,7 +225,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
/* setup format */ - scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
/* * Use following format: @@ -314,7 +314,7 @@ static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) struct davinci_spi_slave *ds = dev_get_priv(bus);
debug("%s speed %u\n", __func__, max_hz); - if (max_hz > CONFIG_SYS_SPI_CLK / 2) + if (max_hz > CFG_SYS_SPI_CLK / 2) return -EINVAL;
ds->freq = max_hz; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index bc5da0a1e6e9..2bb7390bbfb7 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -131,7 +131,7 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) * follows: * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR)) */ - divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz); + divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz); if (divider < 16) { /* This is the easy case, divider is less than 16 */ spr = divider; @@ -205,7 +205,7 @@ static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode) data = readl(®->timing1); data &= ~KW_SPI_TMISO_SAMPLE_MASK;
- if (CONFIG_SYS_TCLK == 250000000 && + if (CFG_SYS_TCLK == 250000000 && mode & SPI_CPOL && mode & SPI_CPHA) data |= KW_SPI_TMISO_SAMPLE_2; diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c index ad1781e6c0f8..84fbc79016a0 100644 --- a/drivers/sysreset/sysreset_xtfpga.c +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -15,8 +15,8 @@ static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type) { switch (type) { case SYSRESET_COLD: - writel(CONFIG_SYS_FPGAREG_RESET_CODE, - CONFIG_SYS_FPGAREG_RESET); + writel(CFG_SYS_FPGAREG_RESET_CODE, + CFG_SYS_FPGAREG_RESET); break; default: return -EPROTONOSUPPORT; diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index 065f10bb742b..2e50d9fbc580 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -59,7 +59,7 @@ static int arm_global_timer_probe(struct udevice *dev) return ret; uc_priv->clock_rate = ret; } else { - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; }
/* init timer */ diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c index 72be2977547a..9c3b64ae5b1b 100644 --- a/drivers/timer/imx-gpt-timer.c +++ b/drivers/timer/imx-gpt-timer.c @@ -28,9 +28,9 @@ #define GPT_CLKSRC_IPG_CLK (1 << 6) #define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
-/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ -#ifndef CONFIG_SYS_HZ_CLOCK -#define CONFIG_SYS_HZ_CLOCK 3000000 +/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ +#ifndef CFG_SYS_HZ_CLOCK +#define CFG_SYS_HZ_CLOCK 3000000 #endif
struct imx_gpt_timer_regs { @@ -60,7 +60,7 @@ static u64 imx_gpt_timer_get_count(struct udevice *dev)
static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate) { - u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1;
/* Reset the timer */ setbits_le32(®s->cr, GPT_CR_SWR); @@ -138,7 +138,7 @@ static int imx_gpt_timer_probe(struct udevice *dev) return ret; }
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
return 0; } diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index d0eab3ce781d..d588f0cbcd18 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -72,7 +72,7 @@ unsigned long notrace timer_early_get_rate(void) if (IS_ENABLED(CONFIG_ARCH_MVEBU)) return MVEBU_TIMER_FIXED_RATE_25MHZ; else - return CONFIG_SYS_TCLK; + return CFG_SYS_TCLK; }
/** @@ -117,7 +117,7 @@ static int orion_timer_probe(struct udevice *dev) if (type == INPUT_CLOCK_25MHZ) uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ; else - uc_priv->clock_rate = CONFIG_SYS_TCLK; + uc_priv->clock_rate = CFG_SYS_TCLK; orion_timer_init(priv->base, type);
return 0; diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f07251e54c01..1213a14ef197 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -97,11 +97,11 @@ static int stm32_timer_probe(struct udevice *dev) rate = clk_get_rate(&clk);
/* we set timer prescaler to obtain a 1MHz timer counter frequency */ - psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + psc = (rate / CFG_SYS_HZ_CLOCK) - 1; writel(psc, ®s->psc);
/* Set timer frequency to 1MHz */ - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
/* Configure timer for auto-reload */ setbits_le32(®s->cr1, CR1_ARPE); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 9acef5ee4f84..3f4418198ccd 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1993,7 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; - gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; + gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE;
gohci.flags = 0; gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 54d1efc8f5f3..b0a99c9cd5d9 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -221,13 +221,13 @@ static struct clk ipu_clk = { .usecount = 0, };
-#if !defined CONFIG_SYS_LDB_CLOCK -#define CONFIG_SYS_LDB_CLOCK 65000000 +#if !defined CFG_SYS_LDB_CLOCK +#define CFG_SYS_LDB_CLOCK 65000000 #endif
static struct clk ldb_clk = { .name = "ldb_clk", - .rate = CONFIG_SYS_LDB_CLOCK, + .rate = CFG_SYS_LDB_CLOCK, .usecount = 0, };
diff --git a/env/Kconfig b/env/Kconfig index 24111dfaf47b..4e506ae262b5 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -140,7 +140,7 @@ config ENV_IS_IN_FLASH type flash chips the second sector can be used: the offset for this sector is given here.
- CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE. + CONFIG_ENV_OFFSET is used relative to CFG_SYS_FLASH_BASE.
CONFIG_ENV_ADDR:
diff --git a/env/embedded.c b/env/embedded.c index 9f26e6cad9c4..27fb45bf8c3e 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -92,6 +92,6 @@ unsigned long env_size __UBOOT_ENV_SECTION__(env_size) = sizeof(env_t); /* * Add in absolutes. */ -GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)); +GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE));
#endif /* ENV_IS_EMBEDDED */ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 17c76bcf3dbc..d60f494b58b5 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -17,8 +17,8 @@ #endif #endif
-#ifndef CONFIG_SYS_BAUDRATE_TABLE -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifndef CFG_SYS_BAUDRATE_TABLE +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif
#endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 6dfa3dd0f02a..246437a51e2f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -13,7 +13,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
@@ -41,11 +41,11 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ -#define CONFIG_SYS_PLL_ODR 0x36 -#define CONFIG_SYS_PLL_FDR 0x7D +#define CFG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CFG_SYS_PLL_ODR 0x36 +#define CFG_SYS_PLL_FDR 0x7D
-#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000
/* * Low Level Configuration Settings @@ -53,9 +53,9 @@ * You should know what you are doing if you make changes here. */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221
/* * Start addresses for the final memory configuration @@ -75,14 +75,14 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* * Configuration for environment @@ -95,15 +95,15 @@
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -117,8 +117,8 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007F0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e28662c6e59a..128ef50b476f 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -18,14 +18,14 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) -#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) -#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) +#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) +#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ #ifdef CONFIG_MCFFEC @@ -50,10 +50,10 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 75000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 +#define CFG_SYS_CLK 75000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
-#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000
/* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x21
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -81,16 +81,16 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -104,15 +104,15 @@ * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP)
@@ -130,13 +130,13 @@ * CS7 - Available */ #ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC00000 -# define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D00 +# define CFG_SYS_CS0_BASE 0xFFC00000 +# define CFG_SYS_CS0_MASK 0x003f0001 +# define CFG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE00000 -# define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D80 +# define CFG_SYS_CS0_BASE 0xFFE00000 +# define CFG_SYS_CS0_MASK 0x001f0001 +# define CFG_SYS_CS0_CTRL 0x00001D80 #endif
#endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index f1da278d5159..0e38eeb4a365 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -18,7 +18,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
@@ -26,9 +26,9 @@ * Clock configuration: enable only one of the following options */
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
/* * Low Level Configuration Settings @@ -36,14 +36,14 @@ * You should know what you are doing if you make changes here. */
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -56,7 +56,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -67,33 +67,33 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE)
/*----------------------------------------------------------------------- @@ -101,25 +101,25 @@ */
/* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CFG_SYS_CS1_BASE 0xe0000000 +#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index bd3c57d1438c..7e37c6d11997 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -8,7 +8,7 @@
#include <linux/stringify.h>
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
/* Configuration for environment @@ -20,7 +20,7 @@ env/embedded.o(.text*);
#ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) +# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG @@ -45,18 +45,18 @@ #define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) -#define CONFIG_SYS_I2C_PINMUX_SET (0) - -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK -#ifdef CONFIG_SYS_FAST_CLK -# define CONFIG_SYS_PLLCR 0x1243E054 -# define CONFIG_SYS_CLK 140000000 +#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CFG_SYS_I2C_PINMUX_SET (0) + +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK +# define CFG_SYS_PLLCR 0x1243E054 +# define CFG_SYS_CLK 140000000 #else -# define CONFIG_SYS_PLLCR 0x135a4140 -# define CONFIG_SYS_CLK 70000000 +# define CFG_SYS_PLLCR 0x135a4140 +# define CFG_SYS_CLK 70000000 #endif
/* @@ -65,14 +65,14 @@ * You should know what you are doing if you make changes here. */
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/* * Start addresses for the final memory configuration @@ -87,10 +87,10 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#define FLASH_SST6401B 0x200 #define SST_ID_xF6401B 0x236D236D @@ -101,45 +101,45 @@ * Amd/Atmel use 0x30 for sector erase, SST use 0x50. * 0x30 is block erase in SST */ -# define CONFIG_SYS_FLASH_SIZE 0x800000 +# define CFG_SYS_FLASH_SIZE 0x800000 #else -# define CONFIG_SYS_SST_SECT 2048 -# define CONFIG_SYS_SST_SECTSZ 0x1000 +# define CFG_SYS_SST_SECT 2048 +# define CFG_SYS_SST_SECTSZ 0x1000 #endif
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE)
-#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK 0x007F0021 -#define CONFIG_SYS_CS0_CTRL 0x00001D80 +#define CFG_SYS_CS0_BASE 0xFF800000 +#define CFG_SYS_CS0_MASK 0x007F0021 +#define CFG_SYS_CS0_CTRL 0x00001D80
-#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK 0x00000001 -#define CONFIG_SYS_CS1_CTRL 0x00003DD8 +#define CFG_SYS_CS1_BASE 0xE0000000 +#define CFG_SYS_CS1_MASK 0x00000001 +#define CFG_SYS_CS1_CTRL 0x00003DD8
/*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 7c3bc032bfee..847b4c2593d8 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -17,7 +17,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
@@ -51,22 +51,22 @@ "save\0" \ ""
-#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000
/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -75,35 +75,35 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -111,11 +111,11 @@ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x00000000 -#define CONFIG_SYS_PADDR 0x0000 -#define CONFIG_SYS_PADAT 0x0000 -#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 -#define CONFIG_SYS_PBDAT 0x0000 -#define CONFIG_SYS_PDCNT 0x00000000 +#define CFG_SYS_PACNT 0x00000000 +#define CFG_SYS_PADDR 0x0000 +#define CFG_SYS_PADAT 0x0000 +#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_SYS_PBDDR 0x0000 +#define CFG_SYS_PBDAT 0x0000 +#define CFG_SYS_PDCNT 0x00000000 #endif /* _M5272C3_H */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 4eb4abea7251..ff9f85358963 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,7 +21,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -34,9 +34,9 @@ /* Available command configuration */
/* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) -#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) +#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) +#define CFG_SYS_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC # define CONFIG_OVERWRITE_ETHADDR_ONCE @@ -54,7 +54,7 @@ "save\0" \ ""
-#define CONFIG_SYS_CLK 150000000 +#define CFG_SYS_CLK 150000000
/* * Low Level Configuration Settings @@ -62,13 +62,13 @@ * You should know what you are doing if you make changes here. */
-#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -77,34 +77,34 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */
-#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CFG_SYS_FLASH_SIZE 0x200000
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -112,12 +112,12 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001
-#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_CTRL 0x00001900 -#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_BASE 0x30000000 +#define CFG_SYS_CS1_CTRL 0x00001900 +#define CFG_SYS_CS1_MASK 0x00070001
#endif /* _M5275EVB_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index eda394467e93..bde9e770e52a 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -17,7 +17,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
@@ -49,25 +49,25 @@ "save\0" \ ""
-#define CONFIG_SYS_CLK 64000000 +#define CFG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -76,65 +76,65 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xf0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP)
/*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xFFE00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001
/*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 159993a46bc5..0e9ba4c3ada8 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -18,17 +18,17 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_TX_ETH_BUFFER 8 -# define CONFIG_SYS_FEC_BUF_USE_SRAM +# define CFG_SYS_TX_ETH_BUFFER 8 +# define CFG_SYS_FEC_BUF_USE_SRAM #endif
-#define CONFIG_SYS_RTC_CNT (0x8000) -#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) +#define CFG_SYS_RTC_CNT (0x8000) +#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
/* I2C */
@@ -54,10 +54,10 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000
/* * Low Level Configuration Settings @@ -67,9 +67,9 @@ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221
/* * Start addresses for the final memory configuration @@ -89,17 +89,17 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +113,15 @@ * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P)
/*----------------------------------------------------------------------- @@ -135,12 +135,12 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0
-#define CONFIG_SYS_CS1_BASE 0xC0000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001FA0 +#define CFG_SYS_CS1_BASE 0xC0000000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d7ece6393498..8f83810f165e 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -18,7 +18,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
@@ -46,12 +46,12 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/* * Low Level Configuration Settings @@ -61,9 +61,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -83,22 +83,22 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
#ifdef CONFIG_CMD_NAND -# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P)
/*----------------------------------------------------------------------- @@ -134,18 +134,18 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780
#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif
#endif /* _M5329EVB_H */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b2fc6923e0d9..43c642edeb18 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -20,7 +20,7 @@ * (easy to change) */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
@@ -48,12 +48,12 @@
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -85,20 +85,20 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
-# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P)
/*----------------------------------------------------------------------- @@ -134,16 +134,16 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780
-#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60
#endif /* _M5373EVB_H */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 2e7140cd86a1..232cf9e99845 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -59,21 +59,21 @@ /* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) -#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ #define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE +#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* Environment Configuration */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d9627e393d9c..85c080cf27a5 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -25,20 +25,20 @@ */
/* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/* * System IO Config */ -#define CONFIG_SYS_SICRH 0x08200000 -#define CONFIG_SYS_SICRL 0x00000000 +#define CFG_SYS_SICRH 0x08200000 +#define CFG_SYS_SICRL 0x00000000
/* * Output Buffer Impedance */ -#define CONFIG_SYS_OBIR 0x30100000 +#define CFG_SYS_OBIR 0x30100000
/* * Device configurations @@ -60,9 +60,9 @@ * DDR Setup */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) +#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
@@ -70,14 +70,14 @@ * Manually set up DDR parameters */ #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | (0 << TIMING_CFG0_WRT_SHIFT) \ | (0 << TIMING_CFG0_RRT_SHIFT) \ | (0 << TIMING_CFG0_WWT_SHIFT) \ @@ -86,7 +86,7 @@ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) /* 0x00260802 */ /* DDR400 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | (7 << TIMING_CFG1_CASLAT_SHIFT) \ @@ -95,7 +95,7 @@ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | (5 << TIMING_CFG2_CPO_SHIFT) \ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ @@ -104,23 +104,23 @@ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) /* 0x02984cc8 */
-#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ +#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) /* 0x04400442 */ /* DDR400 */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 +#define CFG_SYS_DDR_MODE2 0x00000000
/* * Memory test */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
/* * The reserved memory @@ -129,14 +129,14 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
/* * NAND Flash on the Local Bus @@ -146,14 +146,14 @@
/* Vitesse 7385 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CFG_SYS_VSC7385_BASE 0xF0000000
/* * Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) @@ -165,13 +165,13 @@ #define CONFIG_FSL_SERDES2 0xe3100
/* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
/* * Config on-board RTC */ #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* * General PCI @@ -198,7 +198,7 @@
#ifdef CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 2 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC1_PHYIDX 0 @@ -226,7 +226,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/* * Environment Configuration diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 25b4fe0c7d4d..ff02c2cd8472 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -28,16 +28,16 @@ * Only possible on E500 Version 2 or newer cores. */
-#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ @@ -112,32 +112,32 @@ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif
-#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST \ + {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG /* enable hwconfig */
/* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull #else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE #endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 @@ -149,12 +149,12 @@ * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */
/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR2, need: * 64MB mask for AM, OR2[0:7] = 1111 1100 @@ -167,10 +167,10 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/* * Common settings for all Local Bus SDRAM commands. @@ -178,7 +178,7 @@ * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ +#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ | LSDMR_PRETOACT7 \ | LSDMR_ACTTORW7 \ | LSDMR_BL8 \ @@ -226,25 +226,25 @@ #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR #endif
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x69} } #endif
/* @@ -326,7 +326,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
/* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 21491b9f97ca..a8af0a101c84 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,10 +16,10 @@ #include <asm/config_mpc85xx.h>
#ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CFG_SYS_MMC_U_BOOT_START (0x11000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10) #endif
#ifdef CONFIG_SPIFLASH @@ -27,10 +27,10 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) #endif #endif
@@ -111,11 +111,11 @@ extern unsigned long get_sdram_size(void); #endif #define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* * Memory map @@ -136,15 +136,15 @@ extern unsigned long get_sdram_size(void); */ /* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CFG_SYS_FLASH_BASE 0xee000000
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -161,7 +161,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NOR_TWP(0x1c) #define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* CFI for NOR Flash */ @@ -237,85 +237,85 @@ extern unsigned long get_sdram_size(void);
/* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif
/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 +#define CFG_SYS_CPLD_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif #endif @@ -324,11 +324,11 @@ extern unsigned long get_sdram_size(void); #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */ #define I2C_PCA9557_ADDR1 0x18 @@ -343,7 +343,7 @@ extern unsigned long get_sdram_size(void);
/* RTC */ #define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68
/* * SPI interface will not be available in case of NAND boot SPI CS0 will be @@ -393,7 +393,7 @@ extern unsigned long get_sdram_size(void); */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif
@@ -410,7 +410,7 @@ extern unsigned long get_sdram_size(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
/* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c3ef21633354..1e02855fefd8 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -39,32 +39,32 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
/* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ CONFIG_RAMBOOT_TEXT_BASE) #else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -74,18 +74,18 @@ */
/* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 +#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
/* * This board doesn't have a promjet connector. * However, it uses commone corenet board LAW and TLB. * It is necessary to use the same start address with proper offset. */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif
#define CONFIG_FSL_CPLD @@ -130,28 +130,28 @@ | OR_FCM_EHTR) #endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -159,13 +159,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -244,52 +244,52 @@ #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CFG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 +#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 +#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
-#define CONFIG_SYS_TBIPA_VALUE 8 +#define CFG_SYS_TBIPA_VALUE 8 #endif
#ifdef CONFIG_MMC @@ -305,7 +305,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
/* * Environment Configuration diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 417b9ae7b241..bad34d9771ec 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/* @@ -32,7 +32,7 @@ * U-Boot bootcode configuration */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 87b68227a0d9..9a9663b34ba8 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/* @@ -37,7 +37,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b567b63980e9..b5fb0a9b529e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -29,18 +29,18 @@
#ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif
#ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif
#endif /* CONFIG_RAMBOOT_PBL */ @@ -93,7 +93,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -101,20 +101,20 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -125,15 +125,15 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE 0xe8000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -160,30 +160,30 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#ifdef CONFIG_TARGET_T1024RDB /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 #endif
/* NAND Flash on IFC */ @@ -235,72 +235,72 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -315,7 +315,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68
/* * eSPI - Enhanced SPI @@ -363,36 +363,37 @@
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 + #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN @@ -421,7 +422,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 37dfe32e21bf..bee4b704a24f 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -36,18 +36,18 @@
#ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif
#ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif
#endif @@ -63,7 +63,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -71,24 +71,24 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 /* - * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence - * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address - * (CONFIG_SYS_INIT_L3_VADDR) will be different. + * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address + * (CFG_SYS_INIT_L3_VADDR) will be different. */ -#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
@@ -97,11 +97,11 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0xf) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -128,7 +128,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */ #define CPLD_LBMAP_MASK 0x3F @@ -157,25 +157,25 @@ #define CPLD_INT_MASK_TDMR2 0x01 #endif
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -213,55 +213,55 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -269,13 +269,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 @@ -289,7 +289,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68
/*DVI encoder*/ #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 @@ -344,58 +344,58 @@
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CFG_SYS_SGMII1_PHY_ADDR 0x03 #elif defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x01 #elif defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 -#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 -#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x02 +#define CFG_SYS_SGMII2_PHY_ADDR 0x03 +#define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#define CFG_SYS_RGMII1_PHY_ADDR 0x04 +#define CFG_SYS_RGMII2_PHY_ADDR 0x05 #else -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +#define CFG_SYS_RGMII1_PHY_ADDR 0x01 +#define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif
/* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c #endif #endif #endif @@ -409,7 +409,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 798822e5031f..be8c30db26a7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -31,18 +31,18 @@
#ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif
#ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif
#endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,16 +90,16 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -121,8 +121,8 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
#define QIXIS_BASE 0xffdf0000 #define QIXIS_LBMAP_SWITCH 6 @@ -141,23 +141,23 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -195,81 +195,81 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* * I2C @@ -360,28 +360,28 @@
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN @@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ea366b671c02..795873f42336 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -31,18 +31,18 @@
#ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif
#ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif
#endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,10 +90,10 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -116,29 +116,29 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS }
/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -176,65 +176,65 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* * I2C @@ -319,28 +319,28 @@
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN @@ -384,7 +384,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index cc86c9d4a51b..ffd56454939e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -24,10 +24,10 @@
#ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CFG_SYS_MMC_U_BOOT_START 0x00200000 +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif
#endif @@ -51,39 +51,39 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -91,13 +91,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -135,7 +135,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration @@ -159,14 +159,14 @@ /* * IFC Definitions */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -188,8 +188,8 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -227,71 +227,71 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0
/* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ @@ -318,28 +318,28 @@
/* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 50 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 50 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 25d9c96e164f..69b8b048ce39 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -205,8 +205,8 @@ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) */ #if defined(CONFIG_NOR) -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a9a4c8d17fc0..c57a0ddc21dd 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -89,7 +89,7 @@ /* on one chip */
#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #endif
#endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4ff8528cf8ad..bcdff2e98acd 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -9,7 +9,7 @@ #define __CONFIG_AM43XX_EVM_H
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
@@ -25,7 +25,7 @@ /* SPL defines. */
/* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000
/* * When building U-Boot such that there is no previous loader diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 84555f3b13dc..340a8ce6dc88 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -53,9 +53,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h index eba78d3894c8..ee0be972d243 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@
#define CONFIG_HOSTNAME "AMCORE"
-#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ @@ -24,21 +24,21 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0"
-#define CONFIG_SYS_CLK 45000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +#define CFG_SYS_CLK 45000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2) /* Register Base Addrs */ -#define CONFIG_SYS_MBAR 0x10000000 +#define CFG_SYS_MBAR 0x10000000 /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
#define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CFG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */
#define LDS_BOARD_TEXT \ @@ -46,7 +46,7 @@ env/embedded.o(.text*);
/* memory map space for linux boot data */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* * Cache Configuration @@ -56,25 +56,25 @@ * sdram - single region - no masks */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ CF_ACR_EN) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ CF_CACR_EC)
/* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16) /* 4MB, AA=0,V=1 C/I BIT for errata */ -#define CONFIG_SYS_CS0_MASK 0x003f0001 +#define CFG_SYS_CS0_MASK 0x003f0001 /* WS=10, AA=1, PS=16bit (10) */ -#define CONFIG_SYS_CS0_CTRL 0x1980 +#define CFG_SYS_CS0_CTRL 0x1980 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ -#define CONFIG_SYS_CS1_BASE 0x3000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x0100 +#define CFG_SYS_CS1_BASE 0x3000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 63c7dfc1feba..9c6f76383deb 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Miscellaneous configurable options */
diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 865aad2a3f90..034cd7a7cdf8 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000
/* * Serial Port diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 0464a69e8236..c56b35150a5f 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000
/* * Serial Port diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 356d4c35ee2b..c9375b4d162a 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -107,7 +107,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */ diff --git a/include/configs/arbel.h b/include/configs/arbel.h index ed32e772f8e2..60758b0ca02a 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -7,9 +7,9 @@ #define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_BOOTMAPSZ (20 << 20) +#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE +#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */ #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 90cf4705f4f4..c1eec5d06ccb 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -20,7 +20,7 @@ #endif
/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 28341000 +#define CFG_SYS_LDB_CLOCK 28341000
#include "mx6_common.h"
@@ -407,8 +407,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index cbd0d6cea011..bb1bd50838a0 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -17,11 +17,11 @@ #define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) #else -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif
/* diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index b142ea3c3350..f5922fc416eb 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -55,19 +55,19 @@ * interface etc. */
-#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3) #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected * in u-boot command interface */
-#define CONFIG_SYS_UART_PORT (2) -#define CONFIG_SYS_UART2_ALT3_GPIO +#define CFG_SYS_UART_PORT (2) +#define CFG_SYS_UART2_ALT3_GPIO
/* * Watchdog configuration; Watchdog is disabled for running from RAM @@ -125,7 +125,7 @@ * it needs non-blocking CFI routines. */
-#define CONFIG_SYS_FPGA_WAIT 1000 +#define CFG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */
@@ -139,19 +139,19 @@
/* Base register address */
-#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
/* System Conf. Reg. & System Protection Reg. */
-#define CONFIG_SYS_SCR 0x0003; -#define CONFIG_SYS_SPR 0xffff; +#define CFG_SYS_SCR 0x0003; +#define CFG_SYS_SPR 0xffff;
/* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_CTRL 0x221
/* * Start addresses for the final memory configuration @@ -170,23 +170,23 @@ * CS4 - unused * CS5 - unused */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00ff0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fc0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00ff0001 +#define CFG_SYS_CS0_CTRL 0x00001fc0
-#define CONFIG_SYS_CS1_BASE 0x01000000 -#define CONFIG_SYS_CS1_MASK 0x00ff0001 -#define CONFIG_SYS_CS1_CTRL 0x00001fc0 +#define CFG_SYS_CS1_BASE 0x01000000 +#define CFG_SYS_CS1_MASK 0x00ff0001 +#define CFG_SYS_CS1_CTRL 0x00001fc0
-#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK 0x00ff0001 -#define CONFIG_SYS_CS2_CTRL 0x0000fec0 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK 0x00ff0001 +#define CFG_SYS_CS2_CTRL 0x0000fec0
-#define CONFIG_SYS_CS3_BASE 0x21000000 -#define CONFIG_SYS_CS3_MASK 0x00ff0001 -#define CONFIG_SYS_CS3_CTRL 0x0000fec0 +#define CFG_SYS_CS3_BASE 0x21000000 +#define CFG_SYS_CS3_MASK 0x00ff0001 +#define CFG_SYS_CS3_CTRL 0x0000fec0
-#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
@@ -195,12 +195,12 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CFG_SYS_FLASH_SIZE 0x2000000
#define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -208,15 +208,15 @@
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P)
#endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4631acfd6643..4aa876a9f79d 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,7 +12,7 @@ #include <linux/kconfig.h>
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 0d76f419db5b..b9cc7ba974de 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -24,8 +24,8 @@ */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* * SDRAM: 1 bank, min 32, max 128 MB @@ -34,11 +34,11 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif
/* NAND flash */ @@ -51,6 +51,6 @@ #endif
/* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index dcc1cca4791b..56247e390bf6 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -11,16 +11,16 @@ #define __CONFIG_H
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#include <asm/hardware.h>
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -42,6 +42,6 @@ #define CONFIG_DM9000_NO_SROM
/* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index aefa9fc60c40..afdb74785f8a 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -19,20 +19,20 @@ #include <asm/hardware.h>
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Primary Environment Sector */
@@ -50,9 +50,9 @@ #define MASTER_PLL_OUT 3
/* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ @@ -60,31 +60,31 @@ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -98,10 +98,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -110,35 +110,35 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_MR_URSTEN | \ AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -160,6 +160,6 @@ #endif
/* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 08cfee1a4e18..2ceb8067d580 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -41,9 +41,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 76f87c16192e..0f9e2cfb582d 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -10,8 +10,8 @@ #define __AT91SAM9N12_CONFIG_H_
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -35,9 +35,9 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20953f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20953f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e1111b6dd38e..cad00f647b60 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -13,15 +13,15 @@ #include <asm/hardware.h>
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index eb1d1ad60d1a..509c458e5faf 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -9,8 +9,8 @@ #define __CONFIG_H__
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* general purpose I/O */
@@ -38,9 +38,9 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 83ac87b10a58..03e04e6e6805 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -39,15 +39,15 @@
/* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
/* max number of memory banks */ /* * There are 4 banks supported for this Controller, * but we have only 1 bank connected to flash on board */ -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} +#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */ #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) @@ -63,7 +63,7 @@ */
/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */
/* Support autoboot from RAM (kernel image is loaded via debug port) */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 6d82712186d4..04dc50b1cb22 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -19,8 +19,8 @@ * Memory configuration */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_512M
/* diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index cba109b74a9f..43edc91b1011 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -12,7 +12,7 @@
#define CFG_SYS_NS16550_COM1 0xf040c000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 +#define CFG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"
diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index a07f1b7ad0f1..114337294e02 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -12,7 +12,7 @@
#define CFG_SYS_NS16550_COM1 0xf040ab00
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"
diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index f1b68ba67338..c61acf6b86b8 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -7,6 +7,6 @@ #define __BCM963138_H
#define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_HZ_CLOCK 500000000 +#define CFG_SYS_HZ_CLOCK 500000000
#endif diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9769a7140926..57360b60ca9c 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -82,7 +82,7 @@ extern phys_addr_t prior_stage_fdt_address; * initramfs images, in which case this limitation is eliminated. */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CFG_SYS_INIT_RAM_SIZE 0x100000
/* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -102,7 +102,7 @@ extern phys_addr_t prior_stage_fdt_address; /* * Serial console configuration. */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200}
/* diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a075a5b2f326..0842a4a8f543 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -200,7 +200,7 @@ #define PHYS_SDRAM_SIZE (SZ_512M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 0b1fc91d9e17..cb28ae28dd3e 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -26,10 +26,10 @@ #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } +#define CFG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif
/* Board Clock */ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index e40f110cac6e..0d254cd7f9c8 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 508317f231ee..7865b9c17e59 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index c5bda16d2bcd..93426d2661d4 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 32397c26e8ab..e992fe6a560e 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 18c99727a042..224b6977747f 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -14,9 +14,9 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index f8d7148d497e..3211d23049ee 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,9 +14,9 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index d564a32ee526..7e2449ca24fd 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,9 +14,9 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
-#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CFG_SYS_FLASH_BASE 0xbe000000
#endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index f982a4363db6..443ee470107f 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 11d623c28b21..c550f97b935b 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,9 +14,9 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
-#define CONFIG_SYS_FLASH_BASE 0xb8000000 +#define CFG_SYS_FLASH_BASE 0xb8000000
#endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index 30965c85bfaa..f2129140725c 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -14,7 +14,7 @@ /* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif
#endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 7e358a6314bf..3cdd0e47eaeb 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -9,7 +9,7 @@ #include <linux/sizes.h>
/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 }
#endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index 0033a7fb0223..14ce8a4c0f34 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -27,7 +27,7 @@ # define CFG_SYS_SDRAM_BASE 0x80000000 #endif
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* * Console diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 78b2000aa2ed..d35c7c4a591e 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,7 @@
/* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */
#define CONFIG_MXC_GPT_HCLK @@ -77,8 +77,8 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index f1734aaca7f5..3e0b42507888 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -22,7 +22,7 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6f2b8245b986..6f3396bad4c8 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -19,7 +19,7 @@
/* Flat Device Tree Definitions */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/ci20.h b/include/configs/ci20.h index f268dfd0943d..3329c24fa68c 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -12,7 +12,7 @@ /* Memory configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */ #define CFG_SYS_NS16550_CLK 48000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index eb899c455782..b1f9470d9ca4 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -23,8 +23,8 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CFG_SYS_I2C_PCA953X_ADDR 0x20 +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
#undef CONFIG_EXTRA_ENV_SETTINGS
@@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPI Flash support */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 47c4aacc436b..d5c039579759 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE @@ -139,7 +139,7 @@ #define CONFIG_MXC_USB_FLAGS 0
/* Boot */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* misc */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8f058213e9e7..8ad1cfb5ded3 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,7 @@ #define __CONFIG_CM_T43_H
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
@@ -32,7 +32,7 @@ #define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000
/* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 65b9074cd9cb..01828ea2011c 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -29,18 +29,18 @@ * --- */
-#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* --- * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command * interface * --- */
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
/* --- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change @@ -133,21 +133,21 @@ enter a valid image address in flash */ * --- */
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
/* --- * System Conf. Reg. & System Protection Reg. * --- */
-#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -168,28 +168,28 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000
/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -209,15 +209,15 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Port configuration (GPIO) */ -#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external GPIO*/ -#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs (1^=output, 0^=input) */ -#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ -#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ +#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index ca8445a3d05a..12dc946fc782 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -117,8 +117,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14278e9ca4f7..c6a79debd6ba 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -101,7 +101,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index c08095561d83..32a79b025545 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -161,8 +161,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 11283071397f..fa778ec9e2b7 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Host Support */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h index c7a3e47437bc..8a61086ecc15 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -24,8 +24,8 @@ */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -63,10 +63,10 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index e2e1cfedbde1..578277fc75c1 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -17,13 +17,13 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#define CFG_SYS_DV_NOR_BOOT_CFG (0x11) #endif
/* @@ -36,7 +36,7 @@
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -47,17 +47,17 @@ * PLL configuration */
-#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 24 +#define CFG_SYS_DA850_PLL1_PLLM 21
/* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -67,9 +67,9 @@ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -79,7 +79,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (0 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -88,20 +88,20 @@ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (0 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/* * Flash & Environment @@ -125,7 +125,7 @@ #endif
#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ #endif
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b16f3d48e386..4b31bbf4e11a 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -43,8 +43,8 @@ #define PHYS_SDRAM_SIZE SZ_512M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index c473f3d86ebf..66aa6d5c3c45 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -29,8 +29,8 @@ /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M +#define CFG_SYS_FLASH_BASE EMC_CS0_BASE +#define CFG_SYS_FLASH_SIZE SZ_4M
/* * NAND controller diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index ddc436d50190..f9b3d19480ed 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -73,8 +73,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
diff --git a/include/configs/display5.h b/include/configs/display5.h index 0a7428b02caf..7636d2869a9f 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -30,9 +30,9 @@ */
/* Below values are "dummy" - only to avoid build break */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x10000
#define CONFIG_MXC_UART_BASE UART5_BASE
@@ -285,8 +285,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index bb335a0a473c..8217712e3904 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -63,9 +63,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
@@ -87,8 +87,8 @@ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ -#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +#define CFG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ #endif /* NOR support */
diff --git a/include/configs/draak.h b/include/configs/draak.h index 8bfba78dc8e4..8140bc469c52 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __DRAAK_H */ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index 677a48562309..bd88c42a3ba5 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80de73d15d50..426155dbdbf1 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -12,7 +12,7 @@ * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/
-#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
@@ -27,18 +27,18 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/
-/*#define CONFIG_SYS_DRAM_TEST 1 */ -#undef CONFIG_SYS_DRAM_TEST +/*#define CFG_SYS_DRAM_TEST 1 */ +#undef CFG_SYS_DRAM_TEST
/*----------------------------------------------------------------------* * Clock and PLL Configuration * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ +#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*----------------------------------------------------------------------* * Network * @@ -54,14 +54,14 @@ * You should know what you are doing if you make changes here. *-----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000
/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) *-----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -79,34 +79,34 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xF0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 +#define CFG_SYS_FLASH_SIZE 16*1024*1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/*----------------------------------------------------------------------- * Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP)
@@ -114,36 +114,36 @@ * Memory bank definitions */
-#define CONFIG_SYS_CS0_BASE 0xFF000000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_BASE 0xFF000000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS2_BASE 0xE0000000 -#define CONFIG_SYS_CS2_CTRL 0x00001980 -#define CONFIG_SYS_CS2_MASK 0x000F0001 +#define CFG_SYS_CS2_BASE 0xE0000000 +#define CFG_SYS_CS2_CTRL 0x00001980 +#define CFG_SYS_CS2_MASK 0x000F0001
-#define CONFIG_SYS_CS3_BASE 0xE0100000 -#define CONFIG_SYS_CS3_CTRL 0x00001980 -#define CONFIG_SYS_CS3_MASK 0x000F0001 +#define CFG_SYS_CS3_BASE 0xE0100000 +#define CFG_SYS_CS3_CTRL 0x00001980 +#define CFG_SYS_CS3_MASK 0x000F0001
/*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PASPAR 0x0F0F -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PASPAR 0x0F0F +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF
/*----------------------------------------------------------------------- * I2C diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 597efd6745cd..d1882a9646be 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -16,7 +16,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __EBISU_H */ diff --git a/include/configs/edison.h b/include/configs/edison.h index b05141ad6450..455a889b64c1 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,6 +10,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024)
#endif diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index d24bc56f34ab..141f9913e639 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -51,8 +51,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index e39bb94314f3..29b7748e7865 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 6cae663cb8a0..6647148c96f4 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -16,7 +16,7 @@ /* NAND specific changes for etamin due to different page size */ #undef CFG_SYS_NAND_ECCPOS
-#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 97a8ffb4f61e..52eb0be67611 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -18,19 +18,19 @@ /* CPU information */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
/* 32kB internal SRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) +#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CFG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */ -# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
/* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -53,16 +53,16 @@
/* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif
/* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #endif
/* I2C */ -#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CFG_SYS_MAX_I2C_BUS 1
#define I2C_SOFT_DECLARATIONS
diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index cd6cb062eca2..bec1660cf485 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -11,7 +11,7 @@
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index ecd05fe15cec..c9c988b93740 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -8,7 +8,7 @@
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */ #define STR_HELPER(s) #s diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index a94f5a15f0d1..c9e0c13172cc 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,7 +15,7 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0"
-#define CONFIG_SYS_SPI_BASE 0x12D30000 +#define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING
diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 68c36dc2fd95..8672b9e95270 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -18,7 +18,7 @@
#define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index f5353ec79a1a..89e531649a61 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -14,8 +14,8 @@ #endif
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -32,10 +32,10 @@
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a7557144402b..0ba4efe67ac3 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -25,7 +25,7 @@ #endif
/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 }
/* RAM */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6cdfe8c4c3c0..36dcee87c5fb 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -14,7 +14,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ /* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/* * Memory test @@ -28,16 +28,16 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/* @@ -49,7 +49,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/* * Environment Configuration diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 85ceaf8ccb1a..97fe76cfa8ec 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -38,8 +38,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 1dba2e92fb9d..cbaf03c2a226 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -92,11 +92,11 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index fe00272a1bd0..b855bbc25fb8 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -54,8 +54,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* * MTD Command for mtdparts diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 0d281a3379aa..4aef0b4abd12 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) +#define CFG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_PL011_CLOCK 150000000
diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 775f166f1d35..c5ef2f99b0f4 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -26,7 +26,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 914c3ad9ef04..fad1f980481e 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -18,7 +18,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index fcb2dec54ec1..59ea8960071a 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -21,8 +21,8 @@ * Memory configuration */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G
/* diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ae935208ca5..fbfcded47123 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -20,8 +20,8 @@ * Memory configuration */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G
/* diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 594aa4f75e77..b0abd5488262 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -80,7 +80,7 @@ /* CS2 Base address */ #define PHYS_FLASH_1 0xc0000000 /* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Redundant Environment Sector */
/* diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index d4e2583ee8a4..1f30798550c6 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -110,8 +110,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* UART */ #ifdef CONFIG_MXC_UART diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 1b08c5e9a7e6..4e23f1a2dc5d 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -106,8 +106,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index a074df5829b4..402f83c18eae 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -56,7 +56,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 855af29ec96d..99da081cdae8 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPL */ #ifdef CONFIG_SPL diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 0a688afe6cdb..2d9d3c34b0db 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -64,8 +64,8 @@ #define PHYS_SDRAM_SIZE SZ_128M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index e5118f11580e..76771fd66ce9 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -70,8 +70,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index e62f9c5462b2..c228cf7f37ba 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,7 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -123,8 +123,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 143da0011046..03325e6c3a7a 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -71,8 +71,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index c7669305f592..80321cf2d8d3 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -18,8 +18,8 @@ #endif
/* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 9937071874fd..8a694c88a53a 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -15,10 +15,10 @@ #define UBOOT_ITB_OFFSET_FSPI \ (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) #ifdef CONFIG_FSPI_CONF_HEADER -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) #else -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif
@@ -53,8 +53,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index cd47d842ffc7..41ab9307793f 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -38,8 +38,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 58e165c35a7b..28ce834769c3 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -29,8 +29,8 @@ "splblk=0x42\0" \ BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index f532c1052f5d..85fd5e2371f9 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Initial environment variables */ @@ -75,8 +75,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 415248eadfc5..204fc4b31647 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define MEM_LAYOUT_ENV_SETTINGS \ @@ -23,8 +23,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 8857bc7c598b..024b86c7f1d0 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \ @@ -45,8 +45,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 628bb5813ff1..4633843d1bbb 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \ @@ -43,8 +43,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a169be35a492..a585cbf87e44 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 62bcef5eecdb..5443022b04c7 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -11,8 +11,8 @@ #include <asm/arch/imx-regs.h>
/* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index d394762e3bb2..738677ff37cd 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -50,8 +50,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 3e995c972172..d67bad8971dd 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -11,7 +11,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -52,8 +52,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 1943a24b79db..58f7dc6518c1 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,7 +12,7 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ @@ -131,8 +131,8 @@ "fi;\0"
/* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 6GB or 4G DDR */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 7d360583c416..e79aa5707537 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 271376cb9fc8..4df98e3f3735 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -46,8 +46,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 672a9fa7a342..aa29e7884f9e 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -52,8 +52,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index dd354b0265de..3b4cd6562235 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -84,8 +84,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index fe27ac36a3b1..2e2e5ed43cde 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 592df2795b13..d313bdc2a448 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x22040000 @@ -50,8 +50,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 077a4d843dcd..895c50f60253 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -124,8 +124,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index a2c004880a7e..e180387c687a 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -22,6 +22,6 @@ * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index d1a7dab37c55..84228676c7fd 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -29,6 +29,6 @@ * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 2459fe24e24a..f83429082ac7 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -23,7 +23,7 @@ #define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ DMAMEM_SZ_ALL) /* For SPL */ -#define CONFIG_SYS_UBOOT_START 0x202403FD +#define CFG_SYS_UBOOT_START 0x202403FD /* For SPL ends */
#endif /* __IMXRT1170_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 8d0458d1d63f..7a55c6aeefc6 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -6,7 +6,7 @@ * Common ARM Integrator configuration settings */
-#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */
/* * The ARM boot monitor initializes the board. @@ -41,6 +41,6 @@ * - SIB block * - U-Boot environment */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CFG_SYS_FLASH_BASE 0x24000000
/* Timeout values in ticks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index c8457d97161a..6bee098d6a8c 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -17,10 +17,10 @@ #include "integrator-common.h"
/* Integrator/AP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
/* Flash settings */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ +#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
/*----------------------------------------------------------------------- * PCI definitions diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index bf09510d02f6..25bb41ebc46c 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -17,7 +17,7 @@ #include "integrator-common.h"
/* Integrator CP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
#define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104 diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2a0b0c7163a7..e66f994a375f 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -18,14 +18,14 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ -#define CONFIG_SYS_FLASH_BASE 0x000000000 +#define CFG_SYS_FLASH_BASE 0x000000000
/* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif
/* HyperFlash related configuration */ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index e690ef959060..ab204c62b7d6 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,10 +21,10 @@
/* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif
/* U-Boot general configuration */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 35cf27a2eb90..cc5ec219b8db 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -13,7 +13,7 @@ * Miscellaneous configurable options */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 888bb2981f7b..f64c0eee1bb5 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -1,34 +1,34 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS +#define CFG_SYS_SICRL SICRL_IRQ_CKS
-#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ DDRCDR_NZ_MAXZ | \ DDRCDR_M_ODR)
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ODT_WR_CFG | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860242 +#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ @@ -37,7 +37,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -46,7 +46,7 @@ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ @@ -54,7 +54,7 @@ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index fb43fb81bc07..5c9f912383da 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -1,6 +1,6 @@ /* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 64
/* * High Level Configuration Options @@ -9,34 +9,34 @@ /* * System IO Setup */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
/** * DDR RAM settings */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ +#define CFG_SYS_DDR_SDRAM_CFG (\ SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (\ +#define CFG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL (\ +#define CFG_SYS_DDR_INTERVAL (\ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860452 +#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 (\ +#define CFG_SYS_DDR_TIMING_0 (\ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ @@ -46,7 +46,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -55,7 +55,7 @@ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 (\ +#define CFG_SYS_DDR_TIMING_2 (\ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ @@ -64,11 +64,11 @@ (5 << TIMING_CFG2_CPO_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000
/* EEprom support */
/* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CFG_SYS_PAXE_BASE 0xA0000000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index db1daee13633..e6a3613b7a24 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -9,7 +9,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ +#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0 @@ -22,15 +22,15 @@ /* * The reserved memory */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CFG_SYS_FLASH_BASE 0xF0000000
/* Reserve 768 kB for Mon */
/* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* * Init Local Bus Memory Controller: * @@ -44,21 +44,21 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/* I2C */ #define CFG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ {1, {I2C_NULL_HOP} } }
#if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif
/* @@ -66,7 +66,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* * Environment diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index b5913ed70003..7307c495c38e 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,8 +9,8 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h"
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ @@ -19,24 +19,24 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS
/* * IFC Definitions */ /* NOR Flash Definitions */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_TE | \ CSPR_MSEL_NOR | \ @@ -63,18 +63,18 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* NAND Flash Definitions */ #define CFG_SYS_NAND_BASE 0x68000000 @@ -110,40 +110,40 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */ -#define CONFIG_SYS_QRIO_BASE 0x70000000 -#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE +#define CFG_SYS_QRIO_BASE 0x70000000 +#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
-#define CONFIG_SYS_CSPR2_EXT (0x00) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define CFG_SYS_CSPR2_EXT (0x00) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_20 | \ CSOR_GPCM_BCTLD) -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ FTIM0_GPCM_TEADC(0x8) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x6)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) -#define CONFIG_SYS_CS2_FTIM3 0x04000000 +#define CFG_SYS_CS2_FTIM3 0x04000000
/* * Serial Port @@ -155,11 +155,11 @@ */
#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {1, {I2C_NULL_HOP} }, \ } @@ -205,12 +205,12 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ "set_fdthigh=true\0" \ @@ -238,6 +238,6 @@ "ethrotate=no\0" \ ""
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#endif diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index dbf038cefa03..e152714b1169 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -25,10 +25,10 @@ #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
/* Application IFC CS4 MRAM */ -#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS #define SYS_MRAM_CSPR_EXT (0x0f) -#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \ CSPR_PORT_SIZE_8 | /* 8 bit */ \ CSPR_MSEL_GPCM | /* msel = gpcm */ \ CSPR_V /* bank is valid */) @@ -44,14 +44,14 @@ FTIM2_GPCM_TCH(0x2) | \ FTIM2_GPCM_TWP(0x8)) #define SYS_MRAM_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT -#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR -#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK -#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR -#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 -#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 -#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 -#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 +#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CFG_SYS_CSPR4 SYS_MRAM_CSPR +#define CFG_SYS_AMASK4 SYS_MRAM_AMASK +#define CFG_SYS_CSOR4 SYS_MRAM_CSOR +#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
/* Application IFC CS6: BFTIC */ #define SYS_BFTIC_BASE 0xd0000000 @@ -73,20 +73,20 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_BFTIC_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT -#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR -#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK -#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR -#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 -#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 -#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 -#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 +#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
/* Application IFC CS7 PAXE */ -#define CONFIG_SYS_PAXE_BASE 0xd8000000 -#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define CFG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE) #define SYS_PAXE_CSPR_EXT (0x0f) -#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ CSPR_V) /* valid */ @@ -102,14 +102,14 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_PAXE_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT -#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR -#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK -#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR -#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 -#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 -#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 -#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 +#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CFG_SYS_CSPR7 SYS_PAXE_CSPR +#define CFG_SYS_AMASK7 SYS_PAXE_AMASK +#define CFG_SYS_CSOR7 SYS_PAXE_CSOR +#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
/* PRST */ #define KM_BFTIC4_RST 0 @@ -145,25 +145,25 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */ -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS +#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS
/* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -189,12 +189,12 @@ * IFC Definitions */ /* NOR flash on IFC CS0 */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ - CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0x0f) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ @@ -217,18 +217,18 @@ FTIM2_NOR_TWPH(0x6)) #define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* More NOR Flash params */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/ #define CFG_SYS_NAND_BASE 0xfa000000 @@ -266,23 +266,23 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define CFG_SYS_QRIO_BASE 0xfb000000 +#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE) #define SYS_QRIO_CSPR_EXT (0x0f) -#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ @@ -300,28 +300,28 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) #define SYS_QRIO_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT -#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR -#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK -#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 +#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CFG_SYS_CSPR2 SYS_QRIO_CSPR +#define CFG_SYS_AMASK2 SYS_QRIO_AMASK +#define CFG_SYS_CSOR2 SYS_QRIO_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* * Serial Port - controlled on board with jumper J8 @@ -331,7 +331,7 @@ */ #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif
#ifndef __ASSEMBLY__ @@ -351,30 +351,30 @@ int get_scl(void); #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
/* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CFG_SYS_RGMII2_PHY_ADDR 0x11
/* * Hardware Watchdog @@ -387,7 +387,7 @@ int get_scl(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration @@ -412,12 +412,12 @@ int get_scl(void); __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ "set_fdthigh=true\0" \ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index b95402987472..2be996aaaf08 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -12,7 +12,7 @@ #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" @@ -26,7 +26,7 @@ /** * KMCOGE5NE has 512 MB RAM */ -#define CONFIG_SYS_DDR_CS0_CONFIG (\ +#define CFG_SYS_DDR_CS0_CONFIG (\ CSCONFIG_EN | \ CSCONFIG_AP | \ CSCONFIG_ODT_WR_ONLY_CURRENT | \ @@ -35,7 +35,7 @@ CSCONFIG_COL_BIT_10)
/* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 4245875e39e4..910fc1b2cb25 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -16,7 +16,7 @@ #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h"
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index e2808ec02dc1..6fcacdb0c664 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -16,10 +16,10 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 73b595176219..80a32304606a 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -19,8 +19,8 @@ #define PHYS_SDRAM_SIZE (SZ_4G) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000
/* Board and environment settings */ #define CONFIG_HOSTNAME "kontron-mx8mm" diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 9b452818c1e1..2abcb849a281 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -61,8 +61,8 @@ BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index bbf0761814b4..9c3174d0e02c 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -12,17 +12,17 @@
/* we don't have secure memory unless we have a BL31 */ #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#undef CONFIG_SYS_MEM_RESERVE_SECURE +#undef CFG_SYS_MEM_RESERVE_SECURE #endif
/* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 967de66f3c9d..c551585a2062 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -68,8 +68,8 @@ #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index de1fc0bfa4c6..136e228682a6 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -87,8 +87,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 9b70eed46f7c..828f91096344 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ #if defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_I2C_G762_ADDR 0x3e +#define CFG_SYS_I2C_G762_ADDR 0x3e #endif #endif /* CONFIG_CMD_I2C */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index bee064c6f385..2664982715f1 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -17,10 +17,10 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/* * Memory Info @@ -38,7 +38,7 @@ */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/* * U-Boot general configuration diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 3a2c508ffacf..11b3fa6c857d 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -79,8 +79,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b9134508853b..f16c7e912217 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -26,7 +26,7 @@ #endif
/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 }
/* RAM */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index d1ebd99ae144..721da818633a 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -88,8 +88,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* FLASH and environment organization */
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 07124370775b..7598e54ed2b1 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,10 +10,10 @@ #include <asm/arch/stream_id_lsch2.h> #include <linux/sizes.h>
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 54555b34dd47..e772c019077d 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -17,7 +17,7 @@ */
#ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x08 @@ -47,7 +47,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 49a77fd6b6bb..b058308ecdbe 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -41,8 +41,8 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* * Serial Port @@ -104,7 +104,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1f5a80ff085a..5494b71e2b21 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) @@ -19,8 +19,8 @@
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -30,16 +30,16 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -61,10 +61,10 @@ #define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/* * NAND Flash Definitions @@ -111,7 +111,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -131,96 +131,96 @@ #define QIXIS_PWR_CTL2 0x21 #define QIXIS_PWR_CTL2_PCTL 0x2
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80)
/* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ FTIM0_GPCM_TEADC(0xe) | \ FTIM0_GPCM_TEAHC(0xe)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ FTIM2_GPCM_TCH(0xe) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif
#if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif
/* @@ -296,7 +296,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 495460661150..bc9eac700e98 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/* XHCI Support - enabled by default */
@@ -56,8 +56,8 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() @@ -141,7 +141,7 @@ "bootm $load_addr#$board\0"
/* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d77224934c01..f1ccb5fc0840 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -59,18 +59,18 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -94,52 +94,52 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA #endif
/* CPLD */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
/* * Serial Port @@ -298,7 +298,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 064c4f069cbd..bdd3951e85f4 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -13,10 +13,10 @@ /* Link Definitions */
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* * SMP Definitinos diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 253911518669..228fb122f5f3 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -17,7 +17,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 1 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 5 @@ -35,19 +35,19 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif
/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB
/* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index e7b2543b7301..5c134612576c 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,7 +10,7 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0
/* Store environment at top of flash */
@@ -21,7 +21,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_LBMAP_MASK 0xe0 #define QIXIS_LBMAP_SHIFT 0x5 @@ -39,12 +39,12 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e940dff99889..b4048744b1ea 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
@@ -82,14 +82,14 @@ #if defined(CONFIG_TFABOOT) || \ (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -104,7 +104,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 87751f786c8b..dab57382eddf 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -39,13 +39,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -66,10 +66,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA
/* * NAND Flash Definitions @@ -125,7 +125,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -143,130 +143,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80)
/* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif
#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 76251fde57cc..12c4853ea963 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -21,7 +21,7 @@ #define CFG_SYS_NOR_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -41,11 +41,11 @@ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA
/* * NAND Flash Definitions @@ -91,97 +91,97 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/* * Environment diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ce254d8b3f12..cac30e4679eb 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
@@ -68,7 +68,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 8402eac4184c..58ae0fb0a6c1 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,7 +8,7 @@
#include "ls1046a_common.h"
-#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000
/* * NAND Flash Definitions @@ -48,14 +48,14 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
/* EEPROM */ #define I2C_RETIMER_ADDR 0x18 @@ -67,8 +67,8 @@
/* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CFG_SYS_RTC_BUS_NUM 0
/* * Environment diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d565492f1d1c..553ae841caba 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -33,14 +33,14 @@ /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -58,13 +58,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -86,10 +86,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA
/* * NAND Flash Definitions @@ -145,7 +145,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -163,130 +163,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80)
/* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif
#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 0df689159892..f3904e7b3f7b 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -16,7 +16,7 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 #endif
#define CFG_SYS_NAND_BASE 0x7e800000 @@ -55,46 +55,46 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index f8eaee881d06..bacc84f629ae 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -30,10 +30,10 @@ #define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos */ @@ -64,18 +64,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -92,12 +92,12 @@ unsigned long long get_qixis_addr(void);
/* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/* * Carve out a DDR region which will not be used by u-boot/Linux @@ -107,7 +107,7 @@ unsigned long long get_qixis_addr(void); */
#if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif
/* Miscellaneous configurable options */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b75d4ccf5cfd..d84622f32259 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -22,27 +22,27 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -59,13 +59,13 @@ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #endif
@@ -101,7 +101,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 #define QIXIS_QMAP_SHIFT 5 @@ -127,8 +127,8 @@ #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -139,9 +139,9 @@
#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) #else -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) #endif /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ @@ -155,102 +155,102 @@ #define SYS_FPGA_CS_FTIM3 0x0
#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #endif #endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/* * I2C bus multiplexer @@ -281,7 +281,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#ifdef CONFIG_FSL_DSPI #if !defined(CONFIG_TFABOOT) && \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 27510adae677..187b3072f02e 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -20,17 +20,17 @@
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
-#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -44,12 +44,12 @@ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif
@@ -85,7 +85,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 @@ -107,8 +107,8 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -117,8 +117,8 @@ | CSPR_MSEL_GPCM \ | CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ @@ -132,36 +132,36 @@
#if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define I2C_MUX_CH_VOL_MONITOR 0xA /* Voltage monitor on channel 2*/ @@ -191,7 +191,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #endif
#ifndef SPL_NO_ENV diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 21c097ecbbdf..18defd5e5a63 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -17,10 +17,10 @@ /* Link Definitions */
#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/* * SMP Definitinos @@ -56,18 +56,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -84,13 +84,13 @@ unsigned long long get_qixis_addr(void);
/* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 /* For LS2085A */ -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/* * Carve out a DDR region which will not be used by u-boot/Linux @@ -99,7 +99,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif
/* Miscellaneous configurable options */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7315790f1fe1..067587b53c5d 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -10,10 +10,10 @@ #include "ls2080a_common.h"
#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#define CFG_SYS_I2C_IFDR_DIV 0x7e #endif
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -25,27 +25,27 @@ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -61,13 +61,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif
#define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -119,92 +119,92 @@ #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/* * I2C @@ -229,7 +229,7 @@ */ #define RTC #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index daca3be16c51..32a119487234 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,17 +32,17 @@
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -58,13 +58,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif
#define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -113,70 +113,70 @@ #define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#ifdef CONFIG_TARGET_LS2081ARDB #define QIXIS_QMAP_MASK 0x07 @@ -197,7 +197,7 @@ * I2C */ #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@ -212,10 +212,10 @@ */ #define RTC #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #else #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif
#define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ad85e2de6eda..bbee9df404a1 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -10,15 +10,15 @@ #include <asm/arch/config.h> #include <asm/arch/soc.h>
-#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CFG_SYS_FLASH_BASE 0x20000000
/* DDR */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CFG_SYS_SDRAM_SIZE 0x200000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -42,22 +42,22 @@
/* Serial Port */ #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) -#define CONFIG_SYS_SERIAL0 0x21c0000 -#define CONFIG_SYS_SERIAL1 0x21d0000 -#define CONFIG_SYS_SERIAL2 0x21e0000 -#define CONFIG_SYS_SERIAL3 0x21f0000 +#define CFG_SYS_SERIAL0 0x21c0000 +#define CFG_SYS_SERIAL1 0x21d0000 +#define CFG_SYS_SERIAL2 0x21e0000 +#define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1, \ + (void *)CFG_SYS_SERIAL2, \ + (void *)CFG_SYS_SERIAL3 }
/* MC firmware */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/* * Carve out a DDR region which will not be used by u-boot/Linux @@ -66,7 +66,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif
/* I2C bus multiplexer */ @@ -75,10 +75,10 @@
/* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Qixis */ -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66
/* USB */
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 4e8a90485960..9f891064bd5d 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h"
/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0
/* MAC/PHY configuration */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index bb9239cc5996..58c0ff36571e 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h"
/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 4 +#define CFG_SYS_RTC_BUS_NUM 4
/* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index b70abb013f47..157688ef7d7a 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -11,7 +11,7 @@ /* USB */
/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0
/* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index cbdb2fa1357e..f87bbf7ccf32 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -21,8 +21,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* * U-Boot general configurations @@ -58,13 +58,13 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
/* * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif
/* @@ -77,7 +77,7 @@ #endif
/* LVDS display */ -#define CONFIG_SYS_LDB_CLOCK 33260000 +#define CFG_SYS_LDB_CLOCK 33260000 #define CONFIG_IMX_VIDEO_SKIP
/* IIM Fuses */ diff --git a/include/configs/malta.h b/include/configs/malta.h index c9aee00cd357..65f4b05649b2 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -28,7 +28,7 @@ #endif #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* * Serial driver @@ -38,9 +38,9 @@ * Flash configuration */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +# define CFG_SYS_FLASH_BASE 0xffffffffbe000000 #else -# define CONFIG_SYS_FLASH_BASE 0xbe000000 +# define CFG_SYS_FLASH_BASE 0xbe000000 #endif
/* diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 8aa3b0cd808c..7c401a2cfd6c 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,7 +9,7 @@
#include "mx6_common.h"
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000)
/* * Below defines are set but NOT really used since we by @@ -24,12 +24,12 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #define CONFIG_FLASH_VERIFY
/* NOR Flash MTD */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 @@ -116,7 +116,7 @@ "nor_img_addr=0x11000000\0" \ "nor_img_file=core-image-lwn-mccmon6.nor\0" \ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \ "nor_img_size=0x02000000\0" \ "factory_script_file=factory.scr\0" \ "factory_load_script=" \ @@ -215,8 +215,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 2422cbf9f0b6..9e480fe0558e 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -18,8 +18,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment configs */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 2e07886c194b..d190e4b50392 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -28,8 +28,8 @@ */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
/* Misc CPU related */
@@ -47,8 +47,8 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 139b5bca108e..edd2466caa98 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -13,7 +13,7 @@
/* uart */ /* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ +# define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CONFIG_HOSTNAME "microblaze-generic" @@ -95,6 +95,6 @@
/* SPL part */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
#endif /* __CONFIG_H */ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ac5ff9289a52..cfe926c0a141 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -14,7 +14,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 @@ -46,8 +46,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 65cd6f5bc4c2..d5bd49263484 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -10,13 +10,13 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7620_H */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1211bb474880..7c8c67f44697 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -13,7 +13,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x800000 +#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* MMC */ #define MMC_SUPPORTS_TUNING @@ -27,10 +27,10 @@ #endif
/* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 }
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7621_H */ diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index e5d60e1cd2b1..8c297266d8b1 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -10,10 +10,10 @@ #define __MT7622_H
/* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 9c5034f5f086..9df2715fc7dc 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -10,7 +10,7 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 +#define CFG_SYS_INIT_SP_OFFSET 0x80000
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -19,14 +19,14 @@ #endif
/* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 }
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7628_H */ diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index d330adbc01b9..bfa44aacc726 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -18,7 +18,7 @@ /* Defines for SPL */
#define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 249f0b9662d0..14c885ec55c5 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -10,10 +10,10 @@ #define __MT7981_H
/* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 990e411a6406..0c41af1fc329 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -10,10 +10,10 @@ #define __MT7986_H
/* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index d15941660abc..3a35527da10d 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -10,7 +10,7 @@ #define __MT8512_H
/* Uboot definition */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
#define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e45bfd76b6e1..fa275d61d185 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,13 +32,13 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif
-#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE) +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 9c4038be8b04..5c9620371e3c 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -11,7 +11,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 }
/* Default Env vars */ @@ -37,6 +37,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 325000000 +#define CFG_SYS_TCLK 325000000
#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 7641b5622194..9bfc48c52d90 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,7 +15,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 358e06fd2079..beac3ae6496d 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -9,14 +9,14 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 }
/* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 2229980db370..3c99b70a2bb1 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -113,12 +113,12 @@ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON +#define CFG_SYS_DDR_CLKSEL 0 +#define CFG_SYS_CLKTL_CBCDR 0x59E35100 +#define CFG_SYS_MAIN_PWR_ON
/*----------------------------------------------------------------------- * environment organization diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index e84bac67ef72..2bc462cc37ef 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -61,8 +61,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9e837a388337..b52e70c95a04 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -24,7 +24,7 @@ /* PMIC Controller */ #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */ @@ -96,8 +96,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* Framebuffer and LCD */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 52ff7b00b436..7160654eb30c 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -87,7 +87,7 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -97,8 +97,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* FLASH and environment organization */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 431455675444..245530aa640b 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,7 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif
#endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 3c4ba095e4e7..12741c08de58 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -86,8 +86,8 @@
/* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 9c160c41ece6..f6d3b2eeb9cf 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 711b5a334aad..5e95e430c49f 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -140,8 +140,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 3fdf829e9686..1a2160cce594 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,7 +16,7 @@ #define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
#include "mx6sabre_common.h"
@@ -26,7 +26,7 @@ #endif
#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #endif
#define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3c2621d8c91a..358d9f47c0f3 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a3a12aeb3900..6632e4ea29ce 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM_SIZE SZ_2G
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index f0e239fdb6eb..0dd40563c29b 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -79,8 +79,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index a0f9c537e5dd..6f5dffe4fbb8 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -107,8 +107,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 8199b4b8319e..cb1019bd56a7 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -109,8 +109,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 827385c65e2a..4154d328dedf 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -103,8 +103,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index c39b3572b84b..6c165521f7a0 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -82,8 +82,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 362de482f575..85922fa436cb 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -18,7 +18,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */ #define LPUART_BASE LPUART4_RBASE @@ -48,8 +48,8 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 9ef1eea5e61d..99e01896c71b 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -15,7 +15,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */ #define LPUART_BASE LPUART4_RBASE @@ -92,7 +92,7 @@ "bootz; " \ "fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 9d6b3d404844..5df080ade4a2 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -46,11 +46,11 @@ /* Memory sizes */
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CFG_SYS_INIT_RAM_ADDR 0x00000000 #if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (32 * 1024) #elif defined(CONFIG_MX28) -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (128 * 1024) #endif
/* Point initial SP in SRAM so SPL can use it too. */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index cdd12866ac0a..a32fcd57f8fc 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -23,8 +23,8 @@ #define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9d0981131647..dd7f9513199c 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -91,8 +91,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9732039ef126..5701732b9aeb 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -47,7 +47,7 @@ */ #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
/* USB device configuration */ #define CONFIG_USB_DEVICE @@ -64,7 +64,7 @@ * Board ONENAND Info. */
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BASE ONENAND_MAP
/* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -149,7 +149,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/* * Physical Memory Map @@ -161,8 +161,8 @@ */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CFG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CFG_SYS_INIT_RAM_SIZE 0x800
/* * Attached kernel image diff --git a/include/configs/novena.h b/include/configs/novena.h index 8d39d75a42bc..6f588f99c34b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -31,8 +31,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* I2C */ #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 080c659b6ecb..09c4ddb6646b 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nsim.h b/include/configs/nsim.h index b930a538640d..013a3491a39f 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -12,8 +12,8 @@ * Memory configuration */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_256M
/* diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 5ac951a370a4..ea1edab9fc12 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -8,8 +8,8 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index b475354bbc6d..c0ea9e852dce 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,10 +8,10 @@ #define __OCTEON_COMMON_H__
#if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000 +#define CFG_SYS_INIT_SP_OFFSET 0x20180000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 +#define CFG_SYS_INIT_SP_OFFSET 0x00180000 #endif
#define CFG_SYS_SDRAM_BASE 0xffffffff80000000 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index ce8ea583fa10..8b00a2792150 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,7 +14,7 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0890f51eff28..f4e23bbb0f30 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -20,7 +20,7 @@
/* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 6eec955e88f7..8bb8521f1c1c 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -25,7 +25,7 @@
/* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 10f6ba63601a..a6b5e55b5415 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -66,8 +66,8 @@ BOOTENV
/* OneNAND config */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) +#define CFG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 6001037ae886..389553775100 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -144,9 +144,9 @@
/* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif
-#define CONFIG_SYS_FLASH_SIZE 0x4000000 +#define CFG_SYS_FLASH_SIZE 0x4000000
#endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 883cc0b99c9e..1634db860640 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,8 +37,8 @@
/* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 +#define CFG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CFG_SYS_I2C_TCA642X_ADDR 0x22
/* Enabled commands */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 5b0d87a33679..788a1113868b 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,9 +17,9 @@ /* * SoC Configuration */ -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/* * Memory Info @@ -32,7 +32,7 @@
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -44,17 +44,17 @@ */
/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ -#define CONFIG_SYS_DA850_PLL0_PLLM 18 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 18 +#define CFG_SYS_DA850_PLL1_PLLM 21
/* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -64,9 +64,9 @@ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -76,7 +76,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -85,21 +85,21 @@ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/* * Flash & Environment diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 53889d699b26..e42a736136bc 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -15,8 +15,8 @@
/* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB */ #ifdef CONFIG_USB_EHCI_MX6 diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h index d155e553e20d..c96deda61d77 100644 --- a/include/configs/p1_p2_bootsrc.h +++ b/include/configs/p1_p2_bootsrc.h @@ -7,11 +7,11 @@
#include <linux/stringify.h>
-#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) -#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required" #endif
-#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1
#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) #define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 14d702e1efeb..e8b752785b4d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -83,19 +83,19 @@ #endif
#ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) #else -#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) @@ -118,8 +118,8 @@ */ #define CONFIG_L2_CACHE
-#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 @@ -130,40 +130,40 @@ #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif #define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000003f +#define CFG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CFG_SYS_DDR_CS1_BNDS 0x0040007f +#define CFG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CFG_SYS_DDR_INIT_ADDR 0x00000000 +#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CFG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CFG_SYS_DDR_SR_CNTR 0x00000000 +#define CFG_SYS_DDR_RCW_1 0x00000000 +#define CFG_SYS_DDR_RCW_2 0x00000000 +#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CFG_SYS_DDR_CONTROL_2 0x04401050 +#define CFG_SYS_DDR_TIMING_4 0x00220001 +#define CFG_SYS_DDR_TIMING_5 0x03402400 + +#define CFG_SYS_DDR_TIMING_3 0x00020000 +#define CFG_SYS_DDR_TIMING_0 0x00330004 +#define CFG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CFG_SYS_DDR_CLK_CTRL 0x03000000 +#define CFG_SYS_DDR_MODE_1 0x40461520 +#define CFG_SYS_DDR_MODE_2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL 0x0C300000 #endif
/* @@ -186,23 +186,23 @@ * Local Bus Definitions */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CFG_SYS_FLASH_BASE 0xec000000 #else -#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CFG_SYS_FLASH_BASE 0xef000000 #endif
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Nand Flash */ @@ -241,42 +241,42 @@ #endif #endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CFG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif /* CPLD config size: 1Mb */
/* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" -#define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#define CFG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE #endif
/* The size of the VSC7385 firmware image */ @@ -292,18 +292,18 @@ */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -315,15 +315,15 @@ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x29} } #endif
/* @@ -331,8 +331,8 @@ */
#define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CFG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_PCA9557_ADDR 0x18
/* enable read and write access to EEPROM */
@@ -397,7 +397,7 @@ */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif
@@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
/* * Environment Configuration diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 85cedde09884..2a1660bf188d 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -35,8 +35,8 @@ #define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index f7e36f22ce87..4421e740d9ea 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -37,8 +37,8 @@ #define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 586cddf41848..5c2ff5d02ee7 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -119,8 +119,8 @@ #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index cf705dcb1972..3674e4cddaed 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -16,8 +16,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */ #define ENV_MMC \ diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index e08d94141297..1b72739d143d 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -13,23 +13,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* CLIPS FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */ #define WCOM_CLIPS_RST 0 diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index 9a7669c940b4..e4bcae5bb5e1 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -12,23 +12,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* PAXK FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */ #define KM_LIU_RST 0 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index ac68c933a06e..7f73117ac1c8 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -60,8 +60,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index aedaf806e5e7..11a833bb1276 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -59,8 +59,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index d9abbbc28b37..3cc2a693ceee 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -18,9 +18,9 @@ * Memory Layout */ /* Initial RAM for temporary stack, global data */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index fc2cab960c67..9e6c210c40b4 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 22b4976d722f..8af8883fad64 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f5b9eed2bcd9..7028264d7220 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -94,8 +94,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 91baff963862..f9301a5524b9 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -63,8 +63,8 @@
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 3fbddd903a3f..a233fb8ed746 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -22,47 +22,47 @@ #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000
/* clocks */ /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -76,10 +76,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -88,37 +88,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -139,10 +139,10 @@
/* NOR flash */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000
#define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index c1f6334d6a1a..9fd897958a4f 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -22,14 +22,14 @@ #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
/* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ @@ -38,43 +38,43 @@
#if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ +#define CFG_SYS_MATRIX_EBI0CSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +#define CFG_SYS_SDRC_TR_VAL1 0x3AA /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -88,10 +88,10 @@ (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -100,37 +100,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -142,7 +142,7 @@
/* NOR flash, if populated */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -166,7 +166,7 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 4a0a16818ed0..686411eee2ea 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -16,8 +16,8 @@ #define __CONFIG_H
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -53,9 +53,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302
#endif diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 365fdd30c08c..518d7a3639c5 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,10 +7,10 @@ #define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ +#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif
-#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) +#define CFG_SYS_BOOTMAPSZ (0x30 << 20) #define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index bee1ef649488..2b25c31b1d8d 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -9,8 +9,8 @@ #define __PRESIDIO_ASIC_H
/* Generic Timer Definitions */ -#define CONFIG_SYS_TIMER_RATE 25000000 -#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 +#define CFG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMER_COUNTER 0xf4321008
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. @@ -18,7 +18,7 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000
-#define CONFIG_SYS_TIMER_BASE 0xf4321000 +#define CFG_SYS_TIMER_BASE 0xf4321000
/* Use external clock source */ #define PRESIDIO_APB_CLK 125000000 @@ -26,11 +26,11 @@
/* Cortina Serial Configuration */ #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) -#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 PER_UART0_CFG -#define CONFIG_SYS_SERIAL1 PER_UART1_CFG +#define CFG_SYS_SERIAL0 PER_UART0_CFG +#define CFG_SYS_SERIAL1 PER_UART1_CFG
/* SDRAM Bank #1 */ #define DDR_BASE 0x00000000 @@ -58,7 +58,7 @@
/* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC - #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 58020ae95b1d..c41bb341d82e 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-qcs404.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index e7c810957d6d..aa9cae017d9a 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -12,39 +12,39 @@ /* Needed to fill the ccsrbar pointer */
/* Virtual address to CCSRBAR */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR 0xe0000000 /* Physical address should be a function call */ #ifndef __ASSEMBLY__ extern unsigned long long get_phys_ccsrbar_addr_early(void); -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) -#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #endif
/* Virtual address to a temporary map if we need it (max 128MB) */ -#define CONFIG_SYS_TMPVIRT 0xe8000000 +#define CFG_SYS_TMPVIRT 0xe8000000
/* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* RTC */ #define CONFIG_RTC_PT7C4338 @@ -58,7 +58,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/* * Environment Configuration diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index f6ee7201eba1..bad74cc620d6 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -10,12 +10,12 @@ #define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* * NOR Flash ( Spantion S29GL256P ) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BASE (0xA0000000) +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 606a0a7ecde1..a86180ead576 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -15,14 +15,14 @@ #endif
/* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 }
#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 585307259780..e9cbd2538240 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -18,7 +18,7 @@ #define GICC_BASE 0xF1020000
/* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b4c19727478e..a4cae697181d 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,7 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000
#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index fac27a7d27c6..302546630ac6 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,7 +8,7 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 6889ba591b3d..58ad62afe165 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,7 +8,7 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 4aa7e0449dbc..6b55c57dd770 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,7 +9,7 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0xff700000
diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 2c24944d9c3d..e3549275138b 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -17,14 +17,14 @@
/* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER \ +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER \ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif
/* Memory layout */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares * the RAM, and uses a configurable portion at the top. We tell U-Boot that a diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 76836add3027..84a5ae6965dd 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,10 +10,10 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CFG_SYS_TIMER_BASE 0x10350020 +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8)
#define CFG_SYS_SDRAM_BASE 0x60000000
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index ed891ab22a98..3d49d52b381c 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -124,6 +124,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0
-#define CONFIG_SYS_ONENAND_BASE 0xB0000000 +#define CFG_SYS_ONENAND_BASE 0xB0000000
#endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 614d04fda072..06be9c0f6528 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -87,7 +87,7 @@ "mmcrootpart=3\0" \ "opts=always_resume=1"
-#define CONFIG_SYS_ONENAND_BASE 0x0C000000 +#define CFG_SYS_ONENAND_BASE 0x0C000000
#ifndef __ASSEMBLY__ void universal_spi_scl(int bit); diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 41e52546ed32..2e422cd241e9 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __SALVATOR_X_H */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 75302bf5c05d..f44ce909b918 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -10,8 +10,8 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 22813d4c5448..27b39ebf4174 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H__
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 79f354d2e6cc..d62146e77972 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -11,8 +11,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SPL */
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index f826eab9ff2a..1979cb366e54 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 01ed1a3c8e7d..a072b21dfb86 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -11,8 +11,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 2e3c1ea40063..bf3c92bdf396 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3f58928565ff..4f579ad9c561 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -27,7 +27,7 @@
/* NOR flash */ #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif
/* SDRAM */ diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 68fa31fe76fd..59f13edbc850 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -9,8 +9,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x60000000 #define CFG_SYS_SDRAM_SIZE 0x20000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index a3b2a7926fd8..f69fd0ed39c3 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -30,7 +30,7 @@ #define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200}
#ifndef SANDBOX_NO_SDL diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index af5fe27e68bd..f7cdd5a19568 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 31552f4619d7..5a001716fb01 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -35,7 +35,7 @@
#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d2bc73a400e5..794475942a23 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -36,8 +36,8 @@ */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
/* misc settings */
@@ -87,8 +87,8 @@ * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Defines for SPL */
@@ -102,11 +102,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK (198656000/2) +#define CFG_SYS_MASTER_CLOCK (198656000/2) #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x2060bf09 -#define CONFIG_SYS_MCKR 0x100 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10483f0e +#define CFG_SYS_AT91_PLLA 0x2060bf09 +#define CFG_SYS_MCKR 0x100 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10483f0e
#endif /* __CONFIG_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 64963eebe5ce..ffa1a1fcb0ef 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -88,7 +88,7 @@ * Boot configuration */
-#define CONFIG_SYS_ONENAND_BASE 0xE7100000 +#define CFG_SYS_ONENAND_BASE 0xE7100000
/* * Ethernet Contoller driver diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 44b9109d442f..14f9cf560286 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -39,7 +39,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 9b1cb372ece7..b7aa49ce435e 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -15,16 +15,16 @@ #include <linux/sizes.h>
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
/* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* Mem test settings */
diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 95516800793a..afca7e18e9be 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -15,7 +15,7 @@ * Clocks */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CFG_SYS_TIMERBASE OMAP34XX_GPT2
#define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -55,7 +55,7 @@ #define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 }
/* diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 49883ea7a3cc..35c777b774ef 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/* * L4 OSC1 Timer 0 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 261ae56c1dce..29b4b22b3988 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -10,7 +10,7 @@ #include <linux/stringify.h>
/* Eternal oscillator */ -#define CONFIG_SYS_TIMER_RATE 40000000 +#define CFG_SYS_TIMER_RATE 40000000
/* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ @@ -21,7 +21,7 @@ * the last two bytes of the 128 bytes large NVRAM in the * RTC which begin at address 0x20 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Environment settings */
diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 7012097276c7..aa13878177ef 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 7ef7c5da8289..bbbdea6664ca 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -12,12 +12,12 @@ */ #define PHYS_SDRAM_1 0x0 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) #endif
@@ -27,9 +27,9 @@ * at this address to not overwrite the bootcounter by checking, if the * bootcounter address is located in the internal SRAM. */ -#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ - (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE))) +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE))) #endif
/* @@ -48,16 +48,16 @@ /* * Cache */ -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifndef CONFIG_SYS_TIMER_RATE -#define CONFIG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4) +#ifndef CFG_SYS_TIMER_RATE +#define CFG_SYS_TIMER_RATE 25000000 #endif #endif
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 9403e2f4306d..47089f312d2c 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -26,8 +26,8 @@ /* * U-Boot run time memory configurations */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_SIZE 0x40000
/* * U-Boot environment configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c628860eac74..0a2d5815170b 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,20 +42,20 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xE0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */ @@ -63,46 +63,46 @@
/* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CFG_SYS_DDR_TIMING_0 0x00260802 +#define CFG_SYS_DDR_TIMING_1 0x3935D322 +#define CFG_SYS_DDR_TIMING_2 0x14904CC8 +#define CFG_SYS_DDR_MODE 0x00480432 +#define CFG_SYS_DDR_INTERVAL 0x030C0100 +#define CFG_SYS_DDR_CONFIG_2 0x04400000 +#define CFG_SYS_DDR_CONFIG 0xC3008000 +#define CFG_SYS_DDR_CLK_CONTROL 0x03800000 #define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/* * Flash on the LocalBus */ -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } +#define CFG_SYS_FLASH0 0xFE000000 +#define CFG_SYS_FLASH1 0xFC000000 +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 }
-#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */ +#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_SYS_FPGA_BASE 0xc0000000 +#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70)
/* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CFG_SYS_LIME_BASE 0xc8000000
/* * General PCI @@ -137,7 +137,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 008aa5001072..de0f48b79a15 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -54,8 +54,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 3c70856fc70a..a5987c5e17a1 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,7 @@ */
/* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_PL310_BASE 0xa0412000 +#define CFG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */ #define BOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 806323e375df..9294d57ca84e 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000
-#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ +#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
/* Environment */
@@ -22,7 +22,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 51f69010b179..afd7d50428bf 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -7,13 +7,13 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
/* * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 221b7abe1ad7..c8aad47966fe 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -10,15 +10,15 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
/* * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 55e70ce92508..573a6b179561 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -10,15 +10,15 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 12MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M +#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
/* * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index c7d6d9368a2e..14e883a35892 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,15 +10,15 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 6MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M +#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
/* * Configuration of the external SDRAM memory */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -33,7 +33,7 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO)
/* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index f959fcf26f3e..67e6a3a19d21 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -11,11 +11,11 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index c8688e9ca7b5..4786eb001bc1 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -11,11 +11,11 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index f7fa8c51d8e9..e667fe6f6ac2 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -11,11 +11,11 @@ #include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) +#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M)
-#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CFG_SYS_FLASH_BASE 0x90000000
-#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index d71114931427..c259a616133b 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index c51022b40d26..ad8126f61039 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -15,7 +15,7 @@ #include <configs/stm32mp13_common.h>
/* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000, 4000000}
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index f78ce41ed854..c9cfadd9ce0b 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 6bdc286cfca2..38b5aa7319cf 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -14,7 +14,7 @@ #include <configs/stm32mp15_common.h>
/* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000 }
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 234327e017bc..faff8d6ed6d1 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -10,7 +10,7 @@
#define CONFIG_HOSTNAME "stmark2"
-#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0
#define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) @@ -34,24 +34,24 @@ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ ""
-#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#define CFG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000
/* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) +#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32)
/* * Start addresses for the final memory configuration @@ -61,7 +61,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CONFIG_SYS_DRAM_TEST +#define CFG_SYS_DRAM_TEST
#if defined(CONFIG_CF_SBF) #define CONFIG_SERIAL_BOOT @@ -75,7 +75,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment @@ -83,22 +83,22 @@ */
/* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ +#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \ CF_CACR_DEC | CF_CACR_DDCM_P | \ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) +#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 12)
#endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index b2dcb6058b10..7eadb6d421e5 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -6,7 +6,7 @@
#ifndef __CONFIG_STV0991_H #define __CONFIG_STV0991_H -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 @@ -16,8 +16,8 @@ /* user interface */
/* MISC */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */
/* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e1a66f53ff56..1677aafad03b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -62,9 +62,9 @@ * is known yet. * H6 has SRAM A1 at 0x00020000. */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index daa9bbec88a7..699268900109 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -6,7 +6,7 @@ #define __CONFIG_H
/* Timers for fasp(TIMCLK) */ -#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ +#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
/* * SDRAM (for initialize) @@ -28,7 +28,7 @@ */
/* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51
/* Serial (pl011) */ #define UART_CLK (62500000) @@ -36,8 +36,8 @@ #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 1aba986e1e6a..baaf94e2dd54 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -29,8 +29,8 @@ */
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
@@ -49,8 +49,8 @@ * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -136,11 +136,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x202A3F01 -#define CONFIG_SYS_MCKR 0x1300 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10193F05 +#define CFG_SYS_AT91_PLLA 0x202A3F01 +#define CFG_SYS_MCKR 0x1300 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10193F05
#endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index cd1309b3b889..1318f5e5ee44 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,8 +12,8 @@ * Memory configuration */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_128M
/* diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 2d8bde1cee86..f6544f6226c7 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -15,10 +15,10 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_BOOTMAPSZ 0x10000000 +#define CFG_SYS_BOOTMAPSZ 0x10000000
/* Framebuffer */ #define CONFIG_IMX_HDMI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7e764b0000b0..66cf7ae5847e 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,8 @@
/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif
/* Environment */ @@ -42,11 +42,11 @@
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#ifndef CONFIG_ARM64 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
/* Defines for SPL */ #endif diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 04772c9e4efc..57724719a9d6 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -10,7 +10,7 @@ #include "ls1088a_common.h"
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd" #define SD_BOOTCOMMAND "run distro_bootcmd" diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 1f60b9b49790..7becf1eb7cb4 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -8,7 +8,7 @@
#define MEM_BASE 0x00500000
-#define CONFIG_SYS_LOWMEM_BASE MEM_BASE +#define CFG_SYS_LOWMEM_BASE MEM_BASE
/* Link Definitions */
@@ -22,8 +22,8 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) #define GICR_BASE (0x801000002000) -#define CONFIG_SYS_SERIAL0 0x87e024000000 -#define CONFIG_SYS_SERIAL1 0x87e025000000 +#define CFG_SYS_SERIAL0 0x87e024000000 +#define CFG_SYS_SERIAL1 0x87e025000000
/* Miscellaneous configurable options */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e5b23d2a54ca..03849adb5abe 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -74,7 +74,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 4a7c3d5b4495..7b04292d2188 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -25,7 +25,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000
/* * NS16550 Configuration diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 00eb329faa83..ed17b4292096 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 65abb187d96d..ea45bba409cb 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -14,7 +14,7 @@ /* SoC Configuration */
/* Memory Configuration */ -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#ifdef CONFIG_SYS_MALLOC_F_LEN @@ -44,7 +44,7 @@ #endif
/* SPI Configuration */ -#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
/* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR @@ -176,9 +176,9 @@ #include <asm/arch/hardware.h> #include <asm/arch/clock.h> #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) +#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk) #endif
#endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index d282c3956e0c..36a05b6896ea 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,7 +27,7 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CFG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200}
/* Select serial console configuration */ @@ -46,7 +46,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/* SPL */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index ce50e35d8d4b..9a068e261402 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 #endif
/* Get CPU defs */ @@ -20,7 +20,7 @@ #include <asm/arch/omap.h>
/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE
#include <configs/ti_armv7_omap.h>
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index c49c177390b3..37ab2e446724 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,7 +17,7 @@ #define __CONFIG_TI_OMAP5_COMMON_H
/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE
#include <linux/stringify.h>
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index a609aa3a2aa9..0f28690612ab 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -41,6 +41,6 @@ * Else boot FIT image. */
-#define CONFIG_SYS_FLASH_BASE 0x0C000000 +#define CFG_SYS_FLASH_BASE 0x0C000000
#endif /* __TOTAL_COMPUTE_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 137898199177..24943c8dcfb8 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -8,8 +8,8 @@
#define CFG_SYS_SDRAM_BASE 0xa0000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* * Serial Port diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f8e3a2d017a3..9c3454add463 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -269,8 +269,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* * All the defines above are for the TQMa6 SoM diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 999130600ccb..ce897fcd9325 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -17,8 +17,8 @@
/* Config on-board RTC */ #define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_RTC_BUS_NUM 2 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ #define CONFIG_RTC_DS1337_NOOSC
diff --git a/include/configs/trats.h b/include/configs/trats.h index 23dcf20c1f4e..5bd0ca2a9645 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,7 +12,7 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif
/* TRATS has 4 banks of DRAM */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 9c6433ccfd87..cef563696bde 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,7 +13,7 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif
/* TRATS2 has 4 banks of DRAM */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 4ca8eafc9143..fdb420ed874e 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -9,7 +9,7 @@ #define _CONFIG_TURRIS_MOX_H
#define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index c1e80b44c854..fac8c1eeb4e2 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -50,8 +50,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index f73092661a1d..0e0d5b5b3e4c 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -58,8 +58,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index a977271c1e6e..ab199bc726a6 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a57ecffd5961..8cd81f1cdddc 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -37,7 +37,7 @@
#if !defined(CONFIG_ARM64) /* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_RATE 1000000 #endif
#define CFG_SYS_NAND_REGS_BASE 0x68100000 @@ -162,11 +162,11 @@ LINUXBOOT_ENV_SETTINGS \ BOOTENV
-#define CONFIG_SYS_BOOTMAPSZ 0x20000000 +#define CFG_SYS_BOOTMAPSZ 0x20000000
/* only for SPL */
/* subtract sizeof(struct legacy_img_hdr) */ -#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) +#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40)
#endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index d2fd23e1d91d..657dbadd3396 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -17,8 +17,8 @@ #include <asm/hardware.h>
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* * Hardware drivers @@ -28,8 +28,8 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index e944e78603e7..da68d7a0da99 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -61,7 +61,7 @@ #define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index d9e5dfaceaf8..b03159805c15 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,7 +10,7 @@
/* Onboard devices */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index b209d97e5ecb..18ac6b2b0895 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -53,8 +53,8 @@ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \ "${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 1b9f2ca26f69..88839a6e561a 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD @@ -65,8 +65,8 @@ "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 9a46d50c6f39..30c1f5025b05 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -254,9 +254,9 @@ BOOTENV
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 #else -#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) +#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) #endif
#endif /* __VEXPRESS_AEMV8_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index de571f63ee12..e8b6acf8b8fe 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -112,16 +112,16 @@ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
-#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CFG_SYS_SERIAL0 V2M_UART0 +#define CFG_SYS_SERIAL1 V2M_UART1
/* Miscellaneous configurable options */ #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) @@ -135,7 +135,7 @@
/* additions for new relocation code */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -164,7 +164,7 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
/* FLASH and environment organization */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CFG_SYS_FLASH_SIZE 0x04000000
/* Timeout values in ticks */
@@ -177,6 +177,6 @@ */
/* Store environment at top of flash */ -#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } +#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 }
#endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 7b526f725af6..14e6b2bac91c 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -124,7 +124,7 @@ #define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index df0e269b5d20..9f72bdde8167 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -21,7 +21,7 @@ #define CONFIG_USART_ID 30
/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -31,7 +31,7 @@
#ifdef CONFIG_CMD_MMC #define ATMEL_BASE_MMCI 0xfc000000 -#define CONFIG_SYS_MMC_CLK_OD 500000 +#define CFG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7555d97c8148..ab5cd5cf6365 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 38b940d35ea8..43050d61c37e 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */ #define CFG_SYS_NS16550_CLK 40000000 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 3acef2213273..23027b1d3d9e 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -90,8 +90,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h index cba215c379fd..56c90aa1032e 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -85,8 +85,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 32555c9b6af1..065006f912c8 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -42,7 +42,7 @@ */
/* driver configuration */ -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CFG_SYS_MAX_NAND_CHIPS 1 #define CFG_SYS_NAND_BASE MLC_NAND_BASE
/* diff --git a/include/configs/x530.h b/include/configs/x530.h index a0162cab2190..dee87cb77325 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,7 +13,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f76c1f8be0fd..3e17b53dde2d 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -30,7 +30,7 @@ * CPU Features */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024)
/*----------------------------------------------------------------------- * Environment configuration diff --git a/include/configs/xea.h b/include/configs/xea.h index 87f628d4ab8e..b432ab2dc8ef 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -16,9 +16,9 @@
/* SPL */
-#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M -#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K -#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K +#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CFG_SYS_SPI_ARGS_OFFS SZ_512K +#define CFG_SYS_SPI_ARGS_SIZE SZ_32K
/* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8caf5394ed46..ee3130ed3277 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -15,7 +15,7 @@ #define GICR_BASE 0xF9080000
/* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUID for capsule updatable firmware image */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 0ccd38b7e692..7d77189693e2 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -20,7 +20,7 @@ #define GICR_BASE 0xF9060000
/* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 }
#if defined(CONFIG_CMD_DFU) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 60f007a10fcd..efe241df97eb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,7 @@ #define GICC_BASE 0xF9020000
/* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUIDs for capsule updatable firmware images */ @@ -192,9 +192,9 @@ #endif
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 -# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 -# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 +# define CFG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CFG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CFG_SYS_SPI_ARGS_SIZE 0xa0000 #endif
/* u-boot is like dtb */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index b6bc402a7e97..3a7b7e03d6af 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -10,13 +10,13 @@
/* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Boot configuration */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Extend size of kernel image for uncompression */
diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 613ed9595532..3e604894ad48 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_SIZE (128 << 20)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment is in stored in the eMMC boot partition */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 8739bb24841e..9201dac7abce 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -21,12 +21,12 @@ /*===================*/
#if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ +#define CFG_SYS_MEMORY_BASE \ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_IO_BASE 0xf0000000 #else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_IO_BASE 0x90000000 #define CONFIG_MAX_MEM_MAPPED 0x10000000 #endif
@@ -100,16 +100,16 @@ */
/* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ +#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
/* * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): * Bits 0..5 set the lower 6 bits of the default ethernet MAC. * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to * the base of flash * (when on/1) or to the base of RAM (when off/0). */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ #define FPGAREG_MAC_WIDTH 6 #define FPGAREG_MAC_MASK 0x3f @@ -120,8 +120,8 @@ #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
/* Force hard reset of board by writing a code to this register */ -#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ -#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ +#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ +#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
/*====================*/ /* Serial Driver Info */ @@ -137,25 +137,25 @@ /*======================*/
#define CONFIG_ETHBASE 00:50:C2:13:6f:00 -#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) -#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) +#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000) +#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
/*=====================*/ /* Flash & Environment */ /*=====================*/
#ifdef CONFIG_XTFPGA_LX60 -# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x08000000) #elif defined(CONFIG_XTFPGA_KC705) -# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) +# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x00000000) #else -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x08000000) #endif
/* diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2d6522af81b8..b8c142fed37b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -11,12 +11,12 @@
/* Cache options */ #ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_PL310_BASE 0xf8f02000 +# define CFG_SYS_PL310_BASE 0xf8f02000 #endif
#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 -#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#define CFG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
/* GUIDs for capsule updatable firmware images */ #define XILINX_BOOT_IMAGE_GUID \ @@ -29,7 +29,7 @@
/* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Ethernet driver */ @@ -188,8 +188,8 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000
/* Extend size of kernel image for uncompression */ @@ -200,10 +200,10 @@
/* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 -#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ - CONFIG_SYS_SPI_ARGS_SIZE) +#define CFG_SYS_SPI_ARGS_OFFS 0x200000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS (CFG_SYS_SPI_ARGS_OFFS + \ + CFG_SYS_SPI_ARGS_SIZE) #endif
/* SP location before relocation, must use scratch RAM */ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index cb982c2e74f6..ac6e8c4ff867 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -14,9 +14,9 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_INIT_RAM_ADDR -#undef CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CFG_SYS_INIT_RAM_ADDR +#undef CFG_SYS_INIT_RAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000
#endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 07a46a4a1b0a..c701dc1084b9 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -66,7 +66,7 @@ int get_mc_boot_status(void); int get_dpl_apply_status(void); int is_lazy_dpl_addr_valid(void); void fdt_fixup_mc_ddr(u64 *base, u64 *size); -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void); #endif u64 mc_get_dram_addr(void); diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 9f243cd94577..de1e70a6d0ba 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -801,7 +801,7 @@ void init_final_memctl_regs(void); #define IFC_RREGS_64KOFFSET (64*1024)
#define IFC_FCM_BASE_ADDR \ - ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) + ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR)
#define get_ifc_cspr_ext(i) \ (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) diff --git a/include/i2c.h b/include/i2c.h index c07e60b04bd0..51390f8fd84f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -633,10 +633,10 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if !defined(CONFIG_SYS_I2C_MAX_HOPS) +#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 -#define CONFIG_SYS_I2C_MAX_HOPS 0 +#define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ @@ -644,8 +644,8 @@ void i2c_early_init_f(void); #endif
/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#if !defined(CFG_SYS_RTC_BUS_NUM) +#define CFG_SYS_RTC_BUS_NUM 0 #endif
struct i2c_adapter { @@ -705,7 +705,7 @@ struct i2c_next_hop {
struct i2c_bus_hose { int adapter; - struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; + struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; }; #define I2C_NULL_HOP {{-1, ""}, 0, 0} extern struct i2c_bus_hose i2c_bus[]; @@ -931,12 +931,12 @@ unsigned int i2c_get_bus_speed(void); * completely to new multibus support. */ #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) -# if !defined(CONFIG_SYS_MAX_I2C_BUS) -# define CONFIG_SYS_MAX_I2C_BUS 2 +# if !defined(CFG_SYS_MAX_I2C_BUS) +# define CFG_SYS_MAX_I2C_BUS 2 # endif # define I2C_MULTI_BUS 1 #else -# define CONFIG_SYS_MAX_I2C_BUS 1 +# define CFG_SYS_MAX_I2C_BUS 1 # define I2C_MULTI_BUS 0 #endif
diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 053b68a10a4a..636734dd3c63 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,38 +26,38 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS + * to a value that is the same as CFG_SYS_CCSRBAR. */
-#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#ifdef CFG_SYS_CCSRBAR_PHYS +#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \ +CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead." #endif
#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#undef CFG_SYS_CCSRBAR_PHYS_HIGH +#undef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif
-#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT #endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW)
#endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fe474803253..ea8d17d557e4 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -16,9 +16,9 @@ * platform register addresses */
-#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) +#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008)
/* * l2cr values. Look in config_<BOARD>.h for the actual setup diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 1321da191028..52cd1c4dbc4e 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -147,8 +147,8 @@ struct cfi_pri_hdr { u8 minor_version; } __attribute__((packed));
-#ifndef CONFIG_SYS_FLASH_BANKS_LIST -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#ifndef CFG_SYS_FLASH_BANKS_LIST +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif
/* diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index e75c3fa32891..0f6f5c23dee6 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -21,7 +21,7 @@
#define MVEBU_MMC_CLOCKRATE_MAX 50000000 #define MVEBU_MMC_BASE_DIV_MAX 0x7ff -#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 #define MVEBU_MMC_BASE_FAST_CLK_200 200000000
diff --git a/include/post.h b/include/post.h index ec03556e917e..867a66f3007a 100644 --- a/include/post.h +++ b/include/post.h @@ -142,7 +142,7 @@ extern int memory_post_test(int flags);
#define CONFIG_SYS_POST_RTC 0x00000001 #define CONFIG_SYS_POST_WATCHDOG 0x00000002 -#define CONFIG_SYS_POST_MEMORY 0x00000004 +#define CFG_SYS_POST_MEMORY 0x00000004 #define CONFIG_SYS_POST_CPU 0x00000008 #define CONFIG_SYS_POST_I2C 0x00000010 #define CONFIG_SYS_POST_CACHE 0x00000020 @@ -163,7 +163,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CODEC 0x00200000 #define CONFIG_SYS_POST_COPROC 0x00400000 #define CONFIG_SYS_POST_FLASH 0x00800000 -#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000 +#define CFG_SYS_POST_MEM_REGIONS 0x01000000
#endif /* CONFIG_POST */
diff --git a/include/spl.h b/include/spl.h index 3eb27de61666..fb8c279d7264 100644 --- a/include/spl.h +++ b/include/spl.h @@ -470,7 +470,7 @@ void spl_set_bd(void); * spl_set_header_raw_uboot() - Set up a standard SPL image structure * * This sets up the given spl_image which the standard values obtained from - * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START, * CONFIG_TEXT_BASE. * * @spl_image: Image description to set up diff --git a/include/system-constants.h b/include/system-constants.h index 07c3505e8f58..0d6b71b35a06 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,10 +12,10 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif #endif
diff --git a/include/tca642x.h b/include/tca642x.h index bda86c1ed883..c0a3cef5bd5f 100644 --- a/include/tca642x.h +++ b/include/tca642x.h @@ -41,13 +41,13 @@ enum { #define TCA642X_DIR_IN 1
/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_ADDR -#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#ifndef CFG_SYS_I2C_TCA642X_ADDR +#define CFG_SYS_I2C_TCA642X_ADDR (~0) #endif
/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM +#define CFG_SYS_I2C_TCA642X_BUS_NUM (0) #endif
struct tca642x_bank_info { diff --git a/include/tsec.h b/include/tsec.h index 72f34851ad19..de279b211718 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,8 @@
#define RCTRL_PROM 0x00000008
-#ifndef CONFIG_SYS_TBIPA_VALUE -# define CONFIG_SYS_TBIPA_VALUE 0x1f +#ifndef CFG_SYS_TBIPA_VALUE +# define CFG_SYS_TBIPA_VALUE 0x1f #endif
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN diff --git a/lib/time.c b/lib/time.c index f3aaf472d103..82350260eac4 100644 --- a/lib/time.c +++ b/lib/time.c @@ -25,21 +25,21 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SYS_TIMER_RATE +#ifdef CFG_SYS_TIMER_RATE /* Returns tick rate in ticks per second */ ulong notrace get_tbclk(void) { - return CONFIG_SYS_TIMER_RATE; + return CFG_SYS_TIMER_RATE; } #endif
-#ifdef CONFIG_SYS_TIMER_COUNTER +#ifdef CFG_SYS_TIMER_COUNTER unsigned long notrace timer_read_counter(void) { #ifdef CONFIG_SYS_TIMER_COUNTS_DOWN - return ~readl(CONFIG_SYS_TIMER_COUNTER); + return ~readl(CFG_SYS_TIMER_COUNTER); #else - return readl(CONFIG_SYS_TIMER_COUNTER); + return readl(CFG_SYS_TIMER_COUNTER); #endif }
@@ -47,8 +47,8 @@ ulong timer_get_boot_us(void) { ulong count = timer_read_counter();
-#ifdef CONFIG_SYS_TIMER_RATE - const ulong timer_rate = CONFIG_SYS_TIMER_RATE; +#ifdef CFG_SYS_TIMER_RATE + const ulong timer_rate = CFG_SYS_TIMER_RATE;
if (timer_rate == 1000000) return count; diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 8deac75ebb05..71dad7b8c026 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -138,7 +138,7 @@ #include <post.h> #include <watchdog.h>
-#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS) +#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS)
DECLARE_GLOBAL_DATA_PTR;
@@ -535,4 +535,4 @@ int memory_post_test(int flags) return ret; }
-#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */ +#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ diff --git a/post/tests.c b/post/tests.c index 5c019b643df9..fc36e738f731 100644 --- a/post/tests.c +++ b/post/tests.c @@ -109,7 +109,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_RTC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY { "Memory test", "memory", @@ -118,7 +118,7 @@ struct post_test post_list[] = &memory_post_test, NULL, NULL, - CONFIG_SYS_POST_MEMORY + CFG_SYS_POST_MEMORY }, #endif #if CONFIG_POST & CONFIG_SYS_POST_CPU @@ -286,7 +286,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_FLASH }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS +#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", @@ -295,7 +295,7 @@ struct post_test post_list[] = &memory_regions_post_test, NULL, NULL, - CONFIG_SYS_POST_MEM_REGIONS + CFG_SYS_POST_MEM_REGIONS }, #endif }; diff --git a/tools/envcrc.c b/tools/envcrc.c index bce77902476d..a021c785aeed 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -23,13 +23,13 @@
#if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +# define CONFIG_ENV_ADDR (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif # ifndef CONFIG_ENV_OFFSET -# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE) # endif # if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) +# define CONFIG_ENV_ADDR_REDUND (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) # endif # ifndef CONFIG_ENV_SIZE # define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, 16 Nov 2022 at 11:11, Tom Rini trini@konsulko.com wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
board/freescale/ls1043aqds/ls1043aqds.c | 48 +++++++------- board/freescale/ls1043ardb/ls1043ardb.c | 32 +++++----- board/freescale/ls1046aqds/ls1046aqds.c | 48 +++++++------- board/freescale/ls1088a/ls1088a.c | 26 ++++---- include/configs/P1010RDB.h | 42 ++++++------- include/configs/T102xRDB.h | 38 +++++------ include/configs/T104xRDB.h | 48 +++++++------- include/configs/T208xQDS.h | 60 +++++++++--------- include/configs/T208xRDB.h | 36 +++++------ include/configs/T4240RDB.h | 48 +++++++------- include/configs/km/pg-wcom-ls102xa.h | 24 +++---- include/configs/kmcent2.h | 34 +++++----- include/configs/ls1021aqds.h | 60 +++++++++--------- include/configs/ls1021atwr.h | 24 +++---- include/configs/ls1043aqds.h | 84 ++++++++++++------------- include/configs/ls1043ardb.h | 64 +++++++++---------- include/configs/ls1046aqds.h | 84 ++++++++++++------------- include/configs/ls1088aqds.h | 66 +++++++++---------- include/configs/ls1088ardb.h | 26 ++++---- include/configs/ls2080aqds.h | 66 +++++++++---------- include/configs/ls2080ardb.h | 38 +++++------ 21 files changed, 498 insertions(+), 498 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Nov 16, 2022 at 01:10:25PM -0500, Tom Rini wrote:
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org
For the series, (and v2 of #3) applied to u-boot/next, thanks!
participants (4)
-
Andre Przywara -
Heinrich Schuchardt -
Simon Glass -
Tom Rini