[U-Boot-Users] [PATCH]ppc_4xx:netstal HCU5 board: added various fixes and POST
Moved some code to nestal/common/nm_bsp.c. Added support for the vxWorks EDR. Enable trace for Lauterbach, if present. Added support for POST.
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com --- board/netstal/hcu5/Makefile | 3 +- board/netstal/hcu5/README.txt | 3 - board/netstal/hcu5/hcu5.c | 201 ++++++++++++++--------------------------- board/netstal/hcu5/init.S | 63 +++++++++---- board/netstal/hcu5/sdram.c | 74 +++++++-------- 5 files changed, 149 insertions(+), 195 deletions(-)
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 27398b9..9645e45 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -23,9 +23,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a
vpath hcu_flash.c ../common +vpath nm_bsp.c ../common
# NOBJS : Netstal common objects -NOBJS = hcu_flash.o +NOBJS = hcu_flash.o nm_bsp.o COBJS = $(BOARD).o sdram.o SOBJS = init.o
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt index 3118da9..c205108 100644 --- a/board/netstal/hcu5/README.txt +++ b/board/netstal/hcu5/README.txt @@ -10,9 +10,6 @@ TODO: - Fix RTS/CTS problem (HW?) CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after Switching to interrupt driven serial input mode -- Make vxWorks start from u-boot. Possible reasons - - Does vxWorks need an entry for the Machine Check interrupt like this - tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
Caveats: -------- diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 8c23e4d..9b3aeed 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,12 +22,14 @@ #include <asm/processor.h> #include <ppc440.h> #include <asm/mmu.h> -#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
void hcu_led_set(u32 value); - +int board_with_pci(void); +extern void nm_show_print(int generation, int index, int hw_capabilities); +extern void set_params_for_sw_install(int install_requested, char *board_name ); +extern void common_misc_init_r(void); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#undef BOOTSTRAP_OPTION_A_ACTIVE @@ -42,23 +44,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083
-#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) #define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) - -#define DEFAULT_ETH_ADDR "ethaddr" -/* ethaddr for first or etha1ddr for second ethernet */ - -enum { - /* HW_GENERATION_HCU1 is no longer supported */ - HW_GENERATION_HCU2 = 0x10, - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_HCU5 = 0x30, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - +#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000) +#define HCU_SW_INSTALL_REQUESTED 0x10
/* * This function is run very early, out of flash, and before devices are @@ -72,7 +61,6 @@ enum {
int board_early_init_f(void) { - u32 reg;
#ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A @@ -172,12 +160,6 @@ int board_early_init_f(void) mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
- /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); - - pci_pre_init(0); - /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350);
@@ -192,33 +174,27 @@ int board_pre_init(void)
#endif
+int sys_install_requested(void) +{ + u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER; + return (*ioValuePtr & HCU_SW_INSTALL_REQUESTED) != 0; +} + int checkboard(void) { - unsigned int j; u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; u16 generation = *boardVersReg & 0xf0; u16 index = *boardVersReg & 0x0f; u32 ecid0, ecid1, ecid2, ecid3;
- printf("Netstal Maschinen AG: "); - if (generation == HW_GENERATION_HCU3) - printf("HCU3: index %d", index); - else if (generation == HW_GENERATION_HCU4) - printf("HCU4: index %d", index); - else if (generation == HW_GENERATION_HCU5) - printf("HCU5: index %d", index); - printf(" HW 0x%02x\n", *hwVersReg & 0xff); + nm_show_print(generation, index, *hwVersReg & 0xff); mfsdr(SDR0_ECID0, ecid0); mfsdr(SDR0_ECID1, ecid1); mfsdr(SDR0_ECID2, ecid2); mfsdr(SDR0_ECID3, ecid3);
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); - for (j = 0;j < 6; j++) { - hcu_led_set(1 << j); - udelay(200 * 1000); - }
return 0; } @@ -239,7 +215,7 @@ void hcu_led_set(u32 value) /*---------------------------------------------------------------------------+ * get_serial_number *---------------------------------------------------------------------------*/ -static u32 get_serial_number(void) +u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE;
@@ -265,60 +241,10 @@ u32 hcu_get_slot(void) *---------------------------------------------------------------------------*/ int misc_init_r(void) { - char *s = getenv(DEFAULT_ETH_ADDR); - char *e; - int i; - u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1;
- for (i = 0; i < 6; ++i) { - gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - if (gd->bd->bi_enetaddr[3] == 0 && - gd->bd->bi_enetaddr[4] == 0 && - gd->bd->bi_enetaddr[5] == 0) { - char ethaddr[22]; - - /* Must be in sync with CONFIG_ETHADDR */ - gd->bd->bi_enetaddr[0] = 0x00; - gd->bd->bi_enetaddr[1] = 0x60; - gd->bd->bi_enetaddr[2] = 0x13; - gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; - gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; - gd->bd->bi_enetaddr[5] = hcu_get_slot(); - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", - gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], - gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], - gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; - printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, - ethaddr, serial); - setenv(DEFAULT_ETH_ADDR, ethaddr); - } - - /* IP-Adress update */ - { - IPaddr_t ipaddr; - char *ipstring; - - ipstring = getenv("ipaddr"); - if (ipstring == 0) - ipaddr = string_to_ip("172.25.1.99"); - else - ipaddr = string_to_ip(ipstring); - if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { - char tmp[22]; - - ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); - ip_to_string (ipaddr, tmp); - printf("%s: enforce %s\n", __FUNCTION__, tmp); - setenv("ipaddr", tmp); - } - } #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -326,12 +252,14 @@ int misc_init_r(void) 0xffffffff, &flash_info[0]);
+#ifdef CFG_ENV_ADDR_REDUND /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif +#endif
/* * USB stuff... @@ -376,13 +304,34 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); - printf("USB: Host(int phy) Device(ext phy)\n");
+ common_misc_init_r(); + set_params_for_sw_install( sys_install_requested(), "hcu5" ); + /* We cannot easily enable trace before, as there are other + * routines messing around with sdr0_pfc1. And I do not need it. + */ + if (mfspr(dbcr0) & 0x80000000) { /* External debugger alive */ + /* enable trace facilty for Lauterback + * CCR0[DAPUIB]=0 Enable broadcast of instruction data + * to auxiliary processor interface + * CCR0[DTB]=0 Enable broadcast of trace information + * SDR0_PFC0[TRE] Trace signals are enabled instead of + * GPIO49-63 + */ + mtspr(ccr0, mfspr(ccr0) &~ 0x00108000); + mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100); + } return 0; } +#ifdef CONFIG_PCI +int board_with_pci(void) +{ + u32 reg; + mfsdr(sdr_pci0, reg); + return (reg & SDR0_XCR_PAE_MASK); +}
-#if defined(CONFIG_PCI) /************************************************************************* * pci_pre_init * @@ -399,53 +348,37 @@ int pci_pre_init(struct pci_controller *hose) { unsigned long addr;
- /*-------------------------------------------------------------------+ - * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. - * Workaround: Disable write pipelining to DDR SDRAM by setting - * PLB0_ACR[WRP] = 0. - *-------------------------------------------------------------------*/ + if (!board_with_pci()) { return 0; }
- /*-------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------*/ + /*------------------------------------------------------------------- + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + *-------------------------------------------------------------------*/ mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); - /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
- /*-------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------*/ + /*------------------------------------------------------------------- + * Set priority for all PLB4 devices to 0. + *-------------------------------------------------------------------*/ mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb4_acr, addr); /* Sequoia */
/*-------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------*/ + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. + * Workaround: Disable write pipelining to DDR SDRAM by setting + * PLB0_ACR[WRP] = 0. + *-------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */ - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ - - /* mtdcr(plb0_acr, addr); */ /* Sequoia */ mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) ; - /* mtdcr(plb1_acr, addr); */ /* Sequoia */ mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
- return 1; + return board_with_pci(); }
/************************************************************************* @@ -458,17 +391,18 @@ int pci_pre_init(struct pci_controller *hose) ************************************************************************/ void pci_target_init(struct pci_controller *hose) { + if (!board_with_pci()) { return; } /*-------------------------------------------------------------+ * Set up Direct MMIO registers *-------------------------------------------------------------*/ - /*-------------------------------------------------------------+ - | PowerPC440EPX PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address - | 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +-------------------------------------------------------------*/ + /*------------------------------------------------------------- + * PowerPC440EPX PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address + * 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + *-------------------------------------------------------------*/ /* PMM0 Mask/Attribute - disabled b4 setting */ out32r(PCIX0_PMM0MA, 0x00000000); out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ @@ -520,12 +454,13 @@ void pci_target_init(struct pci_controller *hose) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; + if (!board_with_pci()) { return; }
- /*---------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------*/ + /*--------------------------------------------------------------- + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + *--------------------------------------------------------------*/ pci_read_config_word(0, PCI_COMMAND, &temp_short); pci_write_config_word(0, PCI_COMMAND, temp_short | PCI_COMMAND_MASTER | diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index f3a379a..2b2dc52 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -39,41 +39,68 @@ tlbtab: tlbtab_start
- /* vxWorks needs this entry for the Machine Check interrupt, */ - tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) +#ifdef CFG_TLB_FOR_BOOT_FLASH + /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */ + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */ + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB#2: TLB-entry for EBC */ + tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* - * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the + * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
- /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) +#else + tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + /* TLB#4: */ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + /* TLB#5: */ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + /* TLB#6: */ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
- /* TLB-entry for EBC (CFG_CPLD) */ - /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ - /* CAN */ - tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - /* IMC + CPLD */ - tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - /* IMC-Fast */ - tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - /* TLB-entry for Internal Registers & OCM */ - tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + /* TLB#7: */ + tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
/*TLB-entry PCI registers*/ + /* TLB#8: */ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for peripherals */ + /* TLB#9: */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- /* TLB for SDRAM will be added by initdram (sdram.c) */ + /* CAN */ + /* TLB#10: */ + tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB#11: CPLD and IMC-Standard 32 MB */ + tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB#12: */ + tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ /* IMC-Fast 32 MB */ + /* TLB#13: */ + tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* TLB#14: */ + tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + +#ifndef CFG_TLB_FOR_BOOT_FLASH + /* TLB#15: */ + tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif tlbtab_end diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index cbb2839..53812f5 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -62,11 +62,8 @@ void dflush(void); #define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ #define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#ifdef CFG_ENABLE_SDRAM_CACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ -#endif +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE + /* disable caching on DDR2 */
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
@@ -157,38 +154,36 @@ static void blank_string(int size) /*---------------------------------------------------------------------------+ * program_ecc. *---------------------------------------------------------------------------*/ -static void program_ecc(unsigned long start_address, unsigned long num_bytes, - unsigned long tlb_word2_i_value) +static void program_ecc(unsigned long start_address, unsigned long num_bytes) { - unsigned long current_address= start_address; - int loopi = 0; u32 val; - char str[] = "ECC generation -"; - char slash[] = "\|/-\|/-"; +#if defined(CONFIG_PRAM) + u32 *magic; + + /* Check whether vxWorks is using EDR logging, if yes zero */ + /* also PostMortem and user reserved memory */ + magic= (u32 *) (start_address + num_bytes + - (CONFIG_PRAM*1024) + sizeof(u32)); + + debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__, + CONFIG_PRAM, + start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32), + magic, *magic); + if (*magic == 0xbeefbabe) + num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; +#endif +
sync(); eieio();
puts(str);
- if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { - /* ECC bit set method for non-cached memory */ - /* This takes various seconds */ - for(current_address = 0; current_address < num_bytes; - current_address += sizeof(u32)) { - *(u32 *)current_address = 0; - if ((current_address % (2 << 20)) == 0) { - putc('\b'); - putc(slash[loopi++ % 8]); - } - } - } else { - /* ECC bit set method for cached memory */ - /* Fast method, no noticeable delay */ - dcbz_area(start_address, num_bytes); - dflush(); - } + /* ECC bit set method for cached memory */ + /* Fast method, no noticeable delay */ + dcbz_area(start_address, num_bytes); + dflush(); blank_string(strlen(str));
/* Clear error status */ @@ -196,7 +191,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/* - * Clear possible errors + * Clear possible ECC errors * If not done, then we could get an interrupt later on when * exceptions are enabled. */ @@ -212,6 +207,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
#endif
+ /*********************************************************************** * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -233,23 +229,22 @@ long int initdram (int board_type) mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020307); switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { - case 0: - dram_size = 128 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ - mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ - mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ - break; case 1: dram_size = 256 * 1024 * 1024 ; mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; + case 0: default: - sdram_panic(INVALID_HW_CONFIG); + dram_size = 128 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ + mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ + mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; } mtsdram(DDR0_07, 0x00090100); + /* * TCPD=200 cycles of clock input is required to lock the DLL. * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); @@ -288,7 +283,7 @@ long int initdram (int board_type) * Program tlb entries for this size (dynamic) */ remove_tlb(CFG_SDRAM_BASE, 256 << 20); - program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
/* * Setup 2nd TLB with same physical address but different virtual @@ -296,14 +291,13 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
- /* Diminish RAM to initialize */ - dram_size = dram_size - 32 ; #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ - program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0); + program_ecc(CFG_DDR_CACHED_ADDR, dram_size); #endif
return (dram_size); } +
On Monday 14 January 2008, Niklaus Giger wrote:
Moved some code to nestal/common/nm_bsp.c. Added support for the vxWorks EDR. Enable trace for Lauterbach, if present. Added support for POST.
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com
board/netstal/hcu5/Makefile | 3 +- board/netstal/hcu5/README.txt | 3 - board/netstal/hcu5/hcu5.c | 201 ++++++++++++++--------------------------- board/netstal/hcu5/init.S | 63 +++++++++---- board/netstal/hcu5/sdram.c | 74 +++++++-------- 5 files changed, 149 insertions(+), 195 deletions(-)
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 27398b9..9645e45 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -23,9 +23,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a
vpath hcu_flash.c ../common +vpath nm_bsp.c ../common
# NOBJS : Netstal common objects -NOBJS = hcu_flash.o +NOBJS = hcu_flash.o nm_bsp.o COBJS = $(BOARD).o sdram.o SOBJS = init.o
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt index 3118da9..c205108 100644 --- a/board/netstal/hcu5/README.txt +++ b/board/netstal/hcu5/README.txt @@ -10,9 +10,6 @@ TODO:
- Fix RTS/CTS problem (HW?) CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after Switching to interrupt driven serial input mode
-- Make vxWorks start from u-boot. Possible reasons
- Does vxWorks need an entry for the Machine Check interrupt like this
tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?Caveats:
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 8c23e4d..9b3aeed 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,12 +22,14 @@ #include <asm/processor.h> #include <ppc440.h> #include <asm/mmu.h> -#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
void hcu_led_set(u32 value);
+int board_with_pci(void); +extern void nm_show_print(int generation, int index, int hw_capabilities); +extern void set_params_for_sw_install(int install_requested, char *board_name ); +extern void common_misc_init_r(void); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#undef BOOTSTRAP_OPTION_A_ACTIVE @@ -42,23 +44,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083
-#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) #define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
-#define DEFAULT_ETH_ADDR "ethaddr" -/* ethaddr for first or etha1ddr for second ethernet */
-enum {
- /* HW_GENERATION_HCU1 is no longer supported */
- HW_GENERATION_HCU2 = 0x10,
- HW_GENERATION_HCU3 = 0x10,
- HW_GENERATION_HCU4 = 0x20,
- HW_GENERATION_HCU5 = 0x30,
- HW_GENERATION_MCU = 0x08,
- HW_GENERATION_MCU20 = 0x0a,
- HW_GENERATION_MCU25 = 0x09,
-};
+#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000) +#define HCU_SW_INSTALL_REQUESTED 0x10
/*
- This function is run very early, out of flash, and before devices are
@@ -72,7 +61,6 @@ enum {
int board_early_init_f(void) {
- u32 reg;
#ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A @@ -172,12 +160,6 @@ int board_early_init_f(void) mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
- /* PCI arbiter enabled */
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg);
- pci_pre_init(0);
- /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350);
@@ -192,33 +174,27 @@ int board_pre_init(void)
#endif
+int sys_install_requested(void) +{
- u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
- return (*ioValuePtr & HCU_SW_INSTALL_REQUESTED) != 0;
You are accessing CPLD registers here, right? Please use the correct accessor functions like in_be16(). And please check for other places where you access CPLD or other peripheral stuff via pointer access. This will break at some time if you don't use the correct access functions.
+}
int checkboard(void) {
- unsigned int j; u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; u16 generation = *boardVersReg & 0xf0; u16 index = *boardVersReg & 0x0f;
Here too. Please fix this.
u32 ecid0, ecid1, ecid2, ecid3;
- printf("Netstal Maschinen AG: ");
- if (generation == HW_GENERATION_HCU3)
printf("HCU3: index %d", index);- else if (generation == HW_GENERATION_HCU4)
printf("HCU4: index %d", index);- else if (generation == HW_GENERATION_HCU5)
printf("HCU5: index %d", index);- printf(" HW 0x%02x\n", *hwVersReg & 0xff);
nm_show_print(generation, index, *hwVersReg & 0xff); mfsdr(SDR0_ECID0, ecid0); mfsdr(SDR0_ECID1, ecid1); mfsdr(SDR0_ECID2, ecid2); mfsdr(SDR0_ECID3, ecid3);
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
for (j = 0;j < 6; j++) {
hcu_led_set(1 << j);udelay(200 * 1000);}
return 0;
} @@ -239,7 +215,7 @@ void hcu_led_set(u32 value)
/*------------------------------------------------------------------------- --+ * get_serial_number
*-------------------------------------------------------------------------- -*/ -static u32 get_serial_number(void) +u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE;
@@ -265,60 +241,10 @@ u32 hcu_get_slot(void)
*-------------------------------------------------------------------------- -*/ int misc_init_r(void) {
char *s = getenv(DEFAULT_ETH_ADDR);
char *e;
int i;
u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1;
for (i = 0; i < 6; ++i) {
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;if (s)s = (*e) ? e + 1 : e;}
if (gd->bd->bi_enetaddr[3] == 0 &&
gd->bd->bi_enetaddr[4] == 0 &&gd->bd->bi_enetaddr[5] == 0) {char ethaddr[22];/* Must be in sync with CONFIG_ETHADDR */gd->bd->bi_enetaddr[0] = 0x00;gd->bd->bi_enetaddr[1] = 0x60;gd->bd->bi_enetaddr[2] = 0x13;gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;gd->bd->bi_enetaddr[5] = hcu_get_slot();sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,ethaddr, serial);setenv(DEFAULT_ETH_ADDR, ethaddr);}
/* IP-Adress update */
{
IPaddr_t ipaddr;char *ipstring;ipstring = getenv("ipaddr");if (ipstring == 0)ipaddr = string_to_ip("172.25.1.99");elseipaddr = string_to_ip(ipstring);if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {char tmp[22];ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();ip_to_string (ipaddr, tmp);printf("%s: enforce %s\n", __FUNCTION__, tmp);setenv("ipaddr", tmp);}}
#ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -326,12 +252,14 @@ int misc_init_r(void) 0xffffffff, &flash_info[0]);
+#ifdef CFG_ENV_ADDR_REDUND /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif +#endif
/* * USB stuff... @@ -376,13 +304,34 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); mtsdr(SDR0_SRST0, 0x00000000);
- printf("USB: Host(int phy) Device(ext phy)\n");
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu5" );
- /* We cannot easily enable trace before, as there are other
* routines messing around with sdr0_pfc1. And I do not need it.*/- if (mfspr(dbcr0) & 0x80000000) { /* External debugger alive */
/* enable trace facilty for Lauterback* CCR0[DAPUIB]=0 Enable broadcast of instruction data* to auxiliary processor interface* CCR0[DTB]=0 Enable broadcast of trace information* SDR0_PFC0[TRE] Trace signals are enabled instead of* GPIO49-63*/mtspr(ccr0, mfspr(ccr0) &~ 0x00108000);mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100);- } return 0;
} +#ifdef CONFIG_PCI +int board_with_pci(void) +{
- u32 reg;
Newline please.
- mfsdr(sdr_pci0, reg);
- return (reg & SDR0_XCR_PAE_MASK);
+}
-#if defined(CONFIG_PCI) /*************************************************************************
- pci_pre_init
@@ -399,53 +348,37 @@ int pci_pre_init(struct pci_controller *hose) { unsigned long addr;
- /*-------------------------------------------------------------------+
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.* Workaround: Disable write pipelining to DDR SDRAM by setting* PLB0_ACR[WRP] = 0.*-------------------------------------------------------------------*/
- if (!board_with_pci()) { return 0; }
- /*-------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.| Set PLB3 arbiter to fair mode.+-------------------------------------------------------------------*/
- /*-------------------------------------------------------------------
* Set priority for all PLB3 devices to 0.* Set PLB3 arbiter to fair mode.*-------------------------------------------------------------------*/
This isn't aligned.
mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr);
/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
/*-------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.+-------------------------------------------------------------------*/
- /*-------------------------------------------------------------------
* Set priority for all PLB4 devices to 0.*-------------------------------------------------------------------*/
/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb4_acr, addr); /* Sequoia */
/*-------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.+-------------------------------------------------------------------*/
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.* Workaround: Disable write pipelining to DDR SDRAM by setting* PLB0_ACR[WRP] = 0.*-------------------------------------------------------------------*/
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
/* mtdcr(plb0_acr, addr); */ /* Sequoia */ mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) ;
/* mtdcr(plb1_acr, addr); */ /* Sequoia */ mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
return 1;
- return board_with_pci();
}
/************************************************************************* @@ -458,17 +391,18 @@ int pci_pre_init(struct pci_controller *hose) ************************************************************************/ void pci_target_init(struct pci_controller *hose) {
- if (!board_with_pci()) { return; } /*-------------------------------------------------------------+
*-------------------------------------------------------------*/
- Set up Direct MMIO registers
- /*-------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.| Map one 1Gig range of PLB/processor addresses to PCI memory space.| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address| 0xA0000000-0xDFFFFFFF| Use byte reversed out routines to handle endianess.| Make this region non-prefetchable.+-------------------------------------------------------------*/
- /*-------------------------------------------------------------
* PowerPC440EPX PCI Master configuration.* Map one 1Gig range of PLB/processor addresses to PCI memory space.* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address* 0xA0000000-0xDFFFFFFF* Use byte reversed out routines to handle endianess.* Make this region non-prefetchable.*-------------------------------------------------------------*/@@ -520,12 +454,13 @@ void pci_target_init(struct pci_controller *hose) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short;
- if (!board_with_pci()) { return; }
- /*---------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.| Enable PowerPC440 EP to be a master on the PCI bus (PMM).| Enable PowerPC440 EP to act as a PCI memory target (PTM).+--------------------------------------------------------------*/
- /*---------------------------------------------------------------
* Write the PowerPC440 EP PCI Configuration regs.* Enable PowerPC440 EP to be a master on the PCI bus (PMM).* Enable PowerPC440 EP to act as a PCI memory target (PTM).*--------------------------------------------------------------*/diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index f3a379a..2b2dc52 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -39,41 +39,68 @@ tlbtab: tlbtab_start
- /* vxWorks needs this entry for the Machine Check interrupt, */
- tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+#ifdef CFG_TLB_FOR_BOOT_FLASH
- /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_G|SA_I ) +
/* TLB#2: TLB-entry for EBC */
tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/*
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off touse the + * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
- /* TLB-entry for PCI Memory */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1,
AC_R|AC_W|SA_G|SA_I ) +#else
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1,
AC_R|AC_W|AC_X|SA_G ) +#endif
- /*
* TLB entries for SDRAM are not needed on this platform.* They are dynamically generated in the SPD DDR(2) detection* routine.*/- /* TLB#4: */ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1,
AC_R|AC_W|SA_G|SA_I ) + /* TLB#5: */ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + /* TLB#6: */ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
- /* TLB-entry for EBC (CFG_CPLD) */
- /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
- /* CAN */
- tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* IMC + CPLD */- tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I ) - /* IMC-Fast */
- tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I ) - /* TLB-entry for Internal Registers & OCM */
- tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
/* TLB#7: */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
/*TLB-entry PCI registers*/
/* TLB#8: */ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for peripherals */
/* TLB#9: */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- /* TLB for SDRAM will be added by initdram (sdram.c) */
- /* CAN */
- /* TLB#10: */
- tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- /* TLB#11: CPLD and IMC-Standard 32 MB */
- tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- /* TLB#12: */
- tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )
/* IMC-Fast 32 MB */- /* TLB#13: */
- tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- /* TLB#14: */
- tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1,
AC_R|AC_W|AC_X|SA_G|SA_I ) + +#ifndef CFG_TLB_FOR_BOOT_FLASH
- /* TLB#15: */
- tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif tlbtab_end diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index cbb2839..53812f5 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -62,11 +62,8 @@ void dflush(void); #define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ #define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#ifdef CFG_ENABLE_SDRAM_CACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ -#endif +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
- /* disable caching on DDR2 */
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
@@ -157,38 +154,36 @@ static void blank_string(int size)
/*------------------------------------------------------------------------- --+ * program_ecc.
*-------------------------------------------------------------------------- -*/ -static void program_ecc(unsigned long start_address, unsigned long num_bytes, - unsigned long tlb_word2_i_value) +static void program_ecc(unsigned long start_address, unsigned long num_bytes) {
- unsigned long current_address= start_address;
- int loopi = 0; u32 val;
- char str[] = "ECC generation -";
- char slash[] = "\|/-\|/-";
+#if defined(CONFIG_PRAM)
- u32 *magic;
- /* Check whether vxWorks is using EDR logging, if yes zero */
- /* also PostMortem and user reserved memory */
- magic= (u32 *) (start_address + num_bytes
- (CONFIG_PRAM*1024) + sizeof(u32));
magic = (...
please. But again I suggest to use the correct functions to access this memory. Here in_be32().
- debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
CONFIG_PRAM,start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),magic, *magic);- if (*magic == 0xbeefbabe)
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;+#endif
sync(); eieio();
puts(str);
- if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
/* ECC bit set method for non-cached memory *//* This takes various seconds */for(current_address = 0; current_address < num_bytes;current_address += sizeof(u32)) {*(u32 *)current_address = 0;if ((current_address % (2 << 20)) == 0) {putc('\b');putc(slash[loopi++ % 8]);}}- } else {
/* ECC bit set method for cached memory *//* Fast method, no noticeable delay */dcbz_area(start_address, num_bytes);dflush();- }
/* ECC bit set method for cached memory */
/* Fast method, no noticeable delay */
dcbz_area(start_address, num_bytes);
dflush(); blank_string(strlen(str));
/* Clear error status */
@@ -196,7 +191,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/*
* Clear possible errors
* Clear possible ECC errors*/
- If not done, then we could get an interrupt later on when
- exceptions are enabled.
@@ -212,6 +207,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
#endif
/***********************************************************************
- initdram -- 440EPx's DDR controller is a DENALI Core
@@ -233,23 +229,22 @@ long int initdram (int board_type) mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020307); switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
- case 0:
dram_size = 128 * 1024 * 1024 ;mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */break;
- case 0: default:
sdram_panic(INVALID_HW_CONFIG);
dram_size = 128 * 1024 * 1024 ;mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */- /*
- TCPD=200 cycles of clock input is required to lock the DLL.
- CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
@@ -288,7 +283,7 @@ long int initdram (int board_type) * Program tlb entries for this size (dynamic) */ remove_tlb(CFG_SDRAM_BASE, 256 << 20);
- program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
/*
- Setup 2nd TLB with same physical address but different virtual
@@ -296,14 +291,13 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
- /* Diminish RAM to initialize */
- dram_size = dram_size - 32 ;
#ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */
- program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
- program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
#endif
return (dram_size); }
-- 1.5.2.5
Please fix and resubmit.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
In message 200801141530.23152.niklausgiger@gmx.ch you wrote:
Moved some code to nestal/common/nm_bsp.c. Added support for the vxWorks EDR. Enable trace for Lauterbach, if present. Added support for POST.
...
- if (mfspr(dbcr0) & 0x80000000) { /* External debugger alive */
/* enable trace facilty for Lauterback
/* * enable trace facilty for Lauterbach ...
- /*-------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.| Set PLB3 arbiter to fair mode.+-------------------------------------------------------------------*/
- /*-------------------------------------------------------------------
* Set priority for all PLB3 devices to 0.* Set PLB3 arbiter to fair mode.*-------------------------------------------------------------------*/
...
- /*-------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.+-------------------------------------------------------------------*/
- /*-------------------------------------------------------------------
* Set priority for all PLB4 devices to 0.*-------------------------------------------------------------------*/
If you change multiline comments, then please do it right. The preferred style for long (multi-line) comments is:
/* * This is the preferred style for multi-line * comments in the Linux kernel source code. * Please use it consistently. * * Description: A column of asterisks on the left side, * with beginning and ending almost-blank lines. */
- /* TLB#12: */
- tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
Here and in some other places: please mind the maximum line length.
Best regards,
Wolfgang Denk
participants (3)
-
Niklaus Giger -
Stefan Roese -
Wolfgang Denk