[U-Boot] [PATCH v2 00/28] tegra: nyan-big: Support chainloading and add documentation
Every now and then someone wants to chain-load U-Boot on a Chromebook. The procedure is not very complicated but there are some oddities.
This series updates a few things with allow U-Boot to start on nyan-big in this way and adds documentation on how to do it. This provides a central place where the procedure on different devices can be documented.
Changes in v2: - Add new patch containing a .its file for chromium - Explain how to create dummy.txt - Add a comment about how to create a protective MBR - Add new patch containing a .its file for chromium - Add instructions and patches for chain-loading into U-Boot on jerry
Simon Glass (28): display_options: Refactor to allow obtaining the banner Allow displaying the U-Boot banner on a video display arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY arm: Rename HCTR to HTCR arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T arm: Disable LPAE if not enabled power: regulator: Add more debugging and fix a missing newline tegra: Init clocks even when SPL did not run tegra: dts: Add cros-ec SPI settings tegra: spi: Wait a little after setting the clocks tegra: nyan-big: Enable the dhrystone benchmark tegra: video: Don't power up the SOR twice tegra: Enable CP15 init tegra: clock: Avoid a divide-by-zero error tegra: nyan-big: Add a .its file for chromium README: Add instructions for chain-loading U-Boot rockchip: Setup default PWM flags rockchip: Fix regualtor typo in veyron rockchip: rk3288: Add error debugging to veyron_init() rockchip: video: Add remove() methods rockchip: video: Take the vop device out of standby rockchip: jerry: Add a .its file for chromium rockchip: rk3288: Convert clock driver to use shifted masks rockchip: Init clocks again when chain-loading rockchip: rk3288: Allow setting up clocks in U-Boot proper rockchip: Enable the video display banner rockchip: jerry: Disable CONFIG_CONSOLE_SCROLL_LINES README: Add instructions for chain-loading U-Boot on jerry
arch/arm/cpu/arm720t/start.S | 6 +- arch/arm/dts/rk3288-veyron-jerry.dts | 2 +- arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 74 +++---- arch/arm/include/asm/arch-tegra/clock.h | 3 + arch/arm/lib/cache-cp15.c | 13 +- arch/arm/mach-rockchip/rk3288-board.c | 39 +++- arch/arm/mach-tegra/board2.c | 3 + arch/arm/mach-tegra/clock.c | 10 +- arch/arm/mach-tegra/tegra124/clock.c | 18 ++ cmd/version.c | 4 +- common/board_r.c | 1 + common/console.c | 15 +- configs/chromebook_jerry_defconfig | 2 +- configs/nyan-big_defconfig | 2 + doc/README.chromium | 252 ++++++++++++++++++++++++ doc/chromium/chromebook_jerry.its | 42 ++++ doc/chromium/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes doc/chromium/nyan-big.its | 42 ++++ drivers/clk/rockchip/clk_rk3288.c | 146 +++++++------- drivers/power/regulator/regulator-uclass.c | 8 +- drivers/pwm/rk_pwm.c | 1 + drivers/spi/tegra114_spi.c | 1 + drivers/video/rockchip/rk_edp.c | 16 +- drivers/video/rockchip/rk_vop.c | 21 +- drivers/video/tegra124/sor.c | 9 + include/configs/rockchip-common.h | 2 + include/configs/tegra-common-post.h | 2 +- include/console.h | 12 ++ include/display_options.h | 15 ++ lib/display_options.c | 21 +- 32 files changed, 656 insertions(+), 135 deletions(-) create mode 100644 doc/README.chromium create mode 100644 doc/chromium/chromebook_jerry.its create mode 100644 doc/chromium/devkeys/kernel.keyblock create mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk create mode 100644 doc/chromium/nyan-big.its
Move the display options code into a separate function so that the U-Boot banner can be obtained from other code. Adjust the 'version' command to use it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
cmd/version.c | 4 +++- include/display_options.h | 15 +++++++++++++++ lib/display_options.c | 21 +++++++++++++++++---- 3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/cmd/version.c b/cmd/version.c index 1be0667f09..15aab5dc18 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -17,7 +17,9 @@ const char __weak version_string[] = U_BOOT_VERSION_STRING;
static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - printf("\n%s\n", version_string); + char buf[DISPLAY_OPTIONS_BANNER_LENGTH]; + + printf(display_options_get_banner(false, buf, sizeof(buf))); #ifdef CC_VERSION_STRING puts(CC_VERSION_STRING "\n"); #endif diff --git a/include/display_options.h b/include/display_options.h index ac44c459b3..90891a817f 100644 --- a/include/display_options.h +++ b/include/display_options.h @@ -56,4 +56,19 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, */ int display_options(void);
+/* Suggested length of the buffer to pass to display_options_get_banner() */ +#define DISPLAY_OPTIONS_BANNER_LENGTH 120 + +/** + * display_options_get_banner() - Get the U-Boot banner as a string + * + * This returns the U-Boot banner string + * + * @newlines: true to include two newlines at the start + * @buf: place to put string + * @size: Size of buf + * @return buf + */ +char *display_options_get_banner(bool newlines, char *buf, int size); + #endif diff --git a/lib/display_options.c b/lib/display_options.c index 29343fc00e..ebf684f43b 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -13,13 +13,26 @@ #include <linux/ctype.h> #include <asm/io.h>
-int display_options (void) +char *display_options_get_banner(bool newlines, char *buf, int size) { + int len; + + len = snprintf(buf, size, "%s%s", newlines ? "\n\n" : "", + version_string); #if defined(BUILD_TAG) - printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG); -#else - printf ("\n\n%s\n\n", version_string); + len += snprintf(buf + len, size - len, ", Build: %s", BUILD_TAG); #endif + len += snprintf(buf + len, size - len, "\n\n"); + + return buf; +} + +int display_options(void) +{ + char buf[DISPLAY_OPTIONS_BANNER_LENGTH]; + + printf(display_options_get_banner(true, buf, sizeof(buf))); + return 0; }
Move the display options code into a separate function so that the U-Boot banner can be obtained from other code. Adjust the 'version' command to use it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
cmd/version.c | 4 +++- include/display_options.h | 15 +++++++++++++++ lib/display_options.c | 21 +++++++++++++++++---- 3 files changed, 35 insertions(+), 5 deletions(-)
Applied to u-boot-dm, thanks!
At present the U-Boot banner is only displayed on the serial console. If this is not visible to the user, the banner does not show. Some devices have a video display which can usefully display this information.
Add a banner which is printed after relocation only on non-serial devices if CONFIG_DISPLAY_BOARDINFO_LATE is defined.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
common/board_r.c | 1 + common/console.c | 15 +++++++++++---- include/console.h | 12 ++++++++++++ 3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c index 5986cd7674..99b5d22c81 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -847,6 +847,7 @@ static init_fnc_t init_sequence_r[] = { #endif console_init_r, /* fully init console as a device */ #ifdef CONFIG_DISPLAY_BOARDINFO_LATE + console_announce_r, show_board_info, #endif #ifdef CONFIG_ARCH_MISC_INIT diff --git a/common/console.c b/common/console.c index 1232808df5..3fcd7ce66b 100644 --- a/common/console.c +++ b/common/console.c @@ -202,7 +202,6 @@ static void console_putc(int file, const char c) } }
-#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER) static void console_puts_noserial(int file, const char *s) { int i; @@ -214,7 +213,6 @@ static void console_puts_noserial(int file, const char *s) dev->puts(dev, s); } } -#endif
static void console_puts(int file, const char *s) { @@ -248,13 +246,11 @@ static inline void console_putc(int file, const char c) stdio_devices[file]->putc(stdio_devices[file], c); }
-#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER) static inline void console_puts_noserial(int file, const char *s) { if (strcmp(stdio_devices[file]->name, "serial") != 0) stdio_devices[file]->puts(stdio_devices[file], s); } -#endif
static inline void console_puts(int file, const char *s) { @@ -699,6 +695,17 @@ static void console_update_silent(void) #endif }
+int console_announce_r(void) +{ + char buf[DISPLAY_OPTIONS_BANNER_LENGTH]; + + display_options_get_banner(false, buf, sizeof(buf)); + + console_puts_noserial(stdout, buf); + + return 0; +} + /* Called before relocation - use serial functions */ int console_init_f(void) { diff --git a/include/console.h b/include/console.h index 3d37f6a53b..511b38e9e7 100644 --- a/include/console.h +++ b/include/console.h @@ -42,6 +42,18 @@ void console_record_reset(void); */ void console_record_reset_enable(void);
+/** + * console_announce_r() - print a U-Boot console on non-serial consoles + * + * When U-Boot starts up with a display it generally does not account itself + * on the display. The banner is emitted on the UART before relocation instead. + * This function prints a banner on devices which (we assume) did not receive + * it before relocation. + * + * @return 0 (meaning no errors) + */ +int console_announce_r(void); + /* * CONSOLE multiplexing. */
At present the U-Boot banner is only displayed on the serial console. If this is not visible to the user, the banner does not show. Some devices have a video display which can usefully display this information.
Add a banner which is printed after relocation only on non-serial devices if CONFIG_DISPLAY_BOARDINFO_LATE is defined.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
common/board_r.c | 1 + common/console.c | 15 +++++++++++---- include/console.h | 12 ++++++++++++ 3 files changed, 24 insertions(+), 4 deletions(-)
Applied to u-boot-dm, thanks!
This option allows skipping the call to lowlevel() while still performing CP15 init. Support this on ARM720T so it can be used with Tegra.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/cpu/arm720t/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 0bb3441fb8..365d8f08cb 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -38,7 +38,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif
@@ -62,7 +63,8 @@ c_runtime_cpu_setup: ************************************************************************* */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit:
mov ip, lr
This option allows skipping the call to lowlevel() while still performing CP15 init. Support this on ARM720T so it can be used with Tegra.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/cpu/arm720t/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
Applied to u-boot-dm, thanks!
This appears to be a typo. Fix it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5122..0f7020a315 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -147,7 +147,7 @@ static inline void mmu_setup(void) #endif
if (is_hyp()) { - /* Set HCTR to enable LPAE */ + /* Set HTCR to enable LPAE */ asm volatile("mcr p15, 4, %0, c2, c0, 2" : : "r" (reg) : "memory"); /* Set HTTBR0 */
This appears to be a typo. Fix it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use instructions which are invalid on ARMv4T. This happens on Tegra since it has an ARMv4T boot CPU. Add a check for the architecture version to allow the code to be built. It will not actually be executed by the boot CPU, but needs to compile.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0f7020a315..f293573601 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -129,7 +129,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); }
-#ifdef CONFIG_ARMV7_LPAE +#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ for (i = 0; i < 4; i++) { u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use instructions which are invalid on ARMv4T. This happens on Tegra since it has an ARMv4T boot CPU. Add a check for the architecture version to allow the code to be built. It will not actually be executed by the boot CPU, but needs to compile.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature is disabled. This can happen if U-Boot is chain-loaded from another boot loader which does enable LPAE.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f293573601..cf852c061b 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -172,6 +172,15 @@ static inline void mmu_setup(void) : : "r" (MEMORY_ATTRIBUTES) : "memory"); } #elif defined(CONFIG_CPU_V7) + if (is_hyp()) { + /* Set HTCR to disable LPAE */ + asm volatile("mcr p15, 4, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } else { + /* Set TTBCR to disable LPAE */ + asm volatile("mcr p15, 0, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature is disabled. This can happen if U-Boot is chain-loaded from another boot loader which does enable LPAE.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 9 +++++++++ 1 file changed, 9 insertions(+)
Applied to u-boot-dm, thanks!
This file does not report a few possible errors and one message is missing a newline. Fix these.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index a42f80bb2b..0a1d1b36c0 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -146,8 +146,10 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp)
for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) { - if (ret) + if (ret) { + debug("regulator %s, ret=%d\n", dev->name, ret); continue; + }
uc_pdata = dev_get_uclass_platdata(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) @@ -156,7 +158,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) return uclass_get_device_tail(dev, 0, devp); }
- debug("%s: can't find: %s\n", __func__, plat_name); + debug("%s: can't find: %s, ret=%d\n", __func__, plat_name, ret);
return -ENODEV; } @@ -219,7 +221,7 @@ int regulator_autoset_by_name(const char *platname, struct udevice **devp) if (devp) *devp = dev; if (ret) { - debug("Can get the regulator: %s!", platname); + debug("Can get the regulator: %s (err=%d)\n", platname, ret); return ret; }
On 06/01/2017 08:57 AM, Simon Glass wrote:
This file does not report a few possible errors and one message is missing a newline. Fix these.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
And CC'd correct Lukasz's mail account.
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index a42f80bb2b..0a1d1b36c0 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -146,8 +146,10 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp)
for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) {
if (ret)
if (ret) {debug("regulator %s, ret=%d\n", dev->name, ret); continue;}uc_pdata = dev_get_uclass_platdata(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name))
@@ -156,7 +158,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) return uclass_get_device_tail(dev, 0, devp); }
- debug("%s: can't find: %s\n", __func__, plat_name);
debug("%s: can't find: %s, ret=%d\n", __func__, plat_name, ret);
return -ENODEV;
} @@ -219,7 +221,7 @@ int regulator_autoset_by_name(const char *platname, struct udevice **devp) if (devp) *devp = dev; if (ret) {
debug("Can get the regulator: %s!", platname);
debug("Can get the regulator: %s (err=%d)\n", platname, ret);
On 06/01/2017 08:57 AM, Simon Glass wrote:
This file does not report a few possible errors and one message is missing a newline. Fix these.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
And CC'd correct Lukasz's mail account.
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
Applied to u-boot-dm, thanks!
At present early clock init happens in SPL. If SPL did not run (because for example U-Boot is chain-loaded from another boot loader) then the clocks are not set as U-Boot expects.
Add a function to detect this and call the early clock init in U-Boot proper.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/include/asm/arch-tegra/clock.h | 3 +++ arch/arm/mach-tegra/board2.c | 3 +++ arch/arm/mach-tegra/clock.c | 5 +++++ arch/arm/mach-tegra/tegra124/clock.c | 18 ++++++++++++++++++ 4 files changed, 29 insertions(+)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 301de4a899..92180db321 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -288,6 +288,9 @@ void clock_init(void); /* Initialize the PLLs */ void clock_early_init(void);
+/* @return true if hardware indicates that clock_early_init() was called */ +bool clock_early_init_done(void); + /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index e0a39e1a32..bd137969f0 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -181,6 +181,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
int board_early_init_f(void) { + if (!clock_early_init_done()) + clock_early_init(); + #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) #define USBCMD_FS2 (1 << 15) { diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 090dba629c..ce68c7d0cc 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -824,3 +824,8 @@ int clock_external_output(int clk_id)
return 0; } + +__weak bool clock_early_init_done(void) +{ + return true; +} diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 5e4406102f..5ae718b342 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -891,6 +891,24 @@ void clock_early_init(void) udelay(2); }
+/* + * clock_early_init_done - Check if clock_early_init() has been called + * + * Check a register that we set up to see if clock_early_init() has already + * been called. + * + * @return true if clock_early_init() was called, false if not + */ +bool clock_early_init_done(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = readl(&clkrst->crc_sclk_brst_pol); + + return val == 0x20002222; +} + void arch_timer_init(void) { struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
At present early clock init happens in SPL. If SPL did not run (because for example U-Boot is chain-loaded from another boot loader) then the clocks are not set as U-Boot expects.
Add a function to detect this and call the early clock init in U-Boot proper.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/include/asm/arch-tegra/clock.h | 3 +++ arch/arm/mach-tegra/board2.c | 3 +++ arch/arm/mach-tegra/clock.c | 5 +++++ arch/arm/mach-tegra/tegra124/clock.c | 18 ++++++++++++++++++ 4 files changed, 29 insertions(+)
Applied to u-boot-dm, thanks!
At present the interrupt does not work and the SPI bus runs much less quickly than it should. Add settings to fix this.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index fff1d78169..65c3851aff 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -12,4 +12,13 @@ u-boot,dm-pre-reloc; }; }; + + spi@7000d400 { + spi-deactivate-delay = <200>; + spi-max-frequency = <3000000>; + + cros_ec: cros-ec@0 { + ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + }; };
At present the interrupt does not work and the SPI bus runs much less quickly than it should. Add settings to fix this.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
Applied to u-boot-dm, thanks!
For devices that need a delay between SPI transactions we seem to need an additional delay before the first one if the CPU is running at full speed. Add this, under control of the existing setting. At present it will only be enabled with the Chrome OS EC.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/spi/tegra114_spi.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 013bc82380..04b4fce061 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -149,6 +149,7 @@ static int tegra114_spi_probe(struct udevice *bus) bus->name, priv->freq, rate); } } + udelay(plat->deactivate_delay_us);
/* Clear stale status here */ setbits_le32(®s->fifo_status,
For devices that need a delay between SPI transactions we seem to need an additional delay before the first one if the CPU is running at full speed. Add this, under control of the existing setting. At present it will only be enabled with the Chrome OS EC.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/spi/tegra114_spi.c | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-dm, thanks!
Enable this so we can roughly measure CPU performance. Also enable the cache command to allow for timing.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/nyan-big_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index e53cf66168..e2b2babd4c 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -76,5 +77,6 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_BRIDGE=y +CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_ERRNO_STR=y
Enable this so we can roughly measure CPU performance. Also enable the cache command to allow for timing.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/nyan-big_defconfig | 2 ++ 1 file changed, 2 insertions(+)
Applied to u-boot-dm, thanks!
If U-Boot is the secondary boot loader, or has been run from itself, the SOR may already be powered up. Powering it up again causes a hang, so detect this situation and skip it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/video/tegra124/sor.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 1f5e572bda..700ab25d46 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -466,11 +466,20 @@ void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); + u32 reg; int ret;
if (sor->power_is_up) return 0;
+ /* + * If for some reason it is already powered up, don't do it again. + * This can happen if U-Boot is the secondary boot loader. + */ + reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); + if (reg & DP_PADCTL_PD_TXD_0_NO) + return 0; + /* Set link bw */ tegra_dc_sor_set_link_bandwidth(dev, is_lvds ? CLK_CNTRL_DP_LINK_SPEED_LVDS :
Hi Simon,
On Wed, 31 May 2017 17:57:20 -0600 Simon Glass sjg@chromium.org wrote:
If U-Boot is the secondary boot loader, or has been run from itself, the SOR may already be powered up. Powering it up again causes a hang, so detect this situation and skip it.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/tegra124/sor.c | 9 +++++++++ 1 file changed, 9 insertions(+)
Acked-by: Anatolij Gustschin agust@denx.de
Hi Simon,
On Wed, 31 May 2017 17:57:20 -0600 Simon Glass sjg@chromium.org wrote:
If U-Boot is the secondary boot loader, or has been run from itself, the SOR may already be powered up. Powering it up again causes a hang, so detect this situation and skip it.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/tegra124/sor.c | 9 +++++++++ 1 file changed, 9 insertions(+)
Acked-by: Anatolij Gustschin agust@denx.de
Applied to u-boot-dm, thanks!
At present CP15 init is disabled on tegra. Use the correct option so that this init is performed on boot. This enables the instruction cache, for example, which is critical to the machine running at full speed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
include/configs/tegra-common-post.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 1a4a7e2320..846b09aadc 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -105,7 +105,7 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/* remove I2C support */ #ifdef CONFIG_SYS_I2C_TEGRA
At present CP15 init is disabled on tegra. Use the correct option so that this init is performed on boot. This enables the instruction cache, for example, which is critical to the machine running at full speed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
include/configs/tegra-common-post.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
The clock fix-up for tegra is still present in the code. It causes a divide-by-zero bug after relocation when chain-loading U-Boot from coreboot. Fix this by adding a check.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks) ---
Changes in v2: None
arch/arm/mach-tegra/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index ce68c7d0cc..dc58b3027d 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * return value doesn't help. In summary this clock driver is * quite broken but I'm afraid I have no idea how to fix it * without completely replacing it. + * + * Be careful to avoid a divide by zero error. */ - div -= 2; + if (div >= 1) + div -= 2; break; #endif default:
The clock fix-up for tegra is still present in the code. It causes a divide-by-zero bug after relocation when chain-loading U-Boot from coreboot. Fix this by adding a check.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks) ---
Changes in v2: None
arch/arm/mach-tegra/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
Add a sample .its file for booting U-Boot on a nyan-big Chromebook.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch containing a .its file for chromium
doc/chromium/nyan-big.its | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 doc/chromium/nyan-big.its
diff --git a/doc/chromium/nyan-big.its b/doc/chromium/nyan-big.its new file mode 100644 index 0000000000..8dc8d73041 --- /dev/null +++ b/doc/chromium/nyan-big.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../.././b/nyan-big/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "tegra124-nyan-big.dtb"; + data = /incbin/("../.././b/nyan-big/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +};
Add a sample .its file for booting U-Boot on a nyan-big Chromebook.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch containing a .its file for chromium
doc/chromium/nyan-big.its | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 doc/chromium/nyan-big.its
Applied to u-boot-dm, thanks!
Most Chromebooks support chain-loading U-Boot but instructions are somewhat scattered. Add a README to hold this information within the U-Boot tree. Also add the standard developer keys to simplify the instructions, since they are small.
For now this only supports nyan-big.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Explain how to create dummy.txt - Add a comment about how to create a protective MBR
doc/README.chromium | 182 +++++++++++++++++++++++++++ doc/chromium/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes 3 files changed, 182 insertions(+) create mode 100644 doc/README.chromium create mode 100644 doc/chromium/devkeys/kernel.keyblock create mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk
diff --git a/doc/README.chromium b/doc/README.chromium new file mode 100644 index 0000000000..61e285da5e --- /dev/null +++ b/doc/README.chromium @@ -0,0 +1,182 @@ +Running U-Boot from coreboot on Chromebooks +=========================================== + +U-Boot can be used as a secondary boot loader in a few situations such as from +UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on +ARM platforms to start up the machine. + +This document aims to provide a guide to booting U-Boot on a Chromebook. It +is only a starting point, and there are many guides on the interwebs. But +placing this information in the U-Boot tree should make it easier to find for +those who use U-Boot habitually. + +Most of these platforms are supported by U-Boot natively, but it is risky to +replace the ROM unless you have a servo board and cable to restore it with. + + +For all of these the standard U-Boot build instructions apply. For example on +ARM: + + sudo apt install gcc-arm-linux-gnueabi + mkdir b + make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + +You can obtain the vbutil_kernel utility here: + + https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U + + +Snow (Samsung ARM Chromebook) +----------------------------- + +See here: + +https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-... + + +Nyan-big +-------- + +Compiled based on information here: +https://lists.denx.de/pipermail/u-boot/2015-March/209530.html +https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big +https://lists.denx.de/pipermail/u-boot/2017-May/289491.html +https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13... + +1. Patch U-Boot + +Open include/configs/tegra124-common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x80110000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x81000100 + + +2. Build U-Boot + + mkdir b + make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + + +3. Select a .its file + +Select something from doc/chromium which matches your board, or create your +own. + +Note that the device tree node is required, even though it is not actually +used by U-Boot. This is because the Chromebook expects to pass it to the +kernel, and crashes if it is not present. + + +4. Build and sign an image + + ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. Prepare an SD card + + DISK=/dev/sdc # Replace with your actual SD card device + sudo cgpt create $DISK + sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK + sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK + sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk + + +6. Write U-Boot to the SD card + + sudo dd if=u-boot.kpart of=/dev/sdc1; sync + + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600) + + Model: Acer Chromebook 13 CB5-311 + Board: Google/NVIDIA Nyan-big, ID: 1 + + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Tegra124 (Nyan-big) # + + +8. Known problems + +On the serial console the word MMC is chopped at the start of the line: + +C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0 + +This is likely due to some problem with change-over of the serial driver +during relocation (or perhaps updating the clock setup in board_init()). + + +9. Notes + +To check that you copied the u-boot.its file correctly, use these commands. +You should see that the data at 0x100 in u-boot-chromium.fit is the first few +bytes of U-Boot: + + hd u-boot-chromium.fit |head -20 + ... + 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + hd b/nyan-big/u-boot.bin |head + 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + +The 'data' property of the FIT is set up to start at offset 0x100 bytes into +the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes +from the load address. If this changes, you either need to modify U-Boot to be +fully relocatable, or expect it to hang. + + +Other notes +=========== + +flashrom +-------- + + Used to make a backup of your firmware, or to replace it. + + See: https://www.chromium.org/chromium-os/packages/cros-flashrom + + +coreboot +-------- + +Coreboot itself is not designed to actually boot an OS. Instead, a program +called Depthcharge is used. This originally came out of U-Boot and was then +heavily hacked and modified such that is is almost unrecognisable. It does +include a very small part of the U-Boot command-line interface but is not +usable as a general-purpose boot loader. + +In addition, it has a very unusual design in that it does not do device init +itself, but instead relies on coreboot. This is similar to (in U-Boot) having +a SPI driver with an empty probe() method, relying on whatever was set up +beforehand. It can be quite hard to figure out between these two code bases +what settings are actually used. When chain-loading into U-Boot we must be +careful to reinit anything that U-Boot expects. If not, some peripherals (or +the whole machine) may not work. This makes the process of chainloading more +complicated than it could be on some platforms. + +Finally, it supports only a subset of the U-Boot's FIT format. In particular +it uses a fixed address to load the FIT and does not support load/exec +addresses. This means that U-Boot must be able to boot from whatever +address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting +in Depthcharge). In practice this means that the data in the kernel@1 FIT node +(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE. diff --git a/doc/chromium/devkeys/kernel.keyblock b/doc/chromium/devkeys/kernel.keyblock new file mode 100644 index 0000000000000000000000000000000000000000..9740be4e60070658d01e96c13acba8e726f68a59 GIT binary patch literal 1208 zcmZ?v2=e!J^$%uZU|?Vb;vFnN0tgm>1V8{vS3qeGDD422WMF`avqSj`P?`g(4r(0O zY><=#5T9mpaFo?;<IfE~b7uK$=~H)<jvTToS}LUYuR?YXb1Ki2UAED2GsL>quTPJ1 z>(Ke2mAdzM<e7q(jDEE}&U!MrMWX936wcpb_1vZDVsrQ0oRpdCZ+D%!c&&Nal2<Dm zW#>yr_58T4rnsp(c+!WgqdkJV>YPu@g)hvz`magDHh1sz4KIGncd$uw9qpf%>5=KE z6?A>OaYc9j^yRg8E@<CuOh0MAa*G@{N60b8V+zlXamI5UWn#^Cm?o(3bWw+S*5zBb zZk5SAvDNvP+BRd+3eQ?KR}mJ0#}?jcb7FK}++@3Qn01OwwQ^^htkG`e3ED;1Cj<ux z2wgbzsHm~PW}~{(oBi4$*G?zC+Hz&Zz0db;FN)u5>-@4%BktA~cgfj@&UwB{zU3s- zDziH0`k}uj(pLo+xood$O=RA6CFP-K`=n=gET_!b^*&-ApV^G-mwZGDr&O$Od#?ZT zr-JXlTi5M74@R!rn=pI&k~D_h)fYTl^Q#$E4tqR0o;YL9)5+~DoK}-U<hM3xiaxFX zcW3?Ohe=1a-PV`l_#DD!buO;6@V<3SPj>T49@c>B7EXz@mWOo-*Y50>Src>Tna{ih zUXcd>Cr*%4)C`ze_E$eDJ&PgRLH+q&@n`Y#o@75@omYE$!b_Vul_%YQMC`HOxb%Jc z2c?At#%3F0-oEm?r@|9`!*}1BEFr^Xaq%qMA{JiMTx>iiWn-W9ul1%=s+N2`Juh9l z*YuP?X78(tL*J4Q2!8yQR-iZS!=7q6F|~V->koX%vEdGS#D1@!dwt7PX}77Ftdm}u zEj<-*+w+9WyBbdi6V}gc@-k;ClBDN8^0#A|w(G+2MOLf6A6|DL`_zfZ2@hPWy%YAY z6IH#iNPlXUp1F!>CZAQVgW|W6m}T=HFek7?78ERS`*NSlTV!=R&#IK!O{Ww$6#eQp z|C(@pyI)b9uyS!r&c)uMMWWq-785ci-0V&@NW2}`5OMeL2TkKUmXr3YKRe#^?bUh3 zOA9QR!h^ovWuN(&^ZMF(a?d}<6)iY6*RgF{Q;C~A>m^oIP4%>gt7F){ta*On$FsO@ z$<RYH`<Cma@n|J(nBh2?HDto7eWGg7<ux0AaAa)Tapmrf75;a>O@6wtL%NE!@#qW_ z*^cDU^|Kb9_Fmt%+4a_vElUNe0<xao%I`lQJ9XnkkKn^k<@s1kR~^4$b|E*w<I1zW z7j&nK>uz>iEy?#}&ELtZd3@IHkC0xac9!?n`qQsBNXEFy&)%>@C}+9fj^*+~*+2Gq zuVmTs)9lR6s}tAMy%auBf9m?3eJeLy(-7CccAqcXL-1PQ@!a-r9NTj;zhBb`s4H1J zEsN(=_QsF*7RM`p)p8N!U;JIgOxpNa-A%rw-3xYfx4ygZB-8oW&v^BvCljsv)+d!a zZBvhbJFRW=dm}?<z3TPRk4l@0)>_9-Iw-p8w<7z?RYx9OpV^#KWSMWOF!#ZYAGeEC Tp7v_~RjJ<N@pAW}mg74Ct|TeM
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Most Chromebooks support chain-loading U-Boot but instructions are somewhat scattered. Add a README to hold this information within the U-Boot tree. Also add the standard developer keys to simplify the instructions, since they are small.
For now this only supports nyan-big.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Explain how to create dummy.txt - Add a comment about how to create a protective MBR
doc/README.chromium | 182 +++++++++++++++++++++++++++ doc/chromium/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes 3 files changed, 182 insertions(+) create mode 100644 doc/README.chromium create mode 100644 doc/chromium/devkeys/kernel.keyblock create mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk
Applied to u-boot-dm, thanks!
At present if the
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert()) ---
Changes in v2: None
drivers/pwm/rk_pwm.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 59eae0956e..28de62d716 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev) return -EINVAL; } priv->freq = clk_get_rate(&clk); + priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
return 0; }
At present if the
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert()) ---
Changes in v2: None
drivers/pwm/rk_pwm.c | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-dm, thanks!
This typo doesn't actually cause any problems, but is wrong. Fix it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/dts/rk3288-veyron-jerry.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index 8aab607cc5..2e6272b81b 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -21,7 +21,7 @@ stdout-path = &uart2; };
- panel_regulator: panel-regualtor { + panel_regulator: panel-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
This typo doesn't actually cause any problems, but is wrong. Fix it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/dts/rk3288-veyron-jerry.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
Add a debug() statement so we can see when something goes wrong with the regulator.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9894a25e08..18fd0dcd20 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -86,8 +86,10 @@ static int veyron_init(void) int ret;
ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) + if (ret) { + debug("Cannot set regulator name\n"); return ret; + }
/* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000);
Add a debug() statement so we can see when something goes wrong with the regulator.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
Add remove() methods for EDP and VOP so that U-Boot can shut down the video on exit. This avoids leaving DMA running while booting Linux which can cause problems if Linux uses the frame buffer for something else.
It also makes it clear what is needed to shut down video.
While we are here, make rkvop_enable() static.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/video/rockchip/rk_edp.c | 16 +++++++++++++++- drivers/video/rockchip/rk_vop.c | 18 ++++++++++++++++-- 2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 4e2030e8e4..1527f96eca 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1004,7 +1004,20 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev) return 0; }
-int rk_edp_probe(struct udevice *dev) +static int rk_edp_remove(struct udevice *dev) +{ + struct rk_edp_priv *priv = dev_get_priv(dev); + struct rk3288_edp *regs = priv->regs; + + setbits_le32(®s->video_ctl_1, VIDEO_MUTE); + clrbits_le32(®s->video_ctl_1, VIDEO_EN); + clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); + setbits_le32(®s->func_en_1, SW_FUNC_EN_N); + + return 0; +} + +static int rk_edp_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_edp_priv *priv = dev_get_priv(dev); @@ -1080,5 +1093,6 @@ U_BOOT_DRIVER(dp_rockchip) = { .ops = &dp_rockchip_ops, .ofdata_to_platdata = rk_edp_ofdata_to_platdata, .probe = rk_edp_probe, + .remove = rk_edp_remove, .priv_auto_alloc_size = sizeof(struct rk_edp_priv), }; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 48bfcd4f34..b9b0b296ca 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -33,8 +33,9 @@ struct rk_vop_priv { struct rk3288_grf *grf; };
-void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, - int fb_bits_per_pixel, const struct display_timing *edid) +static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, + int fb_bits_per_pixel, + const struct display_timing *edid) { u32 lb_mode; u32 rgb_mode; @@ -281,6 +282,18 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) return 0; }
+static int rk_vop_remove(struct udevice *dev) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + + rk_setreg(&priv->regs->sys_ctrl, V_STANDBY_EN(1)); + + /* wait frame complete (60Hz) to enter standby */ + mdelay(17); + + return 0; +} + static int rk_vop_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); @@ -379,5 +392,6 @@ U_BOOT_DRIVER(rk_vop) = { .ops = &rk_vop_ops, .bind = rk_vop_bind, .probe = rk_vop_probe, + .remove = rk_vop_remove, .priv_auto_alloc_size = sizeof(struct rk_vop_priv), };
On Wed, 31 May 2017 17:57:28 -0600 Simon Glass sjg@chromium.org wrote:
Add remove() methods for EDP and VOP so that U-Boot can shut down the video on exit. This avoids leaving DMA running while booting Linux which can cause problems if Linux uses the frame buffer for something else.
It also makes it clear what is needed to shut down video.
While we are here, make rkvop_enable() static.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/rockchip/rk_edp.c | 16 +++++++++++++++- drivers/video/rockchip/rk_vop.c | 18 ++++++++++++++++-- 2 files changed, 31 insertions(+), 3 deletions(-)
Acked-by: Anatolij Gustschin agust@denx.de
On Wed, 31 May 2017 17:57:28 -0600 Simon Glass sjg@chromium.org wrote:
Add remove() methods for EDP and VOP so that U-Boot can shut down the video on exit. This avoids leaving DMA running while booting Linux which can cause problems if Linux uses the frame buffer for something else.
It also makes it clear what is needed to shut down video.
While we are here, make rkvop_enable() static.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/rockchip/rk_edp.c | 16 +++++++++++++++- drivers/video/rockchip/rk_vop.c | 18 ++++++++++++++++-- 2 files changed, 31 insertions(+), 3 deletions(-)
Acked-by: Anatolij Gustschin agust@denx.de
Applied to u-boot-dm, thanks!
On reset the standby bit is clear, but if U-Boot is chain-loaded from another boot loader it may be set. Clear it before starting up video so that it works correctly.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/video/rockchip/rk_vop.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index b9b0b296ca..d970aae524 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -104,6 +104,9 @@ void rkvop_mode_set(struct rk3288_vop *regs, uint flags; int mode_flags;
+ /* remove from standby */ + rk_clrreg(®s->sys_ctrl, V_STANDBY_EN(1)); + switch (mode) { case VOP_MODE_HDMI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
On Wed, 31 May 2017 17:57:29 -0600 Simon Glass sjg@chromium.org wrote:
On reset the standby bit is clear, but if U-Boot is chain-loaded from another boot loader it may be set. Clear it before starting up video so that it works correctly.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/rockchip/rk_vop.c | 3 +++ 1 file changed, 3 insertions(+)
Acked-by: Anatolij Gustschin agust@denx.de
On Wed, 31 May 2017 17:57:29 -0600 Simon Glass sjg@chromium.org wrote:
On reset the standby bit is clear, but if U-Boot is chain-loaded from another boot loader it may be set. Clear it before starting up video so that it works correctly.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/video/rockchip/rk_vop.c | 3 +++ 1 file changed, 3 insertions(+)
Acked-by: Anatolij Gustschin agust@denx.de
Applied to u-boot-dm, thanks!
Add a sample .its file for booting U-Boot on a jerry Chromebook.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch containing a .its file for chromium
doc/chromium/chromebook_jerry.its | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 doc/chromium/chromebook_jerry.its
diff --git a/doc/chromium/chromebook_jerry.its b/doc/chromium/chromebook_jerry.its new file mode 100644 index 0000000000..8cff840e00 --- /dev/null +++ b/doc/chromium/chromebook_jerry.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../../b/chromebook_jerry/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "rk3288-veryron-jerry.dtb"; + data = /incbin/("../../b/chromebook_jerry/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +};
Add a sample .its file for booting U-Boot on a jerry Chromebook.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch containing a .its file for chromium
doc/chromium/chromebook_jerry.its | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 doc/chromium/chromebook_jerry.its
Applied to u-boot-dm, thanks!
Shifted masks are the standard approach with rockchip since it allows use of the mask without shifting it each time. Update the definitions and the driver to match.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 74 ++++++++------- drivers/clk/rockchip/clk_rk3288.c | 121 ++++++++++-------------- 2 files changed, 90 insertions(+), 105 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d575f4a163..cb0a935edc 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f, + HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT,
MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_PLL_SELECT_CODEC = 0, MMC0_PLL_SELECT_GENERAL, MMC0_PLL_SELECT_24MHZ,
MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, };
/* CRU_CLKSEL12_CON */ enum { EMMC_PLL_SHIFT = 0xe, - EMMC_PLL_MASK = 3, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_PLL_SELECT_CODEC = 0, EMMC_PLL_SELECT_GENERAL, EMMC_PLL_SELECT_24MHZ,
EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f, + EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT,
SDIO0_PLL_SHIFT = 6, - SDIO0_PLL_MASK = 3, + SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, SDIO0_PLL_SELECT_CODEC = 0, SDIO0_PLL_SELECT_GENERAL, SDIO0_PLL_SELECT_24MHZ,
SDIO0_DIV_SHIFT = 0, - SDIO0_DIV_MASK = 0x3f, + SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, };
/* CRU_CLKSEL21_CON */ enum { - MAC_DIV_CON_SHIFT = 0xf, - MAC_DIV_CON_MASK = 0x1f, + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT,
- RMII_EXTCLK_SHIFT = 4, - RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, RMII_EXTCLK_SELECT_EXT_CLK = 1,
- EMAC_PLL_SHIFT = 0, - EMAC_PLL_MASK = 0x3, - EMAC_PLL_SELECT_NEW = 0x0, - EMAC_PLL_SELECT_CODEC = 0x1, - EMAC_PLL_SELECT_GENERAL = 0x2, + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, };
/* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, - SPI1_PLL_MASK = 1, + SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, SPI1_PLL_SELECT_CODEC = 0, SPI1_PLL_SELECT_GENERAL,
SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
SPI0_PLL_SHIFT = 7, - SPI0_PLL_MASK = 1, + SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, SPI0_PLL_SELECT_CODEC = 0, SPI0_PLL_SELECT_GENERAL,
SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, };
/* CRU_CLKSEL37_CON */ enum { PCLK_CORE_DBG_DIV_SHIFT = 9, - PCLK_CORE_DBG_DIV_MASK = 0x1f, + PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
ATCLK_CORE_DIV_CON_SHIFT = 4, - ATCLK_CORE_DIV_CON_MASK = 0x1f, + ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
CLK_L2RAM_DIV_SHIFT = 0, - CLK_L2RAM_DIV_MASK = 7, + CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, };
/* CRU_CLKSEL39_CON */ enum { ACLK_HEVC_PLL_SHIFT = 0xe, - ACLK_HEVC_PLL_MASK = 3, + ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, ACLK_HEVC_PLL_SELECT_CODEC = 0, ACLK_HEVC_PLL_SELECT_GENERAL, ACLK_HEVC_PLL_SELECT_NEW,
ACLK_HEVC_DIV_SHIFT = 8, - ACLK_HEVC_DIV_MASK = 0x1f, + ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT,
SPI2_PLL_SHIFT = 7, - SPI2_PLL_MASK = 1, + SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, SPI2_PLL_SELECT_CODEC = 0, SPI2_PLL_SELECT_GENERAL,
SPI2_DIV_SHIFT = 0, - SPI2_DIV_MASK = 0x7f, + SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, };
/* CRU_MODE_CON */ enum { + CRU_MODE_MASK = 3, + NPLL_MODE_SHIFT = 0xe, - NPLL_MODE_MASK = 3, + NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, NPLL_MODE_SLOW = 0, NPLL_MODE_NORMAL, NPLL_MODE_DEEP,
GPLL_MODE_SHIFT = 0xc, - GPLL_MODE_MASK = 3, + GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORMAL, GPLL_MODE_DEEP,
CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 3, + CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, CPLL_MODE_SLOW = 0, CPLL_MODE_NORMAL, CPLL_MODE_DEEP,
DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 3, + DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORMAL, DPLL_MODE_DEEP,
APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 3, + APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORMAL, APLL_MODE_DEEP, @@ -201,21 +203,21 @@ enum { /* CRU_APLL_CON0 */ enum { CLKR_SHIFT = 8, - CLKR_MASK = 0x3f, + CLKR_MASK = 0x3f << CLKR_SHIFT,
CLKOD_SHIFT = 0, - CLKOD_MASK = 0xf, + CLKOD_MASK = 0xf << CLKOD_SHIFT, };
/* CRU_APLL_CON1 */ enum { LOCK_SHIFT = 0x1f, - LOCK_MASK = 1, + LOCK_MASK = 1 << LOCK_SHIFT, LOCK_UNLOCK = 0, LOCK_LOCK,
CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff, + CLKF_MASK = 0x1fff << CLKF_SHIFT, };
#endif diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 14851ca5aa..f6ef7ecd7a 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -59,14 +59,14 @@ enum { PLL_RESET_SHIFT = 5,
/* CLKSEL0 */ - CORE_SEL_PLL_MASK = 1, CORE_SEL_PLL_SHIFT = 15, - A17_DIV_MASK = 0x1f, + CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, A17_DIV_SHIFT = 8, - MP_DIV_MASK = 0xf, + A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, MP_DIV_SHIFT = 4, - M0_DIV_MASK = 0xf, + MP_DIV_MASK = 0xf << MP_DIV_SHIFT, M0_DIV_SHIFT = 0, + M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
/* CLKSEL1: pd bus clk pll sel: codec or general */ PD_BUS_SEL_PLL_MASK = 15, @@ -75,41 +75,41 @@ enum {
/* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ PD_BUS_PCLK_DIV_SHIFT = 12, - PD_BUS_PCLK_DIV_MASK = 7, + PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
/* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PD_BUS_HCLK_DIV_SHIFT = 8, - PD_BUS_HCLK_DIV_MASK = 3, + PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
/* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ PD_BUS_ACLK_DIV0_SHIFT = 3, - PD_BUS_ACLK_DIV0_MASK = 0x1f, + PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, PD_BUS_ACLK_DIV1_SHIFT = 0, - PD_BUS_ACLK_DIV1_MASK = 0x7, + PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
/* * CLKSEL10 * peripheral bus pclk div: * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 */ - PERI_SEL_PLL_MASK = 1, PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, PERI_SEL_CPLL = 0, PERI_SEL_GPLL,
PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
/* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
/* * peripheral bus aclk div: * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) */ PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, @@ -154,8 +154,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, /* enter reset */ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
- rk_clrsetreg(&pll->con0, - CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); @@ -198,7 +197,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, }
/* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); @@ -208,7 +207,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1);
/* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
return 0; @@ -296,7 +295,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, { /* Assuming mac_clk is fed by an external clock */ rk_clrsetreg(&cru->cru_clksel_con[21], - RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_MASK, RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
return 0; @@ -313,7 +312,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, if (ret) return ret;
- rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_SLOW << NPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_NEW, &npll_config);
@@ -324,7 +323,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); }
- rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
/* vop dclk source clk: npll,dclk_div: 1 */ @@ -352,8 +351,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
/* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
@@ -382,10 +380,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PD_BUS_ACLK_HZ && pclk_div < 0x7);
rk_clrsetreg(&cru->cru_clksel_con[1], - PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT | - PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT | - PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT | - PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT, + PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | + PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, pclk_div << PD_BUS_PCLK_DIV_SHIFT | hclk_div << PD_BUS_HCLK_DIV_SHIFT | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | @@ -407,9 +403,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PERI_ACLK_HZ && (pclk_div < 0x4));
rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -417,8 +412,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
/* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } @@ -427,8 +421,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_SLOW << APLL_MODE_SHIFT);
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); @@ -444,10 +437,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT | - A17_DIV_MASK << A17_DIV_SHIFT | - MP_DIV_MASK << MP_DIV_SHIFT | - M0_DIV_MASK << M0_DIV_SHIFT, + CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | + M0_DIV_MASK, 0 << A17_DIV_SHIFT | 3 << MP_DIV_SHIFT | 1 << M0_DIV_SHIFT); @@ -457,16 +448,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ rk_clrsetreg(&cru->cru_clksel_con[37], - CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT | - ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT | - PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT, + CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | + PCLK_CORE_DBG_DIV_MASK, 1 << CLK_L2RAM_DIV_SHIFT | 3 << ATCLK_CORE_DIV_CON_SHIFT | 3 << PCLK_CORE_DBG_DIV_SHIFT);
/* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_NORMAL << APLL_MODE_SHIFT); }
@@ -486,16 +475,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
con = readl(&cru->cru_mode_con); shift = clk_shift[clk_id]; - switch ((con >> shift) & APLL_MODE_MASK) { + switch ((con >> shift) & CRU_MODE_MASK) { case APLL_MODE_SLOW: return OSC_HZ; case APLL_MODE_NORMAL: /* normal mode */ con = readl(&pll->con0); - no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; - nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; + nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; con = readl(&pll->con1); - nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
return (24 * nf / (nr * no)) * 1000000; case APLL_MODE_DEEP: @@ -515,20 +504,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; case HCLK_SDIO0: case SCLK_SDIO0: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; - div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; + mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; + div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; break; default: return -EINVAL; @@ -561,24 +550,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; case HCLK_SDIO0: case SCLK_SDIO0: rk_clrsetreg(&cru->cru_clksel_con[12], - SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | - SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, + SDIO0_PLL_MASK | SDIO0_DIV_MASK, mux << SDIO0_PLL_SHIFT | (src_clk_div - 1) << SDIO0_DIV_SHIFT); break; @@ -598,18 +584,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK; - div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; + div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; break; case SCLK_SPI1: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK; - div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; + div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; break; case SCLK_SPI2: con = readl(&cru->cru_clksel_con[39]); - mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK; - div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK; + mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; + div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; break; default: return -EINVAL; @@ -629,22 +615,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI0_PLL_MASK << SPI0_PLL_SHIFT | - SPI0_DIV_MASK << SPI0_DIV_SHIFT, + SPI0_PLL_MASK | SPI0_DIV_MASK, SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | src_clk_div << SPI0_DIV_SHIFT); break; case SCLK_SPI1: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI1_PLL_MASK << SPI1_PLL_SHIFT | - SPI1_DIV_MASK << SPI1_DIV_SHIFT, + SPI1_PLL_MASK | SPI1_DIV_MASK, SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | src_clk_div << SPI1_DIV_SHIFT); break; case SCLK_SPI2: rk_clrsetreg(&cru->cru_clksel_con[39], - SPI2_PLL_MASK << SPI2_PLL_SHIFT | - SPI2_DIV_MASK << SPI2_DIV_SHIFT, + SPI2_PLL_MASK | SPI2_DIV_MASK, SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | src_clk_div << SPI2_DIV_SHIFT); break;
Shifted masks are the standard approach with rockchip since it allows use of the mask without shifting it each time. Update the definitions and the driver to match.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 74 ++++++++------- drivers/clk/rockchip/clk_rk3288.c | 121 ++++++++++-------------- 2 files changed, 90 insertions(+), 105 deletions(-)
Applied to u-boot-dm, thanks!
Detect with a previous boot loader has already set up the clocks and set them up again so that U-Boot gets what it expects.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index f6ef7ecd7a..792ee76509 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,10 +131,8 @@ enum {
/* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); -#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -#endif
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -340,9 +338,8 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
return 0; } -#endif +#endif /* CONFIG_SPL_BUILD */
-#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; @@ -416,7 +413,6 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -#endif
void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { @@ -786,6 +782,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) static int rk3288_clk_probe(struct udevice *dev) { struct rk3288_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -796,8 +793,24 @@ static int rk3288_clk_probe(struct udevice *dev)
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru, priv->grf); + init_clocks = true; #endif + if (!(gd->flags & GD_FLG_RELOC)) { + u32 reg; + + /* + * Init clocks in U-Boot proper if the NPLL is runnning. This + * indicates that a previous boot loader set up the clocks, so + * we need to redo it. U-Boot's SPL does not set this clock. + */ + reg = readl(&priv->cru->cru_mode_con); + if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == + NPLL_MODE_NORMAL) + init_clocks = true; + } + + if (init_clocks) + rkclk_init(priv->cru, priv->grf);
return 0; }
Detect with a previous boot loader has already set up the clocks and set them up again so that U-Boot gets what it expects.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)
Applied to u-boot-dm, thanks!
If U-Boot is chain-loaded from a previous boot loader we must set up the clocks the way U-Boot wants them. Add code for this. It will do nothing if SPL has already done the job.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++++++++++++ configs/chromebook_jerry_defconfig | 1 + 2 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 18fd0dcd20..a354d992da 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -309,3 +309,38 @@ U_BOOT_CMD( "display information about clocks", "" ); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 6fc0dcc023..bb880585e1 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_CMD_IMLS is not set
If U-Boot is chain-loaded from a previous boot loader we must set up the clocks the way U-Boot wants them. Add code for this. It will do nothing if SPL has already done the job.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++++++++++++ configs/chromebook_jerry_defconfig | 1 + 2 files changed, 36 insertions(+)
Applied to u-boot-dm, thanks!
Show the U-Boot banner and board information on the video display during boot.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
include/configs/rockchip-common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9d183cee6a..0573571e6e 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -54,4 +54,6 @@ #define CONFIG_ENV_OFFSET (96 * 1024) #endif
+#define CONFIG_DISPLAY_BOARDINFO_LATE + #endif /* _ROCKCHIP_COMMON_H_ */
Show the U-Boot banner and board information on the video display during boot.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
include/configs/rockchip-common.h | 2 ++ 1 file changed, 2 insertions(+)
Applied to u-boot-dm, thanks!
The display on jerry is so fast that this option is not needed. Drop it so that the display scrolls more smoothly.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/chromebook_jerry_defconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index bb880585e1..63de674241 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -75,7 +75,6 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y
The display on jerry is so fast that this option is not needed. Drop it so that the display scrolls more smoothly.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/chromebook_jerry_defconfig | 1 - 1 file changed, 1 deletion(-)
Applied to u-boot-dm, thanks!
Add instructions for chromebook_jerry.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add instructions and patches for chain-loading into U-Boot on jerry
doc/README.chromium | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+)
diff --git a/doc/README.chromium b/doc/README.chromium index 61e285da5e..7bf4d87447 100644 --- a/doc/README.chromium +++ b/doc/README.chromium @@ -145,6 +145,76 @@ from the load address. If this changes, you either need to modify U-Boot to be fully relocatable, or expect it to hang.
+chromebook_jerry +---------------- + +The instruction are similar to those for Nyan with changes as noted below: + +1. Patch U-Boot + +Open include/configs/rk3288_common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x00100000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x02000100 + + + +2. Build U-Boot + + mkdir b + make -j8 O=b/chromebook_jerry CROSS_COMPILE=arm-linux-gnueabi- \ + chromebook_jerry_defconfig all + + +3. See above + +4. Build and sign an image + + ./b/chromebook_jerry/tools/mkimage -f doc/chromium/chromebook_jerry.its \ + u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. See above + +6. See above + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.05-00649-g72acdbf-dirty (May 29 2017 - 14:57:05 -0600) + + Model: Google Jerry + Net: Net Initialization Skipped + No ethernet found. + Hit any key to stop autoboot: 0 + + +8. Known problems + +None as yet. + + +9. Notes + +None as yet. + + Other notes ===========
Add instructions for chromebook_jerry.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add instructions and patches for chain-loading into U-Boot on jerry
doc/README.chromium | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+)
Applied to u-boot-dm, thanks!
participants (4)
-
Anatolij Gustschin -
Jaehoon Chung -
Simon Glass -
sjg＠google.com