800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters,

hwconfig=fsl_ddr:sdram=fixed

To use SPD parameters,

hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1

Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/corenet_ds/corenet_ds.c | 15 -- board/freescale/corenet_ds/ddr.c | 315 ++++++++++++++++++++++++++++++- include/configs/corenet_ds.h | 57 ------ 3 files changed, 314 insertions(+), 73 deletions(-)

diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 1107743..b5a1332 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -29,7 +29,6 @@ #include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_law.h> -#include <asm/fsl_ddr_sdram.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> @@ -239,20 +238,6 @@ int misc_init_r(void) return 0; }

-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - - setup_ddr_tlbs(dram_size / 0x100000); - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_MP void board_lmb_reserve(struct lmb *lmb) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index ce87b56..d387a92 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -8,9 +8,289 @@

#include <common.h> #include <i2c.h> - +#include <hwconfig.h> +#include <asm/mmu.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); + +#define CONFIG_SYS_SDRAM_SIZE 4096 + +#define DATARATE_800MHZ 800000000 +#define DATARATE_900MHZ 900000000 +#define DATARATE_1000MHZ 1000000000 +#define DATARATE_1200MHZ 1200000000 + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + if (sysinfo.freqDDRBus <= DATARATE_800MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_900MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_900, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_1000MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_1000, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_1200MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_1200, sizeof(ddr_cfg_regs)); + else + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS; + ddr_cfg_regs.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS; + ddr_cfg_regs.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS; + ddr_cfg_regs.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS; + ddr_cfg_regs.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG; + ddr_cfg_regs.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG; + ddr_cfg_regs.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG; + ddr_cfg_regs.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (CONFIG_SYS_DDR_CS0_CONFIG & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + lawbar1_target_id = LAW_TRGT_IF_DDR_2; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } + return ddr_size; +}

static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -168,3 +448,36 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Enable ZQ calibration */ popts->zq_en = 1; } + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + int use_spd = 0; + + puts("Initializing...."); + + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub("fsl_ddr", "sdram")) { + if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + use_spd = 1; + else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; + + if (use_spd) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0a0e1e8..6ac35d3 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -134,63 +134,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#else -#define CONFIG_SYS_SDRAM_SIZE 4096 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x01031000 -#define CONFIG_SYS_DDR_TIMING_0 0x55440804 -#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 -#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b -#define CONFIG_SYS_DDR_MODE_1 0x00421850 -#define CONFIG_SYS_DDR_MODE_2 0x00100000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x10400100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03401500 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 -#define CONFIG_SYS_DDR_CONTROL 0xc7048000 -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 -#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 - -#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff -#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG -#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 -#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 -#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 -#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 -#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 -#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 -#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL -#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL -#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT -#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL -#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 -#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 -#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL -#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL -#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL -#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 -#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 -#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 -#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN -#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS -#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE -#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 - #endif

/*