[U-Boot] [PATCH 0/4] rockchip: rk3399: Fix USB3 support
Ever since the dts files were synchronized in commit 0a09f2f1173d ("rockchip: Adjust rk3399 device tree to be closer to linux") USB3 support on Rockchip RK3399 boards has been broken.
This series restores the functionality by adopting the dwc3-of-simple glue driver.
Mark Kettenis (4): rockchip: clk: rk3399: handle clk_enable requests for USB3 usb: dwc3-of-simple: Add support for RK3399 usb: xhci-dwc3: Add USB2 PHY configuration rockchip: xhci: Remove RK3399 support
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ drivers/usb/host/xhci-rockchip.c | 2 -- 5 files changed, 34 insertions(+), 2 deletions(-)
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open.
Signed-off-by: Mark Kettenis kettenis@openbsd.org --- drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 79007b8682..d9950c159b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1080,6 +1080,18 @@ static int rk3399_clk_enable(struct clk *clk) case PCLK_GMAC: /* Required to successfully probe the Designware GMAC driver */ return 0; + + case SCLK_USB3OTG0_REF: + case SCLK_USB3OTG1_REF: + case SCLK_USB3OTG0_SUSPEND: + case SCLK_USB3OTG1_SUSPEND: + case ACLK_USB3OTG0: + case ACLK_USB3OTG1: + case ACLK_USB3_RKSOC_AXI_PERF: + case ACLK_USB3: + case ACLK_USB3_GRF: + /* Required to successfully probe the Designware USB3 driver */ + return 0; }
debug("%s: unsupported clk %ld\n", __func__, clk->id);
Hi Mark,
Thanks for your patches, and see comments below.
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 79007b8682..d9950c159b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1080,6 +1080,18 @@ static int rk3399_clk_enable(struct clk *clk) case PCLK_GMAC: /* Required to successfully probe the Designware GMAC driver */ return 0;
- case SCLK_USB3OTG0_REF:
- case SCLK_USB3OTG1_REF:
- case SCLK_USB3OTG0_SUSPEND:
- case SCLK_USB3OTG1_SUSPEND:
- case ACLK_USB3OTG0:
- case ACLK_USB3OTG1:
- case ACLK_USB3_RKSOC_AXI_PERF:
- case ACLK_USB3:
- case ACLK_USB3_GRF:
/* Required to successfully probe the Designware USB3 driver */return 0;
This look waist of cpu cycles, we don't actually need to init clock for rk3399 in U-Boot, can we just delete the clock node in dts(in -u-boot.dtsi) and also make the probe successfully?
Thanks, - Kever
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
From: Kever Yang kever.yang@rock-chips.com Date: Sun, 30 Jun 2019 21:24:59 +0800
Hi Mark,
Thanks for your patches, and see comments below.
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 79007b8682..d9950c159b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1080,6 +1080,18 @@ static int rk3399_clk_enable(struct clk *clk) case PCLK_GMAC: /* Required to successfully probe the Designware GMAC driver */ return 0;
- case SCLK_USB3OTG0_REF:
- case SCLK_USB3OTG1_REF:
- case SCLK_USB3OTG0_SUSPEND:
- case SCLK_USB3OTG1_SUSPEND:
- case ACLK_USB3OTG0:
- case ACLK_USB3OTG1:
- case ACLK_USB3_RKSOC_AXI_PERF:
- case ACLK_USB3:
- case ACLK_USB3_GRF:
/* Required to successfully probe the Designware USB3 driver */return 0;This look waist of cpu cycles, we don't actually need to init clock for rk3399 in U-Boot, can we just delete the clock node in dts(in -u-boot.dtsi) and also make the probe successfully?
I think that would be a bad idea since it would mean that the clock properties would be missing from the DT passed to the OS.
Thanks,
- Kever
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support.
Signed-off-by: Mark Kettenis kettenis@openbsd.org --- drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b1188bcbf5..ac68aa2d27 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,7 @@ config USB_XHCI_DWC3 config USB_XHCI_DWC3_OF_SIMPLE bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" depends on DM_USB + default y if ARCH_ROCKCHIP default y if DRA7XX help Support USB2/3 functionality in simple SoC integrations with diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index b118997f6e..45df614b09 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -92,6 +92,7 @@ static int dwc3_of_simple_remove(struct udevice *dev)
static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" }, + { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "ti,dwc3" }, { } };
Hi Mark,
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b1188bcbf5..ac68aa2d27 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,7 @@ config USB_XHCI_DWC3 config USB_XHCI_DWC3_OF_SIMPLE bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" depends on DM_USB
- default y if ARCH_ROCKCHIP default y if DRA7XX help Support USB2/3 functionality in simple SoC integrations with
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index b118997f6e..45df614b09 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -92,6 +92,7 @@ static int dwc3_of_simple_remove(struct udevice *dev)
static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" },
- { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "ti,dwc3" }, { }
};
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Signed-off-by: Mark Kettenis kettenis@openbsd.org --- drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e7..ed955dc8b8 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); + const char *phy; + u32 reg; int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); @@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
dwc3_core_init(dwc3_reg);
+ /* Set dwc3 usb2 phy config */ + reg = readl(&dwc3_reg->g_usb2phycfg[0]); + + phy = dev_read_string(dev, "phy_type"); + if (phy && strcmp(phy, "utmi_wide") == 0) { + reg |= DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + } + + if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + + if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + + writel(reg, &dwc3_reg->g_usb2phycfg[0]); + dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks, - Kever On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e7..ed955dc8b8 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
const char *phy;
u32 reg; int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
@@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
dwc3_core_init(dwc3_reg);
- /* Set dwc3 usb2 phy config */
- reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- phy = dev_read_string(dev, "phy_type");
- if (phy && strcmp(phy, "utmi_wide") == 0) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;- }
- if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;- if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;- writel(reg, &dwc3_reg->g_usb2phycfg[0]);
- dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */
On 6/30/19 3:31 PM, Kever Yang wrote:
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Is this a documented DT property or some ad-hoc U-Boot one ? Is this a fix for this release or feature for next ?
Signed-off-by: Mark Kettenis kettenis@openbsd.org
drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e7..ed955dc8b8 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
const char *phy;
u32 reg; int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
@@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
dwc3_core_init(dwc3_reg);
- /* Set dwc3 usb2 phy config */
- reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- phy = dev_read_string(dev, "phy_type");
- if (phy && strcmp(phy, "utmi_wide") == 0) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;- }
- if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;- if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;- writel(reg, &dwc3_reg->g_usb2phycfg[0]);
- dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 15:36:03 +0200
On 6/30/19 3:31 PM, Kever Yang wrote:
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Is this a documented DT property or some ad-hoc U-Boot one ?
Yes, these are all standard Linux DT properties. See usb/generic.txt for "phy_type", and usb/dwc3.txt for "snps,dis-enblslpm_quirk" and "snps,dis-u2-freeclk-exists-quirk".
Is this a fix for this release or feature for next ?
Good question. The series fixes a regression, but that regression was already present in 2019.04 and you can still boot from uSD, eMMC or USB2 without this fixed.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e7..ed955dc8b8 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
const char *phy;
u32 reg; int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
@@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
dwc3_core_init(dwc3_reg);
- /* Set dwc3 usb2 phy config */
- reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- phy = dev_read_string(dev, "phy_type");
- if (phy && strcmp(phy, "utmi_wide") == 0) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;- }
- if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;- if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;- writel(reg, &dwc3_reg->g_usb2phycfg[0]);
- dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */
-- Best regards, Marek Vasut
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-56 Email: marex@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 6/30/19 4:25 PM, Mark Kettenis wrote:
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 15:36:03 +0200
On 6/30/19 3:31 PM, Kever Yang wrote:
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Is this a documented DT property or some ad-hoc U-Boot one ?
Yes, these are all standard Linux DT properties. See usb/generic.txt for "phy_type", and usb/dwc3.txt for "snps,dis-enblslpm_quirk" and "snps,dis-u2-freeclk-exists-quirk".
Is this a fix for this release or feature for next ?
Good question. The series fixes a regression, but that regression was already present in 2019.04 and you can still boot from uSD, eMMC or USB2 without this fixed.
Do we expect this to break anything ?
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 16:31:41 +0200
On 6/30/19 4:25 PM, Mark Kettenis wrote:
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 15:36:03 +0200
On 6/30/19 3:31 PM, Kever Yang wrote:
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Is this a documented DT property or some ad-hoc U-Boot one ?
Yes, these are all standard Linux DT properties. See usb/generic.txt for "phy_type", and usb/dwc3.txt for "snps,dis-enblslpm_quirk" and "snps,dis-u2-freeclk-exists-quirk".
Is this a fix for this release or feature for next ?
Good question. The series fixes a regression, but that regression was already present in 2019.04 and you can still boot from uSD, eMMC or USB2 without this fixed.
Do we expect this to break anything ?
I don't. The DT properties that are being checked are only present for in the DTs for RK3399 boards, so this shouldn't affect any other devices.
But while checking for this I noticed that I misspelled one of the properties, which had a dash in the old U-Boot-specific binding but an underscore in the official Linux binding. So I sent out a v2 of the series.
Cheers,
Mark
On 6/30/19 6:07 PM, Mark Kettenis wrote:
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 16:31:41 +0200
On 6/30/19 4:25 PM, Mark Kettenis wrote:
From: Marek Vasut marex@denx.de Date: Sun, 30 Jun 2019 15:36:03 +0200
On 6/30/19 3:31 PM, Kever Yang wrote:
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Is this a documented DT property or some ad-hoc U-Boot one ?
Yes, these are all standard Linux DT properties. See usb/generic.txt for "phy_type", and usb/dwc3.txt for "snps,dis-enblslpm_quirk" and "snps,dis-u2-freeclk-exists-quirk".
Is this a fix for this release or feature for next ?
Good question. The series fixes a regression, but that regression was already present in 2019.04 and you can still boot from uSD, eMMC or USB2 without this fixed.
Do we expect this to break anything ?
I don't. The DT properties that are being checked are only present for in the DTs for RK3399 boards, so this shouldn't affect any other devices.
But while checking for this I noticed that I misspelled one of the properties, which had a dash in the old U-Boot-specific binding but an underscore in the official Linux binding. So I sent out a v2 of the series.
So now that I see the other patches, this is certainly stuff for next release.
Remove RK3399 compatible strings as this driver is no longer used on that SoC.
Signed-off-by: Mark Kettenis kettenis@openbsd.org --- drivers/usb/host/xhci-rockchip.c | 2 -- 1 file changed, 2 deletions(-)
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index f19bea3a91..e7b0dbcca5 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -167,7 +167,6 @@ static int xhci_usb_remove(struct udevice *dev) }
static const struct udevice_id xhci_usb_ids[] = { - { .compatible = "rockchip,rk3399-xhci" }, { .compatible = "rockchip,rk3328-xhci" }, { } }; @@ -187,7 +186,6 @@ U_BOOT_DRIVER(usb_xhci) = { };
static const struct udevice_id usb_phy_ids[] = { - { .compatible = "rockchip,rk3399-usb3-phy" }, { .compatible = "rockchip,rk3328-usb3-phy" }, { } };
Hi Mark,
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
Remove RK3399 compatible strings as this driver is no longer used on that SoC.
Signed-off-by: Mark Kettenis kettenis@openbsd.org
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/usb/host/xhci-rockchip.c | 2 -- 1 file changed, 2 deletions(-)
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index f19bea3a91..e7b0dbcca5 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -167,7 +167,6 @@ static int xhci_usb_remove(struct udevice *dev) }
static const struct udevice_id xhci_usb_ids[] = {
- { .compatible = "rockchip,rk3399-xhci" }, { .compatible = "rockchip,rk3328-xhci" }, { }
}; @@ -187,7 +186,6 @@ U_BOOT_DRIVER(usb_xhci) = { };
static const struct udevice_id usb_phy_ids[] = {
- { .compatible = "rockchip,rk3399-usb3-phy" }, { .compatible = "rockchip,rk3328-usb3-phy" }, { }
};
On Sat, Jun 29, 2019 at 5:30 PM Mark Kettenis kettenis@openbsd.org wrote:
Ever since the dts files were synchronized in commit 0a09f2f1173d ("rockchip: Adjust rk3399 device tree to be closer to linux") USB3 support on Rockchip RK3399 boards has been broken.
This series restores the functionality by adopting the dwc3-of-simple glue driver.
Mark Kettenis (4): rockchip: clk: rk3399: handle clk_enable requests for USB3 usb: dwc3-of-simple: Add support for RK3399 usb: xhci-dwc3: Add USB2 PHY configuration rockchip: xhci: Remove RK3399 support
For the Series Tested-by: Peter Robinson pbrobinson@gmail.com
Tested by enabling the dwc3 controller on the Rock960
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ drivers/usb/host/xhci-rockchip.c | 2 -- 5 files changed, 34 insertions(+), 2 deletions(-)
-- 2.21.0
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Kever Yang -
Marek Vasut -
Mark Kettenis -
Mark Kettenis -
Peter Robinson