[PATCH 0/4] rockchip: rk3568: Device Tree updates
This series sync rk356x.dtsi and rk3566-radxa-cm3-io.dts from linux v6.4, add bootph-all to common pinctrl nodes and relax FIT load order in rk356x-u-boot.dtsi.
Patch 1-2 sync rk356x device tree from linux v6.4. Patch 3 move common pinctrl nodes to rk356x-u-boot.dtsi. Patch 4 change to try and load FIT from SD-card before eMMC when loading FIT from TPL+SPL media fails.
Jonas Karlman (4): rockchip: rk356x: Sync dtsi from linux v6.4 rockchip: rk3566-radxa-cm3-io: Sync dts from linux v6.4 rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 ------------ arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 ++ arch/arm/dts/rk3568-pinctrl.dtsi | 94 ++++++++++++++++++++ arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 54 ----------- arch/arm/dts/rk356x-u-boot.dtsi | 66 +++++++++++++- arch/arm/dts/rk356x.dtsi | 14 +-- 6 files changed, 175 insertions(+), 117 deletions(-)
Sync rk356x.dtsi from linux v6.4.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3568-pinctrl.dtsi | 94 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk356x.dtsi | 14 +++-- 2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi index 8f90c66dd9e9..0a979bfb63d9 100644 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -3117,4 +3117,98 @@ <0 RK_PA1 0 &pcfg_pull_none>; }; }; + + lcdc { + /omit-if-no-ref/ + lcdc_clock: lcdc-clock { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data16: lcdc-data16 { + rockchip,pins = + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data18: lcdc-data18 { + rockchip,pins = + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + }; diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index e0591c194bec..61680c7ac489 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -422,8 +422,9 @@ clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; rockchip,grf = <&grf>; };
@@ -743,8 +744,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; phy-names = "dphy"; phys = <&dsi_dphy0>; power-domains = <&power RK3568_PD_VO>; @@ -771,8 +772,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe070000 0x0 0x10000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; phy-names = "dphy"; phys = <&dsi_dphy1>; power-domains = <&power RK3568_PD_VO>; @@ -966,6 +967,7 @@ clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux"; device_type = "pci"; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>,
On 2023/7/3 01:34, Jonas Karlman wrote:
Sync rk356x.dtsi from linux v6.4.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3568-pinctrl.dtsi | 94 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk356x.dtsi | 14 +++-- 2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi index 8f90c66dd9e9..0a979bfb63d9 100644 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -3117,4 +3117,98 @@ <0 RK_PA1 0 &pcfg_pull_none>; }; };
- lcdc {
/omit-if-no-ref/lcdc_clock: lcdc-clock {rockchip,pins =/* lcdc_clk */<3 RK_PA0 1 &pcfg_pull_none>,/* lcdc_den */<3 RK_PC3 1 &pcfg_pull_none>,/* lcdc_hsync */<3 RK_PC1 1 &pcfg_pull_none>,/* lcdc_vsync */<3 RK_PC2 1 &pcfg_pull_none>;};/omit-if-no-ref/lcdc_data16: lcdc-data16 {rockchip,pins =/* lcdc_d3 */<2 RK_PD3 1 &pcfg_pull_none>,/* lcdc_d4 */<2 RK_PD4 1 &pcfg_pull_none>,/* lcdc_d5 */<2 RK_PD5 1 &pcfg_pull_none>,/* lcdc_d6 */<2 RK_PD6 1 &pcfg_pull_none>,/* lcdc_d7 */<2 RK_PD7 1 &pcfg_pull_none>,/* lcdc_d10 */<3 RK_PA3 1 &pcfg_pull_none>,/* lcdc_d11 */<3 RK_PA4 1 &pcfg_pull_none>,/* lcdc_d12 */<3 RK_PA5 1 &pcfg_pull_none>,/* lcdc_d13 */<3 RK_PA6 1 &pcfg_pull_none>,/* lcdc_d14 */<3 RK_PA7 1 &pcfg_pull_none>,/* lcdc_d15 */<3 RK_PB0 1 &pcfg_pull_none>,/* lcdc_d19 */<3 RK_PB4 1 &pcfg_pull_none>,/* lcdc_d20 */<3 RK_PB5 1 &pcfg_pull_none>,/* lcdc_d21 */<3 RK_PB6 1 &pcfg_pull_none>,/* lcdc_d22 */<3 RK_PB7 1 &pcfg_pull_none>,/* lcdc_d23 */<3 RK_PC0 1 &pcfg_pull_none>;};/omit-if-no-ref/lcdc_data18: lcdc-data18 {rockchip,pins =/* lcdc_d2 */<2 RK_PD2 1 &pcfg_pull_none>,/* lcdc_d3 */<2 RK_PD3 1 &pcfg_pull_none>,/* lcdc_d4 */<2 RK_PD4 1 &pcfg_pull_none>,/* lcdc_d5 */<2 RK_PD5 1 &pcfg_pull_none>,/* lcdc_d6 */<2 RK_PD6 1 &pcfg_pull_none>,/* lcdc_d7 */<2 RK_PD7 1 &pcfg_pull_none>,/* lcdc_d10 */<3 RK_PA3 1 &pcfg_pull_none>,/* lcdc_d11 */<3 RK_PA4 1 &pcfg_pull_none>,/* lcdc_d12 */<3 RK_PA5 1 &pcfg_pull_none>,/* lcdc_d13 */<3 RK_PA6 1 &pcfg_pull_none>,/* lcdc_d14 */<3 RK_PA7 1 &pcfg_pull_none>,/* lcdc_d15 */<3 RK_PB0 1 &pcfg_pull_none>,/* lcdc_d18 */<3 RK_PB3 1 &pcfg_pull_none>,/* lcdc_d19 */<3 RK_PB4 1 &pcfg_pull_none>,/* lcdc_d20 */<3 RK_PB5 1 &pcfg_pull_none>,/* lcdc_d21 */<3 RK_PB6 1 &pcfg_pull_none>,/* lcdc_d22 */<3 RK_PB7 1 &pcfg_pull_none>,/* lcdc_d23 */<3 RK_PC0 1 &pcfg_pull_none>;};- };
- };
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index e0591c194bec..61680c7ac489 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -422,8 +422,9 @@ clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;assigned-clock-rates = <1200000000>, <200000000>;
assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;assigned-clock-rates = <32768>, <1200000000>, <200000000>;assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;@@ -743,8 +744,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "hclk";clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
clock-names = "pclk";clocks = <&cru PCLK_DSITX_0>;@@ -771,8 +772,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe070000 0x0 0x10000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "hclk";clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
clock-names = "pclk";clocks = <&cru PCLK_DSITX_1>;@@ -966,6 +967,7 @@ clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux"; device_type = "pci";
#interrupt-cells = <1>;
Sync rk3566-radxa-cm3-io.dts from linux v6.4.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts index d89d5263cb5e..5e4236af4fcb 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -254,6 +254,14 @@ status = "okay"; };
+&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
On 2023/7/3 01:34, Jonas Karlman wrote:
Sync rk3566-radxa-cm3-io.dts from linux v6.4.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts index d89d5263cb5e..5e4236af4fcb 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -254,6 +254,14 @@ status = "okay"; };
+&usb2phy0_otg {
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
- &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and UART2 that are typically used by multiple boards. Unreferenced nodes are removed from the SPL device tree during a normal build.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 ----------------- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 54 ----------------- arch/arm/dts/rk356x-u-boot.dtsi | 64 ++++++++++++++++++++ 3 files changed, 64 insertions(+), 110 deletions(-)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 57b77151c57c..c925439f71cd 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -11,67 +11,11 @@ }; };
-&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_datastrobe { - bootph-all; -}; - -&pinctrl { - bootph-all; -}; - -&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - -&sdmmc0_bus4 { - bootph-all; -}; - -&sdmmc0_clk { - bootph-all; -}; - -&sdmmc0_cmd { - bootph-all; -}; - -&sdmmc0_det { - bootph-all; -}; - -&sdmmc0_pwren { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; };
-&uart2m0_xfer { - bootph-all; -}; - &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 0ba38851c25e..45e9390f202d 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -16,26 +16,6 @@ }; };
-&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_datastrobe { - bootph-all; -}; - -&fspi_pins { - bootph-all; -}; - &pcie2x1 { pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; /* Shared vpcie3v3-supply may cause a sys freeze, disable for now */ @@ -47,8 +27,6 @@ };
&pinctrl { - bootph-all; - pcie { pcie3x2_reset_h: pcie3x2-reset-h { rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -56,34 +34,6 @@ }; };
-&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - -&sdmmc0_bus4 { - bootph-all; -}; - -&sdmmc0_clk { - bootph-all; -}; - -&sdmmc0_cmd { - bootph-all; -}; - -&sdmmc0_det { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; @@ -117,10 +67,6 @@ status = "disabled"; };
-&uart2m0_xfer { - bootph-all; -}; - &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index c340c2bba6ff..89c0d830b632 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -59,6 +59,70 @@ status = "okay"; };
+&pinctrl { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&emmc_bus8 { + bootph-all; +}; + +&emmc_clk { + bootph-all; +}; + +&emmc_cmd { + bootph-all; +}; + +&emmc_datastrobe { + bootph-all; +}; + +&emmc_rstnout { + bootph-all; +}; + +&fspi_pins { + bootph-all; +}; + +&sdmmc0_bus4 { + bootph-all; +}; + +&sdmmc0_clk { + bootph-all; +}; + +&sdmmc0_cmd { + bootph-all; +}; + +&sdmmc0_det { + bootph-all; +}; + +&sdmmc0_pwren { + bootph-all; +}; + +&uart2m0_xfer { + bootph-all; +}; + &sdhci { bootph-pre-ram; status = "okay";
On 2023/7/3 01:34, Jonas Karlman wrote:
Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and UART2 that are typically used by multiple boards. Unreferenced nodes are removed from the SPL device tree during a normal build.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 ----------------- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 54 ----------------- arch/arm/dts/rk356x-u-boot.dtsi | 64 ++++++++++++++++++++ 3 files changed, 64 insertions(+), 110 deletions(-)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 57b77151c57c..c925439f71cd 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -11,67 +11,11 @@ }; };
-&emmc_bus8 {
- bootph-all;
-};
-&emmc_clk {
- bootph-all;
-};
-&emmc_cmd {
- bootph-all;
-};
-&emmc_datastrobe {
- bootph-all;
-};
-&pinctrl {
- bootph-all;
-};
-&pcfg_pull_none {
- bootph-all;
-};
-&pcfg_pull_up_drv_level_2 {
- bootph-all;
-};
-&pcfg_pull_up {
- bootph-all;
-};
-&sdmmc0_bus4 {
- bootph-all;
-};
-&sdmmc0_clk {
- bootph-all;
-};
-&sdmmc0_cmd {
- bootph-all;
-};
-&sdmmc0_det {
- bootph-all;
-};
-&sdmmc0_pwren {
- bootph-all;
-};
- &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; };
-&uart2m0_xfer {
- bootph-all;
-};
- &uart2 { clock-frequency = <24000000>; bootph-all;
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 0ba38851c25e..45e9390f202d 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -16,26 +16,6 @@ }; };
-&emmc_bus8 {
- bootph-all;
-};
-&emmc_clk {
- bootph-all;
-};
-&emmc_cmd {
- bootph-all;
-};
-&emmc_datastrobe {
- bootph-all;
-};
-&fspi_pins {
- bootph-all;
-};
- &pcie2x1 { pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; /* Shared vpcie3v3-supply may cause a sys freeze, disable for now */
@@ -47,8 +27,6 @@ };
&pinctrl {
- bootph-all;
- pcie { pcie3x2_reset_h: pcie3x2-reset-h { rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -56,34 +34,6 @@ }; };
-&pcfg_pull_none {
- bootph-all;
-};
-&pcfg_pull_up_drv_level_2 {
- bootph-all;
-};
-&pcfg_pull_up {
- bootph-all;
-};
-&sdmmc0_bus4 {
- bootph-all;
-};
-&sdmmc0_clk {
- bootph-all;
-};
-&sdmmc0_cmd {
- bootph-all;
-};
-&sdmmc0_det {
- bootph-all;
-};
- &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v;
@@ -117,10 +67,6 @@ status = "disabled"; };
-&uart2m0_xfer {
- bootph-all;
-};
- &uart2 { clock-frequency = <24000000>; bootph-all;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index c340c2bba6ff..89c0d830b632 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -59,6 +59,70 @@ status = "okay"; };
+&pinctrl {
- bootph-all;
+};
+&pcfg_pull_none {
- bootph-all;
+};
+&pcfg_pull_up_drv_level_2 {
- bootph-all;
+};
+&pcfg_pull_up {
- bootph-all;
+};
+&emmc_bus8 {
- bootph-all;
+};
+&emmc_clk {
- bootph-all;
+};
+&emmc_cmd {
- bootph-all;
+};
+&emmc_datastrobe {
- bootph-all;
+};
+&emmc_rstnout {
- bootph-all;
+};
+&fspi_pins {
- bootph-all;
+};
+&sdmmc0_bus4 {
- bootph-all;
+};
+&sdmmc0_clk {
- bootph-all;
+};
+&sdmmc0_cmd {
- bootph-all;
+};
+&sdmmc0_det {
- bootph-all;
+};
+&sdmmc0_pwren {
- bootph-all;
+};
+&uart2m0_xfer {
- bootph-all;
+};
- &sdhci { bootph-pre-ram; status = "okay";
BootRom will try to load TPL+SPL from media in the following order: - SPI NOR Flash - SPI NAND Flash - NAND Flash - eMMC - SDMMC
SPL will try to load FIT from media in the order defined in the device tree u-boot,spl-boot-order property.
Change the default order to load FIT from to: - same media as TPL+SPL - SDMMC - eMMC
Boards with strict load order requirements should override the u-boot,spl-boot-order property in the board specific u-boot.dtsi.
Fixes: 42f67fb51cb4 ("rockchip: rk3568: Fix boot device detection") Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk356x-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 89c0d830b632..5644f78ec774 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ };
chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; };
dmc: dmc {
On 2023/7/3 01:34, Jonas Karlman wrote:
BootRom will try to load TPL+SPL from media in the following order:
- SPI NOR Flash
- SPI NAND Flash
- NAND Flash
- eMMC
- SDMMC
SPL will try to load FIT from media in the order defined in the device tree u-boot,spl-boot-order property.
Change the default order to load FIT from to:
- same media as TPL+SPL
- SDMMC
- eMMC
Boards with strict load order requirements should override the u-boot,spl-boot-order property in the board specific u-boot.dtsi.
Fixes: 42f67fb51cb4 ("rockchip: rk3568: Fix boot device detection") Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk356x-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 89c0d830b632..5644f78ec774 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ };
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;};
dmc: dmc {
participants (2)
-
Jonas Karlman -
Kever Yang