For LS102xA, the size of spl/u-boot-spl.bin is variable. This patch adds the support to deal with the variable u-boot size in pblimage tool. It will be padded to 64 byte boundary.

Use pblimage_check_params() to add the specific operations for ARM, such as PBI CRC and END command and the calculation of pbl_cmd_initaddr.

Signed-off-by: Alison Wang alison.wang@freescale.com --- Change log: v2: Remove the definition of CONFIG_SPL_MAX_SIZE. Pad the variable u-boot size to 64 byte boundary in pblimage tool. Use pblimage_check_params() insteady of basing on the file name.

Makefile | 3 +- tools/pblimage.c | 106 ++++++++++++++++++++++++++++++++++++++----------------- 2 files changed, 75 insertions(+), 34 deletions(-)

diff --git a/Makefile b/Makefile index 6221113..0ba106c 100644 --- a/Makefile +++ b/Makefile @@ -963,7 +963,8 @@ u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE #concatenated with u-boot binary. It is need by PowerPC SoC having #internal SRAM <= 512KB. MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ - -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \ + -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE)

spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/tools/pblimage.c b/tools/pblimage.c index 6e6e801..652c8d8 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -8,6 +8,10 @@ #include "pblimage.h" #include "pbl_crc32.h"

+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define PBL_ACS_CONT_CMD 0x81000000 +#define PBL_ADDR_24BIT_MASK 0x00ffffff + /* * Initialize to an invalid value. */ @@ -22,6 +26,13 @@ static int pbl_size; static char *fname = "Unknown"; static int lineno = -1; static struct pbl_header pblimage_header; +static int uboot_size; +static int arch_flag; + +static uint32_t pbl_cmd_initaddr; +static uint32_t pbi_crc_cmd1; +static uint32_t pbi_crc_cmd2; +static uint32_t pbl_end_cmd[4];

static union { @@ -38,20 +49,6 @@ static union * start offset by subtracting the size of the u-boot image from the * top of the allowable 24-bit range. */ -static void init_next_pbl_cmd(FILE *fp_uboot) -{ - struct stat st; - int fd = fileno(fp_uboot); - - if (fstat(fd, &st) == -1) { - printf("Error: Could not determine u-boot image size. %s\n", - strerror(errno)); - exit(EXIT_FAILURE); - } - - next_pbl_cmd = 0x82000000 - st.st_size; -} - static void generate_pbl_cmd(void) { uint32_t val = next_pbl_cmd; @@ -69,8 +66,12 @@ static void pbl_fget(size_t size, FILE *stream) unsigned char c; int c_temp;

- while (size && (c_temp = fgetc(stream)) != EOF) { - c = (unsigned char)c_temp; + while (size) { + c_temp = fgetc(stream); + if (c_temp != EOF) + c = (unsigned char)c_temp; + else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM)) + c = 0xff; *pmem_buf++ = c; pbl_size++; size--; @@ -80,8 +81,8 @@ static void pbl_fget(size_t size, FILE *stream) /* load split u-boot with PBI command 81xxxxxx. */ static void load_uboot(FILE *fp_uboot) { - init_next_pbl_cmd(fp_uboot); - while (next_pbl_cmd < 0x82000000) { + next_pbl_cmd = pbl_cmd_initaddr - uboot_size; + while (next_pbl_cmd < pbl_cmd_initaddr) { generate_pbl_cmd(); pbl_fget(64, fp_uboot); } @@ -154,8 +155,6 @@ static uint32_t reverse_byte(uint32_t val) /* write end command and crc command to memory. */ static void add_end_cmd(void) { - uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, - 0x091380c0, 0x00000000}; uint32_t crc32_pbl; int i; unsigned char *p = (unsigned char *)&pbl_end_cmd; @@ -172,8 +171,8 @@ static void add_end_cmd(void)

/* Add PBI CRC command. */ *pmem_buf++ = 0x08; - *pmem_buf++ = 0x13; - *pmem_buf++ = 0x80; + *pmem_buf++ = pbi_crc_cmd1; + *pmem_buf++ = pbi_crc_cmd2; *pmem_buf++ = 0x40; pbl_size += 4;

@@ -184,17 +183,6 @@ static void add_end_cmd(void) *pmem_buf++ = (crc32_pbl >> 8) & 0xff; *pmem_buf++ = (crc32_pbl) & 0xff; pbl_size += 4; - - if ((pbl_size % 16) != 0) { - for (i = 0; i < 8; i++) { - *pmem_buf++ = 0x0; - pbl_size++; - } - } - if ((pbl_size % 16 != 0)) { - printf("Error: Bad size of image file\n"); - exit(EXIT_FAILURE); - } }

void pbl_load_uboot(int ifd, struct image_tool_params *params) @@ -268,12 +256,64 @@ static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, /*nothing need to do, pbl_load_uboot takes care of whole file. */ }

+int pblimage_check_params(struct image_tool_params *params) +{ + FILE *fp_uboot; + int fd; + struct stat st; + + if (!params) + return EXIT_FAILURE; + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + fd = fileno(fp_uboot); + + if (fstat(fd, &st) == -1) { + printf("Error: Could not determine u-boot image size. %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + /* For the variable size, we need to pad it to 64 byte boundary */ + uboot_size = roundup(st.st_size, 64); + + if (params->arch == IH_ARCH_ARM) { + arch_flag = IH_ARCH_ARM; + pbi_crc_cmd1 = 0x61; + pbi_crc_cmd2 = 0; + pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK; + pbl_cmd_initaddr |= PBL_ACS_CONT_CMD; + pbl_cmd_initaddr |= uboot_size; + pbl_end_cmd[0] = 0x09610000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x096100c0; + pbl_end_cmd[3] = 0x00000000; + } else if (params->arch == IH_ARCH_PPC) { + arch_flag = IH_ARCH_PPC; + pbi_crc_cmd1 = 0x13; + pbi_crc_cmd2 = 0x80; + pbl_cmd_initaddr = 0x82000000; + pbl_end_cmd[0] = 0x09138000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x091380c0; + pbl_end_cmd[3] = 0x00000000; + } + + next_pbl_cmd = pbl_cmd_initaddr; + return 0; +}; + /* pblimage parameters */ static struct image_type_params pblimage_params = { .name = "Freescale PBL Boot Image support", .header_size = sizeof(struct pbl_header), .hdr = (void *)&pblimage_header, .check_image_type = pblimage_check_image_types, + .check_params = pblimage_check_params, .verify_header = pblimage_verify_header, .print_header = pblimage_print_header, .set_header = pblimage_set_header,

On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL.

Signed-off-by: Alison Wang alison.wang@freescale.com --- Change log: v2: New file.

arch/arm/cpu/u-boot-spl.lds | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 4beddf0..bddef74 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,6 +32,9 @@ SECTIONS }

. = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + }

. = .;

Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding.

Signed-off-by: Jason Jin jason.jin@freescale.com Signed-off-by: Alison Wang alison.wang@freescale.com --- Change log: v2: No change.

board/freescale/common/qixis.h | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index d8fed14..52d2021 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif

+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \

This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Chen Lu chen.lu@freescale.com Signed-off-by: Alison Wang alison.wang@freescale.com Signed-off-by: Jason Jin jason.jin@freescale.com --- Change log: v2: Use generic u-boot-spl.lds.

board/freescale/ls1021atwr/ls1021atwr.c | 31 +++++++++++++++- board/freescale/ls1021atwr/ls102xa_pbi.cfg | 13 +++++++ board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 ++++++++ configs/ls1021atwr_sdcard_defconfig | 4 +++ include/configs/ls1021atwr.h | 52 +++++++++++++++++++++++++++ 5 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021atwr_sdcard_defconfig

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..7c0654a 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -16,6 +16,7 @@ #include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -65,6 +66,7 @@ struct cpld_data { u8 rev2; /* Reserved */ };

+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) static void convert_serdes_mux(int type, int need_reset);

void cpld_show(void) @@ -100,11 +102,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif

int checkboard(void) { puts("Board: LS1021ATWR\n"); +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) cpld_show(); +#endif

return 0; } @@ -213,6 +218,7 @@ int board_eth_init(bd_t *bis) } #endif

+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -244,6 +250,7 @@ int config_serdes_mux(void)

return 0; } +#endif

int board_early_init_f(void) { @@ -270,13 +277,33 @@ int board_early_init_f(void) return 0; }

+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int board_init(void) { #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) config_serdes_mux(); #endif - +#endif return 0; }

@@ -304,6 +331,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); }

+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -486,3 +514,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 0000000..76373ce --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,13 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +09570200 00000000 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00080000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..6c83e3b --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#20000000 00404000 60025a00 21042000 +#00200000 00000000 00000000 01038000 +#00000000 001b1200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 00407900 60025a00 21046000 +00000000 00000000 00000000 01038000 +20024800 881b1540 00000000 00000000 diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig new file mode 100644 index 0000000..0eb556a --- /dev/null +++ b/configs/ls1021atwr_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272..cbf4082 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,40 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000

+#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -51,6 +85,7 @@ /* * IFC Definitions */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -93,6 +128,7 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#endif

/* CPLD */

@@ -225,7 +261,12 @@

#define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_CMD_IMLS +#else +#undef CONFIG_CMD_IMLS +#endif

#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -272,17 +313,28 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif

/* * Environment */ #define CONFIG_ENV_OVERWRITE

+#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif

#define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP