Subject: [PATCH] Consolidate mpc83xx cpu for mpc8360e

---

cpu/mpc83xx/cpu.c | 39 ++++-- cpu/mpc83xx/cpu_init.c | 26 +++- cpu/mpc83xx/i2c.c | 10 + cpu/mpc83xx/spd_sdram.c | 333 +++++++++++++++++++++++++++++------------------ cpu/mpc83xx/speed.c | 226 ++++++++++++++++++-------------- cpu/mpc83xx/start.S | 39 ++++-- 6 files changed, 414 insertions(+), 259 deletions(-)

2ec049fdc52d6133a335b1073bf6f749048d1817 diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 20bba6c..16c4ee4 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,6 +23,8 @@ * * 20050101: Eran Liberty (liberty@freescale.com) * Initial file creating (porting from 85XX & 8260) + * 20060520: Dave Liu (Daveliu@freescale.com) + * Add support for mpc8360e */

/* @@ -43,28 +45,43 @@ DECLARE_GLOBAL_DATA_PTR;

int checkcpu(void) { + volatile immap_t *immr; + u32 spridr; ulong clock = gd->cpu_clk; u32 pvr = get_pvr(); char buf[32];

+ immr = (immap_t *)CFG_IMMRBAR; + if ((pvr & 0xFFFF0000) != PVR_83xx) { puts("Not MPC83xx Family!!!\n"); return -1; }

- puts("CPU: MPC83xx, "); - switch(pvr) { - case PVR_8349_REV10: + spridr = immr->sysconf.spridr; + puts("CPU: "); + switch(spridr) { + case SPR_8349E_REV10: + case SPR_8349E_REV11: + puts("MPC8349E, "); break; - case PVR_8349_REV11: + case SPR_8360E_REV10: + case SPR_8360E_REV11: + case SPR_8360E_REV12: + puts("MPC8360E, "); break; default: puts("Rev: Unknown\n"); return -1; /* Not sure what this is */ } - printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4, - (pvr & 0x0f), strmhz(buf, clock)); - +#if defined(CONFIG_MPC8349) + printf("Rev: %02x at %s MHz\n", + (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), + strmhz(buf, clock)); +#elif defined(CONFIG_MPC8360) + printf("Rev: %02x at %s MHz\n", + spridr & 0x0000FFFF, strmhz(buf, clock)); +#endif return 0; }

@@ -195,7 +212,7 @@ #if defined(CONFIG_DDR_ECC) void dma_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile dma8349_t *dma = &immap->dma; + volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 dmamr0 = swab32(dma->dmamr0);

@@ -226,7 +243,7 @@ void dma_init(void) uint dma_check(void) { volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile dma8349_t *dma = &immap->dma; + volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 byte_count = swab32(dma->dmabcr0);

@@ -245,7 +262,7 @@ uint dma_check(void) int dma_xfer(void *dest, u32 count, void *src) { volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile dma8349_t *dma = &immap->dma; + volatile dma83xx_t *dma = &immap->dma; volatile u32 dmamr0;

/* initialize DMASARn, DMADAR and DMAABCRn */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 6ed0992..429fe9a 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,6 +23,8 @@ * * 20050101: Eran Liberty (liberty@freescale.com) * Initial file creating (porting from 85XX & 8260) + * 20060520: Dave Liu (Daveliu@freescale.com) + * Add support for mpc8360e */

#include <common.h> @@ -59,17 +61,27 @@ void cpu_init_f (volatile immap_t * im) /* LCRR - Clock Ratio Register (10.3.1.16) */ im->lbus.lcrr = CFG_LCRR;

+#if defined (CONFIG_MPC8349) + im->clk.sccr = CFG_SCCR_VAL; +#endif /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN;

- /* System General Purpose Register */ -#ifdef CFG_SICRH - im->sysconf.sicrh = CFG_SICRH; -#endif -#ifdef CFG_SICRL - im->sysconf.sicrl = CFG_SICRL; + /* System General Purpose Register */ +#if defined (CONFIG_MPC8360) + im->sysconf.sicrh = CFG_SICRH_VAL; + im->sysconf.sicrl = CFG_SICRL_VAL; +#elif defined(CONFIG_MPC8349) + im->sysconf.sicrh = SICRH_TSOBI1; + im->sysconf.sicrl = SICRL_LDP_A; +#else +#error sicrl no stuff! #endif

+ /* DDR control driver register */ +#if defined (CONFIG_DDR_II) + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; +#endif /* * Memory Controller: */ diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c index 70450f9..08d2c93 100644 --- a/cpu/mpc83xx/i2c.c +++ b/cpu/mpc83xx/i2c.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2006 Freescale Semiconductor, Inc. + * * (C) Copyright 2003,Motorola Inc. * Xianghua Xiao x.xiao@motorola.com * Adapted for Motorola 85xx chip. @@ -31,6 +33,8 @@ * * 20050101: Eran Liberty (liberty@freescale.com) * Initial file creating (porting from 85XX & 8260) + * 20060601: Dave Liu (daveliu@freescale.com) + * Unified variable names for mpc83xx */

#include <common.h> @@ -41,8 +45,8 @@ #ifdef CONFIG_HARD_I2C #include <i2c.h> #include <asm/i2c.h>

-#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) -i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); +#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) || defined(CONFIG_MPC8360EPB) +i2c_t * mpc83xx_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); #endif

void @@ -52,7 +56,7 @@ i2c_init(int speed, int slaveadd) writeb(0x00 , &I2C->cr);

/* set clock */ - writeb(0x3f, &I2C->fdr); + writeb(speed, &I2C->fdr);

/* set default filter */ writeb(0x10,&I2C->dfsrr); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 48624fe..3b5ee33 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2006 Freescale Semiconductor, Inc. + * * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -28,6 +30,10 @@ * * 20050101: Eran Liberty (liberty@freescale.com) * Initial file creating (porting from 85XX & 8260) + * 20060601: Dave Liu (daveliu@freescale.com) + * mpc8360 support and DDR ECC support + * unify variable names for 83xx + * code cleanup */

#include <common.h> @@ -39,7 +45,7 @@ #include <spd_sdram.h>

#ifdef CONFIG_SPD_EEPROM

-#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void dma_init(void); extern uint dma_check(void); extern int dma_xfer(void *dest, uint count, void *src); @@ -52,15 +58,18 @@ #endif /* * Convert picoseconds into clock cycles (rounding up if needed). */ +extern ulong get_ddr_clk(ulong dummy);

int picos_to_clk(int picos) { + unsigned int ddr_bus_clk; int clks;

- clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { - clks++; + ddr_bus_clk = get_ddr_clk(0) >> 1; + clks = picos / ((1000000000 / ddr_bus_clk) * 1000); + if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) { + clks++; }

return clks; @@ -104,32 +113,71 @@ #endif /* SPD_DEBUG */ long int spd_sdram() { volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile ddr8349_t *ddr = &immap->ddr; - volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; + volatile ddr83xx_t *ddr = &immap->ddr; + volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; - unsigned tmp, tmp1; + unsigned tmp; unsigned int memsize; unsigned int law_size; - unsigned char caslat; - unsigned int trfc, trfc_clk, trfc_low; + unsigned char caslat, caslat_ctrl; + unsigned char burstlen; + unsigned int max_bus_clk; + unsigned int max_data_rate, effective_data_rate; + unsigned int ddrc_clk; + unsigned sdram_cfg; + unsigned int ddrc_ecc_enable;

+ + /* Read SPD parameters with I2C */ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif - if (spd.nrows > 2) { - puts("DDR:Only two chip selects are supported on ADS.\n"); + /* Check the memory type */ + if (spd.mem_type != SPD_MEMTYPE_DDR) { + printf("DDR: Module mem type is %02X\n", spd.mem_type); return 0; }

- if (spd.nrow_addr < 12 - || spd.nrow_addr > 14 - || spd.ncol_addr < 8 - || spd.ncol_addr > 11) { - puts("DDR:Row or Col number unsupported.\n"); + /* Check the number of physical bank */ + if (spd.nrows > 2) { + printf("DDR: The number of physical bank is %02X\n", spd.nrows); return 0; }

+ /* Check if the number of row of the module is in the range of DDRC */ + if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + printf("DDR: Row number is out of range of DDRC, row=%02X\n", + spd.nrow_addr); + return 0; + } + + /* Check if the number of col of the module is in the range of DDRC */ + if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { + printf("DDR: Col number is out of range of DDRC, col=%02X\n", + spd.ncol_addr); + return 0; + } + /* Setup DDR chip select register */ +#ifdef CONFIG_MPC8360EPB + ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; + ddr->cs_config[0] = ( 1 << 31 + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); + + if (spd.nrows == 2) { + ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) + | ((banksize(spd.row_dens) >> 23) - 1) ); + ddr->cs_config[1] = ( 1<<31 + | (spd.nrow_addr-12) << 8 + | (spd.ncol_addr-8) ); + debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); + debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); + } +#else ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[2] = ( 1 << 31 | (spd.nrow_addr - 12) << 8 @@ -147,6 +195,7 @@ #endif debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } +#endif

if (spd.mem_type != 0x07) { puts("No DDR module found!\n"); @@ -172,54 +221,84 @@ #endif debug("DDR:ar=0x%08x\n", ecm->ar);

/* - * find the largest CAS + * Find the largest CAS by locating the highest 1 bit + * in the spd.cas_lat field. Translate it to a DDR + * controller field value: + * + * CAS Lat DDR I Ctrl + * Clocks SPD Bit Value + * -------+--------+--------- + * 1.0 0 001 + * 1.5 1 010 + * 2.0 2 011 + * 2.5 3 100 + * 3.0 4 101 + * 3.5 5 110 + * 4.0 6 111 */ - if(spd.cas_lat & 0x40) { - caslat = 7; - } else if (spd.cas_lat & 0x20) { - caslat = 6; - } else if (spd.cas_lat & 0x10) { - caslat = 5; - } else if (spd.cas_lat & 0x08) { - caslat = 4; - } else if (spd.cas_lat & 0x04) { - caslat = 3; - } else if (spd.cas_lat & 0x02) { - caslat = 2; - } else if (spd.cas_lat & 0x01) { - caslat = 1; - } else { - puts("DDR:no valid CAS Latency information.\n"); + caslat = __ilog2(spd.cas_lat); + + if (caslat > 4 ) { + printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat); return 0; } + max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + + (spd.clk_cycle & 0x0f)); + max_data_rate = max_bus_clk * 2; + + debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);

- tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 - + (spd.clk_cycle & 0x0f)); - debug("DDR:Module maximum data rate is: %dMhz\n", tmp); - - tmp1 = get_bus_freq(0) / 1000000; - if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { - /* 90~230 range, treated as DDR 200 */ - if (spd.clk_cycle3 == 0xa0) - caslat -= 2; - else if(spd.clk_cycle2 == 0xa0) - caslat--; - } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { - /* 230-280 range, treated as DDR 266 */ - if (spd.clk_cycle3 == 0x75) - caslat -= 2; - else if (spd.clk_cycle2 == 0x75) - caslat--; - } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { - /* 280~350 range, treated as DDR 333 */ - if (spd.clk_cycle3 == 0x60) - caslat -= 2; - else if (spd.clk_cycle2 == 0x60) - caslat--; - } else if (tmp1 < 90 || tmp1 >= 350) { - /* DDR rate out-of-range */ - puts("DDR:platform frequency is not fit for DDR rate\n"); + ddrc_clk = get_ddr_clk(0) / 1000000; + + if (max_data_rate >= 390) { /* it is DDR 400 */ + printf("DDR: platform not support DDR 400\n"); return 0; + } else if (max_data_rate >= 323) { /* it is DDR 333 */ + if (ddrc_clk <= 350 && ddrc_clk > 280) { + /* DDRC clk at 280~350 */ + effective_data_rate = 333; /* 6ns */ + caslat = caslat; + } else if (ddrc_clk <= 280 && ddrc_clk > 230) { + /* DDRC clk at 230~280 */ + if (spd.clk_cycle2 == 0x75) { + effective_data_rate = 266; /* 7.5ns */ + caslat = caslat - 1; + } + } else if (ddrc_clk <= 230 && ddrc_clk > 90) { + /* DDRC clk at 90~230 */ + if (spd.clk_cycle3 == 0xa0) { + effective_data_rate = 200; /* 10ns */ + caslat = caslat - 2; + } + } + } else if (max_data_rate >= 256) { /* it is DDR 266 */ + if (ddrc_clk <= 350 && ddrc_clk > 280) { + /* DDRC clk at 280~350 */ + printf("DDR: DDR controller freq is more than " + "max data rate of the module\n"); + return 0; + } else if (ddrc_clk <= 280 && ddrc_clk > 230) { + /* DDRC clk at 230~280 */ + effective_data_rate = 266; /* 7.5ns */ + caslat = caslat; + } else if (ddrc_clk <= 230 && ddrc_clk > 90) { + /* DDRC clk at 90~230 */ + if (spd.clk_cycle2 == 0xa0) { + effective_data_rate = 200; /* 10ns */ + caslat = caslat - 1; + } + } + } else if (max_data_rate >= 190) { /* it is DDR 200 */ + if (ddrc_clk <= 350 && ddrc_clk > 230) { + /* DDRC clk at 230~350 */ + printf("DDR: DDR controller freq is more than " + "max data rate of the module\n"); + return 0; + } else if (ddrc_clk <= 230 && ddrc_clk > 90) { + /* DDRC clk at 90~230 */ + effective_data_rate = 200; /* 10ns */ + caslat = caslat; + } }

/* @@ -229,16 +308,14 @@ #endif * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, * use conservative value here. */ - trfc = spd.trfc * 1000; /* up to ps */ - trfc_clk = picos_to_clk(trfc); - trfc_low = (trfc_clk - 8) & 0xf; + caslat_ctrl = (caslat + 1) & 0x07; /* see as above */

ddr->timing_cfg_1 = (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | - ((caslat & 0x07) << 16 ) | - (trfc_low << 12 ) | + ((caslat_ctrl & 0x07) << 16 ) | + (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) | ( 0x300 ) | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);

@@ -246,36 +323,48 @@ #endif

debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); + /* Setup init value, but not enable */ + ddr->sdram_cfg = 0x42000000; + + /* Check DIMM data bus width */ + if (spd.dataw_lsb == 0x20) + { + burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ + printf("\n DDR DIMM: data bus width is 32 bit"); + } + else + { + burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ + printf("\n DDR DIMM: data bus width is 64 bit"); + }

- /* - * Only DDR I is supported - * DDR I and II have different mode-register-set definition + /* Is this an ECC DDR chip? */ + if (spd.config == 0x02) { + printf(" with ECC\n"); + } + else + printf(" without ECC\n"); + + /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, + Burst type is sequential */ switch(caslat) { + case 1: + ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ + break; case 2: - tmp = 0x50; /* 1.5 */ + ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ break; case 3: - tmp = 0x20; /* 2.0 */ + ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ break; case 4: - tmp = 0x60; /* 2.5 */ - break; - case 5: - tmp = 0x30; /* 3.0 */ + ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ break; default: - puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); + printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); return 0; } -#if defined (CONFIG_DDR_32BIT) - /* set burst length to 8 for 32-bit data path */ - tmp |= 0x03; -#else - /* set burst length to 4 - default for 64-bit data path */ - tmp |= 0x02; -#endif - ddr->sdram_mode = tmp; debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);

switch(spd.refresh) { @@ -315,33 +404,15 @@ #endif ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);

- /* - * Is this an ECC DDR chip? - */ -#if defined(CONFIG_DDR_ECC) - if (spd.config == 0x02) { - /* disable error detection */ - ddr->err_disable = ~ECC_ERROR_ENABLE; + /* SS_EN = 0, source synchronous disable + * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd + */ + ddr->sdram_clk_cntl = 0x00000000; + debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);

- /* set single bit error threshold to maximum value, - * reset counter to zero */ - ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | - (0 << ECC_ERROR_MAN_SBEC_SHIFT); - } - debug("DDR:err_disable=0x%08x\n", ddr->err_disable); - debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); -#endif asm("sync;isync");

- udelay(500); - - /* - * SS_EN=1, - * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM - * clock cycle after address/command - */ - /*ddr->sdram_clk_cntl = 0x82000000;*/ - ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05); + udelay(600);

/* * Figure out the settings for the sdram_cfg register. Build up @@ -352,38 +423,48 @@ #endif * sdram_cfg[0] = 1 (ddr sdram logic enable) * sdram_cfg[1] = 1 (self-refresh-enable) * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) + * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) + * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) */ - tmp = 0xc2000000; + sdram_cfg = 0xC2000000;

-#if defined (CONFIG_DDR_32BIT) - /* in 32-Bit mode burst len is 8 beats */ - tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); -#endif - /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) - */ - if (spd.mod_attr == 0x26) { - tmp |= 0x10000000; + /* sdram_cfg[3] = RD_EN - registered DIMM enable */ + if (spd.mod_attr & 0x02) { + sdram_cfg |= 0x10000000; + } + + /* The DIMM is 32bit width */ + if (spd.dataw_lsb == 0x20) { + sdram_cfg |= 0x000C0000; } + ddrc_ecc_enable = 0;

#if defined(CONFIG_DDR_ECC) - /* - * If the user wanted ECC (enabled via sdram_cfg[2]) - */ + /* Enable ECC with sdram_cfg[2] */ if (spd.config == 0x02) { - tmp |= SDRAM_CFG_ECC_EN; + sdram_cfg |= 0x20000000; + ddrc_ecc_enable = 1; + /* disable error detection */ + ddr->err_disable = ~ECC_ERROR_ENABLE; + /* set single bit error threshold to maximum value, + * reset counter to zero */ + ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | + (0 << ECC_ERROR_MAN_SBEC_SHIFT); } + + debug("DDR:err_disable=0x%08x\n", ddr->err_disable); + debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif + printf(" DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");

#if defined(CONFIG_DDR_2T_TIMING) /* * Enable 2T timing by setting sdram_cfg[16]. */ - tmp |= SDRAM_CFG_2T_EN; + sdram_cfg |= SDRAM_CFG_2T_EN; #endif - - ddr->sdram_cfg = tmp; + /* Enable controller, and GO! */ + ddr->sdram_cfg = sdram_cfg; asm("sync;isync"); udelay(500);

@@ -393,7 +474,7 @@ #endif #endif /* CONFIG_SPD_EEPROM */

-#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) /* * Use timebase counter, get_timer() is not availabe * at this point of initialization yet. @@ -431,7 +512,7 @@ void ddr_enable_ecc(unsigned int dram_si { uint *p; volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile ddr8349_t *ddr = &immap->ddr; + volatile ddr83xx_t *ddr= &immap->ddr; unsigned long t_start, t_end; #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) uint i; diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index ad6b3f6..f3f3a9a 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright 2004 Freescale Semiconductor, Inc. + * (C) Copyright 2006 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -26,6 +26,10 @@ * * 20050101: Eran Liberty (liberty@freescale.com) * Initial file creating (porting from 85XX & 8260) + * 200506: Daveliu (daveliu@freescale.com) + * add mpc8360e support + * Code cleanup + * */

#include <common.h> @@ -104,79 +108,53 @@ int get_clocks (void) u32 lcrr;

u32 csb_clk; +#if defined(CONFIG_MPC8349) u32 tsec1_clk; u32 tsec2_clk; - u32 core_clk; u32 usbmph_clk; u32 usbdr_clk; - u32 i2c_clk; +#endif + u32 core_clk; + u32 i2c1_clk; + u32 i2c2_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; u32 ddr_clk; +#if defined (CONFIG_MPC8360) + u32 qepmf; + u32 qepdf; + u32 ddr_sec_clk; + u32 qe_clk; + u32 brg_clk; +#endif

if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - -#ifndef CFG_HRCW_HIGH -# error "CFG_HRCW_HIGH must be defined in board config file" -#endif /* CFG_HCWD_HIGH */ - -#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) - -# ifndef CONFIG_83XX_CLKIN -# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file" -# endif /* CONFIG_83XX_CLKIN */ -# ifdef CONFIG_83XX_PCICLK -# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred" -# endif /* CONFIG_83XX_PCICLK */ - - /* PCI Host Mode */ - if (!(im->reset.rcwh & RCWH_PCIHOST)) { - /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH - * the im->reset.rcwhr PCI Host Mode is disabled - * FIXME: findout if there is a way to issue some warning */ - return -2; - } - if (im->clk.spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN */ - pci_sync_in = CONFIG_83XX_CLKIN / 2; - } - else { - pci_sync_in = CONFIG_83XX_CLKIN; - } - -#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */ - -# ifdef CONFIG_83XX_CLKIN -# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred" -# endif /* CONFIG_83XX_CLKIN */ -# ifndef CONFIG_83XX_PCICLK -# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file" -# endif /* CONFIG_83XX_PCICLK */ - - /* PCI Agent Mode */ - if (im->reset.rcwh & RCWH_PCIHOST) { - /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH - * the im->reset.rcwhr PCI Host Mode is enabled */ - return -3; - } - pci_sync_in = CONFIG_83XX_PCICLK; - -#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ - - /* we have up to date pci_sync_in */ - spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); - - if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { - csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; + + if (im->reset.rcwh & HRCWH_PCI_HOST) { +#if defined(CONFIG_83XX_CLKIN) + pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); +#else + pci_sync_in = 0xDEADBEEF; +#endif } else { - csb_clk = pci_sync_in * spmf * (1 + clkin_div); +#if defined(CONFIG_83XX_PCICLK) + pci_sync_in = CONFIG_83XX_PCICLK; +#else + pci_sync_in = 0xDEADBEEF; +#endif } - + + spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + csb_clk = pci_sync_in * (1 + clkin_div) * spmf; + sccr = im->clk.sccr; + +#if defined(CONFIG_MPC8349) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -212,26 +190,9 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) /* unkown SCCR_TSEC2CM value */ return -5; } - i2c_clk = tsec2_clk; - - switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { - case 0: - enc_clk = 0; - break; - case 1: - enc_clk = csb_clk; - break; - case 2: - enc_clk = csb_clk / 2; - break; - case 3: - enc_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_ENCCM value */ - return -6; - }

+ i2c1_clk = tsec2_clk; + switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -274,8 +235,34 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ return -9; } +#endif +#if defined (CONFIG_MPC8360) + i2c1_clk = csb_clk; +#endif + i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */

+ switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: + enc_clk = 0; + break; + case 1: + enc_clk = csb_clk; + break; + case 2: + enc_clk = csb_clk / 2; + break; + case 3: + enc_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_ENCCM value */ + return -6; + } +#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); +#else +#error Unknown MPC83xx chip +#endif lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: @@ -287,10 +274,16 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) /* unknown lcrr */ return -10; } - +#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; +#if defined (CONFIG_MPC8360) + ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); +#endif +#else +#error Unknown MPC83xx chip +#endif + corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60)

...

5);

if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { /* corecnf_tab_index is too high, possibly worng value */ @@ -318,25 +311,45 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) /* unkown core to csb ratio */ return -12; } + +#if defined (CONFIG_MPC8360) + qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; + qe_clk = (pci_sync_in * qepmf)/(1+qepdf); + brg_clk = 0; +#endif + + gd->csb_clk = csb_clk; +#if defined(CONFIG_MPC8349) + gd->tsec1_clk = tsec1_clk; + gd->tsec2_clk = tsec2_clk; + gd->usbmph_clk = usbmph_clk; + gd->usbdr_clk = usbdr_clk; +#endif + gd->core_clk = core_clk; + gd->i2c1_clk = i2c1_clk; + gd->i2c2_clk = i2c2_clk; + gd->enc_clk = enc_clk; + gd->lbiu_clk = lbiu_clk; + gd->lclk_clk = lclk_clk; + gd->ddr_clk = ddr_clk; +#if defined (CONFIG_MPC8360) + gd->ddr_sec_clk = ddr_sec_clk; + gd->qe_clk = qe_clk; + gd->brg_clk = brg_clk; +#endif + gd->cpu_clk = gd->core_clk; + gd->bus_clk = gd->csb_clk; + return 0;

- gd->csb_clk = csb_clk ; - gd->tsec1_clk = tsec1_clk ; - gd->tsec2_clk = tsec2_clk ; - gd->core_clk = core_clk ; - gd->usbmph_clk = usbmph_clk; - gd->usbdr_clk = usbdr_clk ; - gd->i2c_clk = i2c_clk ; - gd->enc_clk = enc_clk ; - gd->lbiu_clk = lbiu_clk ; - gd->lclk_clk = lclk_clk ; - gd->ddr_clk = ddr_clk ; - gd->pci_clk = pci_sync_in; +}

- gd->cpu_clk = gd->core_clk; - gd->bus_clk = gd->lbiu_clk; - return 0; +ulong get_ddr_clk(ulong dummy) +{ + return gd->ddr_clk; }

+ /******************************************** * get_bus_freq * return system bus freq in Hz @@ -351,14 +364,23 @@ int print_clock_conf (void) printf("Clock configuration:\n"); printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); printf(" Core: %4d MHz\n",gd->core_clk/1000000); - debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); +#if defined (CONFIG_MPC8360) + printf(" QE: %4d MHz\n",gd->qe_clk/1000000); +#endif + printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); - debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000); - debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000); - debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); - debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); - debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); - debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); - + printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000); +#if defined (CONFIG_MPC8360) + printf(" DDR Secondary: %4d MHz\n",gd->ddr_sec_clk/1000000); +#endif + printf(" SEC: %4d MHz\n",gd->enc_clk/1000000); + printf(" I2C1: %4d MHz\n",gd->i2c1_clk/1000000); + printf(" I2C2: %4d MHz\n",gd->i2c2_clk/1000000); +#if defined(CONFIG_MPC8349) + printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); + printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); + printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); + printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); +#endif return 0; } diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 6e02cce..8ecab88 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -174,9 +174,9 @@ #ifndef CFG_RAMBOOT mtlr r5 blr in_flash: -#if 1 /* Remapping flash with LAW0. */ + /* Change BR0 to CFG_FLASH_BASE, and remapping ROM flash with LAW0 */ bl remap_flash_by_law0 -#endif + /* Change ROM flash base address and LAW0 is done! */ #endif /* CFG_RAMBOOT */

/* setup the bats */ @@ -870,6 +870,25 @@ ppcDcbz: dcbz r0,r3 blr

+ .globl ppcDWstore +ppcDWstore: + lfd 1, 0(r4) + stfd 1, 0(r3) + sync + blr + + .globl ppcDWload +ppcDWload: + lfd 1, 0(r3) + stfd 1, 0(r4) + sync + blr + + .globl ppcDcbst +ppcDcbst: + dcbst r0, r3 + blr + /*-------------------------------------------------------------------*/

/* @@ -1214,9 +1233,9 @@ map_flash_by_law1: lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ - lis r4, (0x80000016)@h - ori r4, r4, (0x80000016)@l - stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ + lis r4, (0x80000018)@h + ori r4, r4, (0x80000018)@l + stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 32MB Flash Size */ blr

/* Though all the LBIU Local Access Windows and LBC Banks will be @@ -1234,17 +1253,17 @@ remap_flash_by_law0: stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */

lwz r4, OR0(r3) - lis r5, 0xFF80 /* 8M */ + lis r5, 0xFE00 /* 32M */ or r4, r4, r5 - stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ + stw r4, OR0(r3) /* OR0 <= OR0 | 0xFE000000 */

lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */

- lis r4, (0x80000016)@h - ori r4, r4, (0x80000016)@l - stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ + lis r4, (0x80000018)@h + ori r4, r4, (0x80000018)@l + stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 32MB Flash Size */

xor r4, r4, r4 stw r4, LBLAWBAR1(r3)