[PATCH v2 0/8] clk: mediatek: mt7622: clk migration for OF_UPSTREAM
These are all the required patches to migrate clk and correctly support OF_UPSTREAM. This will align the clk index to upstream to support the same clk implementation with downstream and upstream DTS.
Changes v2: - Fix typo in commit description
Christian Marangi (8): clk: mediatek: mt7622: fix broken peri_cgs clk with XTAL parents clk: mediatek: mt7622: rename AUDIO_AWB3 to AUDIO_AWB2 clk: mediatek: mt7622: move INFRA_TRNG to the bottom clk: mediatek: mt7622: add missing clock define for MAIN_CORE_EN clk: mediatek: mt7622: add missing clock MUX1_SEL clk: mediatek: mt7622: add missing clock PERI_UART4_PD clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock clk: mediatek: mt7622: add missing A1/2SYS clock ID
drivers/clk/mediatek/clk-mt7622.c | 104 +++++++++++++++++++++---- include/dt-bindings/clock/mt7622-clk.h | 68 ++++++++-------- 2 files changed, 124 insertions(+), 48 deletions(-)
Fix broken peri_cgs clock with XTAL parents as they have wrong definition of the parent type.
Correctly fix them and use CLK_PARENT_XTAL for them.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2beb63030f2..4a7c5faff1a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -402,13 +402,17 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, };
-#define GATE_PERI0(_id, _parent, _shift) { \ +#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &peri0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_PERI0(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_PERI0_XTAL(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
#define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -421,14 +425,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -441,7 +445,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
Rename AUDIO_AWB3 to AUDIO_AWB2 to match upstream linux naming in preparation for OF_UPSTREAM support.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- include/dt-bindings/clock/mt7622-clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 76fcaff0e42..78804f40307 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -206,7 +206,7 @@ #define CLK_AUDIO_DLMCH 31 #define CLK_AUDIO_ARB1 32 #define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_AWB2 34 #define CLK_AUDIO_DAI 35 #define CLK_AUDIO_MOD 36 #define CLK_AUDIO_ASRCI3 37
Move INFRA_TRNG clock to the bottom of the clk ID to match upstream linux order. This is in preparation of OF_UPSTREAM.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 2 +- include/dt-bindings/clock/mt7622-clk.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 4a7c5faff1a..8f173b79453 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -382,11 +382,11 @@ static const struct mtk_gate_regs infra_cg_regs = {
static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), - GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), };
/* pericfg */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 78804f40307..2f36abcf8ae 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -121,11 +121,11 @@ /* INFRACFG */
#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_TRNG 1 -#define CLK_INFRA_AUDIO_PD 2 -#define CLK_INFRA_IRRX_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_AUDIO_PD 1 +#define CLK_INFRA_IRRX_PD 2 +#define CLK_INFRA_APXGPT_PD 3 +#define CLK_INFRA_PMIC_PD 4 +#define CLK_INFRA_TRNG 5
/* PERICFG */
Add missing clock for MAIN_CORE_EN. This is a special clock as it's a gate for the APMIXED clocks required as a parent for CPU clocks.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 29 +++++++++++++++++++++++--- include/dt-bindings/clock/mt7622-clk.h | 1 + 2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 8f173b79453..49adffb3b43 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -66,6 +66,24 @@ static const struct mtk_pll_data apmixed_plls[] = { 21, 0x358, 1, 0x35c, 0), };
+static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x8, + .sta_ofs = 0x8, +}; + +#define GATE_APMIXED(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &apmixed_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV, \ + } + +static const struct mtk_gate apmixed_cgs[] = { + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, CLK_APMIXED_MAINPLL, 5), +}; + /* topckgen */ #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -554,12 +572,17 @@ static const struct mtk_gate ssusb_cgs[] = { GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), };
+static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { + .xtal2_rate = 25 * MHZ, + .plls = apmixed_plls, + .gates_offs = CLK_APMIXED_MAIN_CORE_EN, + .gates = apmixed_cgs, +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, - .xtal2_rate = 25 * MHZ, .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, - .plls = apmixed_plls, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, @@ -586,7 +609,7 @@ static int mt7622_apmixedsys_probe(struct udevice *dev) struct mtk_clk_priv *priv = dev_get_priv(dev); int ret;
- ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree); if (ret) return ret;
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 2f36abcf8ae..569bfce0d05 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -169,6 +169,7 @@ #define CLK_APMIXED_AUD2PLL 6 #define CLK_APMIXED_TRGPLL 7 #define CLK_APMIXED_SGMIPLL 8 +#define CLK_APMIXED_MAIN_CORE_EN 9
/* AUDIOSYS */
Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to match the upstream clk ID order in preparation for OF_UPSTREAM.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 24 +++++++++++++++++++++++- include/dt-bindings/clock/mt7622-clk.h | 13 +++++++------ 2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 49adffb3b43..0da7a848163 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -384,6 +384,20 @@ static const struct mtk_composite top_muxes[] = { };
/* infracfg */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) + +static const struct mtk_parent infra_mux1_parents[] = { + XTAL_PARENT(CLK_XTAL), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), + APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), +}; + +static const struct mtk_composite infra_muxes[] = { + MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), +}; + static const struct mtk_gate_regs infra_cg_regs = { .set_ofs = 0x40, .clr_ofs = 0x44, @@ -579,6 +593,14 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { .gates = apmixed_cgs, };
+static const struct mtk_clk_tree mt7622_infra_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_INFRA_MUX1_SEL, + .gates_offs = CLK_INFRA_DBGCLK_PD, + .muxes = infra_muxes, + .gates = infra_cgs, +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, .fdivs_offs = CLK_TOP_TO_USB3_SYS, @@ -630,7 +652,7 @@ static int mt7622_topckgen_probe(struct udevice *dev)
static int mt7622_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree); }
static int mt7622_pericfg_probe(struct udevice *dev) diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 569bfce0d05..0820fab0a22 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -120,12 +120,13 @@
/* INFRACFG */
-#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_AUDIO_PD 1 -#define CLK_INFRA_IRRX_PD 2 -#define CLK_INFRA_APXGPT_PD 3 -#define CLK_INFRA_PMIC_PD 4 -#define CLK_INFRA_TRNG 5 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_AUDIO_PD 2 +#define CLK_INFRA_IRRX_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6
/* PERICFG */
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to match upstream linux clk ID in preparation for OF_UPSTREAM. Also convert infracfg to mux + gate implementation as now we have mux on top of gates.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 1 + include/dt-bindings/clock/mt7622-clk.h | 25 +++++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0da7a848163..5df62e64c9a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -472,6 +472,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21), GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 0820fab0a22..4b6501c1020 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -146,18 +146,19 @@ #define CLK_PERI_UART1_PD 13 #define CLK_PERI_UART2_PD 14 #define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERI_UART4_PD 16 +#define CLK_PERI_BTIF_PD 17 +#define CLK_PERI_I2C0_PD 18 +#define CLK_PERI_I2C1_PD 19 +#define CLK_PERI_I2C2_PD 20 +#define CLK_PERI_SPI1_PD 21 +#define CLK_PERI_AUXADC_PD 22 +#define CLK_PERI_SPI0_PD 23 +#define CLK_PERI_SNFI_PD 24 +#define CLK_PERI_NFI_PD 25 +#define CLK_PERI_NFIECC_PD 26 +#define CLK_PERI_FLASH_PD 27 +#define CLK_PERI_IRTX_PD 28
/* APMIXEDSYS */
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also convert pericfg to mux + gate implementation as now we have also mux on top of gates.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mt7622.c | 22 +++++++++- include/dt-bindings/clock/mt7622-clk.h | 59 +++++++++++++------------- 2 files changed, 51 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 5df62e64c9a..23b9787612a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -422,6 +422,18 @@ static const struct mtk_gate infra_cgs[] = { };
/* pericfg */ +static const int peribus_ck_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL1_D4, +}; + +#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ + MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) + +static const struct mtk_composite peri_muxes[] = { + PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, @@ -602,6 +614,14 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = { .gates = infra_cgs, };
+static const struct mtk_clk_tree mt7622_peri_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_PERIBUS_SEL, + .gates_offs = CLK_PERI_THERM_PD, + .muxes = peri_muxes, + .gates = peri_cgs, +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, .fdivs_offs = CLK_TOP_TO_USB3_SYS, @@ -658,7 +678,7 @@ static int mt7622_infracfg_probe(struct udevice *dev)
static int mt7622_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree); }
static int mt7622_pciesys_probe(struct udevice *dev) diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 4b6501c1020..cd11a1c901e 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -130,35 +130,36 @@
/* PERICFG */
-#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_UART4_PD 16 -#define CLK_PERI_BTIF_PD 17 -#define CLK_PERI_I2C0_PD 18 -#define CLK_PERI_I2C1_PD 19 -#define CLK_PERI_I2C2_PD 20 -#define CLK_PERI_SPI1_PD 21 -#define CLK_PERI_AUXADC_PD 22 -#define CLK_PERI_SPI0_PD 23 -#define CLK_PERI_SNFI_PD 24 -#define CLK_PERI_NFI_PD 25 -#define CLK_PERI_NFIECC_PD 26 -#define CLK_PERI_FLASH_PD 27 -#define CLK_PERI_IRTX_PD 28 +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_THERM_PD 1 +#define CLK_PERI_PWM1_PD 2 +#define CLK_PERI_PWM2_PD 3 +#define CLK_PERI_PWM3_PD 4 +#define CLK_PERI_PWM4_PD 5 +#define CLK_PERI_PWM5_PD 6 +#define CLK_PERI_PWM6_PD 7 +#define CLK_PERI_PWM7_PD 8 +#define CLK_PERI_PWM_PD 9 +#define CLK_PERI_AP_DMA_PD 10 +#define CLK_PERI_MSDC30_0_PD 11 +#define CLK_PERI_MSDC30_1_PD 12 +#define CLK_PERI_UART0_PD 13 +#define CLK_PERI_UART1_PD 14 +#define CLK_PERI_UART2_PD 15 +#define CLK_PERI_UART3_PD 16 +#define CLK_PERI_UART4_PD 17 +#define CLK_PERI_BTIF_PD 18 +#define CLK_PERI_I2C0_PD 19 +#define CLK_PERI_I2C1_PD 20 +#define CLK_PERI_I2C2_PD 21 +#define CLK_PERI_SPI1_PD 22 +#define CLK_PERI_AUXADC_PD 23 +#define CLK_PERI_SPI0_PD 24 +#define CLK_PERI_SNFI_PD 25 +#define CLK_PERI_NFI_PD 26 +#define CLK_PERI_NFIECC_PD 27 +#define CLK_PERI_FLASH_PD 28 +#define CLK_PERI_IRTX_PD 29
/* APMIXEDSYS */
Add missing A1/2SYS clock ID just as a reference for OF_UPSTREAM support. These clocks are not defined and are not usable as current clock topckgen OPs doesn't support gates.
These special node won't ever be used by uboot hence just add them for reference.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- include/dt-bindings/clock/mt7622-clk.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index cd11a1c901e..cdbcaef76eb 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -117,6 +117,8 @@ #define CLK_TOP_I2S1_MCK_DIV_PD 104 #define CLK_TOP_I2S2_MCK_DIV_PD 105 #define CLK_TOP_I2S3_MCK_DIV_PD 106 +#define CLK_TOP_A1SYS_HP_DIV_PD 107 +#define CLK_TOP_A2SYS_HP_DIV_PD 108
/* INFRACFG */
On Sat, 03 Aug 2024 10:43:18 +0200, Christian Marangi wrote:
These are all the required patches to migrate clk and correctly support OF_UPSTREAM. This will align the clk index to upstream to support the same clk implementation with downstream and upstream DTS.
Changes v2:
- Fix typo in commit description
[...]
Applied to u-boot/next, thanks!
participants (2)
-
Christian Marangi -
Tom Rini