[U-Boot] [PATCH 1/8] armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 1001 is observed, change set the same value.
Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index d8b285d..eebfcfe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -22,6 +22,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -42,6 +43,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -77,6 +79,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010539 bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008 + bool "Workaround for USB PHY erratum A009008" + + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0943e83..a91f85e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -52,6 +52,29 @@ bool soc_has_aiop(void) return false; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6)); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6)); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6)); +#elif defined(CONFIG_ARCH_LS2080A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); + val &= ~(0xF << 6); + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +221,7 @@ void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336(); + erratum_a009008(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009008(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..62d7046 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -337,6 +337,12 @@ struct ccsr_gur { #define SCFG_USBPWRFAULT_USB2_SHIFT 2 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM1CR_USB3 0x088 +#define USB_TXVREFTUNE 0x9 + #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59410aa..c622ee5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -133,6 +133,7 @@ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a +#define USB_TXVREFTUNE 0x9 #define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV woards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 28 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index eebfcfe..63f4eec 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -23,6 +23,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -44,6 +45,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -80,6 +82,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -226,6 +229,8 @@ config SYS_FSL_ERRATUM_A010539 config SYS_FSL_ERRATUM_A009008 bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798 + bool "Workaround for USB PHY erratum A009798"
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a91f85e..ad9127a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -75,6 +75,25 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); + val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); +#elif defined(CONFIG_ARCH_LS2080A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -222,6 +241,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008514(); erratum_a008336(); erratum_a009008(); + erratum_a009798(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -498,6 +518,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009660(); erratum_a010539(); erratum_a009008(); + erratum_a009798(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 62d7046..8bd40e8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -342,6 +342,7 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR_USB2 0x07C #define SCFG_USB3PRM1CR_USB3 0x088 #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index c622ee5..2d309d5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -134,6 +134,7 @@ #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
On 07/09/2017 07:41 PM, Ran Wang wrote:
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV woards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 28 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index eebfcfe..63f4eec 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -23,6 +23,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R
@@ -44,6 +45,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R
@@ -80,6 +82,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009798 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -226,6 +229,8 @@ config SYS_FSL_ERRATUM_A010539 config SYS_FSL_ERRATUM_A009008 bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a91f85e..ad9127a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -75,6 +75,25 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
Put a blank line here.
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
- val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_ARCH_LS2080A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
Same here. Move it up together if you can.
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
Put a blank line here.
York
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change setting required for transmitter signal swings to pass compliance tests.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++ 3 files changed, 33 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 63f4eec..867794d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -24,6 +24,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -46,6 +47,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -83,6 +85,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009203 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -232,6 +235,9 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997 + bool "Workaround for USB PHY erratum A008997" + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ad9127a..7ebb8d4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -94,6 +94,27 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ }
+static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 +#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4, + val | (USB_PCSTXSWINGFULL << 9)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -242,6 +263,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008336(); erratum_a009008(); erratum_a009798(); + erratum_a008997(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -519,6 +541,7 @@ void fsl_lsch2_early_init_f(void) erratum_a010539(); erratum_a009008(); erratum_a009798(); + erratum_a008997(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8bd40e8..2e52078 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -339,10 +339,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000 #define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM2CR_USB1 0x074 #define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM2CR_USB2 0x080 #define SCFG_USB3PRM1CR_USB3 0x088 +#define SCFG_USB3PRM2CR_USB3 0x08c #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Changes identified in setup makes the Rx compliance test pass.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 55 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++++ 4 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 867794d..3f63694 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -25,6 +25,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -48,6 +49,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -86,6 +88,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -236,7 +239,14 @@ config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A008997 - bool "Workaround for USB PHY erratum A008997" + bool + help + Workaround for USB PHY erratum A008997 + +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ebb8d4..5810f42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -115,6 +115,59 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + void __iomem *usb_phy = (void __iomem *)USB_PHY1; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + + usb_phy = (void __iomem *)USB_PHY2; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + + usb_phy = (void __iomem *)USB_PHY3; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); +#elif defined(CONFIG_ARCH_LS2080A) + void __iomem *dcsr = (void __iomem *)DCSR_BASE; + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -264,6 +317,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -542,6 +596,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 2e52078..69fd79c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -347,6 +347,14 @@ struct ccsr_gur { #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF #define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY1 0x084F0000 +#define USB_PHY2 0x08500000 +#define USB_PHY3 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 2d309d5..238d647 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -137,6 +137,15 @@ #define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10
+#define DCSR_BASE 0x700000000ULL +#define DCSR_USB_PHY1 0x4600000 +#define DCSR_USB_PHY2 0x4610000 +#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 + #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ #define TP_ITYP_TYPE_ARM 0x0
On 07/09/2017 07:41 PM, Ran Wang wrote:
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Changes identified in setup makes the Rx compliance test pass.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 55 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++++ 4 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 867794d..3f63694 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -25,6 +25,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R
@@ -48,6 +49,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R
@@ -86,6 +88,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -236,7 +239,14 @@ config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A008997
- bool "Workaround for USB PHY erratum A008997"
- bool
- help
Workaround for USB PHY erratum A008997+config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ebb8d4..5810f42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -115,6 +115,59 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
- void __iomem *usb_phy = (void __iomem *)USB_PHY1;
Put a blank line here.
- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_1);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_2);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_3);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_4);- usb_phy = (void __iomem *)USB_PHY2;
- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_1);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_2);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_3);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_4);- usb_phy = (void __iomem *)USB_PHY3;
- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_1);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_2);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_3);- out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_4);+#elif defined(CONFIG_ARCH_LS2080A)
- void __iomem *dcsr = (void __iomem *)DCSR_BASE;
- out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_1);- out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_2);- out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_3);- out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_4);- out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_1);- out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_2);- out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_3);- out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI,
USB_PHY_RX_EQ_VAL_4);+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
Something for you to consider. Use loop instead of repeating codes. Reuse code instead of repeat them under different macros.
The benefit of using loop is not much in this change. So you may consider to create a macro to run for each USB. At least it makes the code easier to read and maintain.
York
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is ovserved, change set the same value.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b61f3cd..11e33d6 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -50,6 +51,11 @@ config SECURE_BOOT config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008 + bool + help + Workaround for USB erratum A009008 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b84a1a6..986337d 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,17 @@ unsigned int get_soc_major_rev(void) return major; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + val &= ~(0xF << 6); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + + void s_init(void) { } @@ -146,6 +157,9 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */ + erratum_a009008(); + return 0; }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c34fd63..6ea8c4b 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -173,6 +173,10 @@ struct ccsr_gur { #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR 0x070 +#define USB_TXVREFTUNE 0x9 + /* Supplemental Configuration Unit */ struct ccsr_scfg { u32 dpslpcr;
On 07/09/2017 07:41 PM, Ran Wang wrote:
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is ovserved, change set the same value.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b61f3cd..11e33d6 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,11 @@ config SECURE_BOOT config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
- bool
- help
Workaround for USB erratum A009008- config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b84a1a6..986337d 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,17 @@ unsigned int get_soc_major_rev(void) return major; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
Put a blank here.
York
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++- arch/arm/cpu/armv7/ls102xa/soc.c | 9 +++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 11e33d6..c605fc0 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -6,6 +6,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -54,7 +55,12 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A009008 bool help - Workaround for USB erratum A009008 + Workaround for USB PHY erratum A009008 + +config SYS_FSL_ERRATUM_A009798 + bool + help + Workaround for USB PHY erratum A009798
config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 986337d..ef44a6c 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -70,6 +70,14 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +}
void s_init(void) { @@ -159,6 +167,7 @@ int arch_soc_init(void)
/* Erratum */ erratum_a009008(); + erratum_a009798();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 6ea8c4b..8cafa07 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -176,6 +176,7 @@ struct ccsr_gur { #define SCFG_BASE 0x01570000 #define SCFG_USB3PRM1CR 0x070 #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF
/* Supplemental Configuration Unit */ struct ccsr_scfg {
On 07/09/2017 07:41 PM, Ran Wang wrote:
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++- arch/arm/cpu/armv7/ls102xa/soc.c | 9 +++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 11e33d6..c605fc0 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -6,6 +6,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009798 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,7 +55,12 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A009008 bool help
Workaround for USB erratum A009008
Workaround for USB PHY erratum A009008+config SYS_FSL_ERRATUM_A009798
bool
help
Workaround for USB PHY erratum A009798config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 986337d..ef44a6c 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -70,6 +70,14 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
Put a blank line here.
York
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass compliance tests.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 13 +++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 3 files changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index c605fc0..4f2e86e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -62,6 +63,11 @@ config SYS_FSL_ERRATUM_A009798 help Workaround for USB PHY erratum A009798
+config SYS_FSL_ERRATUM_A008997 + bool + help + Workaround for USB PHY erratum A008997 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index ef44a6c..15b2299 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -79,6 +79,18 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ }
+static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM2CR / 4); + val &= ~USB_PCSTXSWINGFULL_MASK; + val |= USB_PCSTXSWINGFULL_VAL; + out_be32(scfg + SCFG_USB3PRM2CR / 4, val); +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + + void s_init(void) { } @@ -168,6 +180,7 @@ int arch_soc_init(void) /* Erratum */ erratum_a009008(); erratum_a009798(); + erratum_a008997();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 8cafa07..539c1cf 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -177,6 +177,9 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR 0x070 #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define SCFG_USB3PRM2CR 0x074 +#define USB_PCSTXSWINGFULL_MASK 0x0000FE00 +#define USB_PCSTXSWINGFULL_VAL 0x00008E00
/* Supplemental Configuration Unit */ struct ccsr_scfg {
On 07/09/2017 07:41 PM, Ran Wang wrote:
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass compliance tests.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 13 +++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 3 files changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index c605fc0..4f2e86e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798
- select SYS_FSL_ERRATUM_A008997 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -62,6 +63,11 @@ config SYS_FSL_ERRATUM_A009798 help Workaround for USB PHY erratum A009798
+config SYS_FSL_ERRATUM_A008997
- bool
- help
Workaround for USB PHY erratum A008997- config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index ef44a6c..15b2299 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -79,6 +79,18 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ }
+static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = in_be32(scfg + SCFG_USB3PRM2CR / 4);
Put a blank line here.
York
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 11 +++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 7 +++++++ 3 files changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 4f2e86e..236addb 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -8,6 +8,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -68,6 +69,11 @@ config SYS_FSL_ERRATUM_A008997 help Workaround for USB PHY erratum A008997
+config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 + config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 15b2299..88219ec 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -90,6 +90,16 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009007 + void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +}
void s_init(void) { @@ -181,6 +191,7 @@ int arch_soc_init(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 539c1cf..703e59f 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -181,6 +181,13 @@ struct ccsr_gur { #define USB_PCSTXSWINGFULL_MASK 0x0000FE00 #define USB_PCSTXSWINGFULL_VAL 0x00008E00
+#define USB_PHY_BASE 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8004 +#define USB_PHY_RX_EQ_VAL_4 0x800C + /* Supplemental Configuration Unit */ struct ccsr_scfg { u32 dpslpcr;
On 07/09/2017 07:41 PM, Ran Wang wrote:
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.bhagat@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 11 +++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 7 +++++++ 3 files changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 4f2e86e..236addb 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -8,6 +8,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -68,6 +69,11 @@ config SYS_FSL_ERRATUM_A008997 help Workaround for USB PHY erratum A008997
+config SYS_FSL_ERRATUM_A009007
- bool
- help
Workaround for USB PHY erratum A009007- config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 15b2299..88219ec 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -90,6 +90,16 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
- void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
Put a blank line here.
York
Hello Sir, May I know the review result for this patch set? Thank you. BR Ran
-----Original Message----- From: Ran Wang [mailto:ran.wang_1@nxp.com] Sent: Monday, July 10, 2017 10:24 AM To: Albert Aribaud albert.u.boot@aribaud.net; York Sun york.sun@nxp.com; Suresh Gupta suresh.bhagat@nxp.com Cc: Simon Glass sjg@chromium.org; Sriram Dash sriram.dash@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Andy Tang andy.tang@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; open list u-boot@lists.denx.de; Ran Wang ran.wang_1@nxp.com Subject: [PATCH 1/8] armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 1001 is observed, change set the same value.
Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index d8b285d..eebfcfe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -22,6 +22,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R
@@ -42,6 +43,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R
@@ -77,6 +79,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203
- select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010539 bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008
- bool "Workaround for USB PHY erratum A009008"
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0943e83..a91f85e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -52,6 +52,29 @@ bool soc_has_aiop(void) return false; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4,
val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4,
val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4,
val|(USB_TXVREFTUNE << +6)); #elif defined(CONFIG_ARCH_LS2080A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE <<
6)); +#endif #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
#if defined(CONFIG_FSL_LSCH3) /*
- This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +221,7 @@
void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336();
- erratum_a009008();
#ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU
- to allow only Secure transactions.
@@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539();
- erratum_a009008();
} #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..62d7046 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -337,6 +337,12 @@ struct ccsr_gur { #define SCFG_USBPWRFAULT_USB2_SHIFT 2 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM1CR_USB3 0x088 +#define USB_TXVREFTUNE 0x9
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59410aa..c622ee5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -133,6 +133,7 @@ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a +#define USB_TXVREFTUNE 0x9 #define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
2.1.0.27.g96db324
On 08/02/2017 02:55 AM, Ran Wang wrote:
Hello Sir, May I know the review result for this patch set? Thank you. BR Ran
Ran,
I have seen three versions from Suresh, one version from Yinbo, and one version from you. Neither you or Yinbo updated the version number, or included change log. You have Suresh's signature on 7 of the 8 patches. So I am guessing you are resending the patches based on my comment to Yingbo's patch set. Without any information, I am treating them as new patches and will review them in the order I receive them.
York
Hi York,
-----Original Message----- From: York Sun Sent: Wednesday, August 02, 2017 11:13 PM To: Ran Wang ran.wang_1@nxp.com; Albert Aribaud albert.u.boot@aribaud.net Cc: Simon Glass sjg@chromium.org; Sriram Dash sriram.dash@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Andy Tang andy.tang@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; open list u-boot@lists.denx.de; Xiaobo Xie xiaobo.xie@nxp.com; Suresh Gupta suresh.bhagat@nxp.com Subject: Re: [PATCH 1/8] armv8: Add workaround for USB erratum A-009008
On 08/02/2017 02:55 AM, Ran Wang wrote:
Hello Sir, May I know the review result for this patch set? Thank you. BR Ran
Ran,
I have seen three versions from Suresh, one version from Yinbo, and one version from you. Neither you or Yinbo updated the version number, or included change log. You have Suresh's signature on 7 of the 8 patches.
Yes, actually the patch set what I submitted is basing on Suresh's last one but adding some new defect fix after I re-checked the old patch and chip data sheet and also following your for requirement of using out_le16().
So I am guessing you are resending the patches based on my comment to Yingbo's patch set. Without any information, I am treating them as new patches and will review them in the order I receive them.
Well, I am not sure the submit rule on case of changing submitter and some function in middle way. So I decide to submit it as v1. You can treat it as a new one and review in order (I just don't know the roughly period it will take, so sent out last mail :) ), any question or suggestion please feel free to let me know. Thanks for your time.
BR Ran
Only cosmetic issues found in this set. Please check more comments on patch 4.
On 07/09/2017 07:41 PM, Ran Wang wrote:
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 1001 is observed, change set the same value.
Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index d8b285d..eebfcfe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -22,6 +22,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R
@@ -42,6 +43,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R
@@ -77,6 +79,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203
- select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010539 bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008
- bool "Workaround for USB PHY erratum A009008"
- config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0943e83..a91f85e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -52,6 +52,29 @@ bool soc_has_aiop(void) return false; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
Put a blank line after variable declaration.
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
- val &= ~(0xF << 6);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_ARCH_LS2080A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
Move the common code together. Same comment goes to other patches in this set.
York
participants (2)
-
Ran Wang -
York Sun