[U-Boot] [PATCH v2 0/6] Extend stm32 SDRAM driver
From: Patrice Chotard patrice.chotard@st.com
This series aims to add some improvements to existing ram driver decicated to stm32 SoCs : _ some code clean up _ full DT support, now the FMC base is retrieved through DT _ update DT API by using ofnode_read...() or dev_read..() instead of fdtdec_get..() to support livetree _ add second SDRAM bank support needed for STM32H7-Discovery board which uses the second SDRAM bank _ add stm32 H7 support
v2: _ use dev_read_addr() instead of devfdt_get_addr() in patch 2 _ rework comment in patch 6 _ replace generic_clear_bit/set_bit() by clrbits_le32/setbits_le32() in patch 6
Patrice Chotard (6): ram: stm32: migrate fmc defines in driver file ram: stm32: get base address from DT ram: stm32: replace fdtdec_get by ofnode calls ram: stm32: add second SDRAM bank management ARM: DTS: stm32: remove useless mr-nbanks property ram: stm32: add stm32h7 support
arch/arm/dts/stm32f746-disco.dts | 1 - arch/arm/dts/stm32f769-disco.dts | 1 - arch/arm/include/asm/arch-stm32f7/fmc.h | 74 ------ board/st/stm32f746-disco/stm32f746-disco.c | 1 - doc/device-tree-bindings/ram/st,stm32-fmc.txt | 19 +- drivers/ram/stm32_sdram.c | 338 ++++++++++++++++++++------ 6 files changed, 280 insertions(+), 154 deletions(-) delete mode 100644 arch/arm/include/asm/arch-stm32f7/fmc.h
From: Patrice Chotard patrice.chotard@st.com
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Vikas Manocha vikas.manocha@st.com Reviewed-by: Simon Glass sjg@chromium.org ---
v2: _ add Reviewed-by: Simon Glass
arch/arm/include/asm/arch-stm32f7/fmc.h | 74 ------------------------------ board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/ram/stm32_sdram.c | 59 +++++++++++++++++++++++- 3 files changed, 58 insertions(+), 76 deletions(-) delete mode 100644 arch/arm/include/asm/arch-stm32f7/fmc.h
diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h deleted file mode 100644 index 4741e5a..0000000 --- a/arch/arm/include/asm/arch-stm32f7/fmc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2013 - * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, kamil.lulko@gmail.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_FMC_H_ -#define _MACH_FMC_H_ - -struct stm32_fmc_regs { - u32 sdcr1; /* Control register 1 */ - u32 sdcr2; /* Control register 2 */ - u32 sdtr1; /* Timing register 1 */ - u32 sdtr2; /* Timing register 2 */ - u32 sdcmr; /* Mode register */ - u32 sdrtr; /* Refresh timing register */ - u32 sdsr; /* Status register */ -}; - -/* - * FMC registers base - */ -#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE) - -/* Control register SDCR */ -#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ -#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ -#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ -#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ -#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ -#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ -#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ -#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ -#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ - -/* Timings register SDTR */ -#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ -#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ -#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ -#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ -#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ -#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ -#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ - - -#define FMC_SDCMR_NRFS_SHIFT 5 - -#define FMC_SDCMR_MODE_NORMAL 0 -#define FMC_SDCMR_MODE_START_CLOCK 1 -#define FMC_SDCMR_MODE_PRECHARGE 2 -#define FMC_SDCMR_MODE_AUTOREFRESH 3 -#define FMC_SDCMR_MODE_WRITE_MODE 4 -#define FMC_SDCMR_MODE_SELFREFRESH 5 -#define FMC_SDCMR_MODE_POWERDOWN 6 - -#define FMC_SDCMR_BANK_1 BIT(4) -#define FMC_SDCMR_BANK_2 BIT(3) - -#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 - -#define FMC_SDSR_BUSY BIT(5) - -#define FMC_BUSY_WAIT() do { \ - __asm__ __volatile__ ("dsb" : : : "memory"); \ - while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ - ; \ - } while (0) - - -#endif /* _MACH_FMC_H_ */ diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index fc4c60c..4314c71 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -13,7 +13,6 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/fmc.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 902de2b..4146b9d 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -10,11 +10,68 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/fmc.h> #include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
+struct stm32_fmc_regs { + u32 sdcr1; /* Control register 1 */ + u32 sdcr2; /* Control register 2 */ + u32 sdtr1; /* Timing register 1 */ + u32 sdtr2; /* Timing register 2 */ + u32 sdcmr; /* Mode register */ + u32 sdrtr; /* Refresh timing register */ + u32 sdsr; /* Status register */ +}; + +/* + * FMC registers base + */ +#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY BIT(5) + +#define FMC_BUSY_WAIT() do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + struct stm32_sdram_control { u8 no_columns; u8 no_rows;
On Tue, Jul 18, 2017 at 05:37:24PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Vikas Manocha vikas.manocha@st.com Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
From: Patrice Chotard patrice.chotard@st.com
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM registers are located at offset 0x140 inside FMC block. Update the stm32_fmc_regs fields with all FMC registers to map SDRAM registers at the right address.
These additionals registers will be used later.
Signed-off-by: Patrice Chotard patrice.chotard@st.com ---
v2: _ use dev_read_addr() instead of devfdt_get_addr()
drivers/ram/stm32_sdram.c | 92 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 28 deletions(-)
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 4146b9d..9b2cec4 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -10,25 +10,50 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
struct stm32_fmc_regs { - u32 sdcr1; /* Control register 1 */ - u32 sdcr2; /* Control register 2 */ - u32 sdtr1; /* Timing register 1 */ - u32 sdtr2; /* Timing register 2 */ - u32 sdcmr; /* Mode register */ - u32 sdrtr; /* Refresh timing register */ - u32 sdsr; /* Status register */ + /* 0x0 */ + u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ + u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ + u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ + u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ + u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ + u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ + u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ + u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ + u32 reserved1[24]; + + /* 0x80 */ + u32 pcr; /* NAND Flash control register */ + u32 sr; /* FIFO status and interrupt register */ + u32 pmem; /* Common memory space timing register */ + u32 patt; /* Attribute memory space timing registers */ + u32 reserved2[1]; + u32 eccr; /* ECC result registers */ + u32 reserved3[27]; + + /* 0x104 */ + u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ + u32 reserved4[1]; + u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ + u32 reserved5[1]; + u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ + u32 reserved6[1]; + u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ + u32 reserved7[8]; + + /* 0x140 */ + u32 sdcr1; /* SDRAM Control register 1 */ + u32 sdcr2; /* SDRAM Control register 2 */ + u32 sdtr1; /* SDRAM Timing register 1 */ + u32 sdtr2; /* SDRAM Timing register 2 */ + u32 sdcmr; /* SDRAM Mode register */ + u32 sdrtr; /* SDRAM Refresh timing register */ + u32 sdsr; /* SDRAM Status register */ };
-/* - * FMC registers base - */ -#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE) - /* Control register SDCR */ #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ @@ -66,9 +91,9 @@ struct stm32_fmc_regs {
#define FMC_SDSR_BUSY BIT(5)
-#define FMC_BUSY_WAIT() do { \ +#define FMC_BUSY_WAIT(regs) do { \ __asm__ __volatile__ ("dsb" : : : "memory"); \ - while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ + while (regs->sdsr & FMC_SDSR_BUSY) \ ; \ } while (0)
@@ -93,6 +118,7 @@ struct stm32_sdram_timing { u8 trcd; }; struct stm32_sdram_params { + struct stm32_fmc_regs *base; u8 no_sdram_banks; struct stm32_sdram_control sdram_control; struct stm32_sdram_timing sdram_timing; @@ -106,6 +132,7 @@ struct stm32_sdram_params { int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); + struct stm32_fmc_regs *regs = params->base;
writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT @@ -115,7 +142,7 @@ int stm32_sdram_init(struct udevice *dev) | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); + ®s->sdcr1);
writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT @@ -124,36 +151,36 @@ int stm32_sdram_init(struct udevice *dev) | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); + ®s->sdtr1);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - &STM32_SDRAM_FMC->sdcmr); + ®s->sdcmr); udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(); + FMC_BUSY_WAIT(regs);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - &STM32_SDRAM_FMC->sdcmr); + ®s->sdcmr); udelay(100); - FMC_BUSY_WAIT(); + FMC_BUSY_WAIT(regs);
writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); + | 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr); udelay(100); - FMC_BUSY_WAIT(); + FMC_BUSY_WAIT(regs);
writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - &STM32_SDRAM_FMC->sdcmr); + ®s->sdcmr); udelay(100); - FMC_BUSY_WAIT(); + FMC_BUSY_WAIT(regs);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - &STM32_SDRAM_FMC->sdcmr); - FMC_BUSY_WAIT(); + ®s->sdcmr); + FMC_BUSY_WAIT(regs);
/* Refresh timer */ - writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr); + writel((params->sdram_ref_count) << 1, ®s->sdrtr);
return 0; } @@ -189,7 +216,16 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
static int stm32_fmc_probe(struct udevice *dev) { + struct stm32_sdram_params *params = dev_get_platdata(dev); int ret; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + params->base = (struct stm32_fmc_regs *)addr; + #ifdef CONFIG_CLK struct clk clk;
On Tue, Jul 18, 2017 at 05:37:25PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM registers are located at offset 0x140 inside FMC block. Update the stm32_fmc_regs fields with all FMC registers to map SDRAM registers at the right address.
These additionals registers will be used later.
Signed-off-by: Patrice Chotard patrice.chotard@st.com
Applied to u-boot/master, thanks!
From: Patrice Chotard patrice.chotard@st.com
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org ---
v2: _ add Reviewed-by: Simon Glass
drivers/ram/stm32_sdram.c | 83 +++++++++++++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 36 deletions(-)
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 9b2cec4..4029811 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -120,8 +120,8 @@ struct stm32_sdram_timing { struct stm32_sdram_params { struct stm32_fmc_regs *base; u8 no_sdram_banks; - struct stm32_sdram_control sdram_control; - struct stm32_sdram_timing sdram_timing; + struct stm32_sdram_control *sdram_control; + struct stm32_sdram_timing *sdram_timing; u32 sdram_ref_count; };
@@ -133,24 +133,26 @@ int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); struct stm32_fmc_regs *regs = params->base; - - writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT - | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT - | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT - | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT - | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT - | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT - | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT - | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, + struct stm32_sdram_control *control = params->sdram_control; + struct stm32_sdram_timing *timing = params->sdram_timing; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, ®s->sdcr1);
- writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT - | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT - | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT - | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT - | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT - | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT - | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, ®s->sdtr1);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, @@ -169,7 +171,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT(regs);
writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, ®s->sdcmr); udelay(100); @@ -187,27 +189,36 @@ int stm32_sdram_init(struct udevice *dev)
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { - int ret; - int node = dev_of_offset(dev); - const void *blob = gd->fdt_blob; + ofnode bank_node; struct stm32_sdram_params *params = dev_get_platdata(dev);
- params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); + params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1); debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
- fdt_for_each_subnode(node, blob, node) { - ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", - (u8 *)¶ms->sdram_control, - sizeof(params->sdram_control)); - if (ret) - return ret; - ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", - (u8 *)¶ms->sdram_timing, - sizeof(params->sdram_timing)); - if (ret) - return ret; - - params->sdram_ref_count = fdtdec_get_int(blob, node, + dev_for_each_subnode(bank_node, dev) { + params->sdram_control = (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->sdram_control) { + error("st,sdram-control not found for device: %s", + dev->name); + return -EINVAL; + } + + params->sdram_timing = (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->sdram_timing) { + error("st,sdram-timing not found for device: %s", + dev->name); + return -EINVAL; + } + + params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); }
On Tue, Jul 18, 2017 at 05:37:26PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
From: Patrice Chotard patrice.chotard@st.com
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be configured.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org ---
v2: _ add Reviewed-by: Simon Glass
doc/device-tree-bindings/ram/st,stm32-fmc.txt | 19 ++- drivers/ram/stm32_sdram.c | 215 +++++++++++++++++--------- 2 files changed, 155 insertions(+), 79 deletions(-)
diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt index 3d1392c..99f76d5 100644 --- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt +++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt @@ -40,12 +40,19 @@ Example: pinctrl-names = "default"; status = "okay";
- mr-nbanks = <1>; /* sdram memory configuration from sdram datasheet */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 CAS_3 RD_BURST_EN RD_PIPE_DL_0>; - st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 TRCD_18>; - }; -} + }; + + /* sdram memory configuration from sdram datasheet */ + bank2: bank@1 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + CAS_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + TRCD_18>; + }; + } diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 4029811..6fb89fb 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -117,12 +117,23 @@ struct stm32_sdram_timing { u8 twr; u8 trcd; }; -struct stm32_sdram_params { - struct stm32_fmc_regs *base; - u8 no_sdram_banks; +enum stm32_fmc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + MAX_SDRAM_BANK, +}; + +struct bank_params { struct stm32_sdram_control *sdram_control; struct stm32_sdram_timing *sdram_timing; u32 sdram_ref_count; + enum stm32_fmc_bank target_bank; +}; + +struct stm32_sdram_params { + struct stm32_fmc_regs *base; + u8 no_sdram_banks; + struct bank_params bank_params[MAX_SDRAM_BANK]; };
#define SDRAM_MODE_BL_SHIFT 0 @@ -132,96 +143,154 @@ struct stm32_sdram_params { int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); + struct stm32_sdram_control *control; + struct stm32_sdram_timing *timing; struct stm32_fmc_regs *regs = params->base; - struct stm32_sdram_control *control = params->sdram_control; - struct stm32_sdram_timing *timing = params->sdram_timing; - - writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT - | control->cas_latency << FMC_SDCR_CAS_SHIFT - | control->no_banks << FMC_SDCR_NB_SHIFT - | control->memory_width << FMC_SDCR_MWID_SHIFT - | control->no_rows << FMC_SDCR_NR_SHIFT - | control->no_columns << FMC_SDCR_NC_SHIFT - | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT - | control->rd_burst << FMC_SDCR_RBURST_SHIFT, - ®s->sdcr1); - - writel(timing->trcd << FMC_SDTR_TRCD_SHIFT - | timing->trp << FMC_SDTR_TRP_SHIFT - | timing->twr << FMC_SDTR_TWR_SHIFT - | timing->trc << FMC_SDTR_TRC_SHIFT - | timing->tras << FMC_SDTR_TRAS_SHIFT - | timing->txsr << FMC_SDTR_TXSR_SHIFT - | timing->tmrd << FMC_SDTR_TMRD_SHIFT, - ®s->sdtr1); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - ®s->sdcmr); - udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | control->cas_latency << SDRAM_MODE_CAS_SHIFT) - << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - ®s->sdcmr); - FMC_BUSY_WAIT(regs); - - /* Refresh timer */ - writel((params->sdram_ref_count) << 1, ®s->sdrtr); + enum stm32_fmc_bank target_bank; + u32 ctb; /* SDCMR register: Command Target Bank */ + u32 ref_count; + u8 i; + + for (i = 0; i < params->no_sdram_banks; i++) { + control = params->bank_params[i].sdram_control; + timing = params->bank_params[i].sdram_timing; + target_bank = params->bank_params[i].target_bank; + ref_count = params->bank_params[i].sdram_ref_count; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, + ®s->sdcr1); + + if (target_bank == SDRAM_BANK2) + writel(control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT, + ®s->sdcr2); + + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr1); + + if (target_bank == SDRAM_BANK2) + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr2); + if (target_bank == SDRAM_BANK1) + ctb = FMC_SDCMR_BANK_1; + else + ctb = FMC_SDCMR_BANK_2; + + writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); + FMC_BUSY_WAIT(regs); + + /* Refresh timer */ + writel(ref_count << 1, ®s->sdrtr); + }
return 0; }
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { - ofnode bank_node; struct stm32_sdram_params *params = dev_get_platdata(dev); - - params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1); - debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + struct bank_params *bank_params; + ofnode bank_node; + char *bank_name; + u8 bank = 0;
dev_for_each_subnode(bank_node, dev) { - params->sdram_control = (struct stm32_sdram_control *) - ofnode_read_u8_array_ptr(bank_node, - "st,sdram-control", - sizeof(struct stm32_sdram_control)); - - if (!params->sdram_control) { - error("st,sdram-control not found for device: %s", - dev->name); + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strsep(&bank_name, "@"); + if (!bank_name) { + error("missing sdram bank index"); + return -EINVAL; + } + + bank_params = ¶ms->bank_params[bank]; + strict_strtoul(bank_name, 10, + (long unsigned int *)&bank_params->target_bank); + + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + error("Found bank %d , but only bank 0 and 1 are supported", + bank_params->target_bank); + return -EINVAL; + } + + debug("Find bank %s %u\n", bank_name, bank_params->target_bank); + + params->bank_params[bank].sdram_control = + (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->bank_params[bank].sdram_control) { + error("st,sdram-control not found for %s", + ofnode_get_name(bank_node)); return -EINVAL; }
- params->sdram_timing = (struct stm32_sdram_timing *) - ofnode_read_u8_array_ptr(bank_node, - "st,sdram-timing", - sizeof(struct stm32_sdram_timing));
- if (!params->sdram_timing) { - error("st,sdram-timing not found for device: %s", - dev->name); + params->bank_params[bank].sdram_timing = + (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->bank_params[bank].sdram_timing) { + error("st,sdram-timing not found for %s", + ofnode_get_name(bank_node)); return -EINVAL; }
- params->sdram_ref_count = ofnode_read_u32_default(bank_node, + + bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); + bank++; }
+ params->no_sdram_banks = bank; + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + return 0; }
On Tue, Jul 18, 2017 at 05:37:27PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be configured.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
From: Patrice Chotard patrice.chotard@st.com
FMC driver is now able to discover the bank number by parsing bank subnodes.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org ---
v2: _ add Reviewed-by: Simon Glass
arch/arm/dts/stm32f746-disco.dts | 1 - arch/arm/dts/stm32f769-disco.dts | 1 - 2 files changed, 2 deletions(-)
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 2c7fa79..c92c2e2 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -195,7 +195,6 @@ pinctrl-names = "default"; status = "okay";
- mr-nbanks = <1>; /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4 diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 6591cc8..f34ffcc 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -209,7 +209,6 @@ pinctrl-names = "default"; status = "okay";
- mr-nbanks = <1>; /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
On Tue, Jul 18, 2017 at 05:37:28PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
FMC driver is now able to discover the bank number by parsing bank subnodes.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
From: Patrice Chotard patrice.chotard@st.com
STM32F7 and H7 shared the same SDRAM control block. On STM32H7 few control bits has been added. The current driver need some minor adaptation as FMC block enable/disable for H7.
Signed-off-by: Patrice Chotard patrice.chotard@st.com --- v2: _ rework comment _ replace generic_clear_bit/set_bit() by clrbits_le32/setbits_le32()
drivers/ram/stm32_sdram.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 6fb89fb..b1b0289 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -54,6 +54,12 @@ struct stm32_fmc_regs { u32 sdsr; /* SDRAM Status register */ };
+/* + * NOR/PSRAM Control register BCR1 + * FMC controller Enable, only availabe for H7 + */ +#define FMC_BCR1_FMCEN BIT(31) + /* Control register SDCR */ #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ @@ -123,6 +129,11 @@ enum stm32_fmc_bank { MAX_SDRAM_BANK, };
+enum stm32_fmc_family { + STM32F7_FMC, + STM32H7_FMC, +}; + struct bank_params { struct stm32_sdram_control *sdram_control; struct stm32_sdram_timing *sdram_timing; @@ -134,6 +145,7 @@ struct stm32_sdram_params { struct stm32_fmc_regs *base; u8 no_sdram_banks; struct bank_params bank_params[MAX_SDRAM_BANK]; + enum stm32_fmc_family family; };
#define SDRAM_MODE_BL_SHIFT 0 @@ -151,6 +163,10 @@ int stm32_sdram_init(struct udevice *dev) u32 ref_count; u8 i;
+ /* disable the FMC controller */ + if (params->family == STM32H7_FMC) + clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + for (i = 0; i < params->no_sdram_banks; i++) { control = params->bank_params[i].sdram_control; timing = params->bank_params[i].sdram_timing; @@ -193,6 +209,7 @@ int stm32_sdram_init(struct udevice *dev) | timing->txsr << FMC_SDTR_TXSR_SHIFT | timing->tmrd << FMC_SDTR_TMRD_SHIFT, ®s->sdtr2); + if (target_bank == SDRAM_BANK1) ctb = FMC_SDCMR_BANK_1; else @@ -225,6 +242,10 @@ int stm32_sdram_init(struct udevice *dev) writel(ref_count << 1, ®s->sdrtr); }
+ /* enable the FMC controller */ + if (params->family == STM32H7_FMC) + setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + return 0; }
@@ -305,6 +326,7 @@ static int stm32_fmc_probe(struct udevice *dev) return -EINVAL;
params->base = (struct stm32_fmc_regs *)addr; + params->family = dev_get_driver_data(dev);
#ifdef CONFIG_CLK struct clk clk; @@ -337,7 +359,8 @@ static struct ram_ops stm32_fmc_ops = { };
static const struct udevice_id stm32_fmc_ids[] = { - { .compatible = "st,stm32-fmc" }, + { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, + { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, { } };
On Tue, Jul 18, 2017 at 05:37:29PM +0200, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
STM32F7 and H7 shared the same SDRAM control block. On STM32H7 few control bits has been added. The current driver need some minor adaptation as FMC block enable/disable for H7.
Signed-off-by: Patrice Chotard patrice.chotard@st.com
Applied to u-boot/master, thanks!
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