[PATCH] mtd: spinand: macronix: Add support for serial NAND flash
Macronix NAND Flash devices are available in different configurations and densities.
MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4)
MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%203V,...
MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%201.8...
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8...
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8...
MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%201.8...
Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao jaimeliao@mxic.com.tw --- drivers/mtd/nand/spi/macronix.c | 100 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX35LF2G14AC", 0x20, + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF4G24AD", 0xb5, + NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF4GE4AD", 0xb7, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G14AC", 0xa0, + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G24AD", 0xa4, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AD", 0xa6, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AC", 0xa2, + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G14AC", 0x90, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G24AD", 0x94, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AD", 0x96, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AC", 0x92, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + };
static int macronix_spinand_detect(struct spinand_device *spinand)
Hi Jaime,
Jaime Liao jaimeliao@mxic.com.tw wrote on Thu, 27 May 2021 16:51:12 +0800:
Macronix NAND Flash devices are available in different configurations and densities.
MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4)
MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%203V,...
MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%201.8...
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8...
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8...
MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%201.8...
Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao jaimeliao@mxic.com.tw
drivers/mtd/nand/spi/macronix.c | 100 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- SPINAND_INFO("MX35LF2G14AC", 0x20,
NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),NAND_ECCREQ(4, 512),SPINAND_INFO_OP_VARIANTS(&read_cache_variants,&write_cache_variants,&update_cache_variants),SPINAND_HAS_QE_BIT,SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,mx35lf1ge4ab_ecc_get_status)),
This looks like a copy of your previous patch, with the SPINAND_ID macro dropped.
It would be great if you could clarify your intentions when sending patches. This means: - Counting up patch versions - Explaining their differences and why
So, what is the purpose of this patch give the fact that I already applied one very similar yesterday?
Thanks, Miquèl
Hi Miquel,
"Miquel Raynal" miquel.raynal@bootlin.com wrote on 2021/05/27 下午 04:58:45:
"Miquel Raynal" miquel.raynal@bootlin.com 2021/05/27 下午 04:59
To
"Jaime Liao" jaimeliao@mxic.com.tw,
cc
u-boot@lists.denx.de, jagan@amarulasolutions.com, vigneshr@ti.com, zhengxunli@mxic.com.tw, ycllin@mxic.com.tw
Subject
Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
Hi Jaime,
Jaime Liao jaimeliao@mxic.com.tw wrote on Thu, 27 May 2021 16:51:12 +0800:
Macronix NAND Flash devices are available in different configurations and densities.
MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4)
MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/
MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf
MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND
flash device
(without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/
MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/
MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/
MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/
MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf
Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao jaimeliao@mxic.com.tw
drivers/mtd/nand/spi/macronix.c | 100 +++++++++++++++++++++++++++
+++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/
spi/macronix.c
index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info
macronix_spinand_table[] = {
&update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- SPINAND_INFO("MX35LF2G14AC", 0x20,
NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),NAND_ECCREQ(4, 512),SPINAND_INFO_OP_VARIANTS(&read_cache_variants,&write_cache_variants,&update_cache_variants),SPINAND_HAS_QE_BIT,SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,mx35lf1ge4ab_ecc_get_status)),This looks like a copy of your previous patch, with the SPINAND_ID macro dropped.
It would be great if you could clarify your intentions when sending patches. This means:
- Counting up patch versions
- Explaining their differences and why
So, what is the purpose of this patch give the fact that I already applied one very similar yesterday?
Thanks, Miquèl
Forward my colleague(Jaime)'s mail as below:
"It is grateful for your comments.
Two patches are different for linux kernel and u-boot.
In this u-boot patch, my purpose is add SPI-NAND IDs in u-boot.
For patching reasonable, I have a question.
AFAIK u-boot didn't include sw-ecc engine.
Is it suitable for Flash which are sw-ecc requirement?"
Thanks,
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=====================================================================
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This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
Hi zhengxunli@mxic.com.tw,
zhengxunli@mxic.com.tw wrote on Mon, 31 May 2021 10:16:24 +0800:
Hi Miquel,
"Miquel Raynal" miquel.raynal@bootlin.com wrote on 2021/05/27 下午 04:58:45:
"Miquel Raynal" miquel.raynal@bootlin.com 2021/05/27 下午 04:59
To
"Jaime Liao" jaimeliao@mxic.com.tw,
cc
u-boot@lists.denx.de, jagan@amarulasolutions.com, vigneshr@ti.com, zhengxunli@mxic.com.tw, ycllin@mxic.com.tw
Subject
Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
Hi Jaime,
Jaime Liao jaimeliao@mxic.com.tw wrote on Thu, 27 May 2021 16:51:12 +0800:
Macronix NAND Flash devices are available in different configurations and densities.
MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4)
MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/
MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf
MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND
flash device
(without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/
MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/
MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/
MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/
MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf
Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao jaimeliao@mxic.com.tw
drivers/mtd/nand/spi/macronix.c | 100 +++++++++++++++++++++++++++
+++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/
spi/macronix.c
index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info
macronix_spinand_table[] = {
&update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- SPINAND_INFO("MX35LF2G14AC", 0x20,
NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),NAND_ECCREQ(4, 512),SPINAND_INFO_OP_VARIANTS(&read_cache_variants,&write_cache_variants,&update_cache_variants),SPINAND_HAS_QE_BIT,SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,mx35lf1ge4ab_ecc_get_status)),This looks like a copy of your previous patch, with the SPINAND_ID macro dropped.
It would be great if you could clarify your intentions when sending patches. This means:
- Counting up patch versions
- Explaining their differences and why
So, what is the purpose of this patch give the fact that I already applied one very similar yesterday?
Thanks, Miquèl
Forward my colleague(Jaime)'s mail as below:
"It is grateful for your comments.
Two patches are different for linux kernel and u-boot.
In this u-boot patch, my purpose is add SPI-NAND IDs in u-boot.
Sorry for the misunderstanding, I thought this was intended for Linux.
For patching reasonable, I have a question.
AFAIK u-boot didn't include sw-ecc engine.
True.
Is it suitable for Flash which are sw-ecc requirement?"
Not yet, if there are no on-die ECC engine the parts cannot be used in U-Boot yet.
Thanks, Miquèl
Hi Miquel
"Miquel Raynal" miquel.raynal@bootlin.com 2021/06/07 下午 02:13
收件人
zhengxunli@mxic.com.tw,
副本抄送
jagan@amarulasolutions.com, "Jaime Liao" jaimeliao@mxic.com.tw, u- boot@lists.denx.de, vigneshr@ti.com, ycllin@mxic.com.tw
主旨
Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
Hi zhengxunli@mxic.com.tw,
zhengxunli@mxic.com.tw wrote on Mon, 31 May 2021 10:16:24 +0800:
Hi Miquel,
"Miquel Raynal" miquel.raynal@bootlin.com wrote on 2021/05/27 下午 04:58:45:
"Miquel Raynal" miquel.raynal@bootlin.com 2021/05/27 下午 04:59
To
"Jaime Liao" jaimeliao@mxic.com.tw,
cc
u-boot@lists.denx.de, jagan@amarulasolutions.com, vigneshr@ti.com, zhengxunli@mxic.com.tw, ycllin@mxic.com.tw
Subject
Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND
flash
Hi Jaime,
Jaime Liao jaimeliao@mxic.com.tw wrote on Thu, 27 May 2021
16:51:12
+0800:
Macronix NAND Flash devices are available in different
configurations
and densities.
MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4)
MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/
MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf
MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND
flash device
(without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/
MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/
MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/
MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/
MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf
Validated via normal(default) and QUAD mode by read, erase, read
back,
on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao jaimeliao@mxic.com.tw
drivers/mtd/nand/spi/macronix.c | 100 +++++++++++++++++++++++++++
+++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/
spi/macronix.c
index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info
macronix_spinand_table[] = {
&update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- SPINAND_INFO("MX35LF2G14AC", 0x20,
NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),NAND_ECCREQ(4, 512),SPINAND_INFO_OP_VARIANTS(&read_cache_variants,&write_cache_variants,&update_cache_variants),SPINAND_HAS_QE_BIT,SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,mx35lf1ge4ab_ecc_get_status)),This looks like a copy of your previous patch, with the SPINAND_ID macro dropped.
It would be great if you could clarify your intentions when sending patches. This means:
- Counting up patch versions
- Explaining their differences and why
So, what is the purpose of this patch give the fact that I already applied one very similar yesterday?
Thanks, Miquèl
Forward my colleague(Jaime)'s mail as below:
"It is grateful for your comments.
Two patches are different for linux kernel and u-boot.
In this u-boot patch, my purpose is add SPI-NAND IDs in u-boot.
Sorry for the misunderstanding, I thought this was intended for Linux.
For patching reasonable, I have a question.
AFAIK u-boot didn't include sw-ecc engine.
True.
Is it suitable for Flash which are sw-ecc requirement?"
Not yet, if there are no on-die ECC engine the parts cannot be used in U-Boot yet.
Thanks for your reply, I will send a new patch later with on-die ECC only.
Thanks Jaime
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participants (4)
-
Jaime Liao -
jaimeliao＠mxic.com.tw
-
Miquel Raynal -
zhengxunli＠mxic.com.tw