Hi Anup,

On Sun, Oct 25, 2020 at 11:13 AM Anup Patel anup@brainfault.org wrote:

On Thu, Oct 22, 2020 at 1:23 PM Padmarao Begari padmarao.begari@microchip.com wrote:

...

dma_addr_t holds any valid DMA address. If the DMA API only uses

32/64-bit

...

addresses, dma_addr_t need only be 32/64 bits wide.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

arch/riscv/Kconfig | 5 +++++ arch/riscv/include/asm/types.h | 4 ++++ 2 files changed, 9 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..7ab1ccff40 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,11 @@ config 32BIT config 64BIT bool

+config DMA_ADDR_T_64BIT

•   bool
  

•   depends on 64BIT
  

•   default n
  

This should be "default y if 64BIT".

Ok

...

config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h

b/arch/riscv/include/asm/types.h

...

index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t;

#include <stddef.h>

+#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif

typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1

Apart from above, looks good to me.

Reviewed-by: Anup Patel anup.patel@wdc.com

Thank you for review

Regards Padmarao

Regards, Anup

On Thu, Oct 22, 2020 at 12:52 PM Padmarao Begari padmarao.begari@microchip.com wrote:

Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT is enabled. 32-bit DMA is enabled by default.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

drivers/net/macb.c | 46 ++++++++++++++++++++++++++++++++++++++-------- drivers/net/macb.h | 6 ++++++ 2 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c index b80a259ff7..e0e86a274e 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -81,6 +81,10 @@ DECLARE_GLOBAL_DATA_PTR; struct macb_dma_desc { u32 addr; u32 ctrl; +#ifdef CONFIG_DMA_ADDR_T_64BIT

•   u32 addrh;
  

•   u32 unused;
  

+#endif };

#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) @@ -326,7 +330,10 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, }

    macb->tx_ring[tx_head].ctrl = ctrl;

•   macb->tx_ring[tx_head].addr = paddr;
  

•   macb->tx_ring[tx_head].addr = lower_32_bits(paddr);
  

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•   macb->tx_ring[tx_head].addrh = upper_32_bits(paddr);
  

+#endif barrier(); macb_flush_ring_desc(macb, TX); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); @@ -732,9 +739,20 @@ static int gmac_init_multi_queues(struct macb_device *macb) flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));

•   for (i = 1; i < num_queues; i++)
  

•           gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
  

•   for (i = 1; i < num_queues; i++) {
  

•           gem_writel_queue_TBQP(macb,
  

•                   lower_32_bits(macb->dummy_desc_dma), i - 1);
  

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•           gem_writel_queue_TBQPH(macb,
  

•                   upper_32_bits(macb->dummy_desc_dma), i - 1);
  

+#endif

•           gem_writel_queue_RBQP(macb,
  

•                   lower_32_bits(macb->dummy_desc_dma), i - 1);
  

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•           gem_writel_queue_RBQPH(macb,
  

•                   upper_32_bits(macb->dummy_desc_dma), i - 1);
  

+#endif

•   }
    return 0;
  

}

@@ -760,6 +778,9 @@ static void gmac_configure_dma(struct macb_device *macb) dmacfg &= ~GEM_BIT(ENDIA_DESC);

    dmacfg &= ~GEM_BIT(ADDR64);

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•   dmacfg |= GEM_BIT(ADDR64);
  

+#endif gem_writel(macb, DMACFG, dmacfg); }

@@ -786,8 +807,11 @@ static int _macb_init(struct macb_device *macb, const char *name) for (i = 0; i < MACB_RX_RING_SIZE; i++) { if (i == (MACB_RX_RING_SIZE - 1)) paddr |= MACB_BIT(RX_WRAP);

•           macb->rx_ring[i].addr = paddr;
  

•           macb->rx_ring[i].addr = lower_32_bits(paddr);
            macb->rx_ring[i].ctrl = 0;
  

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•           macb->rx_ring[i].addrh = upper_32_bits(paddr);
  

+#endif paddr += macb->rx_buffer_size; } macb_flush_ring_desc(macb, RX); @@ -800,6 +824,9 @@ static int _macb_init(struct macb_device *macb, const char *name) MACB_BIT(TX_WRAP); else macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); +#ifdef CONFIG_DMA_ADDR_T_64BIT

•           macb->tx_ring[i].addrh = 0x0;
  

+#endif } macb_flush_ring_desc(macb, TX);

@@ -812,9 +839,12 @@ static int _macb_init(struct macb_device *macb, const char *name) gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); #endif

•   macb_writel(macb, RBQP, macb->rx_ring_dma);
  

•   macb_writel(macb, TBQP, macb->tx_ring_dma);
  

•   macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
  

•   macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
  

+#ifdef CONFIG_DMA_ADDR_T_64BIT

•   macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
  

•   macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
  

+#endif if (macb_is_gem(macb)) { /* Initialize DMA properties */ gmac_configure_dma(macb); diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 9b16383eba..72b84ae96e 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -768,5 +768,11 @@ #define GEM_RX_CSUM_CHECKED_MASK 2 #define gem_writel_queue_TBQP(port, value, queue_num) \ writel((value), (port)->regs + GEM_TBQP(queue_num)) +#define gem_writel_queue_TBQPH(port, value, queue_num) \

•   writel((value), (port)->regs + GEM_TBQPH(queue_num))
  

+#define gem_writel_queue_RBQP(port, value, queue_num) \

•   writel((value), (port)->regs + GEM_RBQP(queue_num))
  

+#define gem_writel_queue_RBQPH(port, value, queue_num) \

•   writel((value), (port)->regs + GEM_RBQPH(queue_num))
  
  

#endif /* __DRIVERS_MACB_H__ */

2.17.1

Is there a way to know whether MACB hardware support 64bit DMA address using some MACB version/capability register ? If yes then please use runtime check instead of "#ifdef"

Regards, Anup

Hi Anup,

On Sun, Oct 25, 2020 at 11:50 AM Anup Patel anup@brainfault.org wrote:

On Thu, Oct 22, 2020 at 12:52 PM Padmarao Begari padmarao.begari@microchip.com wrote:

...

Read phy address from device tree and use it to find the phy device if not found then search in the range of 0 to 31.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

drivers/net/macb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c index e0e86a274e..7f592d510c 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -477,6 +477,12 @@ static int macb_phy_find(struct macb_device *macb,

const char *name)

...

    int i;
    u16 phy_id;

•   phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
  

•   if (phy_id != 0xffff) {
  

•           printf("%s: PHY present at %d\n", name, macb->phy_addr);
  

•           return 0;
  

•   }
  

•   /* Search for PHY... */
    for (i = 0; i < 32; i++) {
            macb->phy_addr = i;
  

@@ -1256,6 +1262,8 @@ static int macb_eth_probe(struct udevice *dev) struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; int ret;

•   u32 phy_addr;
  

•   ofnode node;
  
    phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  

"phy-mode",

...

                           NULL);

@@ -1266,6 +1274,13 @@ static int macb_eth_probe(struct udevice *dev) return -EINVAL; }

•   /* Look for a PHY node under the Ethernet node */
  

•   node = dev_read_subnode(dev, "ethernet-phy");
  

•   if (ofnode_valid(node)) {
  

•           ofnode_read_u32(node, "reg", &phy_addr);
  

•           macb->phy_addr = phy_addr;
  

•   }
  

Instead of custom DT property "ethernet-phy", we should use standard "phy-handle" DT property. (Refer, <linux_sources>/Documentation/devicetree/bindings/net/ethernet-controller.yaml)

...

    macb->regs = (void *)pdata->iobase;

    macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);

-- 2.17.1

Ok

Regards Padmarao

Regards, Anup

On Thu, Oct 22, 2020 at 1:11 PM Padmarao Begari padmarao.begari@microchip.com wrote:

Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk_pfsoc.c | 127 +++++++++++++ drivers/clk/microchip/clk_pfsoc.h | 19 ++ drivers/clk/microchip/clk_pfsoc_cfg.c | 134 ++++++++++++++ drivers/clk/microchip/clk_pfsoc_periph.c | 173 ++++++++++++++++++ .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++++ 9 files changed, 506 insertions(+) create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk_pfsoc.c create mode 100644 drivers/clk/microchip/clk_pfsoc.h create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4dfbad7986..1161fe7b5a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d1e295ac7c..bd8a6eed88 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ +obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig new file mode 100644 index 0000000000..b70241559d --- /dev/null +++ b/drivers/clk/microchip/Kconfig @@ -0,0 +1,5 @@ +config CLK_MPFS

•   bool "Clock support for Microchip PolarFire SoC"
  

•   depends on CLK && CLK_CCF
  

•   help
  

•     This enables support clock driver for Microchip PolarFire SoC platform.
  

diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 0000000000..c7f5ad21ae --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1 @@ +obj-y += clk_pfsoc.o clk_pfsoc_cfg.o clk_pfsoc_periph.o diff --git a/drivers/clk/microchip/clk_pfsoc.c b/drivers/clk/microchip/clk_pfsoc.c new file mode 100644 index 0000000000..dd0e9cacb8 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2020 Microchip Technology Inc.
• • Padmarao Begari padmarao.begari@microchip.com
• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <log.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <malloc.h> +#include <linux/err.h>

+#include "clk_pfsoc.h"

+/* All methods are delegated to CCF clocks */

+static ulong pfsoc_clk_get_rate(struct clk *clk) +{

•   struct clk *c;
  

•   int err = clk_get_by_id(clk->id, &c);
  

•   if (err)
  

•           return err;
  

•   return clk_get_rate(c);
  

+}

+static ulong pfsoc_clk_set_rate(struct clk *clk, unsigned long rate) +{

•   struct clk *c;
  

•   int err = clk_get_by_id(clk->id, &c);
  

•   if (err)
  

•           return err;
  

•   return clk_set_rate(c, rate);
  

+}

+static int pfsoc_clk_set_parent(struct clk *clk, struct clk *parent) +{

•   struct clk *c, *p;
  

•   int err = clk_get_by_id(clk->id, &c);
  

•   if (err)
  

•           return err;
  

•   err = clk_get_by_id(parent->id, &p);
  

•   if (err)
  

•           return err;
  

•   return clk_set_parent(c, p);
  

+}

+static int pfsoc_clk_endisable(struct clk *clk, bool enable) +{

•   struct clk *c;
  

•   int err = clk_get_by_id(clk->id, &c);
  

•   if (err)
  

•           return err;
  

•   return enable ? clk_enable(c) : clk_disable(c);
  

+}

+static int pfsoc_clk_enable(struct clk *clk) +{

•   return pfsoc_clk_endisable(clk, true);
  

+}

+static int pfsoc_clk_disable(struct clk *clk) +{

•   return pfsoc_clk_endisable(clk, false);
  

+}

+static int pfsoc_clk_probe(struct udevice *dev) +{

•   int ret;
  

•   void __iomem *base;
  

•   u32 clk_rate;
  

•   struct clk *clk;
  

•   const char *parent_clk_name;
  

•   base = dev_read_addr_ptr(dev);
  

•   if (!base)
  

•           return -ENODEV;
  

•   clk = kzalloc(sizeof(*clk), GFP_KERNEL);
  

•   if (!clk)
  

•           return -ENOMEM;
  

•   ret = clk_get_by_index(dev, 0, clk);
  

•   if (ret)
  

•           return ret;
  

•   dev_read_u32(clk->dev, "clock-frequency", &clk_rate);
  

•   parent_clk_name = clk->dev->name;
  

•   ret = pfsoc_clk_register_cfgs(base, clk_rate, parent_clk_name);
  

•   if (ret)
  

•           return ret;
  

•   ret = pfsoc_clk_register_periphs(base, clk_rate, "clk_ahb");
  

•   return ret;
  

+}

+static const struct clk_ops pfsoc_clk_ops = {

•   .set_rate = pfsoc_clk_set_rate,
  

•   .get_rate = pfsoc_clk_get_rate,
  

•   .set_parent = pfsoc_clk_set_parent,
  

•   .enable = pfsoc_clk_enable,
  

•   .disable = pfsoc_clk_disable,
  

+};

+static const struct udevice_id pfsoc_of_match[] = {

•   { .compatible = "microchip,pfsoc-clkcfg" },
  

•   { }
  

+};

+U_BOOT_DRIVER(pfsoc_clk) = {

•   .name = "pfsoc_clk",
  

•   .id = UCLASS_CLK,
  

•   .of_match = pfsoc_of_match,
  

•   .ops = &pfsoc_clk_ops,
  

•   .probe = pfsoc_clk_probe,
  

+}; diff --git a/drivers/clk/microchip/clk_pfsoc.h b/drivers/clk/microchip/clk_pfsoc.h new file mode 100644 index 0000000000..3058b83f0d --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2020 Microchip Technology Inc.
• • Padmarao Begari padmarao.begari@microchip.com
• */

+#ifndef __MICROCHIP_PFSOC_CLK_H +#define __MICROCHIP_PFSOC_CLK_H

+#include <linux/clk-provider.h>

+int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate,

•                                   const char *parent_name);
  

+int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate,

•                                   const char *parent_name);
  

+int divider_get_val(unsigned long rate, unsigned long parent_rate,

•                                   const struct clk_div_table *table,
  

•                                   u8 width, unsigned long flags);
  

+#endif /* __MICROCHIP_PFSOC_CLK_H */ diff --git a/drivers/clk/microchip/clk_pfsoc_cfg.c b/drivers/clk/microchip/clk_pfsoc_cfg.c new file mode 100644 index 0000000000..2174b5a03e --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_cfg.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2020 Microchip Technology Inc.
• • Padmarao Begari padmarao.begari@microchip.com
• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <asm/io.h> +#include <linux/err.h> +#include <dt-bindings/clock/microchip,pfsoc-clock.h>

+#include "clk_pfsoc.h"

+#define PFSOC_CFG_CLOCK "pfsoc_cfg_clock"

+#define REG_CLOCK_CONFIG_CR 0x08

+static const struct clk_div_table pfsoc_div_cpu_axi_table[] = {

•   { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  

•   { 0, 0 }
  

+};

+static const struct clk_div_table pfsoc_div_ahb_table[] = {

•   { 1, 2 }, { 2, 4}, { 3, 8 },
  

•   { 0, 0 }
  

+};

+struct pfsoc_cfg_clock {

•   unsigned int id;
  

•   const char *name;
  

•   u8 shift;
  

•   u8 width;
  

•   const struct clk_div_table *table;
  

•   unsigned long flags;
  

+};

+struct pfsoc_cfg_hw_clock {

•   struct pfsoc_cfg_clock cfg;
  

•   void __iomem *sys_base;
  

•   u32 prate;
  

•   struct clk hw;
  

+};

+#define to_pfsoc_cfg_clk(_hw) container_of(_hw, struct pfsoc_cfg_hw_clock, hw)

+static ulong pfsoc_cfg_clk_recalc_rate(struct clk *hw) +{

•   struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw);
  

•   struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg;
  

•   void __iomem *base_addr = cfg_hw->sys_base;
  

•   unsigned long rate;
  

•   u32 val;
  

•   val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
  

•   val &= clk_div_mask(cfg->width);
  

•   rate = cfg_hw->prate / (1u << val);
  

•   hw->rate = rate;
  

•   return rate;
  

+}

+static ulong pfsoc_cfg_clk_set_rate(struct clk *hw, ulong rate) +{

•   struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw);
  

•   struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg;
  

•   void __iomem *base_addr = cfg_hw->sys_base;
  

•   u32  val;
  

•   int divider_setting;
  

•   divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags);
  

•   if (divider_setting < 0)
  

•           return divider_setting;
  

•   val = readl(base_addr + REG_CLOCK_CONFIG_CR);
  

•   val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
  

•   val |= divider_setting << cfg->shift;
  

•   writel(val, base_addr + REG_CLOCK_CONFIG_CR);
  

•   return clk_get_rate(hw);
  

+}

+#define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \

•           .cfg.id = _id,                                  \
  

•           .cfg.name = _name,                              \
  

•           .cfg.shift = _shift,                            \
  

•           .cfg.width = _width,                            \
  

•           .cfg.table = _table,                            \
  

•           .cfg.flags = _flags,                            \
  

•   }
  

+static struct pfsoc_cfg_hw_clock pfsoc_cfg_clks[] = {

•   CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, pfsoc_div_cpu_axi_table, 0),
  

•   CLK_CFG(CLK_AXI, "clk_axi", 2, 2, pfsoc_div_cpu_axi_table, 0),
  

•   CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, pfsoc_div_ahb_table, 0),
  

+};

+int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate,

•                                   const char *parent_name)
  

+{

•   int ret;
  

•   int i, id, num_clks;
  

•   const char *name;
  

•   struct clk *hw;
  

•   num_clks = ARRAY_SIZE(pfsoc_cfg_clks);
  

•   for (i = 0; i < num_clks; i++) {
  

•           hw = &pfsoc_cfg_clks[i].hw;
  

•           pfsoc_cfg_clks[i].sys_base = base;
  

•           pfsoc_cfg_clks[i].prate = clk_rate;
  

•           name = pfsoc_cfg_clks[i].cfg.name;
  

•           ret = clk_register(hw, PFSOC_CFG_CLOCK, name, parent_name);
  

•           if (ret)
  

•                   ERR_PTR(ret);
  

•           id = pfsoc_cfg_clks[i].cfg.id;
  

•           clk_dm(id, hw);
  

•   }
  

•   return 0;
  

+}

+const struct clk_ops pfsoc_cfg_clk_ops = {

•   .set_rate = pfsoc_cfg_clk_set_rate,
  

•   .get_rate = pfsoc_cfg_clk_recalc_rate,
  

+};

+U_BOOT_DRIVER(pfsoc_cfg_clock) = {

•   .name   = PFSOC_CFG_CLOCK,
  

•   .id     = UCLASS_CLK,
  

•   .ops    = &pfsoc_cfg_clk_ops,
  

+}; diff --git a/drivers/clk/microchip/clk_pfsoc_periph.c b/drivers/clk/microchip/clk_pfsoc_periph.c new file mode 100644 index 0000000000..c8b3b8f738 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_periph.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2020 Microchip Technology Inc.
• • Padmarao Begari padmarao.begari@microchip.com
• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <asm/io.h> +#include <linux/err.h> +#include <dt-bindings/clock/microchip,pfsoc-clock.h>

+#include "clk_pfsoc.h"

+#define PFSOC_PERIPH_CLOCK "pfsoc_periph_clock"

+#define REG_CLOCK_CONFIG_CR 0x08 +#define REG_SUBBLK_CLOCK_CR 0x84 +#define REG_SUBBLK_RESET_CR 0x88

+#define CFG_CPU_SHIFT 0x0 +#define CFG_AXI_SHIFT 0x2 +#define CFG_AHB_SHIFT 0x4 +#define CFG_WIDTH 0x2

+struct pfsoc_periph_clock {

•   unsigned int id;
  

•   const char *name;
  

•   u8 shift;
  

•   unsigned long flags;
  

+};

+struct pfsoc_periph_hw_clock {

•   struct pfsoc_periph_clock periph;
  

•   void __iomem *sys_base;
  

•   u32 prate;
  

•   struct clk hw;
  

+};

+#define to_pfsoc_periph_clk(_hw) container_of(_hw, struct pfsoc_periph_hw_clock, hw)

+static int pfsoc_periph_clk_enable(struct clk *hw) +{

•   struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw);
  

•   struct pfsoc_periph_clock *periph = &periph_hw->periph;
  

•   void __iomem *base_addr = periph_hw->sys_base;
  

•   u32 reg, val;
  

•   if (periph->flags != CLK_IS_CRITICAL) {
  

•           reg = readl(base_addr + REG_SUBBLK_RESET_CR);
  

•           val = reg & ~(1u << periph->shift);
  

•           writel(val, base_addr + REG_SUBBLK_RESET_CR);
  

•           reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
  

•           val = reg | (1u << periph->shift);
  

•           writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
  

•   }
  

•   return 0;
  

+}

+static int pfsoc_periph_clk_disable(struct clk *hw) +{

•   struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw);
  

•   struct pfsoc_periph_clock *periph = &periph_hw->periph;
  

•   void __iomem *base_addr = periph_hw->sys_base;
  

•   u32 reg, val;
  

•   if (periph->flags != CLK_IS_CRITICAL) {
  

•           reg = readl(base_addr + REG_SUBBLK_RESET_CR);
  

•           val = reg | (1u << periph->shift);
  

•           writel(val, base_addr + REG_SUBBLK_RESET_CR);
  

•           reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
  

•           val = reg & ~(1u << periph->shift);
  

•           writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
  

•   }
  

•   return 0;
  

+}

+static ulong pfsoc_periph_clk_recalc_rate(struct clk *hw) +{

•   struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw);
  

•   void __iomem *base_addr = periph_hw->sys_base;
  

•   unsigned long rate;
  

•   u32 val;
  

•   val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT;
  

•   val &= clk_div_mask(CFG_WIDTH);
  

•   rate = periph_hw->prate / (1u << val);
  

•   hw->rate = rate;
  

•   return rate;
  

+}

+#define CLK_PERIPH(_id, _name, _shift, _flags) { \

•           .periph.id = _id,                       \
  

•           .periph.name = _name,                   \
  

•           .periph.shift = _shift,                 \
  

•           .periph.flags = _flags,                 \
  

•   }
  

+static struct pfsoc_periph_hw_clock pfsoc_periph_clks[] = {

•   CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL),
  

•   CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0),
  

•   CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0),
  

•   CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0),
  

•   CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0),
  

•   CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0),
  

•   CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0),
  

•   CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0),
  

•   CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0),
  

•   CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0),
  

•   CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0),
  

•   CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0),
  

•   CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0),
  

•   CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0),
  

•   CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0),
  

•   CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0),
  

•   CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0),
  

•   CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0),
  

•   CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0),
  

•   CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0),
  

•   CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0),
  

•   CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0),
  

•   CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL),
  

•   CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0),
  

•   CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0),
  

•   CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0),
  

•   CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0),
  

•   CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0),
  

•   CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0),
  

+};

+int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate,

•                                   const char *parent_name)
  

+{

•   int ret;
  

•   int i, id, num_clks;
  

•   const char *name;
  

•   struct clk *hw;
  

•   num_clks = ARRAY_SIZE(pfsoc_periph_clks);
  

•   for (i = 0; i < num_clks; i++)  {
  

•           hw = &pfsoc_periph_clks[i].hw;
  

•           pfsoc_periph_clks[i].sys_base = base;
  

•           pfsoc_periph_clks[i].prate = clk_rate;
  

•           name = pfsoc_periph_clks[i].periph.name;
  

•           ret = clk_register(hw, PFSOC_PERIPH_CLOCK, name, parent_name);
  

•           if (ret)
  

•                   ERR_PTR(ret);
  

•           id = pfsoc_periph_clks[i].periph.id;
  

•           clk_dm(id, hw);
  

•   }
  

•   return 0;
  

+}

+const struct clk_ops pfsoc_periph_clk_ops = {

•   .enable = pfsoc_periph_clk_enable,
  

•   .disable = pfsoc_periph_clk_disable,
  

•   .get_rate = pfsoc_periph_clk_recalc_rate,
  

+};

+U_BOOT_DRIVER(pfsoc_periph_clock) = {

•   .name   = PFSOC_PERIPH_CLOCK,
  

•   .id     = UCLASS_CLK,
  

•   .ops    = &pfsoc_periph_clk_ops,
  

+}; diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h b/include/dt-bindings/clock/microchip,pfsoc-clock.h new file mode 100644 index 0000000000..527cff1a28 --- /dev/null +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright (C) 2020 Microchip Technology Inc.
• • Padmarao Begari padmarao.begari@microchip.com
• */

+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_

+#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2

+#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32

+#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */

2.17.1

There are few minor checkpatch warnings on this patch so can you please fix those.

Apart from this, it looks good to me.

Reviewed-by: Anup Patel anup.patel@wdc.com

Regards, Anup

Hi Anup,

On Sun, Oct 25, 2020 at 11:20 AM Anup Patel anup@brainfault.org wrote:

On Thu, Oct 22, 2020 at 12:53 PM Padmarao Begari padmarao.begari@microchip.com wrote:

...

Add device tree for Microchip PolarFire SoC Icicle Kit.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++++++++++++++++++ 2 files changed, 427 insertions(+) create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 3a6f96c67d..48c43bd122 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb

targets += $(dtb-y)

diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts

b/arch/riscv/dts/microchip-icicle-kit-a000.dts

...

new file mode 100644 index 0000000000..7110d2a78b --- /dev/null +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2020 Microchip Technology Inc */

+/dts-v1/; +#include "dt-bindings/clock/microchip,pfsoc-clock.h"

+/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000

+/ {

•   #address-cells = <2>;
  

•   #size-cells = <2>;
  

•   model = "Microchip PolarFire-SoC";
  

•   compatible = "microchip,polarfire-soc";
  

•   aliases {
  

•           serial0 = &uart0;
  

•           ethernet0 = &emac1;
  

•   };
  

•   chosen {
  

•           stdout-path = "serial0";
  

•   };
  

•   cpucomplex: cpus {
  

•           #address-cells = <1>;
  

•           #size-cells = <0>;
  

•           timebase-frequency = <RTCCLK_FREQ>;
  

•           cpu0: cpu@0 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,e51", "sifive,rocket0",
  

"riscv";

...

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <128>;
  

•                   i-cache-size = <16384>;
  

•                   reg = <0>;
  

•                   riscv,isa = "rv64imac";
  

•                   status = "disabled";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu0intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu1: cpu@1 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0",
  

"riscv";

...

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <1>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu1intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu2: cpu@2 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0",
  

"riscv";

...

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <2>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu2intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu3: cpu@3 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0",
  

"riscv";

...

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <3>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu3intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu4: cpu@4 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0",
  

"riscv";

...

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <4>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu4intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•   };
  

•   refclk: refclk {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <600000000>;
  

•           clock-output-names = "msspllclk";
  

•   };
  

•   ddr: memory@80000000 {
  

•           device_type = "memory";
  

•           reg = <0x0 0x80000000 0x0 0x40000000>;
  

•           clocks = <&clkcfg CLK_DDRC>;
  

•   };
  

•   soc: soc {
  

•           #address-cells = <2>;
  

•           #size-cells = <2>;
  

•           compatible = "sifive,fu540-c000", "sifive,fu540",
  

"simple-bus";

Please drop "fu540" related compatible strings from "soc" DT node.

Ok. I will drop "fu540"

•           ranges;
  

...

•           clint0: clint@2000000 {
  

•                   compatible = "riscv,clint0";
  

•                   interrupts-extended = <&cpu0intc 3 &cpu0intc 7
  

•                                           &cpu1intc 3 &cpu1intc 7
  

•                                           &cpu2intc 3 &cpu2intc 7
  

•                                           &cpu3intc 3 &cpu3intc 7
  

•                                           &cpu4intc 3 &cpu4intc 7>;
  

•                   reg = <0x0 0x2000000 0x0 0x10000>;
  

•                   reg-names = "control";
  

•                   clock-frequency = <RTCCLK_FREQ>;
  

•           };
  

•           cachecontroller: cache-controller@2010000 {
  

•                   compatible = "sifive,fu540-c000-ccache", "cache";
  

•                   cache-block-size = <64>;
  

•                   cache-level = <2>;
  

•                   cache-sets = <1024>;
  

•                   cache-size = <2097152>;
  

•                   cache-unified;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <1 2 3>;
  

•                   reg = <0x0 0x2010000 0x0 0x1000>;
  

•           };
  

•           dma: dma@3000000 {
  

•                   compatible = "sifive,fu540-c000-pdma";
  

•                   reg = <0x0 0x3000000 0x0 0x8000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <23 24 25 26 27 28 29 30>;
  

•                   #dma-cells = <1>;
  

•           };
  

•           plic: interrupt-controller@c000000 {
  

•                   #interrupt-cells = <1>;
  

•                   compatible = "sifive,plic-1.0.0";
  

•                   reg = <0x0 0xc000000 0x0 0x4000000>;
  

•                   riscv,max-priority = <7>;
  

•                   riscv,ndev = <186>;
  

•                   interrupt-controller;
  

•                   interrupts-extended = <
  

•                           &cpu0intc 11
  

•                           &cpu1intc 11 &cpu1intc 9
  

•                           &cpu2intc 11 &cpu2intc 9
  

•                           &cpu3intc 11 &cpu3intc 9
  

•                           &cpu4intc 11 &cpu4intc 9>;
  

•           };
  

•           uart0: serial@20000000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20000000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <90>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART0>;
  

•                   status = "okay";
  

•           };
  

•           clkcfg: clkcfg@20002000 {
  

•                   compatible = "microchip,pfsoc-clkcfg";
  

•                   reg = <0x0 0x20002000 0x0 0x1000>;
  

•                   reg-names = "mss_sysreg";
  

•                   clocks = <&refclk>;
  

•                   #clock-cells = <1>;
  

•                   clock-output-names = "cpu", "axi", "ahb", "envm",
  

•                                   "mac0", "mac1", "mmc", "timer",
  

•                                   "mmuart0", "mmuart1", "mmuart2",
  

•                                   "mmuart3", "mmuart4", "spi0",
  

"spi1",

...

•                                   "i2c0", "i2c1", "can0", "can1",
  

"usb",

...

•                                   "reserved", "rtc", "qspi",
  

"gpio0",

...

•                                   "gpio1", "gpio2", "ddrc", "fic0",
  

•                                   "fic1", "fic2", "fic3", "athena",
  

•                                   "cfm";
  

•           };
  

•           emmc: mmc@20008000 {
  

•                   compatible = "cdns,sd4hc";
  

•                   reg = <0x0 0x20008000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <88 89>;
  

•                   pinctrl-names = "default";
  

•                   clocks = <&clkcfg CLK_MMC>;
  

•                   bus-width = <4>;
  

•                   cap-mmc-highspeed;
  

•                   mmc-ddr-3_3v;
  

•                   max-frequency = <200000000>;
  

•                   non-removable;
  

•                   no-sd;
  

•                   no-sdio;
  

•                   voltage-ranges = <3300 3300>;
  

•                   status = "okay";
  

•           };
  

•           sdcard: sd@20008000 {
  

•                   compatible = "cdns,sd4hc";
  

•                   reg = <0x0 0x20008000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <88>;
  

•                   pinctrl-names = "default";
  

•                   clocks = <&clkcfg CLK_MMC>;
  

•                   bus-width = <4>;
  

•                   disable-wp;
  

•                   cap-sd-highspeed;
  

•                   card-detect-delay = <200>;
  

•                   sd-uhs-sdr12;
  

•                   sd-uhs-sdr25;
  

•                   sd-uhs-sdr50;
  

•                   sd-uhs-sdr104;
  

•                   max-frequency = <200000000>;
  

•                   status = "disabled";
  

•           };
  

•           uart1: serial@20100000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20100000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <91>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART1>;
  

•                   status = "okay";
  

•           };
  

•           uart2: serial@20102000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20102000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <92>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART2>;
  

•                   status = "okay";
  

•           };
  

•           uart3: serial@20104000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20104000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <93>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART3>;
  

•                   status = "okay";
  

•           };
  

•           i2c0: i2c@02010a000 {
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   compatible = "microsemi,ms-pf-mss-i2c";
  

•                   reg = <0x0 0x2010a000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <58>;
  

•                   clocks = <&clkcfg CLK_I2C0>;
  

•                   status = "disabled";
  

•           };
  

•           i2c1: i2c@02010b000 {
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   compatible = "microsemi,ms-pf-mss-i2c";
  

•                   reg = <0x0 0x2010b000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <61>;
  

•                   clocks = <&clkcfg CLK_I2C1>;
  

•                   status = "disabled";
  

•                   pac193x@0x10 {
  

•                           compatible = "microchip,pac1934";
  

•                           reg = <0x10>;
  

•                           samp-rate = <64>;
  

•                           status = "disabled";
  

•                           ch1: channel@0 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDD";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch2: channel@1 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDDA25";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch3: channel@2 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDD25";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch4: channel@3 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDDA";
  

•                                   channel_enabled;
  

•                           };
  

•                   };
  

•           };
  

•           emac0: ethernet@20110000 {
  

•                   compatible = "cdns,macb";
  

•                   reg = <0x0 0x20110000 0x0 0x2000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <64 65 66 67>;
  

•                   mac-address = [00 00 00 00 00 00];
  

•                   phy-mode = "sgmii";
  

•                   clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
  

•                   clock-names = "pclk", "hclk";
  

•                   status = "disabled";
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   phy0: ethernet-phy@8 {
  

•                           reg = <8>;
  

•                           ti,fifo-depth = <0x01>;
  

•                   };
  

•           };
  

•           emac1: ethernet@20112000 {
  

•                   compatible = "cdns,macb";
  

•                   reg = <0x0 0x20112000 0x0 0x2000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <70 71 72 73>;
  

•                   mac-address = [00 00 00 00 00 00];
  

•                   phy-mode = "sgmii";
  

•                   clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
  

•                   clock-names = "pclk", "hclk";
  

•                   status = "okay";
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   phy1: ethernet-phy@9 {
  

•                           reg = <9>;
  

•                           ti,fifo-depth = <0x01>;
  

•                   };
  

•           };
  

•           gpio: gpio@0x20122000 {
  

•                   compatible = "microsemi,ms-pf-mss-gpio";
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <13 14 15 16 17 18 19 20 21 22 23
  

24 25 26

...

•                                   27 28 29 30 31 32 33 34 35 36 37
  

38 39

...

•                                   40 41 42 43 44>;
  

•                   gpio-controller;
  

•                   clocks = <&clkcfg CLK_GPIO2>;
  

•                   reg = <0x00 0x20122000 0x0 0x1000>;
  

•                   reg-names = "control";
  

•                   #gpio-cells = <2>;
  

•                   status = "disabled";
  

•           };
  

•   };
  

+};

2.17.1

Apart from above, looks good to me.

Reviewed-by: Anup Patel anup.patel@wdc.com

Thank you for your review.

Regards Padmarao

Regards, Anup

On Mon, Oct 26, 2020 at 6:14 AM Bin Meng bmeng.cn@gmail.com wrote:

On Thu, Oct 22, 2020 at 3:23 PM Padmarao Begari padmarao.begari@microchip.com wrote:

...

Add device tree for Microchip PolarFire SoC Icicle Kit.

Signed-off-by: Padmarao Begari padmarao.begari@microchip.com

arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++++++++++++++++++ 2 files changed, 427 insertions(+) create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 3a6f96c67d..48c43bd122 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb

targets += $(dtb-y)

diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts b/arch/riscv/dts/microchip-icicle-kit-a000.dts new file mode 100644 index 0000000000..7110d2a78b --- /dev/null +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2020 Microchip Technology Inc */

+/dts-v1/; +#include "dt-bindings/clock/microchip,pfsoc-clock.h"

+/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000

+/ {

•   #address-cells = <2>;
  

•   #size-cells = <2>;
  

•   model = "Microchip PolarFire-SoC";
  

•   compatible = "microchip,polarfire-soc";
  

•   aliases {
  

•           serial0 = &uart0;
  

•           ethernet0 = &emac1;
  

•   };
  

•   chosen {
  

•           stdout-path = "serial0";
  

•   };
  

•   cpucomplex: cpus {
  

•           #address-cells = <1>;
  

•           #size-cells = <0>;
  

•           timebase-frequency = <RTCCLK_FREQ>;
  

•           cpu0: cpu@0 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,e51", "sifive,rocket0", "riscv";
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <128>;
  

•                   i-cache-size = <16384>;
  

•                   reg = <0>;
  

•                   riscv,isa = "rv64imac";
  

•                   status = "disabled";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu0intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu1: cpu@1 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <1>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu1intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu2: cpu@2 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <2>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu2intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu3: cpu@3 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <3>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu3intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•           cpu4: cpu@4 {
  

•                   clocks = <&clkcfg CLK_CPU>;
  

•                   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  

•                   d-cache-block-size = <64>;
  

•                   d-cache-sets = <64>;
  

•                   d-cache-size = <32768>;
  

•                   d-tlb-sets = <1>;
  

•                   d-tlb-size = <32>;
  

•                   device_type = "cpu";
  

•                   i-cache-block-size = <64>;
  

•                   i-cache-sets = <64>;
  

•                   i-cache-size = <32768>;
  

•                   i-tlb-sets = <1>;
  

•                   i-tlb-size = <32>;
  

•                   mmu-type = "riscv,sv39";
  

•                   reg = <4>;
  

•                   riscv,isa = "rv64imafdc";
  

•                   tlb-split;
  

•                   status = "okay";
  

•                   operating-points = <
  

•                           /* kHz  uV */
  

•                           600000  1100000
  

•                           300000   950000
  

•                           150000   750000
  

•                   >;
  

•                   cpu4intc: interrupt-controller {
  

•                           #interrupt-cells = <1>;
  

•                           compatible = "riscv,cpu-intc";
  

•                           interrupt-controller;
  

•                   };
  

•           };
  

•   };
  

•   refclk: refclk {
  

•           compatible = "fixed-clock";
  

•           #clock-cells = <0>;
  

•           clock-frequency = <600000000>;
  

•           clock-output-names = "msspllclk";
  

•   };
  

Any specific reason for keeping refclk outside soc node ?

...

•   ddr: memory@80000000 {
  

•           device_type = "memory";
  

•           reg = <0x0 0x80000000 0x0 0x40000000>;
  

•           clocks = <&clkcfg CLK_DDRC>;
  

•   };
  

•   soc: soc {
  

•           #address-cells = <2>;
  

•           #size-cells = <2>;
  

•           compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
  

•           ranges;
  

•           clint0: clint@2000000 {
  

•                   compatible = "riscv,clint0";
  

•                   interrupts-extended = <&cpu0intc 3 &cpu0intc 7
  

•                                           &cpu1intc 3 &cpu1intc 7
  

•                                           &cpu2intc 3 &cpu2intc 7
  

•                                           &cpu3intc 3 &cpu3intc 7
  

•                                           &cpu4intc 3 &cpu4intc 7>;
  

•                   reg = <0x0 0x2000000 0x0 0x10000>;
  

•                   reg-names = "control";
  

•                   clock-frequency = <RTCCLK_FREQ>;
  

•           };
  

•           cachecontroller: cache-controller@2010000 {
  

•                   compatible = "sifive,fu540-c000-ccache", "cache";
  

•                   cache-block-size = <64>;
  

•                   cache-level = <2>;
  

•                   cache-sets = <1024>;
  

•                   cache-size = <2097152>;
  

•                   cache-unified;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <1 2 3>;
  

•                   reg = <0x0 0x2010000 0x0 0x1000>;
  

•           };
  

•           dma: dma@3000000 {
  

•                   compatible = "sifive,fu540-c000-pdma";
  

•                   reg = <0x0 0x3000000 0x0 0x8000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <23 24 25 26 27 28 29 30>;
  

•                   #dma-cells = <1>;
  

•           };
  

•           plic: interrupt-controller@c000000 {
  

•                   #interrupt-cells = <1>;
  

•                   compatible = "sifive,plic-1.0.0";
  

•                   reg = <0x0 0xc000000 0x0 0x4000000>;
  

•                   riscv,max-priority = <7>;
  

•                   riscv,ndev = <186>;
  

•                   interrupt-controller;
  

•                   interrupts-extended = <
  

•                           &cpu0intc 11
  

•                           &cpu1intc 11 &cpu1intc 9
  

•                           &cpu2intc 11 &cpu2intc 9
  

•                           &cpu3intc 11 &cpu3intc 9
  

•                           &cpu4intc 11 &cpu4intc 9>;
  

•           };
  

•           uart0: serial@20000000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20000000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <90>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART0>;
  

•                   status = "okay";
  

•           };
  

•           clkcfg: clkcfg@20002000 {
  

•                   compatible = "microchip,pfsoc-clkcfg";
  

•                   reg = <0x0 0x20002000 0x0 0x1000>;
  

•                   reg-names = "mss_sysreg";
  

•                   clocks = <&refclk>;
  

•                   #clock-cells = <1>;
  

•                   clock-output-names = "cpu", "axi", "ahb", "envm",
  

•                                   "mac0", "mac1", "mmc", "timer",
  

•                                   "mmuart0", "mmuart1", "mmuart2",
  

•                                   "mmuart3", "mmuart4", "spi0", "spi1",
  

•                                   "i2c0", "i2c1", "can0", "can1", "usb",
  

•                                   "reserved", "rtc", "qspi", "gpio0",
  

•                                   "gpio1", "gpio2", "ddrc", "fic0",
  

•                                   "fic1", "fic2", "fic3", "athena",
  

•                                   "cfm";
  

•           };
  

•           emmc: mmc@20008000 {
  

•                   compatible = "cdns,sd4hc";
  

•                   reg = <0x0 0x20008000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <88 89>;
  

•                   pinctrl-names = "default";
  

•                   clocks = <&clkcfg CLK_MMC>;
  

•                   bus-width = <4>;
  

•                   cap-mmc-highspeed;
  

•                   mmc-ddr-3_3v;
  

•                   max-frequency = <200000000>;
  

•                   non-removable;
  

•                   no-sd;
  

•                   no-sdio;
  

•                   voltage-ranges = <3300 3300>;
  

•                   status = "okay";
  

•           };
  

•           sdcard: sd@20008000 {
  

Will there be any warning that two nodes have the same reg address?

...

•                   compatible = "cdns,sd4hc";
  

•                   reg = <0x0 0x20008000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <88>;
  

•                   pinctrl-names = "default";
  

•                   clocks = <&clkcfg CLK_MMC>;
  

•                   bus-width = <4>;
  

•                   disable-wp;
  

•                   cap-sd-highspeed;
  

•                   card-detect-delay = <200>;
  

•                   sd-uhs-sdr12;
  

•                   sd-uhs-sdr25;
  

•                   sd-uhs-sdr50;
  

•                   sd-uhs-sdr104;
  

•                   max-frequency = <200000000>;
  

•                   status = "disabled";
  

•           };
  

•           uart1: serial@20100000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20100000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <91>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART1>;
  

•                   status = "okay";
  

•           };
  

•           uart2: serial@20102000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20102000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <92>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART2>;
  

•                   status = "okay";
  

•           };
  

•           uart3: serial@20104000 {
  

•                   compatible = "ns16550a";
  

•                   reg = <0x0 0x20104000 0x0 0x400>;
  

•                   reg-io-width = <4>;
  

•                   reg-shift = <2>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <93>;
  

•                   clock-frequency = <150000000>;
  

•                   clocks = <&clkcfg CLK_MMUART3>;
  

•                   status = "okay";
  

•           };
  

•           i2c0: i2c@02010a000 {
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   compatible = "microsemi,ms-pf-mss-i2c";
  

•                   reg = <0x0 0x2010a000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <58>;
  

•                   clocks = <&clkcfg CLK_I2C0>;
  

•                   status = "disabled";
  

•           };
  

•           i2c1: i2c@02010b000 {
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   compatible = "microsemi,ms-pf-mss-i2c";
  

•                   reg = <0x0 0x2010b000 0x0 0x1000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <61>;
  

•                   clocks = <&clkcfg CLK_I2C1>;
  

•                   status = "disabled";
  

•                   pac193x@0x10 {
  

•                           compatible = "microchip,pac1934";
  

•                           reg = <0x10>;
  

•                           samp-rate = <64>;
  

•                           status = "disabled";
  

•                           ch1: channel@0 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDD";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch2: channel@1 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDDA25";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch3: channel@2 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDD25";
  

•                                   channel_enabled;
  

•                           };
  

•                           ch4: channel@3 {
  

•                                   uohms-shunt-res = <10000>;
  

•                                   rail-name = "VDDA";
  

•                                   channel_enabled;
  

•                           };
  

•                   };
  

•           };
  

•           emac0: ethernet@20110000 {
  

•                   compatible = "cdns,macb";
  

•                   reg = <0x0 0x20110000 0x0 0x2000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <64 65 66 67>;
  

•                   mac-address = [00 00 00 00 00 00];
  

•                   phy-mode = "sgmii";
  

•                   clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
  

•                   clock-names = "pclk", "hclk";
  

•                   status = "disabled";
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   phy0: ethernet-phy@8 {
  

•                           reg = <8>;
  

•                           ti,fifo-depth = <0x01>;
  

•                   };
  

•           };
  

•           emac1: ethernet@20112000 {
  

•                   compatible = "cdns,macb";
  

•                   reg = <0x0 0x20112000 0x0 0x2000>;
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <70 71 72 73>;
  

•                   mac-address = [00 00 00 00 00 00];
  

•                   phy-mode = "sgmii";
  

•                   clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
  

•                   clock-names = "pclk", "hclk";
  

•                   status = "okay";
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   phy1: ethernet-phy@9 {
  

•                           reg = <9>;
  

•                           ti,fifo-depth = <0x01>;
  

•                   };
  

•           };
  

•           gpio: gpio@0x20122000 {
  

•                   compatible = "microsemi,ms-pf-mss-gpio";
  

•                   interrupt-parent = <&plic>;
  

•                   interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
  

•                                   27 28 29 30 31 32 33 34 35 36 37 38 39
  

•                                   40 41 42 43 44>;
  

•                   gpio-controller;
  

•                   clocks = <&clkcfg CLK_GPIO2>;
  

•                   reg = <0x00 0x20122000 0x0 0x1000>;
  

•                   reg-names = "control";
  

•                   #gpio-cells = <2>;
  

•                   status = "disabled";
  

•           };
  

•   };
  

+};

Is there any Linux kernel upstream plan for the device tree?