[PATCH v6] arm: add initial support for the Phytium Pomelo Board
From: weichangzheng nicholas_zheng@outlook.com
This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng nicholas_zheng@outlook.com Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd Changes since v5: Modify the CPU node description of the DT --- arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 105 ++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 744 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + select DM + select AHCI + select SCSI_AHCI + select AHCI_PCI + select BLK + select PCI + select DM_PCI + select SCSI + select DM_SCSI + select DM_SERIAL + select DM_ETH if NET + imply CMD_PCI + help + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..b6ed8ea360 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ +/dts-v1/; + +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo", "arm,armv8"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <3>; + enable-method = "psci"; + }; + + cpu@4 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <4>; + enable-method = "psci"; + }; + + cpu@5 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <5>; + enable-method = "psci"; + }; + + cpu@6 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <6>; + enable-method = "psci"; + }; + + cpu@7 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <7>; + enable-method = "psci"; + }; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <48000000>; + clock-output-names = "sysclk_48mhz"; + }; + + uart0: serial@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clocks = <&sysclk_48mhz>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..d76a4a026e --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde lixinde@phytium.com.cn +M: weichangzheng weichangzheng@phytium.com.cn +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig +F: arch/arm/dts/phytium-pomelo.dts diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde lixinde@phytium.com.cn +# weichangzheng weichangzheng@phytium.com.cn +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..005ea5982b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..c6dbed9639 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + u8 dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16 */ + u8 mirror_type;/* 0: stardard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1:ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /*only DDR4*/ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; + + u16 trrd_smin; /*only DDR4*/ + u16 trrd_lmin; /*only DDR4*/ + u16 tccd_lmin; /*only DDR4*/ + u16 twrmin; + + u16 twtr_smin; /*only DDR4*/ + u16 twtr_lmin; /*only DDR4*/ + u16 twtrmin; /*only DDR3*/ + u16 trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + u8 f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 bc00; + u8 bc01; + u8 bc02; + u8 bc03; + u8 bc04; + + u8 bc05; + u8 f5bc5x; + u8 f5bc6x; + /******************* LRDIMM special *****************/ + u8 vrefdq_pr0; + u8 vrefdq_mdram; + u8 rtt_mdram_1866; + u8 rtt_mdram_2400; + u8 rtt_mdram_3200; + + u8 drive_dram; + u8 odt_dram_1866; + u8 odt_dram_2400; + u8 odt_dram_3200; + u8 park_dram_1866; + u8 park_dram_2400; + u8 park_dram_3200; + u8 rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 misc1_enable; + u8 misc2_enable; + u8 force_spd_enable; + u8 misc3_enable; + u8 train_debug; + u8 train_recover; + u8 rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static u8 init_dimm_param(u8 ch, struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (int ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..698d82fd8d --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[3]; + u32 equalization[3]; + u8 rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..a66ffddf09 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 core_pll; + u32 res1; + u32 lmu_pll; + u32 res2; + u32 res3; + u32 res4; + u32 res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..4fbe1e5835 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <init.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..aeb3983f01 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..a963d85fbb --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..01632021b1 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde lixinde@phytium.com.cn + * weichangzheng weichangzheng@phytium.com.cn + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR (0x80000000 + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (0x100000 + 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN 0x3c00000 +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ + "scriptaddr=0x90100000\0" \ + "kernel_addr_r=0x90100000\0" \ + "fdt_addr_r=0x95000000\0" \ + "boot_fit=no\0" \ + "fdtfile=ft-d2000.dtb\0" \ + +#endif +
On Tue, Sep 7, 2021 at 12:34 AM nicholas_zheng@outlook.com wrote:
From: weichangzheng nicholas_zheng@outlook.com
This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng nicholas_zheng@outlook.com Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd Changes since v5: Modify the CPU node description of the DT
This version is worse...
arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 105 ++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 744 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_POMELO
bool "Support Phytium Pomelo Platform"select ARM64select DMselect AHCIselect SCSI_AHCIselect AHCI_PCIselect BLKselect PCIselect DM_PCIselect SCSIselect DM_SCSIselect DM_SERIALselect DM_ETH if NETimply CMD_PCIhelpSupport for pomelo platform.It has 8GB Sdram, uart and pcie.config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..b6ed8ea360 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- dts file for Phytium Pomelo board
- Copyright (C) 2021, Phytium Ltd.
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+/dts-v1/;
+/ {
model = "Phytium Pomelo";compatible = "phytium,pomelo", "arm,armv8";
No. Again, the form is '<board compatible> <soc compatible>'.
#address-cells = <2>;#size-cells = <2>;aliases {serial0 = &uart0;};cpus {#address-cells = <0x2>;#size-cells = <0x0>;cpu0: cpu@0 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";
Is "phytium,pomelo" a CPU core implementation?
Again, "arm,armv8" is only used for CPU cores on software models (e.g Arm Fastmodels Fixed Virtual Platform).
reg = <0>;enable-method = "psci";};cpu@1 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <1>;enable-method = "psci";};cpu@2 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <2>;enable-method = "psci";};cpu@3 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <3>;enable-method = "psci";};cpu@4 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <4>;enable-method = "psci";};cpu@5 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <5>;enable-method = "psci";};cpu@6 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <6>;enable-method = "psci";};cpu@7 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <7>;enable-method = "psci";};};pcie@40000000 {compatible = "pci-host-ecam-generic";device_type = "pci";#address-cells = <3>;#size-cells = <2>;reg = <0x0 0x40000000 0x0 0x10000000>;bus-range = <0x0 0xff>;ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;};sysclk_48mhz: clk48mhz {compatible = "fixed-clock";#clock-cells = <0x0>;clock-frequency = <48000000>;clock-output-names = "sysclk_48mhz";
Wrong indentation.
};uart0: serial@28001000 {
Put memory mapped peripherals under a 'simple-bus' node.
compatible = "arm,pl011";reg = <0x0 0x28001000 0x0 0x1000>;clocks = <&sysclk_48mhz>;};+};
On 9/7/21 6:34 AM, nicholas_zheng@outlook.com wrote:
From: weichangzheng nicholas_zheng@outlook.com
This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng nicholas_zheng@outlook.com Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd Changes since v5: Modify the CPU node description of the DT
arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 105 ++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 744 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_POMELO
- bool "Support Phytium Pomelo Platform"
- select ARM64
- select DM
- select AHCI
- select SCSI_AHCI
- select AHCI_PCI
- select BLK
- select PCI
- select DM_PCI
- select SCSI
- select DM_SCSI
- select DM_SERIAL
- select DM_ETH if NET
- imply CMD_PCI
- help
Support for pomelo platform.It has 8GB Sdram, uart and pcie.- config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64
@@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..b6ed8ea360 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- dts file for Phytium Pomelo board
- Copyright (C) 2021, Phytium Ltd.
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+/dts-v1/;
+/ {
- model = "Phytium Pomelo";
- compatible = "phytium,pomelo", "arm,armv8";
- #address-cells = <2>;
- #size-cells = <2>;
- aliases {
serial0 = &uart0;- };
- cpus {
#address-cells = <0x2>;#size-cells = <0x0>;cpu0: cpu@0 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";
But Pomelo is the *board* name, right? Is there some name for the *cores*? Are those ARM Cortex cores? If yes, use their names (e.g. "arm,cortex-a72"). Otherwise, use some vendor specific name (Xiaomi, Mars?). And we don't keep an "arm,armv8" around.
reg = <0>;
Sorry, I don't think this is correct. First, there need to be two cells for the reg, as you specify this (rightly so) above. But more importantly: the "reg" cells need to match the (masked) MPIDR values of the actual cores (otherwise SMP won't work), and the "cpu@<xxx>" value has just to follow this. So it should look like:
+ cpu6: cpu@300 { + device_type = "cpu"; + compatible = "phytium,d2000"; + reg = <0x0 0x300>; + enable-method = "psci"; + };
So you can keep the numbering for the alias (cpu6:), but copy the "reg" value into the node name, removing any leading zeros (cpu@300).
enable-method = "psci";};cpu@1 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <1>;enable-method = "psci";};cpu@2 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <2>;enable-method = "psci";};cpu@3 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <3>;enable-method = "psci";};cpu@4 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <4>;enable-method = "psci";};cpu@5 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <5>;enable-method = "psci";};cpu@6 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <6>;enable-method = "psci";};cpu@7 {device_type = "cpu";compatible = "phytium,pomelo", "arm,armv8";reg = <7>;enable-method = "psci";};- };
- pcie@40000000 {
compatible = "pci-host-ecam-generic";device_type = "pci";#address-cells = <3>;#size-cells = <2>;reg = <0x0 0x40000000 0x0 0x10000000>;bus-range = <0x0 0xff>;ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;- };
- sysclk_48mhz: clk48mhz {
compatible = "fixed-clock";#clock-cells = <0x0>;clock-frequency = <48000000>;clock-output-names = "sysclk_48mhz";- };
- uart0: serial@28001000 {
compatible = "arm,pl011";reg = <0x0 0x28001000 0x0 0x1000>;clocks = <&sysclk_48mhz>;- };
+}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO
+config SYS_BOARD
- default "pomelo"
+config SYS_VENDOR
- default "phytium"
+config SYS_CONFIG_NAME
- default "pomelo"
+endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..d76a4a026e --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde lixinde@phytium.com.cn +M: weichangzheng weichangzheng@phytium.com.cn +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig +F: arch/arm/dts/phytium-pomelo.dts diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde lixinde@phytium.com.cn +# weichangzheng weichangzheng@phytium.com.cn +#
+obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o
diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..005ea5982b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- (C) Copyright 2021
- Phytium Technology Ltd <www.phytium.com>
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#ifndef _FT_POMELO_H +#define _FT_POMELO_H
+/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05
+/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8
+/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010
+/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3
+/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0
+#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC
+/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013
+/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void);
+#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..c6dbed9639 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h"
+struct ddr_spd {
- /******************* read from spd *****************/
- u8 dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */
- u8 data_width; /* 0: x4; 1: x8; 2: x16 */
- u8 mirror_type;/* 0: stardard; 1: mirror */
- u8 ecc_type; /* 0: no-ecc; 1:ecc */
- u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */
- u8 rank_num;
- u8 row_num;
- u8 col_num;
- u8 bg_num; /*only DDR4*/
- u8 bank_num;
- u16 module_manufacturer_id;
- u16 taamin;
- u16 trcdmin;
- u16 trpmin;
- u16 trasmin;
- u16 trcmin;
- u16 tfawmin;
- u16 trrd_smin; /*only DDR4*/
- u16 trrd_lmin; /*only DDR4*/
- u16 tccd_lmin; /*only DDR4*/
- u16 twrmin;
- u16 twtr_smin; /*only DDR4*/
- u16 twtr_lmin; /*only DDR4*/
- u16 twtrmin; /*only DDR3*/
- u16 trrdmin; /*only DDR3*/
- /******************* RCD control words *****************/
- u8 f0rc03; /*bit[3:2]:CS bit[1:0]:CA */
- u8 f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */
- u8 f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */
- u8 bc00;
- u8 bc01;
- u8 bc02;
- u8 bc03;
- u8 bc04;
- u8 bc05;
- u8 f5bc5x;
- u8 f5bc6x;
- /******************* LRDIMM special *****************/
- u8 vrefdq_pr0;
- u8 vrefdq_mdram;
- u8 rtt_mdram_1866;
- u8 rtt_mdram_2400;
- u8 rtt_mdram_3200;
- u8 drive_dram;
- u8 odt_dram_1866;
- u8 odt_dram_2400;
- u8 odt_dram_3200;
- u8 park_dram_1866;
- u8 park_dram_2400;
- u8 park_dram_3200;
- u8 rcd_num;
+} __attribute((aligned(4)));
+struct mcu_config {
- u32 magic;
- u32 version;
- u32 size;
- u8 rev1[4];
- u8 ch_enable;
- u8 misc1_enable;
- u8 misc2_enable;
- u8 force_spd_enable;
- u8 misc3_enable;
- u8 train_debug;
- u8 train_recover;
- u8 rev2[9];
- struct ddr_spd ddr_spd_info[2];
+} __attribute((aligned(4)));
+static void get_mcu_up_info_default(struct mcu_config *pm) +{
- pm->magic = PARAMETER_MCU_MAGIC;
- pm->version = PARAM_MCU_VERSION;
- pm->size = PARAM_MCU_SIZE;
- pm->ch_enable = PARAM_CH_ENABLE;
- pm->misc1_enable = PARAM_ECC_ENABLE;
- pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE;
- pm->misc3_enable = PARAM_MCU_MISC_ENABLE;
- pm->train_recover = 0x0;
+}
+static u8 init_dimm_param(u8 ch, struct mcu_config *pm) +{
- debug("manual config dimm info...\n");
- pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE;
- pm->ddr_spd_info[ch].data_width = DIMM_X8;
- pm->ddr_spd_info[ch].mirror_type = NO_MIRROR;
- pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE;
- pm->ddr_spd_info[ch].dram_type = DDR4_TYPE;
- pm->ddr_spd_info[ch].rank_num = 1;
- pm->ddr_spd_info[ch].row_num = 16;
- pm->ddr_spd_info[ch].col_num = 10;
- pm->ddr_spd_info[ch].bg_num = 4;
- pm->ddr_spd_info[ch].bank_num = 4;
- pm->ddr_spd_info[ch].taamin = 13750;
- pm->ddr_spd_info[ch].trcdmin = 13750;
- pm->ddr_spd_info[ch].trpmin = 13750;
- pm->ddr_spd_info[ch].trasmin = 32000;
- pm->ddr_spd_info[ch].trcmin = 45750;
- pm->ddr_spd_info[ch].tfawmin = 21000;
- pm->ddr_spd_info[ch].trrd_smin = 3000;
- pm->ddr_spd_info[ch].trrd_lmin = 4900;
- pm->ddr_spd_info[ch].tccd_lmin = 5000;
- pm->ddr_spd_info[ch].twrmin = 15000;
- pm->ddr_spd_info[ch].twtr_smin = 2500;
- pm->ddr_spd_info[ch].twtr_lmin = 7500;
- return 0;
+}
+void get_default_mcu_info(u8 *data) +{
- get_mcu_up_info_default((struct mcu_config *)data);
+}
+void fix_mcu_info(u8 *data) +{
- struct mcu_config *mcu_info = (struct mcu_config *)data;
- for (int ch = 0; ch < 2; ch++)
init_dimm_param(ch, mcu_info);+}
+void ddr_init(void) +{
- u8 buffer[0x100];
- struct arm_smccc_res res;
- get_default_mcu_info(buffer);
- fix_mcu_info(buffer);
- arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
- if (res.a0 != 0)
panic("DRAM init failed :0x%lx\n", res.a0);+} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..698d82fd8d --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h"
+struct pcu_ctr {
- u32 base_config[3];
- u32 equalization[3];
- u8 rev[80];
+} __attribute((aligned(4)));
+struct pcu_config {
- u32 magic;
- u32 version;
- u32 size;
- u8 rev1[4];
- u32 independent_tree;
- u32 base_cfg;
- u8 rev2[16];
- struct pcu_ctr ctr_cfg[2];
+} __attribute((aligned(4)));
+struct pcu_config const peu_base_info = {
- .magic = PARAMETER_PCIE_MAGIC,
- .version = 0x2,
- .size = 0x100,
- .independent_tree = CFG_INDEPENDENT_TREE,
- .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))),
- .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
- .ctr_cfg[0].equalization[0] = 0x7,
- .ctr_cfg[0].equalization[1] = 0x7,
- .ctr_cfg[0].equalization[2] = 0x7,
- .ctr_cfg[1].equalization[0] = 0x7,
- .ctr_cfg[1].equalization[1] = 0x7,
- .ctr_cfg[1].equalization[2] = 0x7,
+};
+void pcie_init(void) +{
- u8 buffer[0x100];
- struct arm_smccc_res res;
- memcpy(buffer, &peu_base_info, sizeof(peu_base_info));
- arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
- if (res.a0 != 0)
panic("PCIE init failed :0x%lx\n", res.a0);+} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..a66ffddf09 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h"
+struct pll_config {
- u32 magic;
- u32 version;
- u32 size;
- u8 rev1[4];
- u32 core_pll;
- u32 res1;
- u32 lmu_pll;
- u32 res2;
- u32 res3;
- u32 res4;
- u32 res5;
+} __attribute((aligned(4)));
+struct pll_config const pll_base_info = {
- .magic = PARAMETER_PLL_MAGIC,
- .version = 0x1,
- .size = 0x30,
- .core_pll = 2300, /*MHz*/
- .lmu_pll = 667, /*MHz*/
+};
+u32 get_reset_source(void) +{
- struct arm_smccc_res res;
- arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
- return res.a0;
+}
+void pll_init(void) +{
- u8 buffer[0x100];
- struct arm_smccc_res res;
- memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
- arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
- if (res.a0 != 0)
panic("PLL init failed :0x%lx\n", res.a0);+}
+void check_reset(void) +{
- u32 rst;
- rst = get_reset_source();
- switch (rst) {
- case CPU_RESET_POWER_ON:
pll_init();break;- case CPU_RESET_PLL:
break;- case CPU_RESET_WATCH_DOG:
break;- default:
panic("other reset source\n");- }
+} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..4fbe1e5835 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <init.h> +#include <asm/u-boot.h> +#include "cpu.h"
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- debug("Phytium ddr init\n");
- ddr_init();
- gd->mem_clk = 0;
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
- sec_init();
- debug("PBF relocate done\n");
- return 0;
+}
+int board_init(void) +{
- return 0;
+}
+void reset_cpu(void) +{
- struct arm_smccc_res res;
- debug("run in reset cpu\n");
- arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
- if (res.a0 != 0)
panic("reset cpu error, %lx\n", res.a0);+}
+int mach_cpu_init(void) +{
- check_reset();
- return 0;
+}
+int board_early_init_f(void) +{
- pcie_init();
- return 0;
+}
+static struct mm_region pomelo_mem_map[] = {
- {
.virt = 0x0UL,.phys = 0x0UL,.size = 0x80000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN |PTE_BLOCK_UXN- },
- {
.virt = 0x80000000UL,.phys = 0x80000000UL,.size = 0x7b000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_NS |PTE_BLOCK_INNER_SHARE- },
- {
0,- }
+};
+struct mm_region *mem_map = pomelo_mem_map;
+int __asm_flush_l3_dcache(void) +{
- int i, pstate;
- for (i = 0; i < HNF_COUNT; i++)
writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);- for (i = 0; i < HNF_COUNT; i++) {
do {pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));- }
- for (i = 0; i < HNF_COUNT; i++)
writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);- return 0;
+}
+int last_stage_init(void) +{
- int ret;
- /* pci e */
- pci_init();
- /* scsi scan */
- ret = scsi_scan(true);
- if (ret) {
printf("scsi scan failed\n");return CMD_RET_FAILURE;- }
- return ret;
+} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..aeb3983f01 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h"
+struct common_config {
- u32 magic;
- u32 version;
- u32 size;
- u8 rev1[4];
- u64 core_bit_map;
+} __attribute((aligned(4)));
+struct common_config const common_base_info = {
- .magic = PARAMETER_COMMON_MAGIC,
- .version = 0x1,
- .core_bit_map = 0x3333,
+};
+void sec_init(void) +{
- u8 buffer[0x100];
- struct arm_smccc_res res;
- memcpy(buffer, &common_base_info, sizeof(common_base_info));
- arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
- if (res.a0 != 0)
panic("SEC init failed :0x%lx\n", res.a0);+} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..a963d85fbb --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..01632021b1 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2021
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__
+/* SDRAM Bank #1 start address */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR (0x80000000 + 0x10000000)
+/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (0x100000 + 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000)
+/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1
+/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN 0x3c00000 +#define CONFIG_BOARD_EARLY_INIT_F
+#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \
- func(SCSI, scsi, 0) \
+#include <config_distro_bootcmd.h> +#endif
+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
- "image=Image\0" \
- BOOTENV \
- "scriptaddr=0x90100000\0" \
- "kernel_addr_r=0x90100000\0" \
Please align this address to 2MB, as this is what newer kernels expect. So it should be 0x90200000.
- "fdt_addr_r=0x95000000\0" \
- "boot_fit=no\0" \
- "fdtfile=ft-d2000.dtb\0" \
Shouldn't this match the .dts filename used above (phytium,pomelo.dtb)?
Cheers, Andre.
+#endif
participants (3)
-
Andre Przywara -
nicholas_zheng＠outlook.com -
Rob Herring