This adds support for the StarFive JH7110 SoC which also feature this SiFive cache controller.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/cache/cache-sifive-ccache.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c index c8766f6242..c1bef0b4d3 100644 --- a/drivers/cache/cache-sifive-ccache.c +++ b/drivers/cache/cache-sifive-ccache.c @@ -62,6 +62,7 @@ static int sifive_ccache_probe(struct udevice *dev) static const struct udevice_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, + { .compatible = "starfive,jh7110-ccache" }, {} };

Add a DM reset driver for StarFive JH7110 SoC.

Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/reset/Kconfig | 16 ++++ drivers/reset/Makefile | 1 + drivers/reset/reset-jh7110.c | 158 +++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/reset/reset-jh7110.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 4cb0ba0850..1ca701bb92 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -172,6 +172,22 @@ config RESET_SIFIVE different hw blocks like DDR, gemgxl. With this driver we leverage U-Boot's reset framework to reset these hardware blocks.

+config RESET_JH7110 + bool "Reset driver for StarFive JH7110 SoC" + depends on DM_RESET && STARFIVE_JH7110 + default y + help + Support for reset controller on StarFive + JH7110 SoCs. + +config SPL_RESET_JH7110 + bool "SPL Reset driver for StarFive JH7110 SoC" + depends on SPL && STARFIVE_JH7110 + default y + help + Support for reset controller on StarFive + JH7110 SoCs in SPL. + config RESET_SYSCON bool "Enable generic syscon reset driver support" depends on DM_RESET diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0620b62809..05967b030a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o +obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c new file mode 100644 index 0000000000..6887b794d6 --- /dev/null +++ b/drivers/reset/reset-jh7110.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <dm.h> +#include <dm/ofnode.h> +#include <dt-bindings/reset/starfive-jh7110.h> +#include <errno.h> +#include <linux/iopoll.h> +#include <reset-uclass.h> + +struct jh7110_reset_priv { + void __iomem *reg; + u32 assert; + u32 status; + u32 resets; +}; + +struct reset_info { + const char *compat; + const u32 nr_resets; + const u32 assert_offset; + const u32 status_offset; +}; + +static const struct reset_info jh7110_rst_info[] = { + { + .compat = "starfive,jh7110-syscrg", + .nr_resets = JH7110_SYSRST_END, + .assert_offset = 0x2F8, + .status_offset = 0x308, + }, + { + .compat = "starfive,jh7110-aoncrg", + .nr_resets = JH7110_AONRST_END, + .assert_offset = 0x38, + .status_offset = 0x3C, + }, + { + .compat = "starfive,jh7110-stgcrg", + .nr_resets = JH7110_STGRST_END, + .assert_offset = 0x74, + .status_offset = 0x78, + } +}; + +static const struct reset_info *jh7110_reset_get_cfg(const char *compat) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++) + if (!strcmp(compat, jh7110_rst_info[i].compat)) + return &jh7110_rst_info[i]; + + return NULL; +} + +static int jh7110_reset_trigger(struct jh7110_reset_priv *priv, + unsigned long id, bool assert) +{ + ulong group; + u32 mask, value, done = 0; + ulong addr; + + group = id / 32; + mask = BIT(id % 32); + + if (!assert) + done ^= mask; + + addr = (ulong)priv->reg + priv->assert + group * sizeof(u32); + value = readl((ulong *)addr); + + if (assert) + value |= mask; + else + value &= ~mask; + + writel(value, (ulong *)addr); + addr = (ulong)priv->reg + priv->status + group * sizeof(u32); + + return readl_poll_timeout((ulong *)addr, value, + (value & mask) == done, 1000); +} + +static int jh7110_reset_assert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, true); + + return 0; +} + +static int jh7110_reset_deassert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, false); + + return 0; +} + +static int jh7110_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int jh7110_reset_request(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + if (rst->id >= priv->resets) + return -EINVAL; + + return 0; +} + +static int jh7110_reset_probe(struct udevice *dev) +{ + struct jh7110_reset_priv *priv = dev_get_priv(dev); + const struct reset_info *cfg; + const char *compat; + + compat = ofnode_get_property(dev_ofnode(dev), "compatible", NULL); + if (!compat) + return -EINVAL; + + cfg = jh7110_reset_get_cfg(compat); + if (!cfg) + return -EINVAL; + + priv->assert = cfg->assert_offset; + priv->status = cfg->status_offset; + priv->resets = cfg->nr_resets; + priv->reg = (void __iomem *)dev_read_addr_index(dev, 0); + + return 0; +} + +const struct reset_ops jh7110_reset_reset_ops = { + .rfree = jh7110_reset_free, + .request = jh7110_reset_request, + .rst_assert = jh7110_reset_assert, + .rst_deassert = jh7110_reset_deassert, +}; + +U_BOOT_DRIVER(jh7110_reset) = { + .name = "jh7110_reset", + .id = UCLASS_RESET, + .ops = &jh7110_reset_reset_ops, + .probe = jh7110_reset_probe, + .priv_auto = sizeof(struct jh7110_reset_priv), +};

Add a DM clock driver for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 ++++++++++++++ drivers/clk/starfive/clk-jh7110.c | 651 ++++++++++++++++++++++++++ drivers/clk/starfive/clk.h | 42 ++ 7 files changed, 1076 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c..4d60c84aad 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c274cda77c..66f5860356 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o

obj-y += analogbits/ obj-y += imx/ +obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 0000000000..e4bf2a5c5e --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on STARFIVE_JH7110 && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM support for clock driver in JH7110. + +config CLK_JH7110 + bool "StarFive JH7110 clock support" + depends on CLK && CLK_CCF && STARFIVE_JH7110 + help + This enables support clock driver for StarFive JH7110 SoC platform. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 0000000000..ec0d157094 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk-jh7110.o +obj-y += clk-jh7110-pll.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c new file mode 100644 index 0000000000..8be9500b62 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm/device.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include "clk.h" + +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" + +#define PLL0_DACPD_MASK BIT(24) +#define PLL0_DSMPD_MASK BIT(25) +#define PLL0_FBDIV_MASK GENMASK(11, 0) +#define PLL0_FRAC_MASK GENMASK(23, 0) +#define PLL0_PD_MASK BIT(27) +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL1_DACPD_MASK BIT(15) +#define PLL1_DSMPD_MASK BIT(16) +#define PLL1_FBDIV_MASK GENMASK(28, 17) +#define PLL1_FRAC_MASK GENMASK(23, 0) +#define PLL1_PD_MASK BIT(27) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL2_DACPD_MASK BIT(15) +#define PLL2_DSMPD_MASK BIT(16) +#define PLL2_FBDIV_MASK GENMASK(28, 17) +#define PLL2_FRAC_MASK GENMASK(23, 0) +#define PLL2_PD_MASK BIT(27) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) +#define PLL2_PREDIV_MASK GENMASK(5, 0) + +#define PLL0_DACPD_OFFSET 0x18 +#define PLL0_DSMPD_OFFSET 0x18 +#define PLL0_FBDIV_OFFSET 0x1C +#define PLL0_FRAC_OFFSET 0x20 +#define PLL0_PD_OFFSET 0x20 +#define PLL0_POSTDIV1_OFFSET 0x20 +#define PLL0_PREDIV_OFFSET 0x24 +#define PLL1_DACPD_OFFSET 0x24 +#define PLL1_DSMPD_OFFSET 0x24 +#define PLL1_FBDIV_OFFSET 0x24 +#define PLL1_FRAC_OFFSET 0x28 +#define PLL1_PD_OFFSET 0x28 +#define PLL1_POSTDIV1_OFFSET 0x28 +#define PLL1_PREDIV_OFFSET 0x2c +#define PLL2_DACPD_OFFSET 0x2c +#define PLL2_DSMPD_OFFSET 0x2c +#define PLL2_FBDIV_OFFSET 0x2c +#define PLL2_FRAC_OFFSET 0x30 +#define PLL2_PD_OFFSET 0x30 +#define PLL2_POSTDIV1_OFFSET 0x30 +#define PLL2_PREDIV_OFFSET 0x34 + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +#define CLK_DDR_BUS_MASK GENMASK(29, 24) +#define CLK_DDR_BUS_OFFSET 0xAC +#define CLK_DDR_BUS_OSC_DIV2 0 +#define CLK_DDR_BUS_PLL1_DIV2 1 +#define CLK_DDR_BUS_PLL1_DIV4 2 +#define CLK_DDR_BUS_PLL1_DIV8 3 + +struct clk_jh7110_pllx { + struct clk clk; + void __iomem *base; + void __iomem *sysreg; + enum starfive_pll_type type; + const struct starfive_pllx_rate *rate_table; + int rate_count; +}; + +#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask))) + +#define GET_PLL(index, type) \ + getbits_le32((ulong)pll->base + index##_##type##_OFFSET, index##_##type##_MASK) + +#define SET_PLL(index, type, val) \ + clrsetbits_le32((ulong)pll->base + index##_##type##_OFFSET, \ + index##_##type##_MASK, \ + ((val) << __ffs(index##_##type##_MASK)) & index##_##type##_MASK) + +#define CLK_DDR_REG_SET(type, val) \ + clrsetbits_le32((ulong)pll->sysreg + CLK_DDR_##type##_OFFSET, \ + CLK_DDR_##type##_MASK, \ + ((val) << __ffs(CLK_DDR_##type##_MASK)) & CLK_DDR_##type##_MASK) + +#define PLLX_RATE(_rate, _pd, _fd, _pd1, _da, _ds) \ + { \ + .rate = (_rate), \ + .prediv = (_pd), \ + .fbdiv = (_fd), \ + .postdiv1 = (_pd1), \ + .dacpd = (_da), \ + .dsmpd = (_ds), \ + } + +#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk) + +static const struct starfive_pllx_rate jh7110_pll0_tbl[] = { + PLLX_RATE(375000000UL, 8, 125, 1, 1, 1), + PLLX_RATE(500000000UL, 6, 125, 1, 1, 1), + PLLX_RATE(625000000UL, 24, 625, 1, 1, 1), + PLLX_RATE(750000000UL, 4, 125, 1, 1, 1), + PLLX_RATE(875000000UL, 24, 875, 1, 1, 1), + PLLX_RATE(1000000000UL, 3, 125, 1, 1, 1), + PLLX_RATE(1250000000UL, 12, 625, 1, 1, 1), + PLLX_RATE(1375000000UL, 24, 1375, 1, 1, 1), + PLLX_RATE(1500000000UL, 2, 125, 1, 1, 1), + PLLX_RATE(1625000000UL, 24, 1625, 1, 1, 1), + PLLX_RATE(1750000000UL, 12, 875, 1, 1, 1), + PLLX_RATE(1800000000UL, 3, 225, 1, 1, 1), +}; + +static const struct starfive_pllx_rate jh7110_pll1_tbl[] = { + PLLX_RATE(1066000000UL, 12, 533, 1, 1, 1), + PLLX_RATE(1200000000UL, 1, 50, 1, 1, 1), + PLLX_RATE(1400000000UL, 6, 350, 1, 1, 1), + PLLX_RATE(1600000000UL, 3, 200, 1, 1, 1), +}; + +static const struct starfive_pllx_rate jh7110_pll2_tbl[] = { + PLLX_RATE(1228800000UL, 15, 768, 1, 1, 1), + PLLX_RATE(1188000000UL, 2, 99, 1, 1, 1), +}; + +struct starfive_pllx_clk starfive_jh7110_pll0 __initdata = { + .type = PLL0, + .rate_table = jh7110_pll0_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll0_tbl), +}; +EXPORT_SYMBOL_GPL(starfive_jh7110_pll0); + +struct starfive_pllx_clk starfive_jh7110_pll1 __initdata = { + .type = PLL1, + .rate_table = jh7110_pll1_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll1_tbl), +}; +EXPORT_SYMBOL_GPL(starfive_jh7110_pll1); + +struct starfive_pllx_clk starfive_jh7110_pll2 __initdata = { + .type = PLL2, + .rate_table = jh7110_pll2_tbl, + .rate_count = ARRAY_SIZE(jh7110_pll2_tbl), +}; +EXPORT_SYMBOL_GPL(starfive_jh7110_pll2); + +static const struct starfive_pllx_rate *jh7110_get_pll_settings + (struct clk_jh7110_pllx *pll, unsigned long rate) +{ + const struct starfive_pllx_rate *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) + if (rate == rate_table[i].rate) + return &rate_table[i]; + + return NULL; +} + +static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, + const struct starfive_pllx_rate *rate) +{ + switch (pll->type) { + case PLL0: + SET_PLL(PLL0, PD, PLL_PD_OFF); + SET_PLL(PLL0, DACPD, rate->dacpd); + SET_PLL(PLL0, DSMPD, rate->dsmpd); + SET_PLL(PLL0, PREDIV, rate->prediv); + SET_PLL(PLL0, FBDIV, rate->fbdiv); + SET_PLL(PLL0, POSTDIV1, rate->postdiv1 >> 1); + SET_PLL(PLL0, PD, PLL_PD_ON); + break; + + case PLL1: + CLK_DDR_REG_SET(BUS, CLK_DDR_BUS_OSC_DIV2); + SET_PLL(PLL1, PD, PLL_PD_OFF); + SET_PLL(PLL1, DACPD, rate->dacpd); + SET_PLL(PLL1, DSMPD, rate->dsmpd); + SET_PLL(PLL1, PREDIV, rate->prediv); + SET_PLL(PLL1, FBDIV, rate->fbdiv); + SET_PLL(PLL1, POSTDIV1, rate->postdiv1 >> 1); + SET_PLL(PLL1, PD, PLL_PD_ON); + udelay(100); + CLK_DDR_REG_SET(BUS, CLK_DDR_BUS_PLL1_DIV2); + break; + + case PLL2: + SET_PLL(PLL2, PD, PLL_PD_OFF); + SET_PLL(PLL2, DACPD, rate->dacpd); + SET_PLL(PLL2, DSMPD, rate->dsmpd); + SET_PLL(PLL2, PREDIV, rate->prediv); + SET_PLL(PLL2, FBDIV, rate->fbdiv); + SET_PLL(PLL2, POSTDIV1, rate->postdiv1 >> 1); + SET_PLL(PLL2, PD, PLL_PD_ON); + break; + + default: + break; + } +} + +static ulong jh7110_pllx_recalc_rate(struct clk *clk) +{ + struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev)); + u64 refclk = clk_get_parent_rate(clk); + u32 dacpd, dsmpd; + u32 prediv, fbdiv, postdiv1; + u64 frac; + + switch (pll->type) { + case PLL0: + dacpd = GET_PLL(PLL0, DACPD); + dsmpd = GET_PLL(PLL0, DSMPD); + prediv = GET_PLL(PLL0, PREDIV); + fbdiv = GET_PLL(PLL0, FBDIV); + postdiv1 = 1 << GET_PLL(PLL0, POSTDIV1); + frac = (u64)GET_PLL(PLL0, FRAC); + break; + + case PLL1: + dacpd = GET_PLL(PLL1, DACPD); + dsmpd = GET_PLL(PLL1, DSMPD); + prediv = GET_PLL(PLL1, PREDIV); + fbdiv = GET_PLL(PLL1, FBDIV); + postdiv1 = 1 << GET_PLL(PLL1, POSTDIV1); + frac = (u64)GET_PLL(PLL1, FRAC); + break; + + case PLL2: + dacpd = GET_PLL(PLL2, DACPD); + dsmpd = GET_PLL(PLL2, DSMPD); + prediv = GET_PLL(PLL2, PREDIV); + fbdiv = GET_PLL(PLL2, FBDIV); + postdiv1 = 1 << GET_PLL(PLL2, POSTDIV1); + frac = (u64)GET_PLL(PLL2, FRAC); + break; + + default: + debug("Unsupported pll type %d.\n", pll->type); + return 0; + } + + /* Integer Mode or Fraction Mode */ + if (dacpd == 1 && dsmpd == 1) + frac = 0; + else if (dacpd == 0 && dsmpd == 0) + do_div(frac, 1 << 24); + else + return -EINVAL; + + refclk *= (fbdiv + frac); + do_div(refclk, prediv * postdiv1); + + return refclk; +} + +static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate) +{ + struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev)); + const struct starfive_pllx_rate *rate; + + switch (pll->type) { + case PLL0: + case PLL1: + case PLL2: + break; + + default: + debug("%s: Unknown pll clk type\n", __func__); + return -EINVAL; + }; + + rate = jh7110_get_pll_settings(pll, drate); + if (!rate) + return -EINVAL; + + jh7110_pll_set_rate(pll, rate); + + return jh7110_pllx_recalc_rate(clk); +} + +static void jh7110_pllx_init_rate(struct clk_jh7110_pllx *pll, ulong drate) +{ + const struct starfive_pllx_rate *rate; + + rate = jh7110_get_pll_settings(pll, drate); + if (!rate) + return; + + jh7110_pll_set_rate(pll, rate); +} + +static const struct clk_ops clk_jh7110_ops = { + .set_rate = jh7110_pllx_set_rate, + .get_rate = jh7110_pllx_recalc_rate, +}; + +struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, + void __iomem *base, void __iomem *sysreg, + const struct starfive_pllx_clk *pll_clk) +{ + struct clk_jh7110_pllx *pll; + struct clk *clk; + char *type_name; + int ret; + + switch (pll_clk->type) { + case PLL0: + case PLL1: + case PLL2: + type_name = UBOOT_DM_CLK_JH7110_PLLX; + break; + + default: + return ERR_PTR(-EINVAL); + }; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->sysreg = sysreg; + pll->type = pll_clk->type; + pll->rate_table = pll_clk->rate_table; + pll->rate_count = pll_clk->rate_count; + + clk = &pll->clk; + ret = clk_register(clk, type_name, name, parent_name); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0) + jh7110_pllx_init_rate(pll, 1250000000); + + if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2) + jh7110_pllx_init_rate(pll, 1188000000); + + return clk; +} + +U_BOOT_DRIVER(jh7110_clk_pllx) = { + .name = UBOOT_DM_CLK_JH7110_PLLX, + .id = UCLASS_CLK, + .ops = &clk_jh7110_ops, +}; diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c new file mode 100644 index 0000000000..223adcc904 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110.c @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang yanhong.wang@starfivetech.com + */ + +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dt-bindings/clock/starfive-jh7110.h> +#include <log.h> +#include <linux/clk-provider.h> + +#include "clk.h" + +#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */ +#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */ +#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */ +#define STARFIVE_CLK_DIV_SHIFT 0 /* [23:0] */ + +#define OFFSET(id) ((id) * 4) +#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4) +#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4) + +struct jh7110_clk_config { + int (*init)(struct udevice *dev); +}; + +struct jh7110_clk_priv { + void __iomem *reg; + const struct jh7110_clk_config *config; +}; + +static const char *cpu_root_sels[2] = { + [0] = "osc", + [1] = "pll0_out", +}; + +static const char *perh_root_sels[2] = { + [0] = "pll0_out", + [1] = "pll2_out", +}; + +static const char *bus_root_sels[2] = { + [0] = "osc", + [1] = "pll2_out", +}; + +static const char *qspi_ref_sels[2] = { + [0] = "osc", + [1] = "qspi_ref_src", +}; + +static const char *gmac1_tx_sels[2] = { + [0] = "gmac1_gtxclk", + [1] = "gmac1_rmii_rtx", +}; + +static const char *gmac0_tx_sels[2] = { + [0] = "gmac0_gtxclk", + [1] = "gmac0_rmii_rtx", +}; + +static ulong starfive_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_get_rate(c); +} + +static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_set_rate(c, rate); +} + +static int __starfive_clk_enable(struct clk *clk, bool enable) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + if (enable) + ret = clk_enable(c); + else + ret = clk_disable(c); + + return ret; +} + +static int starfive_clk_disable(struct clk *clk) +{ + return __starfive_clk_enable(clk, 0); +} + +static int starfive_clk_enable(struct clk *clk) +{ + return __starfive_clk_enable(clk, 1); +} + +static int starfive_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *cp; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + ret = clk_get_by_id(parent->id, &cp); + if (ret) + return ret; + + ret = clk_set_parent(c, cp); + c->dev->parent = cp->dev; + + return ret; +} + +static const struct clk_ops starfive_clk_ops = { + .set_rate = starfive_clk_set_rate, + .get_rate = starfive_clk_get_rate, + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .set_parent = starfive_clk_set_parent, +}; + +static struct clk *starfive_clk_mux(void __iomem *reg, + const char *name, + unsigned int offset, + u8 width, + const char * const *parent_names, + u8 num_parents) +{ + return clk_register_mux(NULL, name, parent_names, num_parents, 0, + reg + offset, STARFIVE_CLK_MUX_SHIFT, + width, 0); +} + +static struct clk *starfive_clk_gate(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg + offset, + STARFIVE_CLK_ENABLE_SHIFT, 0, NULL); +} + +static struct clk *starfive_clk_fix_factor(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent_name, + 0, mult, div); +} + +static struct clk *starfive_clk_divider(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset, + u8 width) +{ + return clk_register_divider(NULL, name, parent_name, 0, reg + offset, + 0, width, CLK_DIVIDER_ONE_BASED); +} + +static struct clk *starfive_clk_composite(void __iomem *reg, + const char *name, + const char * const *parent_names, + unsigned int num_parents, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + int mask_arry[4] = {0x1, 0x3, 0x7, 0xF}; + int mask; + + if (mux_width) { + if (mux_width > 4) + goto fail; + else + mask = mask_arry[mux_width - 1]; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg + offset; + mux->mask = mask; + mux->shift = STARFIVE_CLK_MUX_SHIFT; + mux->num_parents = num_parents; + mux->flags = 0; + mux->parent_names = parent_names; + } + + if (gate_width) { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + + if (!gate) + goto fail; + + gate->reg = reg + offset; + gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT; + gate->flags = 0; + } + + if (div_width) { + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg + offset; + + if (offset == OFFSET(JH7110_SYSCLK_UART3_CORE) || + offset == OFFSET(JH7110_SYSCLK_UART4_CORE) || + offset == OFFSET(JH7110_SYSCLK_UART5_CORE)) { + div->shift = 8; + div->width = 8; + } else { + div->shift = STARFIVE_CLK_DIV_SHIFT; + div->width = div_width; + } + div->flags = CLK_DIVIDER_ONE_BASED; + div->table = NULL; + } + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + &gate->clk, &clk_gate_ops, 0); + + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} + +static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg, + const char *name, + const char *parent_names, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + const char * const *parents; + + parents = &parent_names; + + return starfive_clk_composite(reg, name, parents, 1, offset, + mux_width, gate_width, div_width); +} + +static struct clk *starfive_clk_gate_divider(void __iomem *reg, + const char *name, + const char *parent, + unsigned int offset, + unsigned int width) +{ + const char * const *parent_names; + + parent_names = &parent; + + return starfive_clk_composite(reg, name, parent_names, 1, + offset, 0, 1, width); +} + +static int jh7110_syscrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + fdt_addr_t addr; + int ret; + + ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args); + if (ret) + return ret; + + addr = ofnode_get_addr(args.node); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + clk_dm(JH7110_SYSCLK_PLL0_OUT, + starfive_jh7110_pll("pll0_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll0)); + clk_dm(JH7110_SYSCLK_PLL1_OUT, + starfive_jh7110_pll("pll1_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll1)); + clk_dm(JH7110_SYSCLK_PLL2_OUT, + starfive_jh7110_pll("pll2_out", "osc", (void __iomem *)addr, + priv->reg, &starfive_jh7110_pll2)); + clk_dm(JH7110_SYSCLK_CPU_ROOT, + starfive_clk_mux(priv->reg, "cpu_root", + OFFSET(JH7110_SYSCLK_CPU_ROOT), 1, + cpu_root_sels, ARRAY_SIZE(cpu_root_sels))); + clk_dm(JH7110_SYSCLK_CPU_CORE, + starfive_clk_divider(priv->reg, + "cpu_core", "cpu_root", + OFFSET(JH7110_SYSCLK_CPU_CORE), 3)); + clk_dm(JH7110_SYSCLK_CPU_BUS, + starfive_clk_divider(priv->reg, + "cpu_bus", "cpu_core", + OFFSET(JH7110_SYSCLK_CPU_BUS), 2)); + clk_dm(JH7110_SYSCLK_GMACUSB_ROOT, + starfive_clk_fix_factor(priv->reg, + "gmacusb_root", "pll0_out", 1, 1)); + clk_dm(JH7110_SYSCLK_PERH_ROOT, + starfive_clk_composite(priv->reg, + "perh_root", + perh_root_sels, ARRAY_SIZE(perh_root_sels), + OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2)); + clk_dm(JH7110_SYSCLK_BUS_ROOT, + starfive_clk_mux(priv->reg, "bus_root", + OFFSET(JH7110_SYSCLK_BUS_ROOT), 1, + bus_root_sels, ARRAY_SIZE(bus_root_sels))); + clk_dm(JH7110_SYSCLK_AXI_CFG0, + starfive_clk_divider(priv->reg, + "axi_cfg0", "bus_root", + OFFSET(JH7110_SYSCLK_AXI_CFG0), 2)); + clk_dm(JH7110_SYSCLK_STG_AXIAHB, + starfive_clk_divider(priv->reg, + "stg_axiahb", "axi_cfg0", + OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2)); + clk_dm(JH7110_SYSCLK_AHB0, + starfive_clk_gate(priv->reg, + "ahb0", "stg_axiahb", + OFFSET(JH7110_SYSCLK_AHB0))); + clk_dm(JH7110_SYSCLK_AHB1, + starfive_clk_gate(priv->reg, + "ahb1", "stg_axiahb", + OFFSET(JH7110_SYSCLK_AHB1))); + clk_dm(JH7110_SYSCLK_APB_BUS_FUNC, + starfive_clk_divider(priv->reg, + "apb_bus_func", "stg_axiahb", + OFFSET(JH7110_SYSCLK_APB_BUS_FUNC), 4)); + clk_dm(JH7110_SYSCLK_PCLK2_MUX_FUNC, + starfive_clk_fix_factor(priv->reg, + "pclk2_mux_func", "apb_bus_func", 1, 1)); + clk_dm(JH7110_SYSCLK_PCLK2_MUX, + starfive_clk_fix_factor(priv->reg, + "pclk2_mux", "pclk2_mux_func", 1, 1)); + clk_dm(JH7110_SYSCLK_APB_BUS, + starfive_clk_fix_factor(priv->reg, + "apb_bus", "pclk2_mux", 1, 1)); + clk_dm(JH7110_SYSCLK_APB0, + starfive_clk_gate(priv->reg, + "apb0", "apb_bus", + OFFSET(JH7110_SYSCLK_APB0))); + clk_dm(JH7110_SYSCLK_APB12, + starfive_clk_fix_factor(priv->reg, + "apb12", "apb_bus", 1, 1)); + clk_dm(JH7110_SYSCLK_AON_APB, + starfive_clk_fix_factor(priv->reg, + "aon_apb", "apb_bus_func", 1, 1)); + clk_dm(JH7110_SYSCLK_QSPI_AHB, + starfive_clk_gate(priv->reg, + "qspi_ahb", "ahb1", + OFFSET(JH7110_SYSCLK_QSPI_AHB))); + clk_dm(JH7110_SYSCLK_QSPI_APB, + starfive_clk_gate(priv->reg, + "qspi_apb", "apb12", + OFFSET(JH7110_SYSCLK_QSPI_APB))); + clk_dm(JH7110_SYSCLK_QSPI_REF_SRC, + starfive_clk_divider(priv->reg, + "qspi_ref_src", "gmacusb_root", + OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5)); + clk_dm(JH7110_SYSCLK_QSPI_REF, + starfive_clk_composite(priv->reg, + "qspi_ref", + qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels), + OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0)); + clk_dm(JH7110_SYSCLK_SDIO0_AHB, + starfive_clk_gate(priv->reg, + "sdio0_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_SDIO0_AHB))); + clk_dm(JH7110_SYSCLK_SDIO1_AHB, + starfive_clk_gate(priv->reg, + "sdio1_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_SDIO1_AHB))); + clk_dm(JH7110_SYSCLK_SDIO0_SDCARD, + starfive_clk_fix_parent_composite(priv->reg, + "sdio0_sdcard", "axi_cfg0", + OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4)); + clk_dm(JH7110_SYSCLK_SDIO1_SDCARD, + starfive_clk_fix_parent_composite(priv->reg, + "sdio1_sdcard", "axi_cfg0", + OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4)); + clk_dm(JH7110_SYSCLK_USB_125M, + starfive_clk_divider(priv->reg, + "usb_125m", "gmacusb_root", + OFFSET(JH7110_SYSCLK_USB_125M), 4)); + clk_dm(JH7110_SYSCLK_GMAC1_AHB, + starfive_clk_gate(priv->reg, + "gmac1_ahb", "ahb0", + OFFSET(JH7110_SYSCLK_GMAC1_AHB))); + clk_dm(JH7110_SYSCLK_GMAC1_AXI, + starfive_clk_gate(priv->reg, + "gmac1_axi", "stg_axiahb", + OFFSET(JH7110_SYSCLK_GMAC1_AXI))); + clk_dm(JH7110_SYSCLK_GMAC_SRC, + starfive_clk_divider(priv->reg, + "gmac_src", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC_SRC), 3)); + clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK, + starfive_clk_divider(priv->reg, + "gmac1_gtxclk", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4)); + clk_dm(JH7110_SYSCLK_GMAC1_GTXC, + starfive_clk_gate(priv->reg, + "gmac1_gtxc", "gmac1_gtxclk", + OFFSET(JH7110_SYSCLK_GMAC1_GTXC))); + clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX, + starfive_clk_divider(priv->reg, + "gmac1_rmii_rtx", "gmac1_rmii_refin", + OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5)); + clk_dm(JH7110_SYSCLK_GMAC1_PTP, + starfive_clk_gate_divider(priv->reg, + "gmac1_ptp", "gmac_src", + OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5)); + clk_dm(JH7110_SYSCLK_GMAC1_TX, + starfive_clk_composite(priv->reg, + "gmac1_tx", + gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels), + OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0)); + clk_dm(JH7110_SYSCLK_AON_AHB, + starfive_clk_fix_factor(priv->reg, "aon_ahb", + "stg_axiahb", 1, 1)); + clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK, + starfive_clk_gate_divider(priv->reg, + "gmac0_gtxclk", "gmacusb_root", + OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4)); + clk_dm(JH7110_SYSCLK_GMAC0_PTP, + starfive_clk_gate_divider(priv->reg, + "gmac0_ptp", "gmac_src", + OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5)); + clk_dm(JH7110_SYSCLK_GMAC0_GTXC, + starfive_clk_gate(priv->reg, + "gmac0_gtxc", "gmac0_gtxclk", + OFFSET(JH7110_SYSCLK_GMAC0_GTXC))); + clk_dm(JH7110_SYSCLK_UART0_APB, + starfive_clk_gate(priv->reg, + "uart0_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART0_APB))); + clk_dm(JH7110_SYSCLK_UART0_CORE, + starfive_clk_gate(priv->reg, + "uart0_core", "osc", + OFFSET(JH7110_SYSCLK_UART0_CORE))); + clk_dm(JH7110_SYSCLK_UART1_APB, + starfive_clk_gate(priv->reg, + "uart1_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART1_APB))); + clk_dm(JH7110_SYSCLK_UART1_CORE, + starfive_clk_gate(priv->reg, + "uart1_core", "osc", + OFFSET(JH7110_SYSCLK_UART1_CORE))); + clk_dm(JH7110_SYSCLK_UART2_APB, + starfive_clk_gate(priv->reg, + "uart2_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART2_APB))); + clk_dm(JH7110_SYSCLK_UART2_CORE, + starfive_clk_gate(priv->reg, + "uart2_core", "osc", + OFFSET(JH7110_SYSCLK_UART2_CORE))); + clk_dm(JH7110_SYSCLK_UART3_APB, + starfive_clk_gate(priv->reg, + "uart3_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART3_APB))); + clk_dm(JH7110_SYSCLK_UART3_CORE, + starfive_clk_gate_divider(priv->reg, + "uart3_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART3_CORE), 8)); + clk_dm(JH7110_SYSCLK_UART4_APB, + starfive_clk_gate(priv->reg, + "uart4_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART4_APB))); + clk_dm(JH7110_SYSCLK_UART4_CORE, + starfive_clk_gate_divider(priv->reg, + "uart4_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART4_CORE), 8)); + clk_dm(JH7110_SYSCLK_UART5_APB, + starfive_clk_gate(priv->reg, + "uart5_apb", "apb0", + OFFSET(JH7110_SYSCLK_UART5_APB))); + clk_dm(JH7110_SYSCLK_UART5_CORE, + starfive_clk_gate_divider(priv->reg, + "uart5_core", "perh_root", + OFFSET(JH7110_SYSCLK_UART5_CORE), 8)); + clk_dm(JH7110_SYSCLK_I2C5_APB, + starfive_clk_gate(priv->reg, + "i2c5_apb", "apb12", + OFFSET(JH7110_SYSCLK_I2C5_APB))); + clk_dm(JH7110_SYSCLK_I2C5_CORE, + starfive_clk_fix_factor(priv->reg, + "i2c5_core", "i2c5_apb", 1, 1)); + + return 0; +} + +static int jh7110_aoncrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_AONCLK_GMAC0_AHB, + starfive_clk_gate(priv->reg, + "gmac0_ahb", "aon_ahb", + AONOFFSET(JH7110_AONCLK_GMAC0_AHB))); + clk_dm(JH7110_AONCLK_GMAC0_AXI, + starfive_clk_gate(priv->reg, + "gmac0_axi", "aon_ahb", + AONOFFSET(JH7110_AONCLK_GMAC0_AXI))); + clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX, + starfive_clk_divider(priv->reg, + "gmac0_rmii_rtx", "gmac0_rmii_refin", + AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5)); + clk_dm(JH7110_AONCLK_GMAC0_TX, + starfive_clk_composite(priv->reg, + "gmac0_tx", gmac0_tx_sels, + ARRAY_SIZE(gmac0_tx_sels), + AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0)); + clk_dm(JH7110_AONCLK_OTPC_APB, + starfive_clk_gate(priv->reg, + "otpc_apb", "aon_apb", + AONOFFSET(JH7110_AONCLK_OTPC_APB))); + + return 0; +} + +static int jh7110_stgcrg_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_STGCLK_STG_APB, + starfive_clk_fix_factor(priv->reg, + "stg_apb", "apb_bus", 1, 1)); + clk_dm(JH7110_STGCLK_USB_APB, + starfive_clk_gate(priv->reg, + "usb_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_USB_APB))); + clk_dm(JH7110_STGCLK_USB_UTMI_APB, + starfive_clk_gate(priv->reg, + "usb_utmi_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_USB_UTMI_APB))); + clk_dm(JH7110_STGCLK_USB_AXI, + starfive_clk_gate(priv->reg, + "usb_axi", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_USB_AXI))); + clk_dm(JH7110_STGCLK_USB_LPM, + starfive_clk_gate_divider(priv->reg, + "usb_lpm", "osc", + STGOFFSET(JH7110_STGCLK_USB_LPM), 2)); + clk_dm(JH7110_STGCLK_USB_STB, + starfive_clk_gate_divider(priv->reg, + "usb_stb", "osc", + STGOFFSET(JH7110_STGCLK_USB_STB), 3)); + clk_dm(JH7110_STGCLK_USB_APP_125, + starfive_clk_gate(priv->reg, + "usb_app_125", "usb_125m", + STGOFFSET(JH7110_STGCLK_USB_APP_125))); + clk_dm(JH7110_STGCLK_USB_REFCLK, + starfive_clk_divider(priv->reg, "usb_refclk", "osc", + STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2)); + return 0; +} + +static int jh7110_clk_probe(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + priv->config = (void *)dev_get_driver_data(dev); + priv->reg = (void __iomem *)ofnode_get_addr(dev_ofnode(dev)); + + if (priv->config->init) + return priv->config->init(dev); + + return 0; +} + +static int jh7110_clk_bind(struct udevice *dev) +{ + /* The reset driver does not have a device node, so bind it here */ + return device_bind_driver_to_node(dev, "jh7110_reset", dev->name, + dev_ofnode(dev), NULL); +} + +struct jh7110_clk_config __maybe_unused jh7110_clk_syscrg = { + .init = jh7110_syscrg_init +}; + +struct jh7110_clk_config __maybe_unused jh7110_clk_stgcrg = { + .init = jh7110_stgcrg_init +}; + +struct jh7110_clk_config __maybe_unused jh7110_clk_aoncrg = { + .init = jh7110_aoncrg_init +}; + +static const struct udevice_id jh7110_clk_of_match[] = { + { .compatible = "starfive,jh7110-syscrg", + .data = (ulong)&jh7110_clk_syscrg + }, + { .compatible = "starfive,jh7110-stgcrg", + .data = (ulong)&jh7110_clk_stgcrg + }, + { .compatible = "starfive,jh7110-aoncrg", + .data = (ulong)&jh7110_clk_aoncrg + }, + { } +}; + +U_BOOT_DRIVER(jh7110_clk) = { + .name = "jh7110_clk", + .id = UCLASS_CLK, + .of_match = jh7110_clk_of_match, + .probe = jh7110_clk_probe, + .ops = &starfive_clk_ops, + .priv_auto = sizeof(struct jh7110_clk_priv), + .bind = jh7110_clk_bind, +}; diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h new file mode 100644 index 0000000000..d86280d523 --- /dev/null +++ b/drivers/clk/starfive/clk.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: Yanhong Wang yanhong.wang@starfivetech.com + * + */ + +#ifndef __CLK_STARFIVE_H +#define __CLK_STARFIVE_H + +enum starfive_pll_type { + PLL0 = 0, + PLL1, + PLL2, + PLL_MAX = PLL2 +}; + +struct starfive_pllx_rate { + u64 rate; + u32 prediv; + u32 fbdiv; + u32 frac; + u32 postdiv1; + u32 dacpd; + u32 dsmpd; +}; + +struct starfive_pllx_clk { + enum starfive_pll_type type; + const struct starfive_pllx_rate *rate_table; + int rate_count; + int flags; +}; + +extern struct starfive_pllx_clk starfive_jh7110_pll0; +extern struct starfive_pllx_clk starfive_jh7110_pll1; +extern struct starfive_pllx_clk starfive_jh7110_pll2; + +struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, + void __iomem *base, void __iomem *sysreg, + const struct starfive_pllx_clk *pll_clk); +#endif

From: Jianlong Huang jianlong.huang@starfivetech.com

Add pinctrl definitions for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee kuanlim.lee@linux.starfivetech.com Signed-off-by: Emil Renner Berthing kernel@esmil.dk Signed-off-by: Jianlong Huang jianlong.huang@starfivetech.com Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++++++++++++++++++ 1 file changed, 427 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h new file mode 100644 index 0000000000..fb02345caa --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux pin */ +#define PAD_GPIO0 0 +#define PAD_GPIO1 1 +#define PAD_GPIO2 2 +#define PAD_GPIO3 3 +#define PAD_GPIO4 4 +#define PAD_GPIO5 5 +#define PAD_GPIO6 6 +#define PAD_GPIO7 7 +#define PAD_GPIO8 8 +#define PAD_GPIO9 9 +#define PAD_GPIO10 10 +#define PAD_GPIO11 11 +#define PAD_GPIO12 12 +#define PAD_GPIO13 13 +#define PAD_GPIO14 14 +#define PAD_GPIO15 15 +#define PAD_GPIO16 16 +#define PAD_GPIO17 17 +#define PAD_GPIO18 18 +#define PAD_GPIO19 19 +#define PAD_GPIO20 20 +#define PAD_GPIO21 21 +#define PAD_GPIO22 22 +#define PAD_GPIO23 23 +#define PAD_GPIO24 24 +#define PAD_GPIO25 25 +#define PAD_GPIO26 26 +#define PAD_GPIO27 27 +#define PAD_GPIO28 28 +#define PAD_GPIO29 29 +#define PAD_GPIO30 30 +#define PAD_GPIO31 31 +#define PAD_GPIO32 32 +#define PAD_GPIO33 33 +#define PAD_GPIO34 34 +#define PAD_GPIO35 35 +#define PAD_GPIO36 36 +#define PAD_GPIO37 37 +#define PAD_GPIO38 38 +#define PAD_GPIO39 39 +#define PAD_GPIO40 40 +#define PAD_GPIO41 41 +#define PAD_GPIO42 42 +#define PAD_GPIO43 43 +#define PAD_GPIO44 44 +#define PAD_GPIO45 45 +#define PAD_GPIO46 46 +#define PAD_GPIO47 47 +#define PAD_GPIO48 48 +#define PAD_GPIO49 49 +#define PAD_GPIO50 50 +#define PAD_GPIO51 51 +#define PAD_GPIO52 52 +#define PAD_GPIO53 53 +#define PAD_GPIO54 54 +#define PAD_GPIO55 55 +#define PAD_GPIO56 56 +#define PAD_GPIO57 57 +#define PAD_GPIO58 58 +#define PAD_GPIO59 59 +#define PAD_GPIO60 60 +#define PAD_GPIO61 61 +#define PAD_GPIO62 62 +#define PAD_GPIO63 63 +#define PAD_SD0_CLK 64 +#define PAD_SD0_CMD 65 +#define PAD_SD0_DATA0 66 +#define PAD_SD0_DATA1 67 +#define PAD_SD0_DATA2 68 +#define PAD_SD0_DATA3 69 +#define PAD_SD0_DATA4 70 +#define PAD_SD0_DATA5 71 +#define PAD_SD0_DATA6 72 +#define PAD_SD0_DATA7 73 +#define PAD_SD0_STRB 74 +#define PAD_GMAC1_MDC 75 +#define PAD_GMAC1_MDIO 76 +#define PAD_GMAC1_RXD0 77 +#define PAD_GMAC1_RXD1 78 +#define PAD_GMAC1_RXD2 79 +#define PAD_GMAC1_RXD3 80 +#define PAD_GMAC1_RXDV 81 +#define PAD_GMAC1_RXC 82 +#define PAD_GMAC1_TXD0 83 +#define PAD_GMAC1_TXD1 84 +#define PAD_GMAC1_TXD2 85 +#define PAD_GMAC1_TXD3 86 +#define PAD_GMAC1_TXEN 87 +#define PAD_GMAC1_TXC 88 +#define PAD_QSPI_SCLK 89 +#define PAD_QSPI_CS0 90 +#define PAD_QSPI_DATA0 91 +#define PAD_QSPI_DATA1 92 +#define PAD_QSPI_DATA2 93 +#define PAD_QSPI_DATA3 94 + +/* aon_iomux pin */ +#define PAD_TESTEN 0 +#define PAD_RGPIO0 1 +#define PAD_RGPIO1 2 +#define PAD_RGPIO2 3 +#define PAD_RGPIO3 4 +#define PAD_RSTN 5 +#define PAD_GMAC0_MDC 6 +#define PAD_GMAC0_MDIO 7 +#define PAD_GMAC0_RXD0 8 +#define PAD_GMAC0_RXD1 9 +#define PAD_GMAC0_RXD2 10 +#define PAD_GMAC0_RXD3 11 +#define PAD_GMAC0_RXDV 12 +#define PAD_GMAC0_RXC 13 +#define PAD_GMAC0_TXD0 14 +#define PAD_GMAC0_TXD1 15 +#define PAD_GMAC0_TXD2 16 +#define PAD_GMAC0_TXD3 17 +#define PAD_GMAC0_TXEN 18 +#define PAD_GMAC0_TXC 19 + +/* sys_iomux dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_WAVE511_UART_TX 2 +#define GPOUT_SYS_CAN0_STBY 3 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 +#define GPOUT_SYS_CAN0_TXD 6 +#define GPOUT_SYS_USB_DRIVE_VBUS 7 +#define GPOUT_SYS_QSPI_CS1 8 +#define GPOUT_SYS_SPDIF 9 +#define GPOUT_SYS_HDMI_CEC_SDA 10 +#define GPOUT_SYS_HDMI_DDC_SCL 11 +#define GPOUT_SYS_HDMI_DDC_SDA 12 +#define GPOUT_SYS_WATCHDOG 13 +#define GPOUT_SYS_I2C0_CLK 14 +#define GPOUT_SYS_I2C0_DATA 15 +#define GPOUT_SYS_SDIO0_BACK_END_POWER 16 +#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 +#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 +#define GPOUT_SYS_SDIO0_RST 19 +#define GPOUT_SYS_UART0_TX 20 +#define GPOUT_SYS_HIFI4_JTAG_TDO 21 +#define GPOUT_SYS_JTAG_TDO 22 +#define GPOUT_SYS_PDM_MCLK 23 +#define GPOUT_SYS_PWM_CHANNEL0 24 +#define GPOUT_SYS_PWM_CHANNEL1 25 +#define GPOUT_SYS_PWM_CHANNEL2 26 +#define GPOUT_SYS_PWM_CHANNEL3 27 +#define GPOUT_SYS_PWMDAC_LEFT 28 +#define GPOUT_SYS_PWMDAC_RIGHT 29 +#define GPOUT_SYS_SPI0_CLK 30 +#define GPOUT_SYS_SPI0_FSS 31 +#define GPOUT_SYS_SPI0_TXD 32 +#define GPOUT_SYS_GMAC_PHYCLK 33 +#define GPOUT_SYS_I2SRX_BCLK 34 +#define GPOUT_SYS_I2SRX_LRCK 35 +#define GPOUT_SYS_I2STX0_BCLK 36 +#define GPOUT_SYS_I2STX0_LRCK 37 +#define GPOUT_SYS_MCLK 38 +#define GPOUT_SYS_TDM_CLK 39 +#define GPOUT_SYS_TDM_SYNC 40 +#define GPOUT_SYS_TDM_TXD 41 +#define GPOUT_SYS_TRACE_DATA0 42 +#define GPOUT_SYS_TRACE_DATA1 43 +#define GPOUT_SYS_TRACE_DATA2 44 +#define GPOUT_SYS_TRACE_DATA3 45 +#define GPOUT_SYS_TRACE_REF 46 +#define GPOUT_SYS_CAN1_STBY 47 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 +#define GPOUT_SYS_CAN1_TXD 50 +#define GPOUT_SYS_I2C1_CLK 51 +#define GPOUT_SYS_I2C1_DATA 52 +#define GPOUT_SYS_SDIO1_BACK_END_POWER 53 +#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 +#define GPOUT_SYS_SDIO1_CLK 55 +#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 +#define GPOUT_SYS_SDIO1_CMD 57 +#define GPOUT_SYS_SDIO1_DATA0 58 +#define GPOUT_SYS_SDIO1_DATA1 59 +#define GPOUT_SYS_SDIO1_DATA2 60 +#define GPOUT_SYS_SDIO1_DATA3 61 +#define GPOUT_SYS_SDIO1_DATA4 63 +#define GPOUT_SYS_SDIO1_DATA5 63 +#define GPOUT_SYS_SDIO1_DATA6 64 +#define GPOUT_SYS_SDIO1_DATA7 65 +#define GPOUT_SYS_SDIO1_RST 66 +#define GPOUT_SYS_UART1_RTS 67 +#define GPOUT_SYS_UART1_TX 68 +#define GPOUT_SYS_I2STX1_SDO0 69 +#define GPOUT_SYS_I2STX1_SDO1 70 +#define GPOUT_SYS_I2STX1_SDO2 71 +#define GPOUT_SYS_I2STX1_SDO3 72 +#define GPOUT_SYS_SPI1_CLK 73 +#define GPOUT_SYS_SPI1_FSS 74 +#define GPOUT_SYS_SPI1_TXD 75 +#define GPOUT_SYS_I2C2_CLK 76 +#define GPOUT_SYS_I2C2_DATA 77 +#define GPOUT_SYS_UART2_RTS 78 +#define GPOUT_SYS_UART2_TX 79 +#define GPOUT_SYS_SPI2_CLK 80 +#define GPOUT_SYS_SPI2_FSS 81 +#define GPOUT_SYS_SPI2_TXD 82 +#define GPOUT_SYS_I2C3_CLK 83 +#define GPOUT_SYS_I2C3_DATA 84 +#define GPOUT_SYS_UART3_TX 85 +#define GPOUT_SYS_SPI3_CLK 86 +#define GPOUT_SYS_SPI3_FSS 87 +#define GPOUT_SYS_SPI3_TXD 88 +#define GPOUT_SYS_I2C4_CLK 89 +#define GPOUT_SYS_I2C4_DATA 90 +#define GPOUT_SYS_UART4_RTS 91 +#define GPOUT_SYS_UART4_TX 92 +#define GPOUT_SYS_SPI4_CLK 93 +#define GPOUT_SYS_SPI4_FSS 94 +#define GPOUT_SYS_SPI4_TXD 95 +#define GPOUT_SYS_I2C5_CLK 96 +#define GPOUT_SYS_I2C5_DATA 97 +#define GPOUT_SYS_UART5_RTS 98 +#define GPOUT_SYS_UART5_TX 99 +#define GPOUT_SYS_SPI5_CLK 100 +#define GPOUT_SYS_SPI5_FSS 101 +#define GPOUT_SYS_SPI5_TXD 102 +#define GPOUT_SYS_I2C6_CLK 103 +#define GPOUT_SYS_I2C6_DATA 104 +#define GPOUT_SYS_SPI6_CLK 105 +#define GPOUT_SYS_SPI6_FSS 106 +#define GPOUT_SYS_SPI6_TXD 107 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K_OUT 2 +#define GPOUT_AON_PTC0_PWM4 3 +#define GPOUT_AON_PTC0_PWM5 4 +#define GPOUT_AON_PTC0_PWM6 5 +#define GPOUT_AON_PTC0_PWM7 6 +#define GPOUT_AON_CLK_GCLK0 7 +#define GPOUT_AON_CLK_GCLK1 8 +#define GPOUT_AON_CLK_GCLK2 9 + +/* sys_iomux doen */ +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 +#define GPOEN_SYS_HDMI_CEC_SDA 2 +#define GPOEN_SYS_HDMI_DDC_SCL 3 +#define GPOEN_SYS_HDMI_DDC_SDA 4 +#define GPOEN_SYS_I2C0_CLK 5 +#define GPOEN_SYS_I2C0_DATA 6 +#define GPOEN_SYS_HIFI4_JTAG_TDO 7 +#define GPOEN_SYS_JTAG_TDO 8 +#define GPOEN_SYS_PWM0_CHANNEL0 9 +#define GPOEN_SYS_PWM0_CHANNEL1 10 +#define GPOEN_SYS_PWM0_CHANNEL2 11 +#define GPOEN_SYS_PWM0_CHANNEL3 12 +#define GPOEN_SYS_SPI0_NSSPCTL 13 +#define GPOEN_SYS_SPI0_NSSP 14 +#define GPOEN_SYS_TDM_SYNC 15 +#define GPOEN_SYS_TDM_TXD 16 +#define GPOEN_SYS_I2C1_CLK 17 +#define GPOEN_SYS_I2C1_DATA 18 +#define GPOEN_SYS_SDIO1_CMD 19 +#define GPOEN_SYS_SDIO1_DATA0 20 +#define GPOEN_SYS_SDIO1_DATA1 21 +#define GPOEN_SYS_SDIO1_DATA2 22 +#define GPOEN_SYS_SDIO1_DATA3 23 +#define GPOEN_SYS_SDIO1_DATA4 24 +#define GPOEN_SYS_SDIO1_DATA5 25 +#define GPOEN_SYS_SDIO1_DATA6 26 +#define GPOEN_SYS_SDIO1_DATA7 27 +#define GPOEN_SYS_SPI1_NSSPCTL 28 +#define GPOEN_SYS_SPI1_NSSP 29 +#define GPOEN_SYS_I2C2_CLK 30 +#define GPOEN_SYS_I2C2_DATA 31 +#define GPOEN_SYS_SPI2_NSSPCTL 32 +#define GPOEN_SYS_SPI2_NSSP 33 +#define GPOEN_SYS_I2C3_CLK 34 +#define GPOEN_SYS_I2C3_DATA 35 +#define GPOEN_SYS_SPI3_NSSPCTL 36 +#define GPOEN_SYS_SPI3_NSSP 37 +#define GPOEN_SYS_I2C4_CLK 38 +#define GPOEN_SYS_I2C4_DATA 39 +#define GPOEN_SYS_SPI4_NSSPCTL 40 +#define GPOEN_SYS_SPI4_NSSP 41 +#define GPOEN_SYS_I2C5_CLK 42 +#define GPOEN_SYS_I2C5_DATA 43 +#define GPOEN_SYS_SPI5_NSSPCTL 44 +#define GPOEN_SYS_SPI5_NSSP 45 +#define GPOEN_SYS_I2C6_CLK 46 +#define GPOEN_SYS_I2C6_DATA 47 +#define GPOEN_SYS_SPI6_NSSPCTL 48 +#define GPOEN_SYS_SPI6_NSSP 49 + +/* aon_iomux doen */ +#define GPOEN_AON_PTC0_OE_N_4 2 +#define GPOEN_AON_PTC0_OE_N_5 3 +#define GPOEN_AON_PTC0_OE_N_6 4 +#define GPOEN_AON_PTC0_OE_N_7 5 + +/* sys_iomux gin */ +#define GPI_NONE 255 + +#define GPI_SYS_WAVE511_UART_RX 0 +#define GPI_SYS_CAN0_RXD 1 +#define GPI_SYS_USB_OVERCURRENT 2 +#define GPI_SYS_SPDIF 3 +#define GPI_SYS_JTAG_RST 4 +#define GPI_SYS_HDMI_CEC_SDA 5 +#define GPI_SYS_HDMI_DDC_SCL 6 +#define GPI_SYS_HDMI_DDC_SDA 7 +#define GPI_SYS_HDMI_HPD 8 +#define GPI_SYS_I2C0_CLK 9 +#define GPI_SYS_I2C0_DATA 10 +#define GPI_SYS_SDIO0_CD 11 +#define GPI_SYS_SDIO0_INT 12 +#define GPI_SYS_SDIO0_WP 13 +#define GPI_SYS_UART0_RX 14 +#define GPI_SYS_HIFI4_JTAG_TCK 15 +#define GPI_SYS_HIFI4_JTAG_TDI 16 +#define GPI_SYS_HIFI4_JTAG_TMS 17 +#define GPI_SYS_HIFI4_JTAG_RST 18 +#define GPI_SYS_JTAG_TDI 19 +#define GPI_SYS_JTAG_TMS 20 +#define GPI_SYS_PDM_DMIC0 21 +#define GPI_SYS_PDM_DMIC1 22 +#define GPI_SYS_I2SRX_SDIN0 23 +#define GPI_SYS_I2SRX_SDIN1 24 +#define GPI_SYS_I2SRX_SDIN2 25 +#define GPI_SYS_SPI0_CLK 26 +#define GPI_SYS_SPI0_FSS 27 +#define GPI_SYS_SPI0_RXD 28 +#define GPI_SYS_JTAG_TCK 29 +#define GPI_SYS_MCLK_EXT 30 +#define GPI_SYS_I2SRX_BCLK 31 +#define GPI_SYS_I2SRX_LRCK 32 +#define GPI_SYS_I2STX0_BCLK 33 +#define GPI_SYS_I2STX0_LRCK 34 +#define GPI_SYS_TDM_CLK 35 +#define GPI_SYS_TDM_RXD 36 +#define GPI_SYS_TDM_SYNC 37 +#define GPI_SYS_CAN1_RXD 38 +#define GPI_SYS_I2C1_CLK 39 +#define GPI_SYS_I2C1_DATA 40 +#define GPI_SYS_SDIO1_CD 41 +#define GPI_SYS_SDIO1_INT 42 +#define GPI_SYS_SDIO1_WP 43 +#define GPI_SYS_SDIO1_CMD 44 +#define GPI_SYS_SDIO1_DATA0 45 +#define GPI_SYS_SDIO1_DATA1 46 +#define GPI_SYS_SDIO1_DATA2 47 +#define GPI_SYS_SDIO1_DATA3 48 +#define GPI_SYS_SDIO1_DATA4 49 +#define GPI_SYS_SDIO1_DATA5 50 +#define GPI_SYS_SDIO1_DATA6 51 +#define GPI_SYS_SDIO1_DATA7 52 +#define GPI_SYS_SDIO1_STRB 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_RX 55 +#define GPI_SYS_SPI1_CLK 56 +#define GPI_SYS_SPI1_FSS 57 +#define GPI_SYS_SPI1_RXD 58 +#define GPI_SYS_I2C2_CLK 59 +#define GPI_SYS_I2C2_DATA 60 +#define GPI_SYS_UART2_CTS 61 +#define GPI_SYS_UART2_RX 62 +#define GPI_SYS_SPI2_CLK 63 +#define GPI_SYS_SPI2_FSS 64 +#define GPI_SYS_SPI2_RXD 65 +#define GPI_SYS_I2C3_CLK 66 +#define GPI_SYS_I2C3_DATA 67 +#define GPI_SYS_UART3_RX 68 +#define GPI_SYS_SPI3_CLK 69 +#define GPI_SYS_SPI3_FSS 70 +#define GPI_SYS_SPI3_RXD 71 +#define GPI_SYS_I2C4_CLK 72 +#define GPI_SYS_I2C4_DATA 73 +#define GPI_SYS_UART4_CTS 74 +#define GPI_SYS_UART4_RX 75 +#define GPI_SYS_SPI4_CLK 76 +#define GPI_SYS_SPI4_FSS 77 +#define GPI_SYS_SPI4_RXD 78 +#define GPI_SYS_I2C5_CLK 79 +#define GPI_SYS_I2C5_DATA 80 +#define GPI_SYS_UART5_CTS 81 +#define GPI_SYS_UART5_RX 82 +#define GPI_SYS_SPI5_CLK 83 +#define GPI_SYS_SPI5_FSS 84 +#define GPI_SYS_SPI5_RXD 85 +#define GPI_SYS_I2C6_CLK 86 +#define GPI_SYS_I2C6_DATA 87 +#define GPI_SYS_SPI6_CLK 88 +#define GPI_SYS_SPI6_FSS 89 +#define GPI_SYS_SPI6_RXD 90 + +/* aon_iomux gin */ +#define GPI_AON_PMU_GPIO_WAKEUP_0 0 +#define GPI_AON_PMU_GPIO_WAKEUP_1 1 +#define GPI_AON_PMU_GPIO_WAKEUP_2 2 +#define GPI_AON_PMU_GPIO_WAKEUP_3 3 + +#endif

Add driver for StarFive JH7110 to support ddr initialization in SPL.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 4 +- drivers/ram/starfive/Kconfig | 5 + drivers/ram/starfive/Makefile | 11 + drivers/ram/starfive/ddrcsr_boot.c | 340 +++++ drivers/ram/starfive/ddrphy_start.c | 280 ++++ drivers/ram/starfive/ddrphy_train.c | 384 ++++++ drivers/ram/starfive/ddrphy_utils.c | 1956 +++++++++++++++++++++++++++ drivers/ram/starfive/starfive_ddr.c | 162 +++ drivers/ram/starfive/starfive_ddr.h | 66 + 10 files changed, 3208 insertions(+), 1 deletion(-) create mode 100644 drivers/ram/starfive/Kconfig create mode 100644 drivers/ram/starfive/Makefile create mode 100644 drivers/ram/starfive/ddrcsr_boot.c create mode 100644 drivers/ram/starfive/ddrphy_start.c create mode 100644 drivers/ram/starfive/ddrphy_train.c create mode 100644 drivers/ram/starfive/ddrphy_utils.c create mode 100644 drivers/ram/starfive/starfive_ddr.c create mode 100644 drivers/ram/starfive/starfive_ddr.h

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 86857c0627..91882d9328 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -101,3 +101,4 @@ source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" source "drivers/ram/octeon/Kconfig" +source "drivers/ram/starfive/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 5a39611349..f709893fa2 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o

obj-$(CONFIG_RAM_SIFIVE) += sifive/ - +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ +endif obj-$(CONFIG_ARCH_OCTEON) += octeon/ diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig new file mode 100644 index 0000000000..80c790066f --- /dev/null +++ b/drivers/ram/starfive/Kconfig @@ -0,0 +1,5 @@ +config SPL_STARFIVE_DDR + bool "StarFive DDR driver in SPL" + depends on SPL_RAM && STARFIVE_JH7110 + help + This enables DDR support for the platforms based on StarFive JH7110 SoC. diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile new file mode 100644 index 0000000000..1df42c377b --- /dev/null +++ b/drivers/ram/starfive/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2022 StarFive, Inc +# +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o +endif \ No newline at end of file diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c new file mode 100644 index 0000000000..e17cb251d1 --- /dev/null +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/jh7110-regs.h> +#include <linux/delay.h> +#include <wait_bit.h> + +#include "starfive_ddr.h" + +#define REGOFFSET(offset) ((offset) / 4) + +static const struct ddr_reg_cfg ddr_csr_cfg[] = { + {0x0, 0x0, 0x00000001, REGSETALL}, + {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)}, + {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)}, + {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)}, + {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)}, + {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)}, + {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)}, + {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)}, + {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)}, + {0x10c, 0x0, 0x00000505, REGSETALL}, + {0x11c, 0x0, 0x00000000, REGSETALL}, + {0x500, 0x0, 0x00000201, REGSETALL}, + {0x514, 0x0, 0x00000100, REGSETALL}, + {0x6a8, 0x0, 0x00040000, REGSETALL}, + {0xea8, 0x0, 0x00040000, REGSETALL}, + {0x504, 0x0, 0x40000000, REGSETALL} +}; + +static const struct ddr_reg_cfg ddr_csr_cfg1[] = { + {0x310, 0x0, 0x00020000, REGSETALL}, + {0x310, 0x0, 0x00020001, REGSETALL}, + {0x600, 0x0, 0x002e0176, REGSETALL}, + {0x604, 0x0, 0x002e0176, REGSETALL}, + {0x608, 0x0, 0x001700bb, REGSETALL}, + {0x60c, 0x0, 0x000b005d, REGSETALL}, + {0x610, 0x0, 0x0005002e, REGSETALL}, + {0x614, 0x0, 0x00020017, REGSETALL}, + {0x618, 0x0, 0x00020017, REGSETALL}, + {0x61c, 0x0, 0x00020017, REGSETALL}, + {0x678, 0x0, 0x00000019, REGSETALL}, + {0x100, 0x0, 0x000000f8, REGSETALL}, + {0x620, 0x0, 0x03030404, REGSETALL}, + {0x624, 0x0, 0x04030505, REGSETALL}, + {0x628, 0x0, 0x07030884, REGSETALL}, + {0x62c, 0x0, 0x13150401, REGSETALL}, + {0x630, 0x0, 0x17150604, REGSETALL}, + {0x634, 0x0, 0x00110000, REGSETALL}, + {0x638, 0x0, 0x200a0a08, REGSETALL}, + {0x63c, 0x0, 0x1730f803, REGSETALL}, + {0x640, 0x0, 0x000a0c00, REGSETALL}, + {0x644, 0x0, 0xa005000a, REGSETALL}, + {0x648, 0x0, 0x00000000, REGSETALL}, + {0x64c, 0x0, 0x00081306, REGSETALL}, + {0x650, 0x0, 0x04070304, REGSETALL}, + {0x654, 0x0, 0x00000404, REGSETALL}, + {0x658, 0x0, 0x00000060, REGSETALL}, + {0x65c, 0x0, 0x00030008, REGSETALL}, + {0x660, 0x0, 0x00000000, REGSETALL}, + {0x680, 0x0, 0x00000603, REGSETALL}, + {0x684, 0x0, 0x01000202, REGSETALL}, + {0x688, 0x0, 0x0413040d, REGSETALL}, + {0x68c, 0x0, 0x20002420, REGSETALL}, + {0x690, 0x0, 0x00140000, REGSETALL}, + {0x69c, 0x0, 0x01240074, REGSETALL}, + {0x6a0, 0x0, 0x00000000, REGSETALL}, + {0x6a4, 0x0, 0x20240c00, REGSETALL}, + {0x6a8, 0x0, 0x00040000, REGSETALL}, + {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10010006, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10020000, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x100b0033, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x10, 0x0, 0x00000010, REGSETALL}, + {0x14, 0x0, 0x00000001, REGSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg2[] = { + {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL}, + {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb4, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x300, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x100, REGCLRSETALL}, + {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL}, + {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x250, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x254, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x258, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xac, 0xffffffff, 0x100, REGCLRSETALL}, + {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL}, + {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0x120, 0xffffffff, 0x100, REGCLRSETALL}, + {0x2d0, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2dc, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2e8, 0xffffffff, 0x300, REGCLRSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg3[] = { + {0x100, 0x0, 0x000000e0, REGSETALL}, + {0x620, 0x0, 0x04041417, REGSETALL}, + {0x624, 0x0, 0x09110609, REGSETALL}, + {0x628, 0x0, 0x442d0994, REGSETALL}, + {0x62c, 0x0, 0x271e102b, REGSETALL}, + {0x630, 0x0, 0x291b140a, REGSETALL}, + {0x634, 0x0, 0x001c0000, REGSETALL}, + {0x638, 0x0, 0x200f0f08, REGSETALL}, + {0x63c, 0x0, 0x29420a06, REGSETALL}, + {0x640, 0x0, 0x019e1fc1, REGSETALL}, + {0x644, 0x0, 0x10cb0196, REGSETALL}, + {0x648, 0x0, 0x00000000, REGSETALL}, + {0x64c, 0x0, 0x00082714, REGSETALL}, + {0x650, 0x0, 0x16442f0d, REGSETALL}, + {0x654, 0x0, 0x00001916, REGSETALL}, + {0x658, 0x0, 0x00000060, REGSETALL}, + {0x65c, 0x0, 0x00600020, REGSETALL}, + {0x660, 0x0, 0x00000000, REGSETALL}, + {0x680, 0x0, 0x0c00040f, REGSETALL}, + {0x684, 0x0, 0x03000604, REGSETALL}, + {0x688, 0x0, 0x0515040d, REGSETALL}, + {0x68c, 0x0, 0x20002c20, REGSETALL}, + {0x690, 0x0, 0x00140000, REGSETALL}, + {0x69c, 0x0, 0x01240074, REGSETALL}, + {0x6a0, 0x0, 0x00000000, REGSETALL}, + {0x6a4, 0x0, 0x202c0c00, REGSETALL}, + {0x6a8, 0x0, 0x00040000, REGSETALL}, + {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x300b0066, (F_SET | REG4G)}, + {0x4, 0x0, 0x300b0036, (F_SET | REG8G)}, + {0x4, 0x0, 0x100b0066, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0xc, 0x0, 0x00000002, REGSETALL}, + {0x410, 0x0, 0x00101010, REGSETALL}, + {0x420, 0x0, 0x0c181006, REGSETALL}, + {0x424, 0x0, 0x20200820, REGSETALL}, + {0x428, 0x0, 0x80000020, REGSETALL}, + {0x0, 0x0, 0x00000001, REGSETALL}, + {0x108, 0x0, 0x00003000, REGSETALL}, + {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL}, + {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)}, + {0x330, 0x0, 0x09311fff, (F_SET | REG2G)}, + {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)}, + {0x508, 0x0, 0x00000013, (F_SET | REG2G)}, + {0x324, 0x0, 0x00002000, REGSETALL}, + {0x104, 0x0, 0x90000000, REGSETALL}, + {0x510, 0x0, 0x00000100, REGSETALL}, + {0x514, 0x0, 0x00000000, REGSETALL}, + {0x700, 0x0, 0x00000003, REGSETALL | OFFSET_SEL}, + {0x514, 0x0, 0x00000600, REGSETALL}, + {0x20, 0x0, 0x00000001, REGSETALL}, +}; + +static void ddr_csr_set(u32 *csrreg, u32 *secreg, const struct ddr_reg_cfg *data, + u32 len, u32 mask) +{ + u32 *addr; + u32 i; + + for (i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + if (data[i].flag & OFFSET_SEL) + addr = secreg + REGOFFSET(data[i].offset); + else + addr = csrreg + REGOFFSET(data[i].offset); + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else + out_le32(addr, data[i].val); + } +} + +void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) +{ + u32 len; + u32 val; + u32 mask; + int ret; + + switch (size) { + case DDR_SIZE_2G: + mask = REG2G; + break; + + case DDR_SIZE_4G: + mask = REG4G; + break; + + case DDR_SIZE_8G: + mask = REG8G; + break; + + case DDR_SIZE_16G: + default: + return; + }; + + len = ARRAY_SIZE(ddr_csr_cfg); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask); + + ret = wait_for_bit_le32(csrreg + REGOFFSET(0x504), BIT(31), + true, 1000, false); + if (ret) + return; + + out_le32(csrreg + REGOFFSET(0x504), 0x0); + out_le32(csrreg + REGOFFSET(0x50c), 0x0); + udelay(300); + out_le32(csrreg + REGOFFSET(0x50c), 0x1); + mdelay(3); + + switch (size) { + case DDR_SIZE_2G: + out_le32(csrreg + REGOFFSET(0x10), 0x1c); + break; + + case DDR_SIZE_8G: + case DDR_SIZE_4G: + out_le32(csrreg + REGOFFSET(0x10), 0x3c); + break; + + case DDR_SIZE_16G: + default: + break; + }; + + out_le32(csrreg + REGOFFSET(0x14), 0x1); + udelay(4); + + len = ARRAY_SIZE(ddr_csr_cfg1); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask); + + udelay(4); + out_le32(csrreg + REGOFFSET(0x10), 0x11); + out_le32(csrreg + REGOFFSET(0x14), 0x1); + + switch (size) { + case DDR_SIZE_4G: + case DDR_SIZE_8G: + out_le32(csrreg + REGOFFSET(0x10), 0x20); + out_le32(csrreg + REGOFFSET(0x14), 0x1); + udelay(4); + out_le32(csrreg + REGOFFSET(0x10), 0x21); + out_le32(csrreg + REGOFFSET(0x14), 0x1); + break; + + case DDR_SIZE_2G: + case DDR_SIZE_16G: + default: + break; + }; + + out_le32(csrreg + REGOFFSET(0x514), 0x0); + ret = wait_for_bit_le32(csrreg + REGOFFSET(0x518), BIT(1), + true, 1000, false); + if (ret) + return; + + val = in_le32(csrreg + REGOFFSET(0x518)); + while ((val & 0x2) != 0x0) { + val = in_le32(phyreg + 1); + + if ((val & 0x20) == 0x20) { + switch (val & 0x1f) { + case 0: /* ddrc_clock=12M */ + DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2); + break; + case 1: /* ddrc_clock=200M */ + DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8); + break; + case 2: /* ddrc_clock=800M */ + DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2); + break; + default: + break; + }; + + out_le32(phyreg + 2, 0x1); + ret = wait_for_bit_le32(phyreg + 2, BIT(0), false, 1000, false); + if (ret) + return; + } + + udelay(1); + val = in_le32(csrreg + REGOFFSET(0x518)); + }; + + val = in_le32(phyreg + 2048 + 83); + val = in_le32(phyreg + 2048 + 84); + out_le32(phyreg + 2048 + 84, val & 0xF8000000); + + len = ARRAY_SIZE(ddr_csr_cfg2); + ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask); + + len = ARRAY_SIZE(ddr_csr_cfg3); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask); +} diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c new file mode 100644 index 0000000000..a322006804 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_start.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <asm/io.h> + +#include "starfive_ddr.h" + +static const struct ddr_reg_cfg ddr_start_cfg[] = { + {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {78, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {334, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {590, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {846, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {1793, 0xfffffeff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {1793, 0xfffcffff, 0x0, (OFFSET_SEL | REGCLRSETALL)}, + {125, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {102, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {105, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {92, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {94, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {96, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {381, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {358, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {361, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {348, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {350, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {352, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {637, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {614, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {617, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {604, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {606, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {608, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {893, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {870, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {873, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {860, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {862, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {864, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {1895, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)}, + {1835, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {1793, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {62, 0xfffffeff, 0x0, REGCLRSETALL}, + {66, 0xfffffeff, 0x0, REGCLRSETALL}, + {166, 0xffffff80, 0x00000001, REGCLRSETALL}, + {62, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {62, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {166, 0xffff80ff, 0x00000100, REGCLRSETALL}, + {179, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {67, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {67, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {179, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {166, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {62, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {62, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {166, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {182, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {67, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {67, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {182, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {167, 0xffffff80, 0x00000017, REGCLRSETALL}, + {62, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {62, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {167, 0xffff80ff, 0x00001700, REGCLRSETALL}, + {185, 0xff80ffff, 0x00200000, REGCLRSETALL}, + {67, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {67, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {185, 0x80ffffff, 0x20000000, REGCLRSETALL}, + {10, 0xffffffe0, 0x00000002, REGCLRSETALL}, + {0, 0xfffffffe, 0x00000001, REGCLRSETALL}, + {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)}, + {247, 0xffffffff, 0x00000008, REGCLRSETALL}, + {249, 0xffffffff, 0x00000800, REGCLRSETALL}, + {252, 0xffffffff, 0x00000008, REGCLRSETALL}, + {254, 0xffffffff, 0x00000800, REGCLRSETALL}, + {281, 0xffffffff, 0x33000000, REGCLRSETALL}, + {305, 0xffffffff, 0x33000000, REGCLRSETALL}, + {329, 0xffffffff, 0x33000000, REGCLRSETALL}, + {353, 0xffffffff, 0x33000000, REGCLRSETALL}, + {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {282, 0xffffffff, 0x00160000, REGCLRSETALL}, + {306, 0xffffffff, 0x00160000, REGCLRSETALL}, + {330, 0xffffffff, 0x00160000, REGCLRSETALL}, + {354, 0xffffffff, 0x00160000, REGCLRSETALL}, + {290, 0xffffffff, 0x00160000, REGCLRSETALL}, + {314, 0xffffffff, 0x00160000, REGCLRSETALL}, + {338, 0xffffffff, 0x00160000, REGCLRSETALL}, + {362, 0xffffffff, 0x00160000, REGCLRSETALL}, + {282, 0xffffff00, 0x17, REGCLRSETALL}, + {306, 0xffffff00, 0x17, REGCLRSETALL}, + {330, 0xffffff00, 0x17, REGCLRSETALL}, + {354, 0xffffff00, 0x17, REGCLRSETALL}, + {290, 0xffffff00, 0x17, REGCLRSETALL}, + {314, 0xffffff00, 0x17, REGCLRSETALL}, + {338, 0xffffff00, 0x17, REGCLRSETALL}, + {362, 0xffffff00, 0x17, REGCLRSETALL}, + {282, 0xffff00ff, 0x2000, REGCLRSETALL}, + {306, 0xffff00ff, 0x2000, REGCLRSETALL}, + {330, 0xffff00ff, 0x2000, REGCLRSETALL}, + {354, 0xffff00ff, 0x2000, REGCLRSETALL}, + {290, 0xffff00ff, 0x2000, REGCLRSETALL}, + {314, 0xffff00ff, 0x2000, REGCLRSETALL}, + {338, 0xffff00ff, 0x2000, REGCLRSETALL}, + {362, 0xffff00ff, 0x2000, REGCLRSETALL}, + {65, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {321, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {577, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {833, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {96, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)}, + {352, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)}, + {608, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)}, + {864, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)}, + {96, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {352, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {608, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {864, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {33, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)}, + {289, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)}, + {545, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)}, + {801, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)}, + {1038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {1294, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {1550, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {83, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {339, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {595, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {851, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {1062, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {1318, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {1574, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)}, + {1892, 0xfffc0000, 0x15547, (OFFSET_SEL | REGCLRSETALL)}, + {1893, 0xfffc0000, 0x7, (OFFSET_SEL | REGCLRSETALL)}, + {1852, 0xffffe000, 0x07a, (OFFSET_SEL | REGCLRSETALL)}, + {1853, 0xffffffff, 0x0100, (OFFSET_SEL | REGCLRSETALL)}, + {1822, 0xffffffff, 0xFF, (OFFSET_SEL | REGCLRSETALL)}, + {1896, 0xfffffc00, 0x03d5, (OFFSET_SEL | REGCLRSETALL)}, + {91, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {347, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {603, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {859, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {1912, 0x0, 0xcc3bfc7, (OFFSET_SEL | REGSETALL)}, + {1913, 0x0, 0xff8f, (OFFSET_SEL | REGSETALL)}, + {1914, 0x0, 0x33f07ff, (OFFSET_SEL | REGSETALL)}, + {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)}, + {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)}, + {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)}, + {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)}, + {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)}, + {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)}, + {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {1921, 0x0, 0x188411, (OFFSET_SEL | REGSETALL)}, + {1922, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {1923, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)}, + {1924, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {1925, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)}, + {1926, 0x0, 0x1fffffcf, (OFFSET_SEL | REGSETALL)}, + {1927, 0x0, 0x188400, (OFFSET_SEL | REGSETALL)}, + {1928, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {1929, 0x0, 0x4188411, (OFFSET_SEL | REGSETALL)}, + {1837, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)}, + {1840, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)}, + {1842, 0x0, 0x2ffff, (OFFSET_SEL | REGSETALL)}, + {76, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {332, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {588, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {844, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {77, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, + {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, + {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, + {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, + {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {1028, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)}, + {1284, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)}, + {1540, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)}, + {1848, 0x0, 0x3cf07f8, (OFFSET_SEL | REGSETALL)}, + {1849, 0x0, 0x3f, (OFFSET_SEL | REGSETALL)}, + {1850, 0x0, 0x1fffff, (OFFSET_SEL | REGSETALL)}, + {1851, 0x0, 0x060000, (OFFSET_SEL | REGSETALL)}, + {130, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {386, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {642, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {898, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {131, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)}, + {387, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)}, + {643, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)}, + {899, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)}, + {29, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {285, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {541, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {797, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {30, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {286, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {542, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {798, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {31, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {287, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {543, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {799, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {1071, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {1327, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {1583, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {1808, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {1896, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, +}; + +void ddr_reg_set(u32 *reg, const struct ddr_reg_cfg *data, + u32 len, u32 mask) +{ + u32 *addr; + u32 i; + + for (i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + if (data[i].flag & OFFSET_SEL) + addr = reg + PHY_AC_BASE_ADDR + data[i].offset; + else + addr = reg + PHY_BASE_ADDR + data[i].offset; + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else if (data[i].flag & F_SET) + out_le32(addr, data[i].val); + else + out_le32(addr, in_le32(addr) + data[i].val); + } +} + +void ddr_phy_start(u32 *phyreg, enum ddr_size_t size) +{ + u32 len; + u32 mask; + + switch (size) { + case DDR_SIZE_2G: + mask = REG2G; + break; + + case DDR_SIZE_4G: + mask = REG4G; + break; + + case DDR_SIZE_8G: + mask = REG8G; + break; + + case DDR_SIZE_16G: + default: + return; + }; + + len = ARRAY_SIZE(ddr_start_cfg); + ddr_reg_set(phyreg, ddr_start_cfg, len, mask); + out_le32(phyreg, 0x01); +} diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c new file mode 100644 index 0000000000..ee2296c3b3 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_train.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <asm/io.h> + +static const u32 ddr_train_data[] = { + 0xb00, + 0x101, + 0x640000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1, + 0x7, + 0x10002, + 0x300080f, + 0x1, + 0x5, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1010000, + 0x280a0000, + 0x0, + 0x1, + 0x3200000f, + 0x0, + 0x0, + 0x10102, + 0x1, + 0x0, + 0x0, + 0x0, + 0xaa, + 0x55, + 0xb5, + 0x4a, + 0x56, + 0xa9, + 0xa9, + 0xb5, + 0x1000000, + 0x1000000, + 0x0, + 0xf0f0000, + 0x14, + 0x7d0, + 0x300, + 0x0, + 0x0, + 0x1000000, + 0x10101, + 0x0, + 0x30000, + 0x100, + 0x170f, + 0x0, + 0x0, + 0x0, + 0xa140a01, + 0x204010a, + 0x2080510, + 0x40400, + 0x1000101, + 0x10100, + 0x2040f00, + 0x34000000, + 0x0, + 0x0, + 0x1000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10100, + 0x80101, + 0x2000200, + 0x1000100, + 0x1000000, + 0x2000200, + 0x200, + 0x0, + 0x0, + 0x0, + 0xe000004, + 0xc0d100f, + 0xa09080b, + 0x2010000, + 0x80103, + 0x200, + 0x0, + 0xf000000, + 0x4, + 0xa, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x30100, + 0x1010001, + 0x10200, + 0x4000103, + 0x1050001, + 0x10600, + 0x107, + 0x0, + 0x0, + 0x10001, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10000, + 0x4, + 0x0, + 0x10000, + 0x0, + 0x3c0003, + 0x80100a0, + 0x16, + 0x2c, + 0x33, + 0x20043, + 0x2000200, + 0x4, + 0x60c, + 0xa1400, + 0x280000, + 0x6, + 0x46, + 0x70, + 0x610, + 0x12b, + 0x4001035, + 0x1010404, + 0x1e01, + 0x1e001e, + 0x1000100, + 0x100, + 0x0, + 0x5060403, + 0x1011108, + 0x1010101, + 0xf0a0a, + 0x0, + 0x0, + 0x4000000, + 0x4021008, + 0x4020206, + 0xc0034, + 0x100038, + 0x17003f, + 0x10001, + 0x10001, + 0x10005, + 0x20064, + 0x100010b, + 0x60006, + 0x650100, + 0x1000065, + 0x10c010c, + 0x1e1a1e1a, + 0x1011e1a, + 0xa070601, + 0xa07060d, + 0x100b080d, + 0xc00f, + 0xc01000, + 0xc01000, + 0x21000, + 0x120005, + 0x190064, + 0x10b, + 0x1100, + 0x1e1a0056, + 0x6000101, + 0x130204, + 0x1e1a0058, + 0x1000101, + 0x230408, + 0x1e1a005e, + 0x9000101, + 0x610, + 0x4040800, + 0x40100, + 0x3000277, + 0xa032001, + 0xa0a, + 0x80908, + 0x901, + 0x1100315c, + 0xa062002, + 0xa0a, + 0x141708, + 0x150d, + 0x2d00838e, + 0xf102004, + 0xf0b, + 0x8c, + 0x578, + 0xc20, + 0x7940, + 0x206a, + 0x14424, + 0x730006, + 0x3030133, + 0x4, + 0x0, + 0x4, + 0x1, + 0x5, + 0x2, + 0x6, + 0x50, + 0x1, + 0x5, + 0x28, + 0x73, + 0xd6, + 0x1, + 0x5, + 0x6b, + 0x1000133, + 0x140040, + 0x10001, + 0x1900040, + 0x1000c, + 0x42b0040, + 0x320, + 0x360014, + 0x1010101, + 0x2020101, + 0x8080404, + 0x67676767, + 0x67676767, + 0x67676767, + 0x67676767, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x18171615, + 0x14131211, + 0x7060504, + 0x3020100, + 0x0, + 0x0, + 0x0, + 0x1000000, + 0x4020201, + 0x80804, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, +}; + +void ddr_phy_train(u32 *phyreg) +{ + u32 i, len; + + len = ARRAY_SIZE(ddr_train_data); + for (i = 0; i < len; i++) + out_le32(phyreg + i, ddr_train_data[i]); +} diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c new file mode 100644 index 0000000000..2547efa7f5 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_utils.c @@ -0,0 +1,1956 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <asm/io.h> + +static const u32 ddr_phy_data[] = { + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x200, + 0x0, + 0x0, + 0x0, + 0x0, + 0x400000, + 0x80, + 0xdcba98, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2a, + 0x15, + 0x15, + 0x2a, + 0x33, + 0xc, + 0xc, + 0x33, + 0xa418820, + 0x3f0000, + 0x13f, + 0x20202000, + 0x202020, + 0x20008008, + 0x810, + 0x0, + 0x255, + 0x30000, + 0x300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x42080010, + 0x33e, + 0x1010002, + 0x80, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x200, + 0x0, + 0x0, + 0x0, + 0x0, + 0x400000, + 0x80, + 0xdcba98, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2a, + 0x15, + 0x15, + 0x2a, + 0x33, + 0xc, + 0xc, + 0x33, + 0x0, + 0x0, + 0x0, + 0x20202000, + 0x202020, + 0x20008008, + 0x810, + 0x0, + 0x255, + 0x30000, + 0x300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x42080010, + 0x33e, + 0x1010002, + 0x80, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x200, + 0x0, + 0x0, + 0x0, + 0x0, + 0x400000, + 0x80, + 0xdcba98, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2a, + 0x15, + 0x15, + 0x2a, + 0x33, + 0xc, + 0xc, + 0x33, + 0x0, + 0x10000000, + 0x0, + 0x20202000, + 0x202020, + 0x20008008, + 0x810, + 0x0, + 0x255, + 0x30000, + 0x300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x42080010, + 0x33e, + 0x1010002, + 0x80, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x50000, + 0x4000000, + 0x55, + 0x0, + 0x0, + 0x0, + 0xf0001, + 0x280040, + 0x5002, + 0x10101, + 0x8008, + 0x81020, + 0x0, + 0x0, + 0x1000000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x0, + 0x1010000, + 0x2020101, + 0x4040202, + 0x8080404, + 0xf0f0808, + 0xf0f0f0f, + 0x20200f0f, + 0x1b428000, + 0x4, + 0x1010000, + 0x1070501, + 0x54, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x108, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x4102035, + 0x41020, + 0x1c98c98, + 0x3f400000, + 0x3f3f1f3f, + 0x1f3f3f1f, + 0x1f3f3f, + 0x0, + 0x0, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x76543210, + 0x6010198, + 0x0, + 0x0, + 0x0, + 0x40700, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1142, + 0x3020100, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x2, + 0x4011, + 0x4011, + 0x40, + 0x40, + 0x4011, + 0x1fff00, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x1004011, + 0x200400, + +}; + +void ddr_phy_util(u32 *phyreg) +{ + u32 i, len; + + len = ARRAY_SIZE(ddr_phy_data); + for (i = 1792; i < len; i++) + out_le32(phyreg + i, ddr_phy_data[i]); + + for (i = 0; i < 1792; i++) + out_le32(phyreg + i, ddr_phy_data[i]); +} diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c new file mode 100644 index 0000000000..86aa99d822 --- /dev/null +++ b/drivers/ram/starfive/starfive_ddr.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#include <common.h> +#include <asm/arch/jh7110-regs.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <linux/bitops.h> +#include <linux/sizes.h> +#include <linux/delay.h> +#include <ram.h> +#include <reset.h> + +#include "starfive_ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct starfive_ddr_priv { + struct udevice *dev; + struct ram_info info; + void __iomem *ctrlreg; + void __iomem *phyreg; + struct reset_ctl_bulk rst; + struct clk clk; + u32 fre; +}; + +static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv) +{ + enum ddr_size_t size; + + switch (priv->info.size) { + case SZ_2G: + size = DDR_SIZE_2G; + break; + + case SZ_4G: + size = DDR_SIZE_4G; + break; + + case 0x200000000: + size = DDR_SIZE_8G; + break; + + case 0x400000000: + default: + pr_err("unsupport size %lx\n", priv->info.size); + return -EINVAL; + } + + ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2)); + ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2)); + ddr_phy_start(priv->phyreg, size); + + DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2); + ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR, + priv->phyreg, size); + + return 0; +} + +static int starfive_ddr_probe(struct udevice *dev) +{ + struct starfive_ddr_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + u64 rate; + int ret; + + /* Read memory base and size from DT */ + fdtdec_setup_mem_size_base(); + priv->info.base = gd->ram_base; + priv->info.size = gd->ram_size; + + priv->dev = dev; + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->ctrlreg = (void __iomem *)addr; + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->phyreg = (void __iomem *)addr; + ret = dev_read_u32(dev, "clock-frequency", &priv->fre); + if (ret) + return ret; + + switch (priv->fre) { + case 2133: + rate = 1066000000; + break; + + case 2800: + rate = 1400000000; + break; + + default: + pr_err("Unknown DDR frequency %d\n", priv->fre); + return -EINVAL; + }; + + ret = reset_get_bulk(dev, &priv->rst); + if (ret) + return ret; + + ret = reset_deassert_bulk(&priv->rst); + if (ret < 0) + return ret; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + goto err_free_reset; + + ret = clk_set_rate(&priv->clk, rate); + if (ret < 0) + goto err_free_reset; + + ret = starfive_ddr_setup(dev, priv); + printf("DDR version: dc2e84f0.\n"); + + return ret; + +err_free_reset: + reset_release_bulk(&priv->rst); + + return ret; +} + +static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + struct starfive_ddr_priv *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops starfive_ddr_ops = { + .get_info = starfive_ddr_get_info, +}; + +static const struct udevice_id starfive_ddr_ids[] = { + { .compatible = "starfive,jh7110-dmc" }, + { } +}; + +U_BOOT_DRIVER(starfive_ddr) = { + .name = "starfive_ddr", + .id = UCLASS_RAM, + .of_match = starfive_ddr_ids, + .ops = &starfive_ddr_ops, + .probe = starfive_ddr_probe, + .priv_auto = sizeof(struct starfive_ddr_priv), +}; diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h new file mode 100644 index 0000000000..0360c42930 --- /dev/null +++ b/drivers/ram/starfive/starfive_ddr.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wangyanhong.wang@starfivetech.com + * + */ + +#ifndef __STARFIVE_DDR_H__ +#define __STARFIVE_DDR_H__ + +#define SEC_CTRL_ADDR 0x1000 +#define PHY_BASE_ADDR 0x800 +#define PHY_AC_BASE_ADDR 0x1000 + +#define DDR_BUS_MASK GENMASK(29, 24) +#define DDR_AXI_MASK BIT(31) +#define DDR_BUS_OFFSET 0xAC +#define DDR_AXI_OFFSET 0xB0 + +#define DDR_BUS_OSC_DIV2 0 +#define DDR_BUS_PLL1_DIV2 1 +#define DDR_BUS_PLL1_DIV4 2 +#define DDR_BUS_PLL1_DIV8 3 +#define DDR_AXI_DISABLE 0 +#define DDR_AXI_ENABLE 1 + +#define OFFSET_SEL BIT(31) +#define REG2G BIT(30) +#define REG4G BIT(29) +#define REG8G BIT(28) +#define F_ADDSET BIT(2) +#define F_SET BIT(1) +#define F_CLRSET BIT(0) +#define REGALL (REG2G | REG4G | REG8G) +#define REGSETALL (F_SET | REGALL) +#define REGCLRSETALL (F_CLRSET | REGALL) +#define REGADDSETALL (F_ADDSET | REGALL) + +struct ddr_reg_cfg { + u32 offset; + u32 mask; + u32 val; + u32 flag; +}; + +enum ddr_size_t { + DDR_SIZE_2G, + DDR_SIZE_4G, + DDR_SIZE_8G, + DDR_SIZE_16G, +}; + +void ddr_phy_train(u32 *phyreg); +void ddr_phy_util(u32 *phyreg); +void ddr_phy_start(u32 *phyreg, enum ddr_size_t size); +void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size); + +#define DDR_REG_TRIGGER(addr, mask, value) \ + out_le32((addr), (in_le32(addr) & (mask)) | (value)) + +#define DDR_REG_SET(type, val) \ + clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \ + DDR_##type##_MASK, \ + ((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK) + +#endif /*__STARFIVE_DDR_H__*/

Add Kconfig to select the basic functions for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/cpu/jh7110/Kconfig | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 0000000000..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT

Add board support for StarFive VisionFive v2.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/Kconfig | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220..e341c364f1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6

+config TARGET_STARFIVE_VISIONFIVE2 + bool "Support StarFive VisionFive2 Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive2/Kconfig"

# platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig"

# architecture-specific options below

Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- arch/riscv/dts/jh7110-u-boot.dtsi | 86 +++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi new file mode 100644 index 0000000000..243237e83a --- /dev/null +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <dt-bindings/reset/starfive-jh7110.h> + +/ { + cpus: cpus { + u-boot,dm-spl; + + cpu0: cpu@0 { + u-boot,dm-spl; + status = "okay"; + cpu0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + cpu1: cpu@1 { + u-boot,dm-spl; + cpu1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + cpu2: cpu@2 { + u-boot,dm-spl; + cpu2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + cpu3: cpu@3 { + u-boot,dm-spl; + cpu3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + + cpu4: cpu@4 { + u-boot,dm-spl; + cpu4_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + soc { + u-boot,dm-spl; + + clint: clint@2000000 { + u-boot,dm-spl; + }; + + dmc: dmc@15700000 { + u-boot,dm-spl; + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clock-names = "pll1"; + clock-frequency = <2133>; + }; + }; +}; + +&gmac0_rmii_refin { + u-boot,dm-spl; +}; + +&aoncrg { + u-boot,dm-spl; +}; + +&syscrg { + u-boot,dm-spl; +}; + +&stgcrg { + u-boot,dm-spl; +};

This is the initial basic config for StarFive VisionFive v2 board. It includes consol, Norflash, sdio, ddr etc.

Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com --- configs/starfive_visionfive2_defconfig | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 configs/starfive_visionfive2_defconfig

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig new file mode 100644 index 0000000000..54ae6b2a43 --- /dev/null +++ b/configs/starfive_visionfive2_defconfig @@ -0,0 +1,72 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2" +CONFIG_SPL_TEXT_BASE=0x8000000 +CONFIG_SYS_PROMPT="StarFive #" +CONFIG_SPL_MMC=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TARGET_STARFIVE_VISIONFIVE2=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000 +CONFIG_FIT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" +CONFIG_DEFAULT_FDT_FILE="starfive/starfive_visionfive2.dtb" +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_BSS_START_ADDR=0x8040000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x8180000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_JH7110=y +# CONFIG_I2C is not set +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_STARFIVE=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RESET=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_TIMER_EARLY=y +CONFIG_OF_LIBFDT_OVERLAY=y